201138300 六、發明說明： 【發明所屬之技術領域】 本發明内容是有關於一種電子裝置，且特別是有關於 一種邏輯信號傳送電路。 【先前技術】 在一般用以傳送外部邏輯信號（如：時序信號）的電 路中，雖然外部邏輯信號的低電壓準位係固定在接地電 壓，但外部邏輯信號的高電壓準位卻會於不同情況下變 動。舉例而言，外部邏輯信號的高電壓準位可能於1.5V和 5.0V之間的範圍内變動。 然而，若是外部邏輯信號的高電壓準位不穩定的話， 則邏輯信號傳送電路之後接續的電路可能會根據不穩定的 邏輯信號動作，並因此有誤動作的情形。 此外，當邏輯信號從低電壓準位轉移至高電壓準位 時，會因轉移的過程而有大量的傳輸延遲（Propagation Delay)，使得邏輯信號的傳輸無法有效進行。 【發明内容】 本發明内容之一目的是在提供一種邏輯信號傳送電 路，藉以解決邏輯信號傳送時不穩定且具有傳輸延遲的問 題。 本發明内容之一技術樣態係關於一種邏輯信號傳送電 路，其包含一互補式金氧半導體反相器、一第一電晶體開 201138300 關以及一反相器。互補式金氧半導體反相器包含一 p型電 晶體以及一 N型電晶體，並用以反相一輸入信號。第一電 晶體開關連接於互補式金氧半導體反相器之一輸入端。反 相器連接於P型電晶體和第一電晶體開關之間，其中當第 一電晶體開關開啟時，反相器關閉P型電晶體，當第一電 ' 晶體開關關閉時，反相器開啟P型電晶體。 本發明内容之一技術樣態係關於一種邏輯信號傳送電 路，其包含一互補式金氧半導體反相器、一第一電晶體開 Φ 關以及一反相器。互補式金氧半導體反相器包含一 P型電 晶體以及一 N型電晶體，其中N型電晶體與P型電晶體串 疊連接。第一電晶體開關之控制端連接於N型電晶體之閘 極。反相器具有一輸入端以及一輸出端，輸出端連接於P 型電晶體之閘極，而第一電晶體開關連接於反相器和一接 地電壓之間。 根據本發明之技術内容，應用前述邏輯信號傳送電路 不僅可於外部邏輯信號的高電壓準位在1.5V和5.0V之間 φ 的範圍内不穩定變動的情形下，將外部邏輯信號轉換為所 需的邏輯信號，更可避免產生擊穿電流（shoot through current )，且邏輯信號的傳輸甚至可因較少的傳輸延遲 (Propagation Delay )而有效地進行。 【實施方式】 下文係舉實施例配合所附圖式作詳細說明，但所提供 之實施例並非用以限制本發明所涵蓋的範圍，而結構運作 之描述非用以限制其執行之順序，任何由元件重新組合之 201138300 結構，所產生具有均等功效的裝置，皆為本發明所涵蓋的 範圍。其中圖式僅以說明為目的，並未依照原尺寸作圖。 第1圖係依照本發明一實施例繪示一種邏輯信號傳送 電路的示意圖。邏輯信號傳送電路100可應用於閘極脈波 . 調變器（gate pulse modulator)中，並包含一互補式金氧半 導體（Complementary Metal Oxide Semiconductor，CMOS) 反相器110、一電晶體開關Ml以及一反相器IV1。CMOS 反相器110具有一輸入端IN，並用以對輸入端in所傳來 φ 之一輸入信號VIN作反相動作，以輸出一邏輯信號VFLK 或VFLKB。CMOS反相器110包含一 P型電晶體MP4A以 及一 N型電晶體MN4，其中電晶體MN4串疊連接於電晶 體MP4A，且其閘極連接於輸入端IN。電晶體開關Ml具 有一控制端’其連接於輸入端IN和電晶體MN4的閘極， 因而由輸入信號VIN所控制。反相器IV1連接於電晶體 MP4A和電晶體開關Ml之間，且亦具有一輸入端和一輸出 端，其輸出端連接於電晶體MP4A的閘極。電晶體開關Ml φ 則是連接於反相器IV1的輸入端和一接地電壓GND之間。 於操作上，當電晶體開關Ml開啟時，反相器IV1關 閉電晶體MP4A，而當電晶體開關Ml關閉時，反相器IV1 開啟電晶體MP4A。 具體而言’當輸入信號VIN發出至輸入端IN (或電晶 « 體MN4的閘極）而具有高位準（如：介於1.5V和5.0V) 時’電晶體開關Ml由輸入信號VIN所開啟，反相器IV1 的輸入端經由電晶體開關Ml拉降至接地電壓GND (低位 準），且反相器IV1之輪出端係拉升至一電源電壓Vdd(高 201138300 位準）’以關閉電晶體MP4A。因此，電晶體MN4由輸入 信號VIN所開啟’以將CMOS反相器110的輸出端OUT 拉降至接地電壓GND。 另一方面’當輸入信號VIN發出而具有低位準（如接 地電壓）時，電晶體開關Ml係由輸入信號VIN所關閉， 反相器IV1之輸入端係經由例如電晶體M5拉升至VDD(高 ’ 位準）’而反相器1V1之輸出端係拉降至接地電壓（低位201138300 VI. Description of the Invention: [Technical Field] The present invention relates to an electronic device, and more particularly to a logic signal transmission circuit. [Prior Art] In a circuit generally used to transmit an external logic signal (such as a timing signal), although the low voltage level of the external logic signal is fixed to the ground voltage, the high voltage level of the external logic signal may be different. Change in the case. For example, the high voltage level of the external logic signal may vary between 1.5V and 5.0V. However, if the high voltage level of the external logic signal is unstable, the circuit following the logic signal transmission circuit may operate according to the unstable logic signal, and thus there is a malfunction. In addition, when the logic signal is transferred from the low voltage level to the high voltage level, there is a large amount of propagation delay (Propagation Delay) due to the transfer process, so that the transmission of the logic signal cannot be performed efficiently. SUMMARY OF THE INVENTION An object of the present invention is to provide a logic signal transmission circuit for solving the problem of unstable logic signal transmission and transmission delay. One aspect of the present invention relates to a logic signal transmission circuit including a complementary MOS inverter, a first transistor opening 201138300, and an inverter. The complementary CMOS inverter includes a p-type transistor and an N-type transistor for inverting an input signal. The first transistor switch is coupled to one of the inputs of the complementary MOS inverter. The inverter is connected between the P-type transistor and the first transistor switch, wherein when the first transistor switch is turned on, the inverter turns off the P-type transistor, and when the first electric crystal switch is turned off, the inverter Turn on the P-type transistor. One aspect of the present invention relates to a logic signal transmission circuit including a complementary MOS inverter, a first transistor Φ, and an inverter. The complementary CMOS inverter comprises a P-type transistor and an N-type transistor, wherein the N-type transistor is connected in series with the P-type transistor. The control terminal of the first transistor switch is connected to the gate of the N-type transistor. The inverter has an input terminal and an output terminal connected to the gate of the P-type transistor, and the first transistor switch is connected between the inverter and a ground voltage. According to the technical content of the present invention, the logic signal transmission circuit can be used to convert an external logic signal into a situation in which the high voltage level of the external logic signal is unstablely fluctuated within a range of φ between 1.5V and 5.0V. The required logic signal can avoid the shoot through current, and the transmission of the logic signal can be effectively performed even with less Propagation Delay. The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the present invention, and the description of structural operation is not intended to limit the order of execution thereof. The 201138300 structure recombined by the components, which produces equal devices, is within the scope of the present invention. The drawings are for illustrative purposes only and are not drawn to the original dimensions. 1 is a schematic diagram showing a logic signal transmission circuit according to an embodiment of the invention. The logic signal transmission circuit 100 can be applied to a gate pulse modulator, and includes a complementary metal oxide semiconductor (CMOS) inverter 110, a transistor switch M1, and An inverter IV1. The CMOS inverter 110 has an input terminal IN for inverting an input signal VIN transmitted from the input terminal in to output a logic signal VFLK or VFLKB. The CMOS inverter 110 includes a P-type transistor MP4A and an N-type transistor MN4, wherein the transistor MN4 is connected in series to the transistor MP4A, and its gate is connected to the input terminal IN. The transistor switch M1 has a control terminal 'connected to the input terminal IN and the gate of the transistor MN4, and thus is controlled by the input signal VIN. The inverter IV1 is connected between the transistor MP4A and the transistor switch M1, and also has an input terminal and an output terminal, and an output terminal thereof is connected to the gate of the transistor MP4A. The transistor switch M1 φ is connected between the input terminal of the inverter IV1 and a ground voltage GND. In operation, when the transistor switch M1 is turned on, the inverter IV1 turns off the transistor MP4A, and when the transistor switch M1 is turned off, the inverter IV1 turns on the transistor MP4A. Specifically, 'when the input signal VIN is sent to the input terminal IN (or the gate of the crystallized body MN4) and has a high level (eg, between 1.5V and 5.0V), the transistor switch M1 is input signal VIN. When turned on, the input terminal of the inverter IV1 is pulled down to the ground voltage GND (low level) via the transistor switch M1, and the wheel terminal of the inverter IV1 is pulled up to a power supply voltage Vdd (high 201138300 level). Turn off the transistor MP4A. Therefore, the transistor MN4 is turned "on" by the input signal VIN to pull the output terminal OUT of the CMOS inverter 110 down to the ground voltage GND. On the other hand, when the input signal VIN is emitted and has a low level (such as a ground voltage), the transistor switch M1 is turned off by the input signal VIN, and the input terminal of the inverter IV1 is pulled up to VDD via, for example, the transistor M5 ( High 'level' and the output of inverter 1V1 is pulled down to ground (low)
準）’以開啟電晶體MP4A，使得CMOS反相器110的輸出 φ 端0υτ係經由例如電流源120拉升至VDD (高位準），其 中電流源120係連接於電壓VDD和電晶體ΜΡ4Α之間，且 可由一電晶體MP4來實現，電晶體mp4由低位準電壓VSS 控制而持續開啟。如此一來，電晶體ΜΝ4便可由輸入信號 VIN來關閉。 值得注意的是’當輪入信號VIN的電壓位準增加而於 達到一最大值之前（亦即，由低位準轉移至達到高位準之 前），例如達到電晶體開關M1的臨界電壓（如〇7V)，使 • 得電晶體開㈣M1開啟時，反相器IV1的輸入端經由電晶 體開關Ml立即拉降至接地電壓GND，反相器IV1的輸出 端立即拉升至電壓VDD，以關閉電晶體Mp4A，且電晶體 丽4由輸入“號VIN開啟。因此，即使輸入信號VIN的 尚電壓位準不穩定地於l 5 v和5 Q v之間變動，邏輯信號 傳送電路1〇〇仍可將輸入信號VIN轉換為所需的邏輯信 號。 再者’由於輸入信號VIN的電壓位準自低位準轉移至 局位準’實質上需要-段時間’造成邏輯信號傳送電路1〇〇 201138300 中的傳輸延遲，是故可藉由輸入信號VIN的電壓位準增加 而達到尚位準之前，電晶體開關Μ1開啟的情形下，反相 器IV1的輸入端經由電晶體開關Ml立即拉降至接地電壓 GND ’而後反相器IV1的輸出端立即拉升至電壓VDD以 關閉電晶體MP4A，使得傳輸延遲的時間因此減少。如此 一來’便可避免CMOS反相器110進行切換時所產生的擊 • 穿電流（shootthrough current)，且邏輯信號的傳輸可因較 少的傳輸延遲而有效進行。 • 在本實施例中，邏輯信號傳送電路100更可包含一啟 始電晶體MENI ’其具有一控制端’用以接收一啟始信號 PGB，並連接於電晶體MN4的閘極和接地電壓GND之間。 具體而言，當邏輯信號傳送電路100尚未穩定操作時，啟 始信號PGB發出而開啟電晶體MENI，以使CMOS反相器 110無法操作，藉以設定CMOS反相器110和接續電路的 初始狀態。 在本實施例中，邏輯信號傳送電路100更可包含一靜 • 電放電（ESD)電晶體ME，其中電晶體ME具有一控制端， 用以接收由啟始信號PGB反相而得之一信號PG，並連接 於電晶體MN4之閘極和用以接收外部邏輯信號vflKjn 的輸入節點之間。電晶體ME由信號PG所控制，以進行靜 電放電的操作，並傳送邏輯信號VFLK_IN作為輸入信號 ' VIN 〇 〇 ; 第2圖係依照本發明另一實施例繪示一種邏輯信號傳 送電路的示意圖。相較於第1圖，邏輯信號傳送電路2〇〇 更包含電晶體開關M2，其與電晶體開關Ml串疊連接，且 201138300 電晶體開關M2連接於電晶體開關Ml和反相器IV1的輸 入端之間。電晶體開關M2具有一控制端，控制端連接於 電晶體MN4的閘極（或輸入端in)，使得電晶體開關M2 由輸入信號VIN控制。 在操作上，包含電晶體開關Ml和M2的邏輯信號傳送 電路200’係進行類似於第1圖中包含電晶體開關Ml之邏 輯信號傳送電路100的動作。舉例而言’當輸入信號VIN 發出至輸入端IN (或電晶體MN4的閘極）而具有高位準 時，電晶體開關Ml和M2均由輸入信號VIN所開啟，反 相器IV1的輸入端經由電晶體開關Ml和M2拉降至接地 電壓GND (低位準），且反相器IV1之輸出端係拉升至電 源電壓VDD (高位準）’以關閉電晶體MP4A。 同樣地，當輸入信號VIN的電壓位準增加而於達到一 最大值之前（亦即，由低位準轉移至達到高位準之前），例 如達到電晶體開關Ml和M2的臨界電壓，使得電晶體開關 和M2開啟時，反相器ΐνι的輸入端經由電晶體開關 1和M2立即拉降至接地電壓GNd，而反相器ΙλΠ的輸 出缒立即拉升至電壓VDD，以關閉電晶體Mp4A，且電晶The transistor MP4A is turned on so that the output φ terminal 0υτ of the CMOS inverter 110 is pulled up to VDD (high level) via, for example, the current source 120, wherein the current source 120 is connected between the voltage VDD and the transistor ΜΡ4Α. And can be realized by a transistor MP4, and the transistor mp4 is continuously turned on by the low level voltage VSS. In this way, the transistor ΜΝ4 can be turned off by the input signal VIN. It is worth noting that 'when the voltage level of the turn-in signal VIN increases before reaching a maximum value (that is, before moving from the low level to the high level), for example, reaching the threshold voltage of the transistor switch M1 (eg 〇7V) ), when the transistor is turned on (4) When M1 is turned on, the input terminal of the inverter IV1 is immediately pulled down to the ground voltage GND via the transistor switch M1, and the output terminal of the inverter IV1 is immediately pulled up to the voltage VDD to turn off the transistor. Mp4A, and the transistor MN4 is turned on by the input "number VIN. Therefore, even if the voltage level of the input signal VIN is unstable between 15v and 5Qv, the logic signal transmission circuit 1 can still The input signal VIN is converted to the desired logic signal. Further, 'the voltage level of the input signal VIN shifts from the low level to the local level 'substantially needs - the period of time' causes the transmission in the logic signal transmission circuit 1〇〇201138300 The delay is such that the input of the inverter IV1 is immediately pulled down to the ground via the transistor switch M1 before the transistor switch Μ1 is turned on by the voltage level of the input signal VIN increasing. The output of the inverter IV1 is immediately pulled up to the voltage VDD to turn off the transistor MP4A, so that the time of the transmission delay is thus reduced. Thus, the attack generated when the CMOS inverter 110 is switched can be avoided. • The shootthrough current, and the transmission of the logic signal can be effectively performed due to less transmission delay. • In this embodiment, the logic signal transmission circuit 100 can further include a start transistor MENI 'which has a control The terminal ' is configured to receive a start signal PGB and is connected between the gate of the transistor MN4 and the ground voltage GND. Specifically, when the logic signal transmission circuit 100 has not been stably operated, the start signal PGB is turned on and turned on. The crystal MENI is such that the CMOS inverter 110 is inoperable, thereby setting the initial state of the CMOS inverter 110 and the connection circuit. In the embodiment, the logic signal transmission circuit 100 further includes an electrostatic discharge (ESD) a crystal ME, wherein the transistor ME has a control terminal for receiving a signal PG inverted by the start signal PGB, and is connected to the gate of the transistor MN4 and used for receiving Between the input nodes of the logic signal vflKjn, the transistor ME is controlled by the signal PG to perform the electrostatic discharge operation, and transmits the logic signal VFLK_IN as the input signal 'VIN 〇〇; FIG. 2 is drawn according to another embodiment of the present invention. A schematic diagram of a logic signal transmission circuit is shown. Compared to FIG. 1, the logic signal transmission circuit 2 further includes a transistor switch M2 connected in series with the transistor switch M1, and the 201138300 transistor switch M2 is connected to the transistor. Between the switch M1 and the input of the inverter IV1. The transistor switch M2 has a control terminal connected to the gate (or input terminal in) of the transistor MN4 such that the transistor switch M2 is controlled by the input signal VIN. In operation, the logic signal transfer circuit 200' including the transistor switches M1 and M2 performs an action similar to the logic signal transfer circuit 100 including the transistor switch M1 in Fig. 1. For example, when the input signal VIN is sent to the input terminal IN (or the gate of the transistor MN4) and has a high level, the transistor switches M1 and M2 are both turned on by the input signal VIN, and the input terminal of the inverter IV1 is powered. The crystal switches M1 and M2 are pulled down to the ground voltage GND (low level), and the output of the inverter IV1 is pulled up to the power supply voltage VDD (high level) to turn off the transistor MP4A. Similarly, when the voltage level of the input signal VIN increases until a maximum value is reached (ie, before the low level is reached to reach the high level), for example, the threshold voltages of the transistor switches M1 and M2 are reached, so that the transistor switch When M2 is turned on, the input of the inverter ΐνι is immediately pulled down to the ground voltage GNd via the transistor switches 1 and M2, and the output of the inverter ΙλΠ is immediately pulled up to the voltage VDD to turn off the transistor Mp4A, and the electricity is turned off. crystal
體MN4由輸入信號VIN開啟。因此，即使輸入信號viN 的两電壓位準不穩定地於1.5 V和5.0 V之間變動，邏輯信 銳傳送電路200仍可將輸入信號VIN轉換為所需的邏輯信 號。 ; 再者，藉由輸入信號VIN的電壓位準增加而達到高位 準之前’電晶體開關Ml和M2開啟的情形下，反相器ινι 的輪入端經由電晶體開關Ml和M2立即拉降至接地電壓 201138300 GND，可使得傳輸延遲的時間因此減少。如此一來，便可 避免產生擊穿電流’且邏輯信號的傳輸可因此有效進行。 第3圖係依照本發明又一實施例繪示一種邏輯信號傳 送電路的示意圖。相較於第2圖，邏輯信號傳送電路3〇〇 更包含一磁滯（hysteresis)電晶體M3 ’其用以對邏輯信號 傳送電路300賦予一磁滯特性，並由反相器ινί所控制。 磁滯電晶體M3與電晶體開關M2串疊連接，並與電晶體開 關Ml並聯相接’且亦具有一控制端，連接於反相器 φ 的輸出端’以接收由反相器IV1所輸出之信號HYS。 當磁滯電晶體M3與電晶體開關Ml和M2共同操作 時，磁滯電晶體M3會對邏輯信號傳送電路3〇〇賦予磁滞 特性。第4圖係依照本發明實施例繪示一種輸入信號viN 相對輸出邏輯信號VFLK的磁滯曲線示意圖。同時參照第 3圖和第4圖’當輸入彳5戒VIN的電壓位準增加至二個臨 界電壓（2VTH)以開啟電晶體開關Ml和M2時，由反相 器IV1輸出之信號HYS會拉升至電壓vdd (高位準），以 φ 開啟磁滯電晶體M3。此時，磁滯電晶體M3比電晶體開關 Ml更加導通或開啟（例如：M3的導通電阻rds，on比M1 小），因此節點NX理想上可視為與接地電壓gnd連接。 . 之後，當輸入信號VIN的電壓位準減少至一個臨界電壓 • (VTH)時，電晶體開關M2會關閉。如此一來，當磁滞 電晶體M3與電晶體開關Ml和M2共同操作時，邏輯信號 傳送電路300便可藉由磁滞電晶體M3的操作而被賦;磁 滯特性。 其次’亦可藉由改變電晶體開關Ml和M2其中一者的 201138300 尺寸大小’或同時改變電晶體開關Ml和M2的尺寸大小， 來調整第4圖中的轉換點（即電壓VTH或2VTH)。另外， 將電晶體開關Ml串疊連接於電晶體開關m2,也可使轉換 點增加至超過1.0 V。此外，若是省略電晶體開關M2的話， 則轉換點可能位於電晶體MN4的臨界電壓（一般為〇.7 v 〜0.9 V)。 由上述本發明之實施例可知，應用前述邏輯信號傳送 電路，不僅可於外部邏輯信號的高電壓位準在1 5¥和5.〇v # 之間的範圍内不穩定變動的情形下，將外部邏輯信號轉換 為所需的邏輯信號，更可避免產生擊穿電流（sh〇〇t through current )’且邏輯信號的傳輸甚至可因較少的傳輸延遲 (Propagation Delay)而有效地進行。 雖然本發明已以實施方式揭露如上，然其並非用以限 定本發明’任何本領域具通常知識者，在不脫離本發明之 精神和範圍内’當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係依照本發明一實施例繪示一種邏輯信號傳送 ， 電路的示意圖。 - 第2圖係依照本發明另一實施例繪示一種邏輯信號傳 送電路的示意圖。 第3圖係依照本發明又一實施例繪示一種邏輯信號傳 送電路的示意圖。 第4圖係依照本發明實施例繪示一種輸入信號相對輸 201138300 出邏輯信號的磁滯曲線示意圖。 【主要元件符號說明】 100、200、300 :邏輯信號傳送電路 110 : CMOS反相器 120 :電流源Body MN4 is turned on by input signal VIN. Therefore, even if the two voltage levels of the input signal viN are unstable between 1.5 V and 5.0 V, the logic signal transmission circuit 200 can convert the input signal VIN into a desired logic signal. Furthermore, in the case where the transistor switches M1 and M2 are turned on by the voltage level of the input signal VIN increasing to a high level, the turn-in end of the inverter ινι is immediately pulled down via the transistor switches M1 and M2. The ground voltage of 201138300 GND can reduce the transmission delay time. In this way, the breakdown current ' can be avoided and the transmission of the logic signal can be performed efficiently. Figure 3 is a schematic diagram showing a logic signal transmission circuit in accordance with still another embodiment of the present invention. In contrast to Fig. 2, the logic signal transfer circuit 3A further includes a hysteresis transistor M3' for imparting a hysteresis characteristic to the logic signal transfer circuit 300 and controlled by the inverter ινί. The hysteresis transistor M3 is connected in series with the transistor switch M2 and is connected in parallel with the transistor switch M1. It also has a control terminal connected to the output terminal of the inverter φ for receiving output by the inverter IV1. The signal HYS. When the hysteresis transistor M3 operates in conjunction with the transistor switches M1 and M2, the hysteresis transistor M3 imparts hysteresis characteristics to the logic signal transmission circuit 3〇〇. FIG. 4 is a schematic diagram showing a hysteresis curve of an input signal viN versus an output logic signal VFLK according to an embodiment of the invention. Referring to FIG. 3 and FIG. 4 simultaneously, when the voltage level of the input 彳5 or VIN is increased to two threshold voltages (2VTH) to turn on the transistor switches M1 and M2, the signal HYS outputted by the inverter IV1 is pulled. Raise to voltage vdd (high level) and turn on hysteresis transistor M3 with φ. At this time, the hysteresis transistor M3 is turned on or on more than the transistor switch M1 (for example, the on-resistance rds of M3, on is smaller than M1), so the node NX is ideally connected as being connected to the ground voltage gnd. After that, when the voltage level of the input signal VIN is reduced to a threshold voltage • (VTH), the transistor switch M2 is turned off. As a result, when the hysteresis transistor M3 operates in conjunction with the transistor switches M1 and M2, the logic signal transmission circuit 300 can be imparted by the operation of the hysteresis transistor M3; hysteresis characteristics. Secondly, the switching point in Figure 4 (ie voltage VTH or 2VTH) can also be adjusted by changing the size of the 201138300 of one of the transistor switches M1 and M2 or by simultaneously changing the size of the transistor switches M1 and M2. . In addition, connecting the transistor switch M1 to the transistor switch m2 in series can also increase the switching point to more than 1.0 V. In addition, if the transistor switch M2 is omitted, the switching point may be at the threshold voltage of the transistor MN4 (generally 〇.7 v to 0.9 V). It can be seen from the above embodiments of the present invention that the application of the logic signal transmission circuit described above can be performed not only in the case where the high voltage level of the external logic signal is unstablely changed within a range between 1 5 ¥ and 5. 〇 v # The external logic signal is converted to the desired logic signal, and the breakdown current can be avoided, and the transmission of the logic signal can be performed efficiently even with less Propagation Delay. The present invention has been disclosed in the above embodiments, and it is not intended to limit the invention to any of ordinary skill in the art, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing a logic signal transmission and circuit according to an embodiment of the invention. - Figure 2 is a schematic diagram showing a logic signal transmission circuit in accordance with another embodiment of the present invention. Figure 3 is a schematic diagram showing a logic signal transmission circuit in accordance with still another embodiment of the present invention. FIG. 4 is a schematic diagram showing a hysteresis curve of an input signal relative to a logic signal of 201138300 according to an embodiment of the invention. [Main component symbol description] 100, 200, 300: logic signal transmission circuit 110 : CMOS inverter 120 : current source
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