201123195 P51980116TW 32720twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明疋有關於-種電阻式記憶體，且特別是有關於 -種用於電阻式記，隨的電阻式鋪猶證方法及直驗證 裝置。 、 【先前技術】 電阻式記憶體為目前具有潛力的下世代非揮發性記憶體 技術之- ’其擁有低功率消耗、面積小及操作速度快等優點。 除此之外’電阻式記憶體之阻抗比值甚至可以達到刚倍，因 此電阻式記鐘讀缺，未來將會取代卩祕記憶體等技 财㈣対在高賴下和職導通路徑， 你正二狀，則具有隔離的效果。藉*提供高低電壓的操 作^電阻式記鐘的阻抗可啸據所提供之賴的不同，而呈 現尚阻抗狀態或低阻抗狀態。 ^且式記憶體在操作中，會有元件無法轉態成功的現 的是，大部份無法轉態成功之元件均屬於下次繼續 ==機會可以正常操作的元件，而此種可以更正之元件無 寫入^财齡紐騎。目前阻式記憶體 ^二提出來驗證與更正所述軟性錯誤，以提升電阻 式δ己憶體之良率與可靠度。 參照圖1 ’圖1是單極性電阻式記憶體的電路圖。單 包括了單極性電阻式記憶胞ηοΐ —I極性電阻式記憶胞⑽具有電介質與兩個 3 201123195 P51980116TW 32720twf.doc/n 電極端1 1 1與1 12，雷曰挪1 1 r\ 其中電晶體之祕連接:電極端=閘極、源極與没極， 要提ΐίΐίΐ，電阻式記憶胞110進行寫入動作，則需 ==::=2°，且同時需要提供寫入電 110仍然故恤錄態目此早祕電喊記憶胞 要提==極性電阻式記憶胞110進行抹除動作，則需 將部份電荷】子電極端U1 ’抹除電壓會 憶胞η呈現^^ ^ 使得單極性電阻式記 後，因aU 待電極端111的抹除被移除 阻式!載子自電介質中被移除，因此單極性電 入^壓^ 11()仍然呈現高阻抗狀態。其中抹除電壓較寫 在單極性電阻式記憶胞110進行抹 ^ ==阻式記憶胞u。的狀態，則需=閘= 阻式—120 ’且同時需要提供讀取電壓給單極性電 輸^;t110的電極端11卜此時只要對電極端112所 胞=;ΓΪΓ測’便可以得知目前單極性電阻式記憶 小二狀態或高阻抗狀態。其中讀取電壓 201123195 P51980116TW 32720twf.doc/n 清參照圖2，圖2是傳統電阻式記憶體寫入驗證方法 的流程圖。首先，在步騍S2〇1中，提供電壓給電晶體^0 的閘極端，以使得電晶趲12〇呈現導通狀態。接著，在+ 驟S202中提供初始寫入電壓給單極性電阻式記憶胞^ 的電極端111，並且在步锦S203時，結束提供給單極性電 阻式記憶胞110的電極端m之初始寫入電壓。在步驟 S204中’提供讀取電壓给單極性電阻式記憶胞ιι〇的電極 端Π1並在步驟S2〇5中，_單極性電阻式記憶胞 的狀L卩判斷單極性電阻式記憶胞110是否順利地 入。若單極性電阻式錢胞11G·地 單 式記憶胞11G轉態成功，接著，結束整個 相反地’若單極性電阻式記憶胞u ，二代表單極性電阻1 在步驟S2G6中’提供—個可成功寫入電ί ί早^電阻式記憶胞⑽的電極端⑴。在步驟S207 中’、、、°束提供給單極性電阻式記憶胞110的電極端1U之 功，人電壓。在步驟識中，提供讀取電壓給單極 ，電阻式s己憶胞110的電極端1H，並在步，驟S2〇9中，價 測早極性電阻式記憶胞11〇的狀態，以判斷單極性電 是否順利地被寫人。若單極性電阻式記憶胞ιι〇 =’i，寫人’則代表單極性電阻式記憶胞nG轉態成 接著、、、。束整個寫人驗證方法。相反地，若單極性電 阻式記憶胞m未順利地被寫入，則代表單極性電阻式記 5 201123195 P51980116TW 32720twf.doc/n 憶胞110轉態失敗，則回到步驟S2〇6，並提供另一個與前 次不同的可成功寫入電壓。 接著，請參考圖3〜圖6，圖3〜圖ό是單極性電阻式 s己憶胞110的電極端1Π上可能之電壓的波形圖。要說明 的是，單極性電阻式記憶體1〇〇採用前述的傳統寫入驗證 方法，且圖3〜圖6都是假設單極性電阻式記憶胞u〇在 提供多次的寫入電壓才成功地轉態。圖3〜圖5中，先提 供初始電壓給電極端m，之後結束初始電壓，並提供讀 取電壓給電極端m。因為單極性電阻式記· lu未成 ^地轉態、’因此必須再提供另—個可成功寫人電壓給電極 端in，並在結束可成功寫入電壓後，再提供讀取電壓給 電，端111來判斷為單極性電阻式記憶胞U1是否成功地 °曰若單極性電阻式記憶胞ln仍未成功地轉態，則重 ，地提供可成功寫人電壓，朗單極性雜找憶胞⑴ 成功地轉態為止。 在圖3中，初始寫入電壓的工作週期較小，之後的可 Λ ^ ί入電H週細逐漸增A。在® 4中，初始寫 電壓與之後的可成功寫人電壓之波形相同。在圖$中， 寫人電壓的私壓^1小，之後的寫人電壓之碰則逐漸 曰^ °在圖6中’初始寫人電壓的電壓與工作週期較小， 之後的寫人電壓之電壓紅作週期則逐漸增大 =明的是’傳統的抹除驗證綠與上述的寫入驗證 似’所述寫人電壓需改成抹除電壓，且驗證單極性 電阻式記憶胞no是否順利被寫入需改成驗證單極性電阻 201123195 P51980116TW 32720twf.doc/n 式記憶胞110是否順利被抹除。另外，傳統的寫入/抹除驗 證方法都是先寫入/抹除，再讀取驗證，若單極性電阻式記 憶胞110無法順利地被寫入/抹除，則再次寫入/抹除。因 此，傳統的寫入/抹除驗證方法除了多出讀取時間外，更浪 費了寫入/抹除與讀取之間的設定/保持時間。 【發明内容】 # 本發明之示範實施例用於電阻式記憶體的一種驗證 方法’其中言阻式記憶體操作於多個阻抗狀態。持續地提 供轉態信號至電阻式記憶體，並同時偵測電阻式記憶體所 因此產生的偵測電流。選擇狀態信號的幅值，其中狀態信 號的幅值對應於電阻式記憶體的其中一個阻抗狀態。根據 债測電流與狀態信號產生判斷結果，並根據判斷結果判斷 電阻式記憶體是否轉換至狀態信號所對應的阻抗狀態。若 電阻式記憶體轉換至狀態信號所對應的阻抗狀態，則結束 提供轉態信號。 ® 本發明的示範實施例提供一種驗證裝置，所述驗證裝 置用以驗證電阻式記憶體，且所述驗證電路包括信號選擇 器、轉態信號控制電路、電壓信號源與驗證電路。其中所 述信號選擇器連接於所述電阻式記憶體之兩端，所述轉態 信號控制電路連接於所述信號選擇器，所述電壓信號源連 接於所述轉態信號控制電路，且所述驗證電路連接於所述 轉態信號控制電路與所述信號選擇器。所述信號選擇器受 控於設定/重設致能信號，用以提供轉態信號給所述電阻式 201123195 lysvmo fW 32720twf.doc/n έ己憶體之兩端的其中一端，並接收來自於所述電阻式記憶 體之兩端的另一端之偵測電流。所述轉態信號控制電路受 控於判斷結果，用以透過所述信號選擇器來提供所述轉態 信號給所述電阻式記憶體。所述電壓信號源用以提供設定 電壓與重設電壓給所述轉態信號控制電路作為產生所述轉 態信號的參考。所述驗證電路，透過所述信號選擇器接收 所述偵測電流，並根據偵測電流產生判斷結果，以判斷所 述電阻式記憶體是否是成功地轉換其阻抗狀態。 為讓本發明之上述特徵能更明顯易懂，下文特舉示範 實施例，並配合所附圖式作詳細說明如下。 【實施方式】 本發明之示範實施例提供了一種驗證方法，其可以用 於電阻式記，itH人或絲的驗證，此驗證方法可以用 於單階或㈣操作之雜式記憶體。除此之外，本發明之 示範實施例亦提供對應於所述多種驗證方法❹種驗證裳 置0 、 ，階操作之電阻式記憶體的阻抗狀態具有低阻抗狀 阻抗狀態。低阻抗狀態表示儲存位元G，高阻抗^ 悲表示儲存位元1 ;或者你阳_ 狀 - λ 1抗狀態表示儲存位元丨，冑$ ==!所述單階操作之電阻式記憶體的= 高阻抗狀態轉換至低阻抗狀態，戈者Ϊ 自低阻抗狀態轉換至高阻抗狀熊。 ^考疋 201123195 P51980116TW 32720twf.doc/n 請參照圖7，圖7是本發明之示範例子所提供的電阻 式記憶體之電路圖。所述電阻式記憶體7〇〇可以是單極性 或雙極性元件，且電阻式記憶體7〇〇包括電晶體72〇與電 阻式記憶胞710，其中電阻式記憶胞γιο包括與在電極端 711、712之間的電介質，其結構如同圖7所示，由下由上 包括了氮化鈦層（對應於電極端712)、二氧化铪層（對應於 電介質）、以及對應於電極端711的鈦層、氮化鈦層與銅鋁 φ 合金層。另外，所述雙極性元件是指電阻式記憶胞710的 電流可以從電極端711至7Γ2流過，或從電極端712至711 流過。 凊參照圖7與圖8，圖8是本發明之示範例子所提供 的用於單階操作之電阻式記憶體之驗證方法之流程圖。首 先，在步驟S801中，提供閘極電壓給所述電晶體72〇，以 控制所述電晶體720呈現導通狀態。接著，.在步驟S8〇2 中，提供轉態信號給所述電阻式記憶胞71〇的電極端7ιι 或712，並同時偵測電阻式記憶胞710所產生的偵測電流。 攀 在步驟S803中，根據所述制電流產生判斷結果， ，在步驟S8G4中’根據判斷結果判斷電阻式記憶胞71〇 疋否成功地轉態(從低阻抗狀態轉換至高阻抗狀態，或從高 阻^大態轉換至低阻抗狀態）。若電阻式記憶胞71〇成功地 轉感，則在步驟S8〇5中，結束提供所述轉態信號，並接 著結束驗證方法。若電阻式記憶胞？1〇未成功地轉態，則 回到^驟S8G2巾’並_地提供轉態信號。 刚述轉,¾½號為寫入電壓或抹除電壓，所述轉態信號 201123195 P51980116TW 32720twf.doc/n 的長度隨時間增加，且轉態信號可為方波。請參照圖9A 與圖9B ’圖9A疋電p且式記憶胞？1〇之電極端711的電壓 與電阻式記憶胞710所產生的電流之波形圖，目9B是電 阻式δ己憶胞110之電極端712的電壓與電阻式記憶胞71〇 所產生的電流之波形圖。 在圖9Α中’虛線所示的電壓與電流曲線是對應於電 阻式記憶胞710轉換至低阻抗狀態雜況。請參照實線所 不的電祕電流曲線，當轉態㈣綱地使電阻式記憶胞 710從轉換至低阻抗狀態時，電極端712的偵測電流會逐 漸變大，並維持在IL附近，因此藉由偵測電流便可以得知 電阻式汜憶胞710順利地轉態。之後，在電阻式記憶胞71〇 順利地轉態後，便結束所述的轉態信號。 在圖9Α中，實線所示的電壓與電流曲線是對應於電 阻式5己憶月包710轉換至高阻抗狀態的狀況n照虛線所 示的電壓與流曲線，f轉態信號順利地使電阻式記憶胞 710#從轉換至高阻抗狀態時，電極端712的偵測電流會逐 漸變大’並維持在IH附近，因此藉由偵測電流便可以得 知電阻式記憶胞710順利地轉態。之後，在電阻式記憶胞 71〇順利地轉態後，便結束所述的轉態信號。 如同前面所述，本發明之示範實施例的驗證方法適用 於，極性元件的電阻是記憶體7〇〇，因此，轉態信號可以 被提供給電極端711或712。在圖9B中，實線所示的電壓 與電流曲線是對應於電阻式記憶胞7丨〇轉換至高阻抗狀態 的狀況。請參照實線所示的電壓與電流曲線，當轉態信號 201123195 P51980116TW 32720twf.doc/n 順利1使電阻式記憶胞710順利地轉換至高阻抗狀態時， 電極端712的偵測電流會逐漸變小，並維持在m附近， 因此藉由偵測電流便可以得知電阻式記憶胞71〇順利地轉 態。在電阻式記憶胞71〇順利地轉態後，便結束所述的 態信號。 、在圖9B中，虛線所示的電壓與電流曲線是對應於電 阻式記憶胞710轉換至低阻抗狀態的狀況。請參照實線所 鲁不的電壓與電流曲線，當轉態信號順利地使電阻式記憶胞 710轉換至低阻抗狀態時，電極端712的偵測電流幾乎不 變，並維持在IL附近，因此藉由偵測電流便可以得知電阻 式記憶胞710順利地轉態。在電阻式記憶胞71〇順利地轉 態後，便結束所述的轉態信號。 本發明之示範實施例另提供一種驗證方法’其適合用 於可操作於多階的電阻式記憶體之寫入或抹除的驗證。所 述可操作於多階的電阻式記憶體的阻抗狀態可以具有多種 鲁 不同的阻抗狀態，以四階的阻抗狀態為例，當電阻式記憶 體儲存位元00時，其阻抗狀態可以為第一高阻抗狀態，當 電阻式記憶體儲存位元〇 1時，其阻抗狀態可以為第二高阻 抗狀態’當電阻式記憶體儲存位元10時，其阻抗狀態可以 為第二低阻抗狀態，當電阻式記憶體儲存位元11時，其阻 抗狀態可以為第一低阻抗狀態。所述第一高阻抗狀態所對 應的阻抗值大於第二高阻抗狀態，所述第二高阻抗狀態所 對應的阻抗值大於第二低阻抗狀態，且所述第二低阻抗狀 態所對應的阻抗值大於第一低阻抗狀態。另外，前述儲存 11 201123195 FMyKOllbTW 32720twf.doc/n 位元與阻抗狀態的對應關係僅是一種示範實施例，並非用 以限定本發明。 睛參照圖7與圖10，圖10是本發明之示範例子所提 供的用於多階操作之電阻式記憶體之驗證方法之流程圖。 首先，在步驟S851中，提供閘極電壓給所述電晶體72〇， 以控制所述電晶體720呈現導通狀態。接著，在^驟％52 中，選擇狀態信號的幅值，其十狀態信號的幅值與電阻式 記憶胞710所要轉換的阻抗狀態相關。以上述四階的阻抗 狀態為例，若電阻式記憶胞710要轉換至第一高阻抗狀 態，則狀悲彳§號的幅值可能為TH1 ;若電阻式記憶胞71〇 要轉換至第一向阻抗狀態，則狀態信號的幅值可能為 TH2 ;若電阻式記憶胞71〇要轉換至第一低阻抗狀態，則 狀態信號的幅值可能為TL1 ;若電阻式記憶胞71〇 ^轉換 至第二低阻抗狀態，則狀態信號的幅值可能為TL2。 接著，在步驟S853中，提供轉態信號給所述電阻式 記憶胞710的電極端711或712，並同時债測電阻式記憶 胞710所產生的偵測電流。在步驟S854中，根據所述偵 測電流與狀態信號產生判斷結果，並在步驟S855中，根 據判斷結果判斷電阻式記憶胞71 〇是否成功地轉換至狀態 信號的幅值所對應的阻抗狀態。若電阻式記憶胞71〇成功 地，^ ’則在步驟Μ%巾，結束提供所述觀信號，並 接著結束驗證方法。若電阻式記憶胞710未成功地轉態， 則回到步驟S853中。 要說明的是’上述的轉態信號可以是用以控制電阻式 12 201123195 P51980116TW 32720twf.doc/n 記憶胞710之阻抗狀態的寫入電壓與抹除電壓。除此之 外，所述狀態信號可以狀態電流或者是狀態電壓。舉例來 說，例如要驗證電阻式記憶胞710是否能轉換至第一高阻 抗狀態，則可以選擇狀態電流的幅值為TIH1。接著只要判 斷偵測電流是否小於狀態電流，便能夠確定電阻式記憶胞 710是否成功轉態’以及決定是否要結束轉態信號。另外， 前述例子中的偵測電流亦可以先經過放大後，再將放大後 的偵測電流與狀態電流比較來確定電阻式記憶胞71〇是否201123195 P51980116TW 32720twf.doc/n VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a resistive memory, and in particular to a resistive type, Certificate method and direct verification device. [Prior Art] Resistive memory is the next generation of non-volatile memory technology with potential - 'It has the advantages of low power consumption, small area and fast operation speed. In addition, the resistance ratio of resistive memory can even reach just double, so the resistive clock is missing, and in the future it will replace the secret memory and other technologies. (4) Under the high and the career path, you are two Shape, it has the effect of isolation. By providing * high and low voltage operation ^ The resistance of the resistive clock can be compared to the difference provided, and it is still in an impedance state or a low impedance state. ^ And in the operation of the memory, there will be components that can not be successfully transferred. Most of the components that cannot be successfully converted belong to the next time == chance that the device can operate normally, and this can be corrected. The component is not written to ^财龄纽骑. Currently, resistive memory is proposed to verify and correct the soft error to improve the yield and reliability of the resistive δ hexamed body. Referring to Fig. 1, Fig. 1 is a circuit diagram of a unipolar resistive memory. Single includes a unipolar resistive memory cell ηοΐ—I polarity resistive memory cell (10) has a dielectric with two 3 201123195 P51980116TW 32720twf.doc/n electrode terminals 1 1 1 and 1 12, Thunderbolt 1 1 r\ where the transistor The secret connection: electrode end = gate, source and immersion, to improve ΐ ΐ ΐ 电阻, resistive memory cell 110 to write action, you need ==::= 2 °, and at the same time need to provide write power 110 still In the morning, the secret memory calls the memory cell to raise == the polarity resistive memory cell 110 performs the erasing action, then the partial charge] sub-electrode end U1 'wipe the voltage will recall the cell η to render ^^ ^ After the unipolar resistance type is recorded, the resist is removed due to the erasing of the aU to the electrode terminal 111! The carrier is removed from the dielectric, so the unipolar input voltage is still in a high impedance state. The erase voltage is written in the unipolar resistive memory cell 110 to erase ^ == resistive memory cell u. The state needs to be = gate = resistive - 120 ' and at the same time need to provide the read voltage to the unipolar electrical input ^; the electrode end 11 of t110 at this time as long as the opposite end of the electrode end 112 =; Know the current unipolar resistive memory small two state or high impedance state. The read voltage is 201123195 P51980116TW 32720twf.doc/n Referring to FIG. 2, FIG. 2 is a flow chart of a conventional resistive memory write verification method. First, in step S2〇1, a voltage is supplied to the gate terminal of the transistor ^0 so that the transistor 〇12 turns into an on state. Next, an initial write voltage is supplied to the electrode terminal 111 of the unipolar resistive memory cell in the step S202, and at the step S203, the initial writing of the electrode terminal m supplied to the unipolar resistive memory cell 110 is ended. Voltage. In step S204, 'the read voltage is supplied to the electrode terminal Π1 of the unipolar resistive memory cell ιι and in step S2〇5, the unipolar resistive memory cell L 卩 determines whether the unipolar resistive memory cell 110 is Entered smoothly. If the unipolar resistive cell 11G· ground single memory cell 11G transition state is successful, then, the end is reversed 'if the unipolar resistive memory cell u, the second represents the unipolar resistance 1 'provided in step S2G6 Successfully written to the electrode end (1) of the resistive memory cell (10). In step S207, the ', , , ° beam is supplied to the electrode terminal 1U of the unipolar resistive memory cell 110, and the human voltage. In the step identification, the reading voltage is supplied to the electrode terminal 1H of the unipolar, resistive suffix cell 110, and in the step, step S2 〇9, the state of the early polarity resistive memory cell 11 价 is measured to determine Whether unipolar electricity is successfully written. If the unipolar resistive memory cell ιι〇 = 'i, the writer' represents the unipolar resistive memory cell nG transition to the next, , , . The entire write verification method. Conversely, if the unipolar resistive memory cell m is not successfully written, it means that the unipolar resistive type 5 201123195 P51980116TW 32720twf.doc/n memory cell 110 fails to return, then returns to step S2〇6 and provides Another can be successfully written to the voltage different from the previous one. Next, please refer to FIG. 3 to FIG. 6. FIG. 3 to FIG. 3 are waveform diagrams of possible voltages on the electrode terminal 1 of the unipolar resistive suffix cell 110. It should be noted that the unipolar resistive memory 1 〇〇 adopts the aforementioned conventional write verification method, and FIGS. 3 to 6 assume that the unipolar resistive memory cell 〇 succeeds in providing multiple write voltages. Ground state. In Figs. 3 to 5, the initial voltage is first supplied to the electrode terminal m, after which the initial voltage is terminated, and the read voltage is supplied to the electrode terminal m. Because the unipolar resistive type lu is not turned into a ground state, 'so another voltage must be successfully written to the electrode terminal in, and after the voltage can be successfully written to the end, the read voltage is supplied again, and the terminal 111 is provided. To determine whether the unipolar resistive memory cell U1 is successful. If the unipolar resistive memory cell ln has not successfully transitioned, it can provide a successful write voltage, and the unipolar hybrid memory cell (1) successfully Until the transition. In Fig. 3, the initial write voltage has a small duty cycle, and the subsequent φ ^ ̄ ^ input voltage is gradually increased by A. In ® 4, the initial write voltage is the same as the waveform of the subsequent successfully writeable voltage. In Figure $, the private voltage of the write voltage is small, and then the voltage of the write voltage is gradually 曰 ^ ° in Figure 6 'the initial write voltage and the duty cycle is small, after the write voltage The voltage red cycle is gradually increased. = It is clear that 'the traditional erase verification green is the same as the above write verification.' The write voltage needs to be changed to the erase voltage, and it is verified whether the unipolar resistive memory cell is smooth. It is required to be changed to verify that the unipolar resistance 201123195 P51980116TW 32720twf.doc/n memory cell 110 is successfully erased. In addition, the conventional write/erase verification method is to write/erase first, and then read and verify. If the unipolar resistive memory cell 110 cannot be successfully written/erased, it is written/erased again. . Therefore, the conventional write/erase verification method wastes the setting/holding time between writing/erasing and reading in addition to the reading time. SUMMARY OF THE INVENTION An exemplary embodiment of the present invention is a verification method for a resistive memory in which a resistive memory operates in a plurality of impedance states. Continuously provide the transition signal to the resistive memory and simultaneously detect the detected current generated by the resistive memory. The amplitude of the status signal is selected, wherein the magnitude of the status signal corresponds to one of the impedance states of the resistive memory. The judgment result is generated according to the debt measurement current and the state signal, and based on the judgment result, it is judged whether the resistive memory is switched to the impedance state corresponding to the state signal. If the resistive memory switches to the impedance state corresponding to the status signal, it ends the supply of the transition signal. An exemplary embodiment of the present invention provides a verification device for verifying a resistive memory, and the verification circuit includes a signal selector, a transition signal control circuit, a voltage signal source, and a verification circuit. The signal selector is connected to the two ends of the resistive memory, the transition signal control circuit is connected to the signal selector, and the voltage signal source is connected to the transition signal control circuit, and The verification circuit is coupled to the transition signal control circuit and the signal selector. The signal selector is controlled by a set/reset enable signal for providing a transition signal to one end of the resistive type 201123195 lysvmo fW 32720twf.doc/n έ 忆 , , and receiving from the The current detected at the other end of the resistive memory. The transition signal control circuit is controlled by the determination result for providing the transition signal to the resistive memory through the signal selector. The voltage signal source is configured to provide a set voltage and a reset voltage to the transition signal control circuit as a reference for generating the transition signal. The verification circuit receives the detection current through the signal selector, and generates a determination result according to the detection current to determine whether the resistive memory successfully converts its impedance state. In order to make the above-described features of the present invention more comprehensible, the following exemplary embodiments are described in detail with reference to the accompanying drawings. [Embodiment] An exemplary embodiment of the present invention provides a verification method which can be used for resistive recording, verification of itH or wire, and the verification method can be applied to a single-stage or (four)-operated hybrid memory. In addition, an exemplary embodiment of the present invention also provides a low-impedance impedance state of the resistive memory of the resistive memory corresponding to the plurality of verification methods. The low-impedance state indicates the storage bit G, the high-impedance sorrow indicates the storage bit 1; or the YANG-like-λ 1 anti-state indicates the storage bit 丨, 胄$==! The single-order operation of the resistive memory = High-impedance state transitions to a low-impedance state, and the transition from a low-impedance state to a high-impedance bear. ^考疋 201123195 P51980116TW 32720twf.doc/n Please refer to FIG. 7, which is a circuit diagram of a resistive memory provided by an exemplary embodiment of the present invention. The resistive memory 7〇〇 can be a unipolar or bipolar element, and the resistive memory 7〇〇 includes a transistor 72〇 and a resistive memory cell 710, wherein the resistive memory cell γιο includes and the electrode end 711 The dielectric between 712, which has the structure as shown in FIG. 7, includes a titanium nitride layer (corresponding to the electrode terminal 712), a ceria layer (corresponding to the dielectric), and a corresponding electrode terminal 711. Titanium layer, titanium nitride layer and copper aluminum φ alloy layer. Further, the bipolar element means that the current of the resistive memory cell 710 can flow from the electrode terminals 711 to 7Γ2 or from the electrode terminals 712 to 711. Referring to Figures 7 and 8, Figure 8 is a flow chart of a method for verifying a resistive memory for single-stage operation provided by an exemplary embodiment of the present invention. First, in step S801, a gate voltage is supplied to the transistor 72A to control the transistor 720 to assume an on state. Next, in step S8〇2, a transition signal is supplied to the electrode terminal 7ι or 712 of the resistive memory cell 71〇, and the detection current generated by the resistive memory cell 710 is simultaneously detected. In step S803, based on the generated current generation determination result, it is determined in step S8G4 that the resistive memory cell 71 is successfully transitioned from the low impedance state to the high impedance state or from the high state. The resistance is converted to a low impedance state). If the resistive memory cell 71 is successfully transposed, then in step S8〇5, the provision of the transition signal is terminated, and the verification method is terminated. If the resistive memory cell? 1〇 Unsuccessful transition, then return to the S8G2 towel to provide a transition signal. Just described, the 3⁄41⁄2 is the write voltage or the erase voltage, and the length of the transition signal 201123195 P51980116TW 32720twf.doc/n increases with time, and the transition signal can be a square wave. Please refer to FIG. 9A and FIG. 9B' FIG. 9A. A waveform diagram of the voltage of the electrode terminal 711 and the current generated by the resistive memory cell 710, and the voltage of the electrode terminal 712 of the resistive δ cell 110 and the current generated by the resistive memory cell 71 之Waveform diagram. The voltage and current curves shown by the dashed lines in Fig. 9A correspond to the transition of the resistive memory cell 710 to the low impedance state. Please refer to the secret current curve of the solid line. When the transition state (4) is used to switch the resistive memory cell 710 from the low impedance state, the detection current of the electrode terminal 712 will gradually become larger and maintain near the IL. Therefore, by detecting the current, it can be known that the resistive memory cell 710 smoothly transitions. Thereafter, after the resistive memory cell 71 顺利 smoothly transitions, the transition signal is terminated. In Fig. 9A, the voltage and current curves shown by the solid line correspond to the voltage and current curves indicated by the broken line in the condition that the resistive type 5 sigma moon pack 710 is switched to the high impedance state, and the f-state signal smoothly makes the resistance When the memory cell 710# transitions from the high impedance state, the detection current of the electrode terminal 712 gradually becomes larger and maintains near the IH, so that the resistance memory cell 710 can be smoothly changed by detecting the current. Thereafter, after the resistive memory cell 71 〇 smoothly transitions, the transition signal is terminated. As described above, the verification method of the exemplary embodiment of the present invention is applied to the fact that the resistance of the polar element is the memory 7〇〇, and therefore, the transition signal can be supplied to the electrode terminal 711 or 712. In Fig. 9B, the voltage and current curves shown by the solid lines correspond to the state in which the resistive memory cell 7 is switched to the high impedance state. Please refer to the voltage and current curves shown by the solid line. When the transition signal 201123195 P51980116TW 32720twf.doc/n is smooth 1 and the resistive memory cell 710 is smoothly switched to the high impedance state, the detection current of the electrode terminal 712 will gradually become smaller. And maintaining it near m, so by detecting the current, it can be known that the resistive memory cell 71 〇 smoothly transitions. After the resistive memory cell 71 has successfully transitioned, the state signal is terminated. In Fig. 9B, the voltage and current curves shown by the broken lines correspond to the state in which the resistive memory cell 710 is switched to the low impedance state. Please refer to the voltage and current curves of the solid line. When the transition signal smoothly switches the resistive memory cell 710 to the low impedance state, the detection current of the electrode terminal 712 is almost constant and is maintained near the IL. By detecting the current, it can be known that the resistive memory cell 710 smoothly transitions. After the resistive memory cell 71 has successfully transitioned, the transition signal is terminated. Exemplary embodiments of the present invention further provide a verification method that is suitable for verification of writing or erasing of a multi-stage resistive memory. The impedance state of the multi-step resistive memory can have a plurality of different impedance states. Taking the fourth-order impedance state as an example, when the resistive memory stores the bit 00, the impedance state can be In a high-impedance state, when the resistive memory stores the bit 〇1, the impedance state thereof may be the second high-impedance state. When the resistive memory stores the bit 10, the impedance state may be the second low-impedance state. When the resistive memory stores the bit 11, its impedance state may be the first low impedance state. The impedance value corresponding to the first high impedance state is greater than the second high impedance state, the impedance value corresponding to the second high impedance state is greater than the second low impedance state, and the impedance corresponding to the second low impedance state The value is greater than the first low impedance state. In addition, the correspondence between the foregoing storage 11 201123195 FMyKOllbTW 32720twf.doc/n bit and the impedance state is merely an exemplary embodiment and is not intended to limit the present invention. Referring to Figures 7 and 10, Figure 10 is a flow chart of a method for verifying a resistive memory for multi-stage operation provided by an exemplary embodiment of the present invention. First, in step S851, a gate voltage is supplied to the transistor 72A to control the transistor 720 to assume an on state. Next, in step %52, the magnitude of the state signal is selected, and the magnitude of the ten-state signal is related to the impedance state to be converted by the resistive memory cell 710. Taking the fourth-order impedance state as an example, if the resistive memory cell 710 is to be converted to the first high-impedance state, the amplitude of the sigmoid § § may be TH1; if the resistive memory cell 71 is to be converted to the first To the impedance state, the amplitude of the state signal may be TH2; if the resistive memory cell 71 is to be converted to the first low impedance state, the magnitude of the state signal may be TL1; if the resistive memory cell 71 is converted to In the second low impedance state, the magnitude of the status signal may be TL2. Next, in step S853, a transition signal is supplied to the electrode terminal 711 or 712 of the resistive memory cell 710, and at the same time, the detected current generated by the resistive memory cell 710 is measured. In step S854, a determination result is generated based on the detection current and the state signal, and in step S855, it is judged based on the determination result whether or not the resistive memory cell 71 is successfully switched to the impedance state corresponding to the amplitude of the state signal. If the resistive memory cell 71 is successfully succeeded, then at step Μ%, the end of the observation signal is provided, and then the verification method is ended. If the resistive memory cell 710 has not successfully transitioned, it returns to step S853. It should be noted that the above-mentioned transition signal may be a write voltage and an erase voltage for controlling the impedance state of the resistive transistor 12 201123195 P51980116TW 32720twf.doc/n memory cell 710. In addition to this, the status signal can be a state current or a state voltage. For example, to verify whether the resistive memory cell 710 can be switched to the first high impedance state, the magnitude of the state current can be selected to be TIH1. Then, if it is determined whether the detected current is less than the state current, it can be determined whether the resistive memory cell 710 has successfully transitioned and determined whether to terminate the transition signal. In addition, the detection current in the above example may also be amplified first, and then the amplified detection current is compared with the state current to determine whether the resistive memory cell 71 is
成功轉態’以及決定是否要結束轉態信號。 再舉一例來說，要驗證電阻式記憶胞710是否能轉換 至第一低阻抗狀態，則可以選擇狀態電壓的幅值為 TVL1。接著只要放大偵測電流，將放大後的偵测電流拖 成偵測電壓，並判斷偵測電壓是否大於狀態電壓，、 確定電阻式記憶胞71〇是否成功轉態，以及決 月匕夠 束轉態信號。 、疋疋否要結 —另舉一例來說，要驗證電阻式記憶胞71〇 至第二高阻抗狀態，則可以選擇狀態電:車 T'H2 ’其中所述狀態電壓用以控制反向器 =只要放大㉝測電流，將放大後的侧 換奪 電；，並將所述偵測電壓送入所述反向器，便，^ 所輸出的判斷結果判斷電阻式記憶胞7 悲’以及決定是否要結束轉態信號。 成; s #又舉一例來說，要驗證電阻式記憶胞710 θ a 二低阻抗狀態，則可以選擇狀態電流的巾^為月Μ 13 201123195 rjiy〇u,1〇TW 32720twf.doc/n 接著只要放大偵測電流，比較放大後的偵測電流與狀態電 流，以及將所述比較結果送至反向器，便能夠根據所述反 向器所輸出的判斷結果判斷電阻式記憶胞71〇是否成功轉 態’以及決定是否要結束轉態信號。除此之外，上述反向 器亦可以使用電壓比較器來取代，電壓比較器接收電流比 較器所輸出的比較結果並產生判斷結果。如此，便能根據 電壓比較器所輸出的判斷結果判斷電阻式記憶胞71〇是否 成功轉態，以及決定是否要結束轉態信號。 前述轉態信號的長度隨時間增加，且轉態信號可為方 波。請參照圖11A與11B，圖11A是電阻式記憶胞71〇之 電極端711的電壓與電阻式記憶胞71〇所產生的電流之波 形圖，圖11B是電晶體720之源極端的電壓與電阻式記憶 胞710所產生的電流之波形圖。 在圖11A中’電壓曲線VC101與電流曲線ici〇i是 對應於電阻式記憶胞710轉換至第一低阻抗狀態的狀況， 電壓曲線VC102與電流曲線iCl〇2是對應於電阻式記憶胞 710轉換至第二低阻抗狀態的狀況，電壓曲線vcl〇3與電 流曲線IC103是對應於電阻式記憶胞71〇轉換至第二高阻 抗狀態的狀況，電壓曲線VC104與電流曲線IC104是對應 於電阻式記憶胞710轉換至第—高阻抗狀態的狀況。 當轉態信號順利地使電阻式記憶胞7丨〇從轉換至第一 低阻抗狀態時，電極端712的偵測電流會逐漸變大，並維 持在IL1附近，因此藉由偵測電流便可以得知電阻式記憶 胞710順利地轉態。之後，在電阻式記憶胞71〇順利地轉 14 201123195 JKMy»uil6TW 32720twf.doc/n 態後’便結束所述的轉態信號。當轉態信號順利地使電阻 式記憶胞710從轉換至第二低阻抗狀態時，電極端712的 偵測電流會逐漸變大，並維持在IL2附近，因此藉由偵測 電流便可以得知電阻式記憶胞71 〇順利地轉態。之後，在 電阻式記憶胞710順利地轉態後，便結束所述的轉態信號。 當轉態信號順利地使電阻式記憶胞71 〇從轉換至第二 高阻抗狀態時’電極端712的偵測電流會逐漸變大，並維 • 持在1H2附近，因此藉由偵測電流便可以得知電阻式記憶 胞710順利地轉態。之後’在電阻式記憶胞71〇順利地轉 態後’便結束所述的轉態信號。當轉態信號順利地使電阻 式記憶胞710從轉換至第一高阻抗狀態時’電極端712的 偵測電流會逐漸變大，並維持在〗]^附近，因此藉由偵測 電流便可以得知電阻式記憶胞71〇順利地轉態。之後，在 電阻式記憶胞710順利地轉態後，便結束所述的轉態信號。 如同前面所述’本發明之示範實施例的驗證方法適用 於雙極性元件的電阻是記憶體700，因此，轉態信號可以 被k供給電極端711或712。在圖11B中，電壓曲線VCl U 與電流曲線IC111是對應於電阻式記憶胞710轉換至第一 低阻抗狀態的狀況’電壓曲線VC112與電流曲線IC112是 對應於電阻式記憶胞71〇轉換至第二低阻抗狀態的狀況， 電壓曲線VC113與電流曲線ICU3是對應於電阻式記憶胞 710轉換至第二尚阻抗狀態的狀況，電壓曲線VC114與電 流曲線IC114是對應於電阻式記憶胞71〇轉換至第一高阻 抗狀態的狀況。 15 201123195 F5198ϋ 116 TW 32720twf.doc/n 當轉態信號順利地使電阻式記憶胞710從轉換至第— 低阻抗狀態時，電極端712的偵測電流會逐漸變小，並維 持在IL1附近，因此藉由偵測電流便可以得知電阻式記憮 胞710順利地轉態。之後，在電阻式記憶胞71〇順利地^ 態後，便結束所述的轉態信號。當轉態信號順利地使電限 式s己憶胞710從轉換至第二低阻抗狀態時’電極端Μ]的 偵測電流會逐漸變小’並維持在IL2附近，因此藉由偵測 電流便可以得知電阻式記憶胞710順利地轉態。之後，在 電阻式記憶胞710順利地轉態後，便結束所述的轉態信號。 當轉態信號順利地使電阻式記憶胞710從轉換至第二 高阻抗狀態時，電極端712的偵測電流會逐漸變小，並維 持在IH2附近，因此藉由偵測電流便可以得知電阻式記憶 胞710順利地轉態。之後，在電阻式記憶胞71〇順利地轉 態後，便結束所述的轉態信號。當轉態信號順利地使電阻 式記憶胞710從轉換至第一高阻抗狀態時，電極端712的 偵測電流會逐漸變小，並維持在IH1附近，因此藉由偵測 電流便可以得知電阻式記憶胞71〇順利地轉態。之後，在 電阻式記憶胞710順利地轉態後，便結束所述的轉態信號。 接著，請參照圖12，圖12是本發明之示範實施例所 提供的電阻式記憶體之驗證裝置之電路圖。電阻式記憶體 7〇〇連接於驗證裝置200，驗證裝置200包括信號選擇器 210、轉態信號控制電路22〇、電壓信號源23〇與驗證電路 240。電壓信號源23〇連接於轉態信號控制電路22〇，轉態 4號控制電路220連接於信號選擇器21〇,信號選擇器21〇 16 201123195 P51980116TW 32720twf.doc/n 連接於電極端711與電晶體72Q的源極端，驗證電路_ 連接於轉態信號控制電路22G與信號選擇器21〇。 在此示範實施例中，偉號選擇器21()包 ;二其中/工器211的第一輪入端與第二輸入端分 接於驗24〇 . Γ ❸源極端，其輸出端則連 接於驗也電路，多工器212的第—輸出端與第二輸 Τ刀別連接於，極端711與電晶體72〇的源極端，其輸入 端則連接於轉態信號控制電路220。 電壓信顏230㈣產生提供產生㈣㈣的電麗， 電壓或抹除電^，其中寫入電壓與抹 式記憶胞711之阻抗狀態發生改變 的，壓㈣。用以產生寫人電壓與抹除電壓之可以曰 設定電壓與重設電壓。轉態信號控制電路2 = 定電壓與重設電壓的週期，並據此提供寫 =其卜給多工器212。多工器212根據設 月唬決疋要提供寫入電壓給電極端711，或者 除f壓給電晶體720的源極端。多工器21U艮據設定/重設 致能信號選擇將來自於電極端71!或電晶體72〇的源極ς 其中之一的電流作為偵測電流，送至驗證電路2奶。 驗證電路240會根據偵測電流來判斷電阻式記憶胞 71〇是否成功地㈣，若電阻式記憶胞71G成功地轉^ 則會通知轉態信號控制電路22〇停止提供轉態信號。^詳 細地說，驗證電路240接收狀態信號，驗證電^二〇是根 據狀態信號與偵測電流來產生判斷結果，並且根據判 17 201123195 r) lyoui i〇 rW 32720twf.doc/n 果來判斷電阻式記憶胞710成功地轉態。其中對於單階 作的電阻式記憶體而言，狀態信號的幅值可以是—個^定 值，另外，對於多階操作的電阻式記憶體而言，狀態信= 的幅值是根據所要驗證之電阻式記憶胞7丨〇的阻抗^ ^ = 選擇。狀態信號會根據驗證電路240之實施方式，而g可 能是狀態電壓或狀態電流。 請參照圖13A與圖12，圖13A是本發明之示範實施 例所提供之驗證電路240的電路圖。在圖13A中，驗證電 路240包括電流放大器24U、電流電壓轉換器2412、電壓 比較器2413與電壓源2414,其中電流放大器2411連接於 電流電壓轉換器2412，電流電壓轉換器2412連接於電壓 比較器2413的第一輸入端，電壓源2414連接於電壓比較 器2413的第二輸入端，電壓比較器2413的輸出端連接於 轉態信號控制電路220。 電流放大器2411用以接收偵測電流，並放大偵測電 流。電流電壓轉換器2 412用以將放大後的偵測電流轉換為 偵測電壓。電壓源2414所提供的狀態電壓之幅值為Vn， 且電壓源2414所提供的狀態電壓之幅值可以根據所要驗 證之電阻式記憶胞710的阻抗狀態來選擇。電壓比較器 2413比較偵測電壓與電壓源2414所提供的狀態電壓，以 產生判斷結杲。所述判斷結果帶有電阻式記憶胞71〇是否 成功地轉態之訊息，且所述判斷結果會被送至轉態信號控 制電路220。轉態信號控制電路220會根據所述判斷結果 來決定是否提供轉態信號給電阻式記憶體7〇〇。 18 201123195 FMy8UH6TW 32720twf.doc/n 請參照圖12與13A，以上述操作於四階的電阻式記 憶體700來說明’若要驗證電阻式記憶胞710是否能夠成 功地轉換至第一高阻抗狀態，且設定/重設致能信號讓解多 工器211輸出寫入電壓給電極端711，則設定/重設致能信 號會讓多工器212接收來自於電晶體720源極端的偵測電 流。接著，電流放大器2411用以接收偵測電流，並放大偵 測電流。電流電壓轉換器2412用以將放大後的偵測電流轉 籲換為偵測電壓。電壓源2414所提供的狀態電壓之幅值為Successfully transitioned and decided whether to end the transition signal. As another example, to verify whether the resistive memory cell 710 can be switched to the first low impedance state, the magnitude of the state voltage can be selected to be TVL1. Then, as long as the detection current is amplified, the amplified detection current is dragged into the detection voltage, and it is determined whether the detection voltage is greater than the state voltage, whether the resistive memory cell 71〇 is successfully changed, and the moon is sufficient to turn. State signal. , 疋疋 No to be concluded - another example, to verify the resistive memory cell 71 〇 to the second high-impedance state, you can select the state of electricity: car T'H2 'where the state voltage is used to control the inverter = As long as the current is amplified 33, the amplified side is replaced with power; and the detected voltage is sent to the inverter, and the judgment result of the output judges the resistance memory cell 7 and determines Whether to end the transition signal. For example, to verify the resistance of the memory cell 710 θ a two low impedance state, you can select the state current of the towel ^ for the month 13 201123195 rjiy〇u, 1〇TW 32720twf.doc/n As long as the detection current is amplified, the amplified detection current and the state current are compared, and the comparison result is sent to the inverter, the resistance memory cell 71 can be judged according to the judgment result output by the inverter. A successful transition 'and decide whether to end the transition signal. In addition, the above inverter can also be replaced by a voltage comparator that receives the comparison result output by the current comparator and produces a judgment result. In this way, it is possible to determine whether the resistive memory cell 71 is successfully transitioned based on the judgment result output by the voltage comparator, and to determine whether or not to terminate the transition signal. The length of the aforementioned transition signal increases with time, and the transition signal can be a square wave. Referring to FIGS. 11A and 11B, FIG. 11A is a waveform diagram of the voltage of the electrode terminal 711 of the resistive memory cell 71 and the current generated by the resistive memory cell 71, and FIG. 11B is the voltage and resistance of the source terminal of the transistor 720. A waveform diagram of the current generated by the memory cell 710. In FIG. 11A, the voltage curve VC101 and the current curve ici〇i correspond to a condition in which the resistive memory cell 710 is switched to the first low impedance state, and the voltage curve VC102 and the current curve iCl〇2 correspond to the resistive memory cell 710 conversion. In the second low impedance state, the voltage curve vcl〇3 and the current curve IC103 correspond to the state in which the resistive memory cell 71 is switched to the second high impedance state, and the voltage curve VC104 and the current curve IC104 correspond to the resistive memory. The cell 710 transitions to the state of the first high impedance state. When the transition signal smoothly switches the resistive memory cell 7丨〇 to the first low impedance state, the detection current of the electrode terminal 712 gradually becomes larger and maintains near the IL1, so that the current can be detected by detecting the current. It is known that the resistive memory cell 710 is smoothly transitioned. After that, the resistive memory cell 71 〇 smoothly turns 14 201123195 JKMy»uil6TW 32720twf.doc/n state to end the transition signal. When the transition signal smoothly switches the resistive memory cell 710 from the second low impedance state, the detection current of the electrode terminal 712 gradually increases and remains near the IL2, so that the current can be detected by detecting the current. The resistive memory cell 71 〇 smoothly transitions. Thereafter, after the resistive memory cell 710 is smoothly transitioned, the transition signal is terminated. When the transition signal smoothly switches the resistive memory cell 71 〇 to the second high-impedance state, the detection current of the electrode terminal 712 gradually becomes larger, and the dimension is held near 1H2, so by detecting the current It can be known that the resistive memory cell 710 smoothly transitions. Then, after the resistive memory cell 71 has successfully transitioned, the transition signal is terminated. When the transition signal smoothly transitions the resistive memory cell 710 from the first high-impedance state, the detection current of the electrode terminal 712 gradually increases and remains near the vicinity of the gate, so that the current can be detected by detecting the current. It is known that the resistive memory cell 71 〇 smoothly transitions. Thereafter, after the resistive memory cell 710 is smoothly transitioned, the transition signal is terminated. As described above, the verification method of the exemplary embodiment of the present invention is applied to the memory of the bipolar element is the memory 700, and therefore, the transition signal can be supplied to the electrode terminal 711 or 712 by k. In FIG. 11B, the voltage curve VCl U and the current curve IC 111 correspond to the condition in which the resistive memory cell 710 is switched to the first low impedance state. The voltage curve VC112 and the current curve IC 112 correspond to the resistive memory cell 71. In the case of the two low-impedance states, the voltage curve VC113 and the current curve ICU3 correspond to the state in which the resistive memory cell 710 is switched to the second still-impedance state, and the voltage curve VC114 and the current curve IC114 are corresponding to the resistive memory cell 71〇 to The condition of the first high impedance state. 15 201123195 F5198ϋ 116 TW 32720twf.doc/n When the transition signal smoothly switches the resistive memory cell 710 from the first to the low impedance state, the detection current of the electrode terminal 712 gradually becomes smaller and remains near IL1. Therefore, by detecting the current, it can be known that the resistive recording cell 710 smoothly transitions. Thereafter, after the resistive memory cell 71 is successfully turned on, the transition signal is terminated. When the transition signal smoothly changes the electrical limit type MSC 710 from the second low impedance state, the detection current of the 'electrode terminal 会' will gradually decrease and maintain near IL2, thus detecting current It can be known that the resistive memory cell 710 smoothly transitions. Thereafter, after the resistive memory cell 710 is smoothly transitioned, the transition signal is terminated. When the transition signal smoothly switches the resistive memory cell 710 from the second high impedance state, the detection current of the electrode terminal 712 gradually decreases and remains near IH2, so that the current can be detected by detecting the current. The resistive memory cell 710 smoothly transitions. Thereafter, after the resistive memory cell 71 is smoothly turned, the transition signal is terminated. When the transition signal smoothly switches the resistive memory cell 710 from the first high impedance state, the detection current of the electrode terminal 712 gradually decreases and remains near IH1, so that it can be known by detecting the current. The resistive memory cell 71〇 smoothly transitions. Thereafter, after the resistive memory cell 710 is smoothly transitioned, the transition signal is terminated. Next, please refer to FIG. 12. FIG. 12 is a circuit diagram of a verification device for a resistive memory according to an exemplary embodiment of the present invention. The resistive memory 7 is connected to the verification device 200. The verification device 200 includes a signal selector 210, a transition signal control circuit 22, a voltage signal source 23A, and a verification circuit 240. The voltage signal source 23〇 is connected to the transition signal control circuit 22〇, the transition state No. 4 control circuit 220 is connected to the signal selector 21〇, and the signal selector 21〇16 201123195 P51980116TW 32720twf.doc/n is connected to the electrode terminal 711 and the electric The source terminal of the crystal 72Q, the verification circuit _ is connected to the transition signal control circuit 22G and the signal selector 21A. In this exemplary embodiment, the horn selector 21 () package; the first wheel end and the second input end of the 211 are connected to the 〇 24 〇. ❸ 极端 source extreme, the output is connected In the circuit, the first output terminal of the multiplexer 212 is connected to the second source switch, the terminal end of the terminal 711 and the transistor 72A, and the input terminal thereof is connected to the transition signal control circuit 220. The voltage signal 230 (4) is generated to provide (4) (4) of the voltage, voltage or erase voltage, wherein the write voltage and the impedance state of the wiped memory cell 711 are changed, and the voltage is (4). It can be used to generate the write voltage and erase voltage to set the voltage and reset voltage. The transition signal control circuit 2 = the period of the constant voltage and the reset voltage, and accordingly provides a write to the multiplexer 212. The multiplexer 212 supplies a write voltage to the electrode terminal 711 in accordance with the designation, or a bias voltage to the source terminal of the transistor 720. The multiplexer 21U selects/resets the enable signal to select the current from one of the source terminal 71! or the source ς of the transistor 72A as the detection current, and sends it to the verification circuit 2 milk. The verification circuit 240 determines whether the resistive memory cell 71 is successfully (4) according to the detected current. If the resistive memory cell 71G successfully rotates, it notifies the transition signal control circuit 22 to stop providing the transition signal. In detail, the verification circuit 240 receives the status signal, and the verification circuit generates the determination result according to the status signal and the detection current, and determines the resistance according to the judgment of 201123195 r) lyoui i〇rW 32720twf.doc/n. The memory cell 710 successfully transitions. For a single-stage resistive memory, the amplitude of the state signal can be a constant value. In addition, for a resistive memory of multi-step operation, the magnitude of the state signal = is based on the required verification. The impedance of the resistive memory cell 7丨〇 ^ ^ = selection. The status signal will be based on the implementation of verification circuit 240, and g may be a state voltage or a state current. Referring to Figures 13A and 12, Figure 13A is a circuit diagram of a verification circuit 240 provided by an exemplary embodiment of the present invention. In FIG. 13A, the verification circuit 240 includes a current amplifier 24U, a current voltage converter 2412, a voltage comparator 2413 and a voltage source 2414, wherein the current amplifier 2411 is connected to the current voltage converter 2412, and the current voltage converter 2412 is connected to the voltage comparator. At a first input of 2413, a voltage source 2414 is coupled to a second input of a voltage comparator 2413, and an output of the voltage comparator 2413 is coupled to a transition signal control circuit 220. The current amplifier 2411 is configured to receive the detected current and amplify the detected current. The current-to-voltage converter 2 412 is configured to convert the amplified detection current into a detection voltage. The magnitude of the state voltage provided by voltage source 2414 is Vn, and the magnitude of the state voltage provided by voltage source 2414 can be selected based on the impedance state of resistive memory cell 710 to be verified. Voltage comparator 2413 compares the sense voltage with the state voltage provided by voltage source 2414 to produce a decision threshold. The result of the determination is accompanied by a message indicating whether the resistive memory cell 71 is successfully transitioned, and the result of the determination is sent to the transition signal control circuit 220. The transition signal control circuit 220 determines whether to provide a transition signal to the resistive memory 7 according to the determination result. 18 201123195 FMy8UH6TW 32720twf.doc/n Referring to Figures 12 and 13A, the above operation is performed on the fourth-order resistive memory 700 to indicate "if the resistive memory cell 710 can be successfully converted to the first high-impedance state," And the set/reset enable signal causes the demultiplexer 211 to output the write voltage to the electrode terminal 711, and the set/reset enable signal causes the multiplexer 212 to receive the detected current from the source terminal of the transistor 720. Next, the current amplifier 2411 is configured to receive the detected current and amplify the detected current. The current-to-voltage converter 2412 is configured to convert the amplified detection current to a detection voltage. The magnitude of the state voltage provided by voltage source 2414
Vn被選擇為TVH1，電壓比較器2413比較偵測電壓與電 壓源2414所提供的狀態電壓。若偵測電壓大於狀態電壓， 則電壓比較器2413所產生的比較結果為真，亦即電阻式記 憶胞710是成功地轉換至第一高阻抗狀態，且比較結果會 指示轉態信號控制電路220結束提供轉態信號給電阻式記 憶體700。 若要驗證電阻式記憶胞710是否能夠成功地轉換至第 • —高阻抗狀態’且設定/重設致能信號讓解多工器211輸出 抹除電壓給電晶體720的源極端，則設定/重設致能信號會 讓多工器212接收來自於電極端711的偵測電流。接著， 電流放大器2411用以接收偵測電流，並放大偵測電流。電 流電壓轉換器2412用以將放大後的偵測電流轉換為偵測 電壓。電壓源2414所提供的狀態電壓之幅值為Vn被選擇 為TVH1 ’電壓比較器2413比較偵測電壓與電壓源2414 所提供的狀態電壓。若偵測電壓小於狀態電壓，則電壓比 車乂器2413所產生的比較結果為真，亦即電阻式記憶胞71〇 19 201123195 rji^ovnoTW 32720twf.doc/n 疋成功地轉換至第一高阻抗狀態，且比較結果會指示轉態 信號控制電路220結束提供轉態信號給電阻式記憶體7〇〇。 請參照圖13B，圖13B是本發明之另一示範實施例所 k供之驗電路240的電路圖。在圖13B中，驗證電路240 包括電流放大器2421、電流電壓轉換器2422與反向器 2423’其中電流放大器2421連接於電流電壓轉換器2422, 電流電壓轉換器2422連接於反向器2423的輸入端，反向 器2423的輸出端連接於轉態信號控制電路220。 電流放大器2421用以接收偵測電流，並放大偵測電 流。電流電壓轉換器2422用以將放大後的偵測電流與一基 準電流相比較，此基準電流，可根據不同阻態，進行調整， 經比較後轉換為一輸出電壓。反向器2423用以根據所接收 到的輸出電壓產生判斷結果’其中所述判斷結果帶有電阻 式記憶胞710是否成功地轉態之訊息，且所述判斷結果會 被送至轉態信號控制電路220。轉態信號控制電路220會 根據所述判斷結果來決定是否提供轉態信號給電阻式記憶 體700。要說明的是，反向器2423更接收狀態電壓，狀態 電壓可以用來控制反向器2423的轉換曲線，且所述狀態電 壓之幅值可以根據所要驗證之電阻式記憶胞71〇的阻抗狀 態來選擇。 請參照圖13C，圖13C是本發明之示範實施例所提供 之驗證電路240的電路圖。在圖13C中，驗證電路240包 括電流放大器2431、電流比較器2432、電壓比較器2433 與電壓源2434，其中電流放大器2421連接於電流比較器 201123195 P519X0116TW 32720twf.doc/n 2432,電壓比較器2433的第一輸入端與第二輸入端連接於 電流比較器2432與電壓源2434,電壓比較器2433的輸出 端連接於轉態信號控制電路220。 電流放大器2431用以接收偵測電流，並放大偵測電 流。電流比較器2432用以比較放大後的偵測電流轉換與狀 態電流，以產生偵測電壓。電壓源2434所提供的狀態電壓 之幅值為Vn，且電壓源2434所提供的狀態電壓之幅值可 以根據所要驗證之電阻式記憶胞710的阻抗狀態來選擇。 電壓比較器2433比較偵測電壓與電壓源2434所提供的狀 態電壓，以產生判斷結果。所述判斷結果帶有電阻式記憶 胞710是否成功地轉態之訊息，且所述判斷結果會被送至 轉態信號控制電路220。轉態信號控制電路220會根據所 述判斷結果來決定是否提供轉態信號給電阻式記憶體 700。 請參照圖13D，圖13D是本發明之示範實施例所提供 之驗證電路240的電路圖。在圖13D中，驗證電路240包 括電流放大器2441、電流比較器2442與反向器2443，其 中電流放大器2441連接於電流比較器2442，電流比較器 2442連接於反向器2443的輸入端，反向器2443的輸出端 連接於轉態信號控制電路220。 電流放大器2441用以接收偵測電流，並放大偵測電 流。電流比較器2442用以比較放大後的偵測電流與狀態電 流’並輸出偵測電壓。反向器2443用以根據所接收到的價 測電壓產生判斷結果，其中所述判斷結果帶有電阻式記憶 21 201123195 ^lysunorw 32720twf.d〇c/n 胞=否成功地轉態之訊息，且所述判斷結果會被送至 轉悲彳s唬控制電路220。轉態信號控制電路22〇會根據所 述判斷結果來決定是否提供轉態信號給 電阻式記憶體 兀〇。要說明的是，反向器2443更接收狀態電壓，狀態電 壓可以用來控制反向器2443的轉換曲線，且所述狀態電壓 之幅值可以根據所要驗證之電阻式記憶胞71〇的阻抗狀態 來選擇。 接著，請參照圖14A，圖14A是圖13Λ之驗證電路 240之細部電路圖。圖14 a更包括了多工器211的細部電 路圖’多工器211是由反向器INV與傳輸閘PG1、PG2所 組成’其中重設致能信號RESET_EN經過反向器INV成 為設定致能信號，信號RESET_In與SET__In分別是來自於 多工器212之第一輸出端與第二輸出端的信號。傳輸閘 PG1與PG2的控制端分別受控於重設致能信號resET_EN 與設定致能信號，以藉此決定讓傳輸閘PG1輸出信號 RESET_In，或者讓傳輸閘PG2輸出信號SET_In。 電流放大器2411是由一個電晶體Ml與M2所組成的 電流鏡構成，電晶體Ml與M2的尺寸會有呈現一個比例， 以藉此將偵測電流放大。電流電壓轉換器2412包括了由電 晶體]V[3與M4所組成的電流鏡以及一個將電流信號II轉 換為電壓信號的電阻R1，以據此輸出偵測電壓Vp。電壓 比較器2413包括了由電晶體M6〜M9構成的差動放大對 以及電晶體M10〜M15所構成多個反向單元。差動放大對 根據偵測電壓Vp與電壓源2414所提供的狀態電壓Vn之 22 201123195 P51980116TW 32720twf.d〇c/n 大小決定輸出的電壓值為正值或負值。電晶體M10〜Ml3 構成的兩個串聯的反向單元形成了一個緩衝器，並用以根 據差動放大對所輸出的電壓值來輸出比較結果，電晶體 M14、M15所構成的反向單元則用以根據差動放大對所輪 出的電壓值來輸出反向的比較結果。要說明的是，電壓源 2414所提供的狀態電壓Vn之幅值可以根據所要驗證之電 阻式記憶胞710的阻抗狀態來選擇，換言之，可以藉由調 _ 整狀態電壓Vn之幅值來達到多階操作。 接著，請參照圖14B，圖14B是圖13B之驗證電路 240之細部電路圖。圖14B更包括了多工器211的細部電 路圖，多工器211的細部電路如同前面所述，故不在此重 新贅述。電流放大器2421與電流放大器2411相同，故不 在此贅述，同樣地’電流電壓轉換器2422與電流電壓轉換 器2412相同’亦不再贅述。反向器2423包括了電晶體 M10〜]M13所構成的兩個反向單元，電晶體M1〇與Mu 所組成的反向單元用以根據電壓Vp的電壓值決定輸出的 • 判斷結果，電晶體M10〜M13所組成的兩個串聯之反向單 元則用以根據電壓Vp的電壓值決定輪出反向的判斷結果。Vn is selected as TVH1, and voltage comparator 2413 compares the detected voltage with the state voltage provided by voltage source 2414. If the detected voltage is greater than the state voltage, the comparison result generated by the voltage comparator 2413 is true, that is, the resistive memory cell 710 is successfully switched to the first high impedance state, and the comparison result indicates the transition signal control circuit 220. End of providing the transition signal to the resistive memory 700. To verify whether the resistive memory cell 710 can successfully switch to the -high impedance state and set/reset the enable signal to cause the demultiplexer 211 to output the erase voltage to the source terminal of the transistor 720, then set/weight Setting the enable signal causes the multiplexer 212 to receive the detected current from the electrode terminal 711. Then, the current amplifier 2411 is configured to receive the detection current and amplify the detection current. The current voltage converter 2412 is configured to convert the amplified detection current into a detection voltage. The magnitude of the state voltage provided by voltage source 2414 is selected as TVH1' voltage comparator 2413 compares the sense voltage with the state voltage provided by voltage source 2414. If the detected voltage is less than the state voltage, the comparison result of the voltage is higher than that of the brake device 2413, that is, the resistive memory cell 71〇19 201123195 rji^ovnoTW 32720twf.doc/n 疋 successfully converted to the first high impedance The state, and the result of the comparison, instructs the transition signal control circuit 220 to end providing the transition signal to the resistive memory 7〇〇. Referring to Figure 13B, Figure 13B is a circuit diagram of a circuit 240 for verification of another exemplary embodiment of the present invention. In FIG. 13B, the verification circuit 240 includes a current amplifier 2421, a current voltage converter 2422, and an inverter 2423'. The current amplifier 2421 is connected to the current voltage converter 2422, and the current voltage converter 2422 is connected to the input terminal of the inverter 2423. The output of the inverter 2423 is coupled to the transition signal control circuit 220. The current amplifier 2421 is configured to receive the detected current and amplify the detected current. The current-to-voltage converter 2422 is configured to compare the amplified detection current with a reference current, which can be adjusted according to different resistance states, and converted into an output voltage after comparison. The inverter 2423 is configured to generate a determination result according to the received output voltage, wherein the determination result has a message that the resistive memory cell 710 is successfully transitioned, and the determination result is sent to the transition signal control. Circuit 220. The transition signal control circuit 220 determines whether to provide a transition signal to the resistive memory 700 based on the result of the determination. It should be noted that the inverter 2423 further receives the state voltage, and the state voltage can be used to control the conversion curve of the inverter 2423, and the magnitude of the state voltage can be determined according to the impedance state of the resistive memory cell 71〇 to be verified. Come choose. Referring to Figure 13C, Figure 13C is a circuit diagram of a verification circuit 240 provided by an exemplary embodiment of the present invention. In FIG. 13C, the verification circuit 240 includes a current amplifier 2431, a current comparator 2432, a voltage comparator 2433 and a voltage source 2434, wherein the current amplifier 2421 is connected to the current comparator 201123195 P519X0116TW 32720twf.doc/n 2432, the voltage comparator 2433 The first input terminal and the second input terminal are connected to the current comparator 2432 and the voltage source 2434, and the output terminal of the voltage comparator 2433 is connected to the transition signal control circuit 220. The current amplifier 2431 is configured to receive the detected current and amplify the detected current. The current comparator 2432 is configured to compare the amplified detected current transition and the state current to generate a detected voltage. The magnitude of the state voltage provided by voltage source 2434 is Vn, and the magnitude of the state voltage provided by voltage source 2434 can be selected based on the impedance state of resistive memory cell 710 to be verified. The voltage comparator 2433 compares the detected voltage with the state voltage supplied by the voltage source 2434 to produce a determination result. The result of the determination is accompanied by a message indicating whether the resistive memory cell 710 has successfully transitioned, and the result of the determination is sent to the transition signal control circuit 220. The transition signal control circuit 220 determines whether to provide a transition signal to the resistive memory 700 based on the result of the determination. Referring to Figure 13D, Figure 13D is a circuit diagram of a verification circuit 240 provided by an exemplary embodiment of the present invention. In FIG. 13D, the verification circuit 240 includes a current amplifier 2441, a current comparator 2442, and an inverter 2443, wherein the current amplifier 2441 is connected to the current comparator 2442, and the current comparator 2442 is connected to the input of the inverter 2443, inverting. The output of the device 2443 is coupled to the transition signal control circuit 220. The current amplifier 2441 is configured to receive the detected current and amplify the detected current. The current comparator 2442 is for comparing the amplified detection current with the state current ' and outputting the detection voltage. The inverter 2443 is configured to generate a determination result according to the received price measurement voltage, wherein the determination result has a resistive memory 21 201123195 ^lysunorw 32720twf.d〇c/n cell=no successful transition state message, and The result of the determination is sent to the control circuit 220. The transition signal control circuit 22 determines whether to provide a transition signal to the resistive memory based on the result of the determination. It should be noted that the inverter 2443 further receives the state voltage, and the state voltage can be used to control the conversion curve of the inverter 2443, and the magnitude of the state voltage can be determined according to the impedance state of the resistive memory cell 71〇 to be verified. Come choose. Next, please refer to FIG. 14A, which is a detailed circuit diagram of the verification circuit 240 of FIG. 14a further includes a detailed circuit diagram of the multiplexer 211. The multiplexer 211 is composed of an inverter INV and transmission gates PG1, PG2. The reset enable signal RESET_EN is set to an enable signal through the inverter INV. The signals RESET_In and SET__In are signals from the first output and the second output of the multiplexer 212, respectively. The control terminals of the transfer gates PG1 and PG2 are respectively controlled by the reset enable signal resET_EN and the set enable signal, thereby determining whether the transfer gate PG1 outputs the signal RESET_In or the transfer gate PG2 outputs the signal SET_In. The current amplifier 2411 is constituted by a current mirror composed of a transistor M1 and M2, and the sizes of the transistors M1 and M2 are proportional to thereby amplifying the detection current. The current-to-voltage converter 2412 includes a current mirror composed of a transistor V[3 and M4 and a resistor R1 that converts the current signal II into a voltage signal to thereby output a detection voltage Vp. The voltage comparator 2413 includes a differential amplifying pair composed of transistors M6 to M9 and a plurality of inverting units formed by the transistors M10 to M15. The differential amplification pair determines the output voltage value as a positive value or a negative value according to the detection voltage Vp and the state voltage Vn provided by the voltage source 2414. 2011 23195 P51980116TW 32720twf.d〇c/n. The two series of reverse units formed by the transistors M10 to Ml3 form a buffer for outputting the comparison result according to the differential amplification of the output voltage value, and the reverse unit formed by the transistors M14 and M15 is used. The reverse comparison result is outputted according to the voltage value rotated by the differential amplification pair. It should be noted that the magnitude of the state voltage Vn provided by the voltage source 2414 can be selected according to the impedance state of the resistive memory cell 710 to be verified, in other words, by adjusting the amplitude of the state voltage Vn. Order operation. Next, please refer to FIG. 14B, which is a detailed circuit diagram of the verification circuit 240 of FIG. 13B. Fig. 14B further includes a detailed circuit diagram of the multiplexer 211, and the detailed circuit of the multiplexer 211 is as described above, and therefore will not be repeated here. The current amplifier 2421 is the same as the current amplifier 2411, and therefore will not be described herein. Similarly, the 'current-to-voltage converter 2422 is the same as the current-to-voltage converter 2412' and will not be described again. The inverter 2423 includes two inverting units formed by the transistors M10 to M13, and the inverting unit composed of the transistors M1 and Mu is used to determine the output of the voltage according to the voltage value of the voltage Vp. The two series of reverse units composed of M10 to M13 are used to determine the determination result of the rotation in the reverse direction according to the voltage value of the voltage Vp.
接著，請參照圖14C，圖14C是圖13B之驗證電路 240之另一細部電路圖。圖14 C更包括了多工器211的細 部電路圖，多工器211的細部電路如同前面所述，故不在 此重新贅述。電流放大器2421與電流放大器24Π相同， 故不在此贅述，另外，反向器2423的詳細電路已經於前面 介紹過’亦不再贅述。圖14C與14B不同的是，圖！4C 23 201123195 P51980116TW 32720twf.doc/n 的電流電壓轉換器2422實際上為一個由電流比較器所形 成的電流電壓轉換器。電壓VCON可以控制電晶體M5的 電流’並產生一基準電流12，電流信號II會與電流信號 12比較，而產生偵測電壓Vp。除此之外，圖14C本身亦 可以是圖13D之驗證電路的詳細電路圖，換言之，圖14C 的電流放大電路2421為圖13D的電流放大器2441的詳細 電路’圖14C的電流比較器為圖13D的電流放大器2442 的詳細電路’圖14C的反向器2423為圖13D的反向器2443 的詳細電路。 接著’請參照圖14D，圖14D是圖13C之驗證電路 240之細部電路圖。圖14]B更包括了多工器211的細部電 路圖，多工态2Π的細部電路如同前面所述，故不在此重 新贅述。電流放大器2421與電流放大器2411相同，電流 比較器2432如同前面所述’電壓比較器2433與電壓比較 器2413相同，故皆不再贅述。 綜上所述’本發明之示範實施例所提供的驗證方法與 驗證電路在驗證電阻式記憶體時，其驗證時間可以較傳統 的驗證方法少了寫入與讀取之間的設定/保持時間與讀取 時間除此之外，驗證方法與驗證電路可以用於驗證操作 於多階或單階的電阻式記憶體，且可以針對雙極性 性的電阻式記憶體進行驗證。 —平令 雖然本發明已以示範實施例揭露如上，然並並 之=所屬技術領域中具有通常知識者，在不 本發月之精砷和範圍内，當可作些許之更動與潤飾， 24 201123195 P51980116TW 32720twf.doc/n =發明之鋪範圍當視後附之申請專利範圍所界定者為 【圖式簡單說明】 圖1是單極性電阻式記憶體的電路圖。 圖2是傳統電阻式記題寫人驗證方法的流程圖。 圖3〜圖6是單極性電阻式記憶胞u 上可能之電壓的波糊。 电極^ 111 路圖圖7是本發明之示範例子所提供的電阻式記憶體之電 圖8是本發明之示範例子所提供的用於單階 阻式記憶體之驗證方法之流程圖。 ’、 圖9A是電阻式記憶胞71〇之電極端711的 阻式記憶胞710所產生的電流之波形圖。 ” 圖9B是電晶體720七原極端的電壓與電阻 71〇所產生的電流之波形圖。 ^隐胞 圖10是本發明之示範例子所提供的用於多階 電阻式§己憶體之驗證方法之流程圖。 '、 圖11A是電阻式記憶胞谓之電極端？11❸電壓 阻式s己憶胞710所產生的電流之波形圖。 /、 圖11B是電晶體72〇之源極端之源極端的電壓鱼 式記憶胞710所產生的電流之波形圖。 ^电阻 圖12是本發明之示範實施例所提供的電阻 之驗證裝置之電路圖。 '"體 圖13A疋本發明之示範實施例所提供之驗證電路Μ。 25 201123195 P51980I16TW 32720twf.d〇c/n 的電路圖。 圖13B是本發明之另一 路240的電路圖。 圖13C是本發明之另一 路240的電路圖。 示範實施例所提供之驗證 示範實施例所提供之驗證 電 電 圖13D疋本發明之另一示範實施例所提供之驗證電 路240的電路圖。 圖14A疋圖13A之驗證電路240之細部電路圖。 圖14B疋圖13B之驗證電路24〇之細部電路圖。 圖14C疋圖13B之驗證電路24〇之另一細部電路圖。 圖14D是圖13C之驗證電路240之細部電路圖。 【主要元件符號說明】 1〇〇 :單極性電阻式記憶體 110 :單極性電阻式記憶胞 111、112 :電極端 120 :電晶體 S201〜S209 :步驟流程 7〇〇 :電阻式記憶體 710 :電阻式記憶胞 720 :電晶體 711、712 :電極端 S801〜S805 :步驟流程 S851〜S856 :步驟流程 VC101 〜VC104、VC111 〜VC114:電壓曲線 26 201123195 P51980116TW 32720twf.doc/n IC101 〜IC 104、IC 111〜IC 114 :電流曲線 200 :驗證裝置 210 :信號選擇器 211、212 :多工器 220 :轉態信號控制電路 230 :電壓信號源 240 :驗證電路 2411 :電流放大器 2412 :電流電壓轉換器 2413 :電壓比較器 2414 :電壓源 2421 :電流放大器 2422:電流電壓轉換器 2423 :反向器 2431 :電流放大器 2432 :電流比較器 2433 :電壓比較器 2434 :電壓源 2441 :電流放大器 2442 :電流比較器 2443 :反向器 INV :反向器 PG1、PG2 :傳輸閘 R1 :電阻Next, please refer to FIG. 14C, which is another detailed circuit diagram of the verification circuit 240 of FIG. 13B. Fig. 14C further includes a detailed circuit diagram of the multiplexer 211, and the detailed circuit of the multiplexer 211 is as described above, and therefore will not be described again. The current amplifier 2421 is the same as the current amplifier 24A, and therefore will not be described herein. In addition, the detailed circuit of the inverter 2423 has been described above and will not be described again. Figure 14C differs from 14B in that! The current-to-voltage converter 2422 of 4C 23 201123195 P51980116TW 32720twf.doc/n is actually a current-to-voltage converter formed by a current comparator. The voltage VCON can control the current ' of the transistor M5 and generate a reference current 12 which is compared with the current signal 12 to produce a detection voltage Vp. In addition, FIG. 14C itself may also be a detailed circuit diagram of the verification circuit of FIG. 13D. In other words, the current amplification circuit 2421 of FIG. 14C is the detailed circuit of the current amplifier 2441 of FIG. 13D. The current comparator of FIG. 14C is the current comparator of FIG. 13D. The detailed circuit of the current amplifier 2442's inverter 2423 of FIG. 14C is the detailed circuit of the inverter 2443 of FIG. 13D. Next, please refer to Fig. 14D, which is a detailed circuit diagram of the verification circuit 240 of Fig. 13C. Fig. 14] B further includes a detailed circuit diagram of the multiplexer 211, and the detailed circuit of the multi-mode 2 is as described above, and therefore will not be repeated here. The current amplifier 2421 is the same as the current amplifier 2411, and the current comparator 2432 is the same as the voltage comparator 2433 and the voltage comparator 2413 as described above, and therefore will not be described again. In summary, the verification method and the verification circuit provided by the exemplary embodiment of the present invention can verify the setting time of the resistive memory when the resistive memory is verified, and the setting/holding time between writing and reading can be reduced compared with the conventional verification method. In addition to the read time, the verification method and verification circuit can be used to verify the operation of multi-level or single-order resistive memory, and can be verified for bipolar resistive memory. - GENERAL EMBODIMENT Although the present invention has been disclosed above in the exemplary embodiments, and is generally within the skill of the art, some modifications and refinements may be made within the scope of the present invention. 201123195 P51980116TW 32720twf.doc/n = The scope of the invention is defined as the scope of the patent application, which is defined by the scope of the patent application. [Figure 1 is a circuit diagram of a unipolar resistive memory. 2 is a flow chart of a conventional resistive character writer verification method. Figures 3 to 6 are wave pastes of possible voltages on a unipolar resistive memory cell u. Electrode ^ 111 Road Figure 7 is an electrical circuit of a resistive memory provided by an exemplary embodiment of the present invention. Figure 8 is a flow chart of a verification method for a single-stage resistive memory provided by an exemplary embodiment of the present invention. FIG. 9A is a waveform diagram of current generated by the resistive memory cell 710 of the electrode terminal 711 of the resistive memory cell 71. Fig. 9B is a waveform diagram of the voltage generated by the voltage of the primary end of the transistor 720 and the current generated by the resistor 71. ^The cryptogram is a verification of the multi-step resistive § recall provided by the exemplary embodiment of the present invention. Flowchart of the method. ', Figure 11A is the waveform of the current generated by the electrode end of the resistive memory cell, 11 ❸ voltage resistive s MSC 710. /, Figure 11B is the source of the source of the transistor 72 极端A waveform diagram of the current generated by the extreme voltage fish memory cell 710. [Resistor Figure 12 is a circuit diagram of a verification device for a resistor provided by an exemplary embodiment of the present invention. '" Figure 13A shows an exemplary embodiment of the present invention Figure 23B is a circuit diagram of another path 240 of the present invention. Figure 13C is a circuit diagram of another path 240 of the present invention. Verify the circuit diagram of the verification circuit 240 provided by another exemplary embodiment of the present invention provided by the exemplary embodiment. Figure 14A is a detailed circuit diagram of the verification circuit 240 of Figure 13A. Figure 14B Figure 13B Figure 14C is a detailed circuit diagram of the verification circuit 24 of Figure 13B. Figure 14D is a detailed circuit diagram of the verification circuit 240 of Figure 13C. [Main component symbol description] 1〇〇: unipolar resistance Memory 110: unipolar resistive memory cell 111, 112: electrode terminal 120: transistor S201~S209: step flow 7: resistive memory 710: resistive memory cell 720: transistor 711, 712: electricity Extreme S801 to S805: Steps S851 to S856: Step Flows VC101 to VC104, VC111 to VC114: Voltage Curve 26 201123195 P51980116TW 32720twf.doc/n IC101 to IC 104, IC 111 to IC 114: Current Curve 200: Verification Device 210: Signal selectors 211, 212: multiplexer 220: transition signal control circuit 230: voltage signal source 240: verification circuit 2411: current amplifier 2412: current voltage converter 2413: voltage comparator 2414: voltage source 2421: current amplifier 2422 : Current-to-Voltage Converter 2423: Inverter 2431: Current Amplifier 2432: Current Comparator 2433: Voltage Comparator 2434: Voltage Source 2441: Current Amplifier 2442: Current Comparison 2443: inverter INV: inverter PG1, PG2: pass gates R1: Resistance
Ml〜M15 :電晶體 27Ml~M15: transistor 27