TWI708254B - Method and electronic circuit for verifying operation performed by cell of rram - Google Patents

Abstract

The disclosure is directed to a method and an apparatus for verifying an operation performed on a cell of a RRAM. In an aspect of the disclosure, the method would include not limited to by apply a first write voltage continuously on a cell of the RRAM during a writing operation; during the writing operation, measuring a rate of change of the resistance of the cell continuously; detecting whether the rate of change of the resistance is changed; detecting whether the resistance is below a target resistance value in response to detect that the rate of change of the resistance is changed; and having determined the cell is valid in response to having detected the first resistance dropping below the target resistance value.

Description

Method and electronic circuit for verifying operation performed on memory cell of resistive random access memory

The present invention relates to a verification method, and more particularly, to a method and an electronic device for verifying operations performed on a memory cell of a resistive random access memory (RRAM).

The conventional method for verifying operations such as writing operations or programming operations on the memory cell of a resistive random access memory chip is to detect the resistance value of the memory cell by applying an electric pulse to the memory cell, and The detected resistance value is then compared with a predetermined target value. If the resistance value detected during the write operation has reached the target value, the write operation is regarded as successful. However, if the detected resistance value does not reach the target value, the write operation is deemed to have failed or not yet completed. If the write operation has not been completed, the write operation should be allowed to continue. But if the write operation fails, then the previous write operation will be deleted to allow the same memory cell to be rewritten. If the detected resistance does not reach the target value after the write operation is completed, the failure to reach the target value may be due to a defect in the memory cell, a write failure, or other factors. In that case, the previous write operation will be deleted, and the same memory cell can be rewritten again.

FIG. 1A shows a hypothetical situation where the conventional verification method is applied to verify the operation on the memory cell of the resistive random access memory chip. At the first verification point 101, since the write operation has not been completed, the detected resistance value may not change, so the write operation will be allowed to continue. At the second verification point 102, the detected resistance value has reached and exceeded the target value 111, so the write operation is considered successful. Or, if the resistance value reaches and exceeds the target value 111 but the resistance value is detected to fail to reach the target value 111 at the third verification point 103, then it is not judged whether the write operation has not been completed and should be allowed to continue or the previous write operation Should be erased for subsequent rewriting.

FIG. 1B shows another hypothetical situation where the conventional test method is applied to verify the operation on the memory cell of the resistive random access memory chip. In this case, at the fourth verification point 104, the detected resistance value 105 has not reached the target value 111, but it is difficult to judge the write operation because the resistance value is detected at the time point based on the time point reference Whether it has actually failed, and at each point in time, the conventional test method will obtain a detected resistance value.

Based on the hypothetical scenarios in FIGS. 1A and 1B, it can be seen that if the verification method only compares the detected resistance value of the memory cell with a predetermined target value, it is difficult to know whether rewriting has occurred. Even if the conventional verification method can solve some problems, the conventional verification method still cannot detect some memory cells that never reach the target value of 111. Therefore, verifying the operation on the memory cell of the resistive random access memory requires more complicated methods.

The present invention provides a method and an electronic circuit for verifying operations performed on a memory cell of a resistive random access memory (RRAM).

In one aspect, the present invention relates to a method for verifying operations performed on a memory cell of a resistive random access memory. The method includes, but is not limited to: during the write operation, continuously applying the first write voltage to the memory cell of the resistive random access memory; during the write operation, continuously measuring the resistance change rate of the memory cell; detecting resistance Whether the change rate has changed; when a change in the resistance change rate is detected, whether the first resistance is lower than the target resistance value is detected; and when it has been detected that the first resistance is lower than the target resistance value, it is judged that the memory cell is valid.

In one aspect, the present invention relates to an electronic circuit that performs operations on the memory cell of a resistive random access memory, and the circuit will include, but is not limited to: a controller circuit, which is used to continue during a write operation. Apply the first write voltage to the memory cell of the resistive random access memory; during the write operation, continuously measure the resistance change rate of the memory cell; detect whether the resistance change rate has changed; when the resistance change rate is detected When it changes, it is detected whether the first resistance is lower than the target resistance value; and when it has been detected that the first resistance is lower than the target resistance value, it is judged that the memory cell is valid.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Exemplary embodiments of the present invention will now be described in detail, examples of which are shown in the accompanying drawings. The same reference numbers may be used in the drawings and specification to indicate the same or similar parts.

As mentioned above, for verification operations performed on a memory cell of a resistive random access memory (RRAM), the resistance value is measured at a specific verification time point. At the third verification point 103 shown in FIG. 2, the measured resistance value is already lower than the target resistance value 111, so the write operation will be considered successful. However, or assuming that the resistance value of the memory cell has previously reached the target resistance value 111 but has returned to the target resistance value 111, the resistance value measured at the second verification point 102 may erroneously indicate that the write operation is unsuccessful. Therefore, the present invention solves the above-mentioned problems by introducing mechanisms and circuits to more accurately detect whether the resistance of the memory cell of the resistive random access memory reaches the target resistance value 111.

In order to test resistive random access memory more accurately, the present invention provides a method and device for verifying operations performed on the memory cell of the resistive random access memory on a per-memory cell basis. The present invention is based on judging the resistance change rate (dR/dT) of the memory cell of the resistive random access memory to verify the operation performed on the memory cell of the resistive random access memory during the writing process, and compare it with the original Combination of test methods. After detecting the rate of change, the write operation can be regarded as completely automatic stop to prevent rewriting from occurring, thereby reducing the write time. After detecting the specific change pattern of the resistance value, the resistance value can be measured. When measuring after detecting a specific change pattern, if the resistance value of the memory cell has reached the target resistance value, it can be judged that the memory cell is valid. If the resistance value of the memory cell has not reached the target resistance value after the specific change pattern is detected, the write voltage can be reversed to perform another iteration of the write operation.

Figure 2 further explains the above-mentioned specific change mode. During the period 211 when the resistance value of the memory cell decreases, the method and device of the present invention will provide a mechanism for measuring the resistance change rate of the memory cell. As shown in Figure 2, as the resistance decreases, (-dR/dT) will reflect the corresponding increase in the negative resistance change rate of the memory cell. As the resistance value of the memory cell gradually decreases, the (-dR/dT) of the memory cell will begin to increase. When (-dR/dT) has exceeded the negative resistance threshold change 212, it is determined whether the resistance of the memory cell is lower than the target resistance value 111. If the resistance of the memory cell is lower than the target resistance value 111, the write operation is considered successful and completed. Otherwise, if the resistance of the memory cell is higher than the target resistance value 111, it is deemed that the writing operation has failed, and the inversion of the writing voltage will be applied to repeat the same writing operation.

3A and 3B respectively describe a method and an apparatus for verifying operations performed on a memory cell of a resistive random access memory. Referring to FIG. 3A, in step S301, during the write operation, the first write voltage is continuously applied to the memory cell of the resistive random access memory. In step S302, during the write operation, the resistive random access memory will continue to measure the resistance change rate of the memory cell. In step S303, the resistive random access memory will detect whether the resistance change rate has changed (for example, the negative resistance threshold change 212). In step S304, when a change in the resistance change rate is detected, the resistive random access memory will detect whether the first resistance is lower than the target resistance value. In step S305, when it has been detected that the first resistance is lower than the target resistance value, it is determined that the memory cell is valid.

According to one of the exemplary embodiments, when it is not detected that the second resistance is lower than the target resistance value, it is determined that the memory cell is invalid. When this happens, the resistive random access memory can apply a second write voltage that is opposite to the first write voltage (for example, 3V changes to -3V) to the memory cell, and then perform the same write operation. One iteration.

According to an exemplary embodiment, when it is detected that the absolute value of the resistance change rate is greater than the resistance change rate threshold, it is determined that the resistance change rate has changed.

According to an exemplary embodiment, when a change in the resistance change rate of the memory cell is detected at the first point in time, the writing operation is stopped to avoid rewriting and reduce the writing time.

According to an exemplary embodiment, the first write voltage is adjusted according to the resistance change rate and the first resistance.

According to an exemplary embodiment, applying a bias to the memory cell of the resistive random access memory may include applying a first bias to the memory cell of the resistive random access memory, and detecting the resistance of the resistive random access memory Whether the write current drawn by the memory cell changes, and when it is not detected that the write current of the memory cell has changed, increase the first bias voltage to the second bias voltage.

According to an exemplary embodiment, measuring the first resistance of the memory cell and the resistance change rate of the memory cell at the first time point may be performed by applying a first write voltage to detect the write current and the change rate of the write current, And according to the ratio between the write voltage on the memory cell and the write current on the memory cell in a period of time, the resistance and the resistance change rate of the memory cell are obtained.

According to an exemplary embodiment, the measurement of the resistance change rate is performed by a first current mirror circuit connected to a first resistance-capacitance filter with a first delay. Measuring the rate of change may include detecting the first output current of the first current mirror circuit. If the first output current increases, the resistance change rate is positive; otherwise, if the first output current decreases, the resistance change rate is negative.

According to an exemplary embodiment, the detection rate of change is performed by a second current mirror circuit, which is connected to a second resistance-capacitance filter with a second delay, and the second resistance-capacitance filter has a greater delay than the first delay. Larger capacitance value for long delay.

According to an exemplary embodiment, detecting the first resistance of the memory cell and detecting the second resistance of the memory cell is performed by measuring the second output current of the third current mirror circuit connected to the resistive random memory cell.

3B, the device 300 will include, but is not limited to, a resistive random access memory cell 301, a first current mirror circuit 302, a second current mirror circuit 303, a third current mirror circuit 304, and a controller circuit 305 Measuring device. The resistive random access memory cell 301 is the object under test. The first current mirror circuit 302 and the second current mirror circuit 303 are optional components for measuring the resistance change rate of the resistive random access memory cell 301. The third current mirror circuit 304 is used to measure the resistance of the resistive random access memory cell 301. The measurement device may include one or more test equipment, which may be automated and controlled by the controller circuit 305. The controller circuit 305 can be programmed or designed to implement the steps and exemplary embodiments shown in FIG. 2. The controller circuit 305 can be realized by using a programmable unit, such as a microprocessor, a microcontroller, a DSP chip, an FPGA, and so on. The function of the controller circuit 305 can also be realized by a separate electronic device or an integrated circuit. Details on the operating principles of FIGS. 2, 3A and 3B will be described in detail in the later part of the present invention.

4 and 5 illustrate two exemplary embodiments of verifying the operation method performed on the memory cell of the resistive random access memory. Referring to FIG. 4, in step S401, a first bias is applied to the memory cell of the resistive random access memory to detect whether the write current drawn by the memory cell of the resistive random access memory changes. If there is a change, step S402 is executed. If the write current drawn from the resistive random access memory does not change, the write bias voltage can be increased to the second bias voltage to determine whether the write current has changed. The process of changing the write bias may be repeated until the write current has changed, or until the second predetermined period expires from step S401. If the write current has changed or the predetermined period has expired, step S402 is executed to determine whether the memory cell is considered valid by reaching the target resistance value (for example, 111). Step S402 is the same as step S501, and will be described in the next embodiment. If it is determined in step S501 that the resistance of the resistive random access memory has never reached the target resistance value, then in step S404, the resistive random access memory will apply a reverse write bias to restart the write operation. If it is determined in step S501 that the resistance of the resistive random access memory has never reached the target resistance value, then in step S403, it is determined that the memory cell is valid.

Referring to FIG. 5, before step S501, it is assumed that step S401 has been performed and the write current has changed or the second predetermined period has expired. Then in step S501, the first resistance of the memory cell and the resistance change rate of the memory cell are measured. The first resistance of the memory cell and the resistance change rate of the memory cell can be measured at the same time at the first time point. When the resistance change rate has been detected, the second resistance of the resistive random access memory is measured, otherwise, the write bias is increased in step S501a. In addition, when the rate of change of resistance is detected, the writing operation will be stopped to avoid rewriting and save writing time. When it has been detected that the second resistance is lower than the target resistance value (for example, the target resistance value 111), then in step S502, the writing operation is completed and it is determined that the memory cell is valid. However, if the second resistance never falls below the target resistance value within the first predetermined period, then in step S503, the current writing operation will be reversed, and step S501 will be repeated by starting another writing operation. Detect memory cell resistance. If after a certain number of failures, the memory cell can be considered invalid and stop the write operation.

Fig. 6 and Fig. 7 respectively show the hypotheses of the operation of the memory cell passing the test and failing the verification process. Referring to FIG. 6, the resistance value is measured after the resistance change rate is detected in advance. At the verification time 601, if it has been determined that the resistance value of the memory cell is lower than the target resistance value, the memory cell has passed the test. The write operation will stop to avoid subsequent rewriting. Referring to FIG. 7, the resistance value is measured after the resistance value change rate has been previously detected. At the verification time 702, if the resistance value of the memory cell that has been judged to be failed falls below the target resistance value within the first predetermined period, the memory cell fails the test. Then, the current write operation will be reversed, and another iteration of the write operation will be performed and the resistance value and resistance value change rate of the memory cell will be measured.

FIGS. 8 to 10 show exemplary embodiments of a circuit of an electronic device, which perform verification operations performed on a memory cell of a resistive random access memory. Referring to FIG. 8, the electronic device may include a plurality of current mirror circuits that mirror the current I_RRAM. The current I_RRAM is the current from the resistive random access memory cell. When the write bias is applied, the current I_RRAM will be drawn from the resistive random access memory cell. Transistor Q1 and transistor Q2 form a current mirror circuit, so that the current I_CM matches the current I_RRAM. When the transistor Q4 and the transistor Q5 form another current mirror circuit, the current Io will mirror the current I_CM. Therefore, the resistance of the resistive random access memory cell can be known by measuring the current Io. Moreover, the resistance change rate of the resistive random access memory can be provided by the RC delay circuit 801. Since transistor Q1 and transistor Q3 form another current mirror circuit, a series capacitor is connected between the gate of transistor Q1 and the gate of transistor Q3, and the inductor is located between the gate of transistor Q1 and the transistor. The current is divided between the gates of Q3, and the change rate of the resistivity RRAM can be determined based on the value of the current Id (for example, the first output current). If the current Id increases, the resistance change rate of the resistive random access memory is positive; otherwise, if the current Id decreases, the resistance change rate of the resistive random access memory is negative. It is worth noting that since the current Io does not include a delay, the resistance of the resistive random access memory can be measured before the resistance change rate of the resistive random access memory is measured.

Referring to FIG. 9, for this exemplary embodiment, transistor Q1 and transistor Q3 form a first current mirror circuit, transistor Q1 and transistor Q6 form a second current mirror circuit, and transistor Q1 and transistor Q2 form a third current. Mirror circuit. The first current mirror circuit includes a first RC delay circuit 901 connected between the gate of transistor Q1 and the gate of transistor Q3, and the second current mirror circuit includes a gate connected to the gate of transistor Q1 and the gate of transistor Q6. The second RC delay circuit 902 between the gates. One of the first current mirror circuit and the second current mirror circuit may be an arbitrary element. Assuming that the capacitor of the first RC delay circuit 901 has a larger capacitance value than the capacitor of the second RC delay circuit 902, the first RC delay circuit 901 will allow detection of a resistance change rate for faster than the second RC delay circuit 902. In other words, the second RC delay circuit 902 with a larger capacitance value will allow the detection of the rapidly changing resistance value of the resistive random access memory cell, while the first RC delay circuit 901 with a smaller capacitance value will allow the detection Resistance value that changes slowly or does not respond. The third current mirror detects the resistance value of the resistive random access memory cell as the current I_CM, which mirrors the current from the resistive random access memory cell.

Referring to FIG. 10, for this exemplary embodiment, the electronic device includes multiple current mirror circuits that mirror the current I_RRAM, where the current I_RRAM is the current from the resistive random access memory. When the write bias is applied, the current I_RRAM is extracted from the resistive random access memory cell. The current I_CM1 will match I_RRAM. The current I_CM1 is equal to the current I_R, which allows the measurement circuit 1003 to measure the resistance value of the resistive random access memory cell. The current I_CM2 will match the current I_RRAM. The current I_CM2 is equal to the current Io, which allows the measurement circuit 1002 to measure the resistance value of the RRAM cell. The resistance change rate of the resistive random access memory can be determined based on the value of the current Id. The current Id mirrors the current I_RRAM, and an RC delay circuit 1001 is connected in between. If the current Id increases, the resistance change rate of the resistive random access memory is positive; otherwise, if the current Id decreases, the resistance change rate of the resistive random access memory is negative.

In view of the foregoing description, the present invention is suitable for testing resistive random access memory cells, and can provide information about the resistance change rate of the resistive random access memory cells. In addition to the resistance value, the test device will be able to more accurately determine whether the resistive random access memory cell has passed the test. Furthermore, unnecessary rewriting can be avoided, and writing time can be saved.

Unless explicitly described, elements, actions or instructions used in the detailed description of the disclosed embodiments of the present invention should be construed as being absolutely critical or necessary to the present invention. Moreover, as used herein, each indefinite article "one" and "one" can include more than one item. If you plan to use only one item, use "single" or similar terms.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

101: The first verification point

102: second verification point

103: Third verification point

104: Fourth verification point

105: resistance value

111: target value/target resistance value

211: period

212: Negative resistance threshold change

S301, S302, S303, S304, S305, S401, S402, S403, S404, S501, S501a, S502, S503: steps

300: device

301: Resistive random access memory cell

302: The first current mirror circuit

303: Second current mirror circuit

304: third current mirror circuit

305: Controller circuit

601, 702: verification time point

Id, Io, I_CM, I_CM1, I_CM2, I_R, I_RRAM: current

Q1, Q2, Q3, Q4, Q5, Q6: Transistor

801, 901, 902, 1001: RC delay circuit

1002, 1003: measuring circuit

FIG. 1A shows a hypothetical situation where a conventional verification method is applied to verify a write operation performed on a memory cell of a resistive random access memory chip. FIG. 1B shows another hypothetical situation where a conventional verification method is applied to verify a write operation performed on a memory cell of a resistive random access memory chip. FIG. 2 illustrates the application of a verification method to verify a write operation performed on a memory cell of a resistive random access memory chip according to one of the exemplary embodiments of the present invention. FIG. 3A shows a flowchart of a method for verifying operations performed on a memory cell of a resistive random access memory according to one of the exemplary embodiments of the present invention. FIG. 3B shows an electronic circuit for verifying operations performed on a memory cell of a resistive random access memory according to one of the exemplary embodiments of the present invention. 4 shows a flowchart of a method for verifying operations performed on a memory cell of a resistive random access memory according to the first exemplary embodiment of the present invention. FIG. 5 shows a flowchart of a method for verifying operations performed on a memory cell of a resistive random access memory according to a second exemplary embodiment of the present invention. FIG. 6 shows a hypothetical situation in which a change in resistance value is detected by using a method of verifying operations performed on a memory cell of a resistive random access memory according to the first exemplary embodiment of the present invention. FIG. 7 shows another hypothetical situation where the resistance value change is detected by using the method of verifying the operation performed on the memory cell of the resistive random access memory according to the first exemplary embodiment of the present invention. FIG. 8 shows a test device for verifying operations performed on a memory cell of a resistive random access memory according to the first exemplary embodiment of the present invention. FIG. 9 shows a test device for verifying operations performed on a memory cell of a resistive random access memory according to a second exemplary embodiment of the present invention. FIG. 10 shows a test device for verifying operations performed on a memory cell of a resistive random access memory according to a third exemplary embodiment of the present invention.

S301, S302, S303, S304, S305: steps

Claims (10)

A method for verifying an operation performed on a memory cell of a resistive random access memory, the method comprising: continuously applying a first write to the memory cell of the resistive random access memory during a write operation Input voltage; during the write operation, continuously measure the resistance change rate of the memory cell; detect whether the resistance change rate has changed; when the resistance change rate is detected to change, detect whether the first resistance is lower than the target resistance value ; And when it has been detected that the first resistance is lower than the target resistance value, it is determined that the memory cell is valid. For example, the method of item 1 in the scope of the patent application further includes: when it is not detected that the first resistance is lower than the target resistance value, judging that the memory cell is invalid. For example, the method of item 2 of the scope of the patent application further includes: when it is determined that the memory cell has failed, applying a recovery voltage that is opposite to the first write voltage. For example, the method of item 3 of the scope of patent application further includes: after applying the recovery voltage, measuring the second resistance change rate of the memory cell; detecting whether the second resistance change rate has changed; when the second resistance change is detected When the rate changes, detecting whether the second resistance is lower than the target resistance value; and When it is not detected that the second resistance is lower than the target resistance value, it is determined that the memory cell is invalid. For example, in the method of claim 1, wherein performing the write operation includes: when a first write voltage is applied to the memory cell of the resistive random access memory, detecting the resistance of the resistive random access memory Whether the write current drawn by the memory cell changes; and when the write current of the memory cell is not detected to change, the first write voltage is increased. For example, the method of claim 1, wherein measuring the resistance change rate includes: detecting the first output current of the first current mirror circuit; if the first output current increases, the resistance change rate is positive; and if the first output current increases, the resistance change rate is positive; When the output current decreases, the resistance change rate is negative. An electronic device for verifying operations performed on a memory cell of a resistive random access memory includes: a controller circuit for: continuing the memory of the resistive random access memory during a write operation The first write voltage is applied to the cell; during the write operation, the resistance change rate of the memory cell is continuously measured; whether the resistance change rate changes; when the resistance change rate is detected, the first resistance whether Lower than the target resistance value; and when it is detected that the first resistance is lower than the target resistance value, it is determined that the memory cell is valid. For example, the electronic device of the seventh item of the scope of patent application, wherein the controller circuit connected to the first current mirror circuit is executed to measure the resistance change rate, and the first current mirror circuit is connected to the first resistance capacitor with the first delay filter. For example, the electronic device of claim 8, wherein the controller circuit connected to a second current mirror circuit is executed to measure the first resistance change rate, and the second current mirror circuit is connected to a second delay A resistance-capacitance filter, and the second resistance-capacitance filter has a larger capacitance value with a longer delay than the first delay. For example, the electronic device of the seventh item of the scope of patent application, wherein the measurement of the first resistance of the memory cell executed by the controller circuit and the measurement of the controller are performed by measuring the second output current of the third current mirror circuit The second resistance of the memory cell executed by the circuit, wherein the third current mirror circuit is connected to the memory cell of the resistive random access memory.

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