201121375 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種埋入式電子元件結構，特別有關 於一種具承受應力變化能力的複合埋入式元件結構及其製 造方法。 【先前技術】 電子產品的發展趨勢已逐漸地進化為輕、薄、短、小、 兩速、高頻和多功能的領域。為了滿足實際應用需求，半 導體封裝技術已經逐漸從球栅陣列(baii grid array，簡稱 BGA)封裝和覆晶載板(flip chip，簡稱FC)進化為二維(31)) 的堆獅。歧，嫩叫㈣ bond，簡稱WB)技術將各種封裝體組裝接合，以 功能的結構體。 於先前技術中，利用FC技術或WB技術將主動元件晶 片與載板級裝成一封裝體，並將一個以卜 叠或安裝於同-載板上。考量:二的f裝體進行堆 連接，及增加載板表面的受面積/體積比值，=== 因而業界開始研發將主動或被動元件埋^載^201121375 VI. Description of the Invention: [Technical Field] The present invention relates to a buried electronic component structure, and more particularly to a composite buried component structure capable of withstanding stress change and a method of fabricating the same. [Prior Art] The development trend of electronic products has gradually evolved into the fields of light, thin, short, small, two-speed, high-frequency and multi-functional. In order to meet the needs of practical applications, semiconductor packaging technology has gradually evolved from a ball grid array (BGA) package and a flip chip (FC) to a two-dimensional (31) pile of lions. Dissimilarity, tenderness (4) bond, referred to as WB) technology, the various packages are assembled and joined to the functional structure. In the prior art, the active device wafer and the carrier board are mounted in a package using FC technology or WB technology, and one is stacked or mounted on the same carrier. Considerations: The two f-packages are connected to the stack, and the area/volume ratio of the surface of the carrier is increased. === Therefore, the industry has begun research and development to embed active or passive components.
在傳統埋入式載板+，由於構成 的材料組成，在不_環境及 H由不R m，堆而庶甘… 度下，造成不同的應 變 進而使基板形變及伸縮等變化，導致味產画雞、 對位不*、降低及信賴性表現*佳等影響。、 【發明内容】 201121375 本發明之實施例提供一種複合埋入式元件結構，包 括：至少兩核心基板構成的一複合基板結構，該至少兩核 心基板之間是藉由一黏結層結合；一第一開口於一上層核 心基板中，及一第二開口於一下層核心基板中，其中該第 一開口大於該第二開口構成一倒凸字型空間；一晶片具有 第一組電性接觸墊，固定於至少兩絕緣材料疊層上，並鑲 入該倒凸字型空間，其中該晶片埋入該第二開口中，並與 該下層核心基板之間具有一空隙；多個導盲孔穿透該至少 兩材料疊層，對應並電性連接該些電性接觸墊；以及一絕 緣層設置於該複合基板結構上，且覆蓋該些導盲孔與該至 少兩絕緣材料疊層上。 本發明之實施例另提供一種複合埋入式元件結構，包 括：一第一埋入式封裝構件包括：一第一和一第二核心基 板構成的一第一複合基板結構，該第一和第二核心基板是 藉由一第一黏結層結合，其中一倒凸字型空間形成於該第 一和第二核心基板中；一第一晶片具有第一組電性接觸 墊，固定於至少兩絕緣材料疊層上，並鑲入該倒凸字型空 間，其中該第一晶片與該第二核心基板之間具有一空隙； 多個導盲孔穿透該至少兩絕緣材料疊層，並對應該第一組 電性接觸墊；一第一絕緣層設置於該第一複合基板結構， 且覆蓋該些導盲孔與該至少兩材料疊層上；以及一第一增 層結構設置於該第一絕緣層上；一第二埋入式封裝構件包 括：一第三和一第四核心基板構成的一第二複合基板結 構，該第三和第四核心基板是藉由一第二黏結層結合，其 中一凸字型空間形成於該第三和第四核心基板中；一第二 晶片具有第二組電性接觸墊，固定於至少兩絕緣材料疊層 201121375 上’並镶入該凸字型空間’其中該弟二晶片與該苐四核心 基板之間具有一空隙；多個導盲孔穿透該至少兩絕緣材料 疊層，並對應該第二組電性接觸墊；一第二絕緣層設置於 該第二複合基板結構，且覆蓋該些導盲孔與該至少兩材料 疊層上；以及一第二增層結構設置於該第二絕緣層上；其 中該第一和第二埋入式封裝構件為背對背設置，其間藉由 一第三黏結層結合。 本發明之實施例又提供一種複合埋入式元件結構的製 造方法，包括：提供一晶片具有第一組電性接觸墊，固定 於至少兩絕緣材料疊層上，構成一預封裝體；壓合該預封 裝體、一第一核心板和一第二核心板構成的一複合結構， 該第一和第二核心板是藉由一第一黏結層結合，其中該複 合結構具有一倒凸字型空間，且該預封裝體埋入該倒凸字 型空間中，及其中該晶片與該第二核心基板之間具有一空 隙；形成多個導盲孔穿透該至少兩絕緣材料疊層，並對應 該些電性接觸墊；形成一絕緣層設置於該複合結構上，且 覆蓋該些導盲孔與該至少兩絕緣材料疊層上；以及形成一 增層結構設置於該絕緣層上。 本發明之實施例再提供一種複合埋入式元件結構的製 造方法，包括：提供一第一晶片具有第一組電性接觸墊與 一第二晶片具有第二組電性接觸墊，固定於至少兩絕緣材 料疊層上，切割分離成一第一和一第二預封裝體；.壓合該 第一預封裝體、一第一核心板和一第二核心板構成的一第 一埋入式封裝構件以及該第二預封裝體、一第三核心板和 一第四核心板構成的一第二埋入式封裝構件，其中該第一 和第二核心板是藉由一第一黏結層結合，其中該複合結構 201121375 具有一倒凸字型空間，且該第一預封裝體埋入該倒凸字型 空間中，及其中該第一晶片與該第二核心基板之間具有一 空隙；其中該第三和第四核心板是藉由一第二黏結層結 合，其中該複合結構具有一凸字型空間，且該第二預封裝 體埋入該凸字型空間中，及其中該第二晶片與該第四核心 基板之間具有一空隙；以及其中該第一和第二埋入式封裝 構件為背對背設置，其間藉由一第三黏結層結合；形成多 個導盲孔分別穿透該至少兩絕緣材料疊層，並對應該第一 組和第二組電性接觸墊；形成一第一絕緣層設置於該第一 埋入式封裝構件上，且覆蓋該些導盲孔與該至少兩絕緣材 料疊層上，及形成一第二絕緣層設置於該第二埋入式封裝 構件上，且覆蓋該些導盲孔與該至少兩絕緣材料疊層上； 以及形成一第一增層結構設置於該第一絕緣層上，及形成 一第二增層結構設置於該第二絕緣層上。 為使本發明能更明顯易懂，下文特舉實施例，並配合 所附圖式，作詳細說明如下： 【實施方式】 以下以各實施例詳細說明並伴隨著圖式說明之範例， 做為本發明之參考依據。在圖式或說明書描述中，相似或 相同之部分皆使用相同之圖號。且在圖式中，實施例之形 狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式 中各元件之部分將以分別描述說明之，值得注意的是，圖 中未繪示或描述之元件，為所屬技術領域中具有通常知識 者所知的形式，另外，特定之實施例僅為揭示本發明使用 之特定方式，其並非用以限定本發明。 201121375 有鑑於此，本發明 ^ 的複合埋人式電子元例提供—種可承受應力變化 片組嵌埋至基板内，此構’將-具有複合結構的晶 應力變化所產生的形變、Γ構可承受應力增減，降低基板因 第1〜11圖係顯示拇嫱φ & 元伊構的f造料據發明之—實施例的複合埋入式 R法，於各製程步驟的剖面示意圖。請參 J ' 提供一承載板110、第一絕緣膜122及第 一絕a、、4 ’、並壓合成—複合載板結構。承載板110的 用，疋以承載為主’於後續的製程中會被移除，因此並不 限定其材質。第-絕緣膜122和第二絕緣膜124為不同的 脂） 3緣膜122具有良好的應力抵抗能力（例如聚亞 —絕緣膜124以樹脂材料為主（例如ABF樹 倒置貼附於第二絕緣 請參閱第2圖，將多個晶片13〇In the traditional buried carrier board, due to the composition of the material, in the absence of the environment and H from the R m, the heap and the weight of the ..., resulting in different strains and then the substrate deformation and expansion and other changes, resulting in taste Draw the chicken, the match is not *, the reduction and the reliability performance * good influence. According to an embodiment of the present invention, a composite embedded component structure includes: a composite substrate structure composed of at least two core substrates, wherein the at least two core substrates are bonded by a bonding layer; Opening in an upper core substrate, and a second opening in the lower core substrate, wherein the first opening is larger than the second opening to form an inverted convex space; and the wafer has a first set of electrical contact pads. And being embedded in the at least two insulating material stacks and embedded in the inverted convex space, wherein the wafer is buried in the second opening and has a gap with the lower core substrate; the plurality of guiding holes penetrate The at least two material layers are correspondingly and electrically connected to the electrical contact pads; and an insulating layer is disposed on the composite substrate structure and covers the conductive vias and the at least two insulating material layers. An embodiment of the present invention further provides a composite embedded component structure, including: a first embedded package component comprising: a first composite substrate structure formed by a first and a second core substrate, the first and the first The two core substrates are combined by a first bonding layer, wherein an inverted convex space is formed in the first and second core substrates; a first wafer has a first set of electrical contact pads fixed to at least two insulation layers a material stack, and is embedded in the inverted convex space, wherein a gap is formed between the first wafer and the second core substrate; a plurality of guiding holes penetrate the at least two insulating material stacks, and a first set of electrical contact pads; a first insulating layer disposed on the first composite substrate structure and covering the via holes and the at least two material stacks; and a first buildup structure disposed on the first On the insulating layer; a second embedded package member includes: a second composite substrate structure composed of a third and a fourth core substrate, wherein the third and fourth core substrates are combined by a second bonding layer. One of the convex type space shapes Forming in the third and fourth core substrates; a second wafer having a second set of electrical contact pads fixed on at least two insulating material stacks 201121375 and embedded in the embossed space Having a gap with the 核心 four core substrate; a plurality of guiding blind holes penetrating the at least two insulating material stacks, and a second set of electrical contact pads; and a second insulating layer disposed on the second composite substrate a structure, and covering the guide holes and the at least two material layers; and a second build-up structure disposed on the second insulation layer; wherein the first and second buried package members are disposed back to back, In the meantime, it is combined by a third bonding layer. The embodiment of the present invention further provides a method for fabricating a composite embedded component structure, comprising: providing a wafer having a first set of electrical contact pads, fixed on at least two layers of insulating material to form a pre-package; a composite structure comprising a pre-package body, a first core plate and a second core plate, wherein the first and second core plates are combined by a first bonding layer, wherein the composite structure has an inverted convex shape Space, and the pre-package is buried in the inverted convex space, and a gap between the wafer and the second core substrate; forming a plurality of blind vias penetrating the at least two insulating material stacks, and Corresponding to the electrical contact pads; forming an insulating layer disposed on the composite structure and covering the conductive vias and the at least two insulating material layers; and forming a build-up structure disposed on the insulating layer. The embodiment of the present invention further provides a method for fabricating a composite buried component structure, comprising: providing a first wafer having a first set of electrical contact pads and a second wafer having a second set of electrical contact pads, fixed to at least The first insulating package is laminated and separated into a first and a second pre-package; a first buried package is formed by pressing the first pre-package, a first core plate and a second core plate a second embedded package member comprising the second pre-package, a third core plate and a fourth core plate, wherein the first and second core plates are combined by a first adhesive layer. The composite structure 201121375 has an inverted convex space, and the first pre-package is buried in the inverted convex space, and a gap is formed between the first wafer and the second core substrate; The third and fourth core plates are combined by a second bonding layer, wherein the composite structure has a convex space, and the second pre-package is buried in the convex space, and the second chip And the fourth core substrate Having a gap; and wherein the first and second embedded package members are disposed back to back with a third bonding layer bonded therebetween; forming a plurality of via holes respectively penetrating the at least two insulating material stacks, and The first and second sets of electrical contact pads are formed; a first insulating layer is disposed on the first embedded package member, and the conductive vias are overlaid on the at least two insulating materials and formed a second insulating layer is disposed on the second buried package member and covers the via holes and the at least two insulating material layers; and a first build-up structure is disposed on the first insulating layer And forming a second build-up structure disposed on the second insulating layer. The present invention will be described in detail below with reference to the accompanying drawings, in which: FIG. Reference basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention. In view of this, the composite buried electron element of the present invention provides a stress-susceptible slice embedded in a substrate, and the deformation and structure of the crystal stress change of the composite structure The stress can be increased or decreased, and the substrate can be reduced in the first to eleventh drawings. The figure shows the thumb φ and the composition of the composite embossing method according to the invention - the cross-sectional schematic diagram of each process step. Please refer to J ' to provide a carrier plate 110, a first insulating film 122, and a first a, 4', and a composite-composite carrier structure. The use of the carrier plate 110, which is mainly carried by the carrier, is removed in subsequent processes, and thus the material is not limited. The first insulating film 122 and the second insulating film 124 are different greases. 3 The edge film 122 has good stress resistance (for example, the poly insulating film 124 is mainly made of a resin material (for example, the ABF tree is inverted and attached to the second insulating layer). Please refer to Figure 2 for multiple wafers 13〇
Lt r將第二絕_124固化-曰曰 著二=導體製程所製作的電子裝置，其主要元件設 ί亚由金屬化連線連接至表面接觸墊132。晶 1觸執Ϊ面面尚複合載板結構的第二絕緣膜124，使 付接觸墊132埋入第二絕緣膜124中。 請參閱第3圖，移除承载板m，使承載板11〇與第一 絕緣膜122分離，於此第-絕緣膜122做為一離型膜。於 一實施例中，於移除承載板的過程中，可選擇移除或關 部份=離型膜。接著，進行裁切㈣135以分離成獨立的 ，封裝體100。預封裝艘刚包括晶片部分13Q的寬度為 見’及複合承載板部分的寬度為L。 請參閱第4圖，以成義分別將第―核心板21〇上銳 201121375 孔形成第一窗口 215，以及將第二核心板220上銑孔形成 第二窗口 225。第一窗口 215的尺寸約大於或等於複合承 載板部分的寬度為L，第二窗口 225的尺寸約大於或等於 晶片部分130的寬度為2。 接著，請參閱第5圖，將預封裝體100、第一核心板 210與第二核心板220加以組裝。第一核心板210與第二 核心板220之間夾置一黏結層（例如聚丙烯(PP)) 230，預封 裝體100的複合承載板部分埋入第一核心板210的第一窗 口 215中，進行熱壓合，使得預封裝體100埋入第一核心 ® 板210與第二核心板220中。由於預封裝體100和第一窗 口 215間僅存在微小缝隙，在熱壓合的過中，黏結層的材 料會順應該微小孔隙流動。根據.本發明之一實施例，第一 核心板210的厚度約等於第一和第二絕緣膜複合層的厚 度。於另一實施例中，預封裝體1〇〇和第二窗口 225之間 留下缝隙229,第二核心板220的厚度大於或等於晶片130 的厚度留下一空隙228，如第6圖所示。 應注意的是，雖然本發明所述實施例是以第一和第二 • 核心板壓合的複合結構，然並限定於此，亦可選用多層堆 疊的核心板。於一實施例中，缝隙229和空隙228可消除 除封裝體100的熱應力，或者可將一導熱膠（未繪示）填入 缝隙229和空隙228,以導出封裝體100所產生的熱應力。 請參閱第7圖，實施一雷射鑽孔製程形成多個開口 150，對應各個接觸墊132，穿透第一和第二絕緣膜122、 124，露出接觸墊132的表面。開口 150的型式為盲孔，亦 可使用其他製程，例如光阻微影及蝕刻製程形成開口 150 對應各個接觸墊132的位置。 201121375 接著，請參閱第8圖，形成一導電層240於第一核心 板210與第一絕緣膜122上，順應性地填入開口 150的表 面。形成導電層240的方法包括濺鍍法、塗佈法、物理氣 相沉積法(PVD)或化學氣相沉積法（CVD)。接著，貼附一光 阻層250於導電層240上，並進行影像轉移，形成開環， 露出開口 150區域。 請參閱第9圖，進行電鍍，形成電鍍金屬260 (例如銅 /錫/錫銀銅/鎳/鋁/鎢/上述或其他合金)於開環内，填滿該開 口 150與接觸墊132電性接觸。接著，請參閱第10圖，去 除光阻層250，並蝕刻移除多餘的導電層240，露出第一核 籲 心板210。接著，壓合一絕緣膜270於第一核心板210和 電鍍金屬260上，完成符合埋入式元件結構封裝體200的 製作。 應了解的是，於另一實施例中，可藉由形成多層絕緣 層及金屬化的製程，形成增層結構，包括層間介電層310、 内連線320和導電金屬盲孔330、360，如第11圖所示。 接著，後續進行SR和B/E製程，以完成電路板的製作。 根據本發明所揭露的實施例，藉由多層核心板之間夾籲 置黏結層，而構成複合基板結構，可吸收應力變化，減缓 基板變形狀況。再者，在晶片的電性連接端採絕緣膜(例如 ABF樹脂）與離型膜(例如PI)結合之複合結構，可吸收應力 變化，減缓晶片受應力變化產生形變。更有甚者，晶片的 電性連接結構因應力變化而導致的破損斷裂情形，亦可因 此結構設計而減輕。由於埋入式晶片組採複合式結構，其 本身已具承受應力變化的效果，在搭配複合核心板的設 計，可更進一步地強化應力變化的承受度。此外，晶片組 10 .201121375 係採用鑲埋的方式壓合至核心板中，因此晶片的固定性 佳，不因外力而脫落。再者，在晶片的下方採中空設計， 即形成空隙構造。當基板熱脹冷縮變形時，不影響主體結 構。此外，亦可選擇填入導熱膠，將晶片所產生的熱能， 藉由傳導導出。 第12〜19圖係顯示根據本發明另一實施例的複合埋入 式元件結構的製造方法，於各製程步驟的剖面示意圖。請 參閱第12圖，將兩組構件加以壓合組裝，包括第一組預封 裝體100a、第一核心板210a與第二核心板220a，以及第 ® 一組預封裝體100b、第三核心板210b與第四核心板220b， 加以壓合組裝。第一核心板210a與第二核心板220a之間 夾置一黏結層（例如聚丙烯(PP)) 230a，第一預封裝體100a 的複合承載板部分埋入第一核心板210a的第一窗口中，進 行熱壓合，使得第一預封裝體l〇〇a埋入第一核心板210a 與第二核心板220a中。同時，第三核心板210b與第四核 心板220b之間夾置一黏結層（例如聚丙烯(PP)) 230b，第二 預封裝體l〇〇b的複合承載板部分埋入第三核心板210b的 • 第一窗口中，進行熱壓合，使得第二預封裝體l〇〇b埋入第 三核心板210b與第四核心板220b中。由於第一和第二預 封裝體100a和100b與第二和第四核心板的窗口間僅存在 微小缝隙，在熱墨合的過中，黏結層的材料會順應該微小 孔隙流動，並在間隙之間留下缝隙229a和229b。第二核 心板220a的厚度大於或等於晶片130a的厚度，並留下一 空隙228a。相同地，第四核心板220b的厚度大於或等於 晶片130b的厚度，並留下一空隙228b，如第13圖所示。 請參閱第14圖，實施一雷射鑽孔製程形成多個開口 150a，對應各個接觸墊132a，穿透第一和第二絕緣膜122a、 r si 11 201121375 124a ’，露出接觸墊132a的表面。相對地，可另實施一雷射 鑽孔製程形成多個開口 15〇b，對應各個接觸墊132b，穿透 第三和第四絕緣膜122b、124b，露出接觸墊132b的表面。 開口 150a、150b的型式為盲孔，亦可使用其他製程，例如 光阻微影及蝕刻製程形成開口 150a、150b對應各個接觸墊 132a、132b 的位置。 接著，請參閱第15圖，形成一第一導電層24〇a於第 一核心板210a與第一絕緣膜122a上，順應性地填入開口 150a的表面。相對地，形成一第二導電層240b於第三核 心板210b與第三絕緣膜i22b上，順應性地填入開口 15沘 的表面。 形成第一和第二導電層24〇a、24〇b的方法包括濺鍍 法、塗佈法/物理氣相沉積法(PVD)或化學氣相沉積法 (CVD)接者，貼附一光阻層25〇a於第一導電層24〇a上， 並進行影像轉移，形成開環，露出開口 150a區域，以及貼 附另一光阻層25〇b於第二導電層240b上，並進行影像轉 移，形成開環，露出開口 150b區域。 請參閱第16圖，進行電鍍，形成電鍍金屬26〇a(例如 銅/錫/錫銀銅/鎳/鋁/鎢/上述或其他合金)於開環内，填滿該 開口 150a與接觸墊132a電性接觸，並電鑛金屬260b (例 如銅/錫/錫銀銅/鎳/鋁/鎢/上述或其他合金)於開環内，填滿 該開口 150b與接觸墊132b電性接觸。 接著’請參閱第17圖，去除光阻層250a、250b，並蝕 刻移除多餘的第一和第二導電層240a、240b，露出第一核 心板210a和第三核心板21 〇b。接著，壓合一第一絕緣膜 270a於弟一核心板210a和電鑛金屬260a上，以及壓^— 弟一絕緣膜270b於第三核心板21〇b和電鐘金屬260b上。 請參閱第18圖，可藉由形成多層絕緣層及金屬化的製 12 201121375 程，分別形成增層結構於第一和第二絕緣膜270a、270b 上。所述第一絕緣膜270a上之增層結構包括層間介電層 310a、内連線320a和導電金屬盲孔330a、360a，第二絕緣 膜270b上之增層結構包括層間介電層31 、内連線320b 和導電金屬盲孔330b、360b。Lt r will be the second electronic device fabricated by the second-conductor process, the main components of which are connected to the surface contact pads 132 by metallization wires. The second insulating film 124 of the composite carrier structure of the crystal 1 touch surface is buried in the second insulating film 124. Referring to Fig. 3, the carrier board m is removed to separate the carrier board 11 from the first insulating film 122, and the first insulating film 122 is used as a release film. In one embodiment, during removal of the carrier sheet, it is optional to remove or turn off the portion = release film. Next, a cutting (four) 135 is performed to separate into separate packages 100. The width of the pre-packaged vessel just including the wafer portion 13Q is 'and the width of the composite carrier portion is L. Referring to FIG. 4, the first core plate 21 is sharpened to form a first window 215, and the second core plate 220 is grounded to form a second window 225. The size of the first window 215 is greater than or equal to the width of the composite carrier plate portion being L, and the size of the second window 225 is greater than or equal to the width of the wafer portion 130 being two. Next, referring to Fig. 5, the pre-package 100, the first core board 210, and the second core board 220 are assembled. A bonding layer (for example, polypropylene (PP)) 230 is interposed between the first core board 210 and the second core board 220, and the composite carrier board of the pre-package 100 is partially buried in the first window 215 of the first core board 210. The thermocompression is performed such that the pre-package 100 is buried in the first core plate 210 and the second core plate 220. Since there is only a slight gap between the pre-package body 100 and the first window 215, the material of the bonding layer flows in accordance with the minute pores during the thermocompression. According to an embodiment of the invention, the thickness of the first core plate 210 is approximately equal to the thickness of the first and second insulating film composite layers. In another embodiment, a gap 229 is left between the pre-package body 1 and the second window 225. The thickness of the second core plate 220 is greater than or equal to the thickness of the wafer 130 leaving a gap 228, as shown in FIG. Show. It should be noted that although the embodiment of the present invention is a composite structure in which the first and second core sheets are pressed together, and is limited thereto, a multi-layer stacked core board may be selected. In one embodiment, the slits 229 and the voids 228 can eliminate the thermal stress of the package 100, or a thermal adhesive (not shown) can be filled into the slits 229 and the voids 228 to derive the thermal stress generated by the package 100. . Referring to FIG. 7, a laser drilling process is implemented to form a plurality of openings 150, corresponding to the respective contact pads 132, penetrating the first and second insulating films 122, 124 to expose the surface of the contact pads 132. The opening 150 is of a blind hole type, and other processes such as photoresist lithography and etching processes may be used to form the opening 150 corresponding to the position of each of the contact pads 132. 201121375 Next, referring to FIG. 8, a conductive layer 240 is formed on the first core plate 210 and the first insulating film 122, and is compliantly filled in the surface of the opening 150. The method of forming the conductive layer 240 includes sputtering, coating, physical vapor deposition (PVD) or chemical vapor deposition (CVD). Next, a photoresist layer 250 is attached to the conductive layer 240, and image transfer is performed to form an open loop to expose the opening 150 region. Referring to FIG. 9, electroplating is performed to form an electroplated metal 260 (eg, copper/tin/tin-silver-copper/nickel/aluminum/tungsten/the above or other alloy) in the open loop to fill the opening 150 and the contact pad 132. contact. Next, referring to FIG. 10, the photoresist layer 250 is removed, and the excess conductive layer 240 is etched away to expose the first core board 210. Then, an insulating film 270 is pressed onto the first core plate 210 and the plating metal 260 to complete the fabrication of the embedded component structure package 200. It should be understood that, in another embodiment, the build-up structure may be formed by forming a plurality of insulating layers and a metallization process, including an interlayer dielectric layer 310, interconnects 320, and conductive metal blind vias 330, 360. As shown in Figure 11. Then, the SR and B/E processes are subsequently performed to complete the fabrication of the board. According to the embodiment of the present invention, the composite substrate structure is formed by sandwiching the adhesive layer between the plurality of core plates, thereby absorbing the stress variation and slowing the deformation of the substrate. Furthermore, a composite structure in which an insulating film (for example, ABF resin) and a release film (for example, PI) are combined at the electrical connection end of the wafer absorbs stress variations and slows the deformation of the wafer due to stress changes. What is more, the damage and fracture of the electrical connection structure of the wafer due to stress changes can also be alleviated by the structural design. Since the embedded wafer group adopts a composite structure, it has the effect of undergoing stress change, and the design of the composite core plate can further enhance the tolerance of stress variation. In addition, the wafer set 10 .201121375 is laminated into the core board by means of a buried method, so that the wafer is excellent in fixing property and does not fall off due to an external force. Furthermore, a hollow design is employed below the wafer to form a void structure. When the substrate is inflated and contracted, it does not affect the structure of the main body. In addition, it is also possible to fill in the thermal conductive adhesive and transfer the thermal energy generated by the wafer by conduction. 12 to 19 are cross-sectional views showing the manufacturing method of the composite embedded element structure according to another embodiment of the present invention, in each process step. Referring to FIG. 12, two sets of components are press-fitted, including a first set of pre-packages 100a, a first core board 210a and a second core board 220a, and a first set of pre-packages 100b and a third core board. 210b and the fourth core plate 220b are assembled and assembled. A bonding layer (for example, polypropylene (PP)) 230a is interposed between the first core board 210a and the second core board 220a, and the composite carrying board of the first pre-package 100a is partially embedded in the first window of the first core board 210a. The thermocompression bonding is performed such that the first pre-package body 10a is buried in the first core board 210a and the second core board 220a. At the same time, a bonding layer (for example, polypropylene (PP)) 230b is interposed between the third core board 210b and the fourth core board 220b, and the composite carrier board of the second pre-package lb is partially buried in the third core board. In the first window of 210b, thermal pressing is performed, so that the second pre-package lb is buried in the third core board 210b and the fourth core board 220b. Since there is only a slight gap between the first and second pre-package bodies 100a and 100b and the windows of the second and fourth core plates, in the thermal ink, the material of the bonding layer flows along the tiny pores and is in the gap. Between the gaps 229a and 229b are left. The thickness of the second core plate 220a is greater than or equal to the thickness of the wafer 130a and leaves a void 228a. Similarly, the thickness of the fourth core plate 220b is greater than or equal to the thickness of the wafer 130b, leaving a gap 228b as shown in Fig. 13. Referring to Fig. 14, a laser drilling process is performed to form a plurality of openings 150a corresponding to the respective contact pads 132a, penetrating the first and second insulating films 122a, rsi 11 201121375 124a' to expose the surface of the contact pads 132a. In contrast, a laser drilling process may be additionally performed to form a plurality of openings 15?b corresponding to the respective contact pads 132b, penetrating the third and fourth insulating films 122b, 124b to expose the surface of the contact pads 132b. The openings 150a, 150b are of a blind hole type, and other processes such as photoresist lithography and etching processes may be used to form the openings 150a, 150b corresponding to the positions of the respective contact pads 132a, 132b. Next, referring to Fig. 15, a first conductive layer 24A is formed on the first core plate 210a and the first insulating film 122a, and is compliantly filled in the surface of the opening 150a. In contrast, a second conductive layer 240b is formed on the third core plate 210b and the third insulating film i22b, and is compliantly filled in the surface of the opening 15?. The method of forming the first and second conductive layers 24a, 24b includes a sputtering method, a coating method/physical vapor deposition (PVD) or a chemical vapor deposition (CVD) method, and attaching a light The resist layer 25〇a is on the first conductive layer 24〇a, and performs image transfer, forming an open loop, exposing the area of the opening 150a, and attaching another photoresist layer 25〇b to the second conductive layer 240b, and performing The image is transferred to form an open loop, exposing the area of the opening 150b. Referring to FIG. 16, electroplating is performed to form an electroplated metal 26〇a (for example, copper/tin/tin-silver-copper/nickel/aluminum/tungsten/the above or other alloy) in the open loop to fill the opening 150a and the contact pad 132a. Electrically contacted, and the ore metal 260b (e.g., copper/tin/tin-silver-copper/nickel/aluminum/tungsten/the above or other alloys) is filled in the open loop to fill the opening 150b in electrical contact with the contact pad 132b. Next, referring to Fig. 17, the photoresist layers 250a, 250b are removed, and the excess first and second conductive layers 240a, 240b are etched away to expose the first core plate 210a and the third core plate 21b. Next, a first insulating film 270a is pressed onto the core plate 210a and the electric ore metal 260a, and the insulating film 270b is pressed onto the third core plate 21b and the electric clock metal 260b. Referring to Fig. 18, a buildup structure is formed on the first and second insulating films 270a, 270b, respectively, by forming a plurality of insulating layers and a metallization process. The build-up structure on the first insulating film 270a includes an interlayer dielectric layer 310a, an interconnecting line 320a and conductive metal blind holes 330a, 360a, and the build-up structure on the second insulating film 270b includes an interlayer dielectric layer 31, Wire 320b and conductive metal blind holes 330b, 360b.
接著’可選擇在形成增層結構的製程中，同時形成導 通孔結構。请參閱第19圖，在晶片封裝體的周邊區域形成 導通孔結構500 ’導通孔結構500的内側壁上具有導電層 510，使得上下層的晶片堆疊l〇〇a和i〇〇b能藉由導電層 510電性連接。導通孔内部填充絕緣材料或灌孔材料52〇S。 接著，後續進行SR和B/E製程，以完成雙層或多層埋入 式元件結構封裝體400的製作。 另一方面，亦可選擇在晶片封裝體的周邊區域不形成 導通孔結構。亦即，在完成增層結構之後，以物理剝除或 化學餘刻方法去除黏結層41G，使封|體分開成為兩個獨 立的埋入式兀件結構封裝體200a和2〇〇b，如第2〇圖所示。 接著，後續分別進行SR和B/E t程，以完成電路板的製 作。 應注意的是，本發明所揭露的各實施例所採用的晶片 並不限於皁面晶片，亦即主動元件並非僅製作於晶圓的一 面上，亦可採用雙面晶片或三維堆疊晶片。請參閱第Η 圖，利用第1~11圖所揭露的實施例的製程步驟;採用三維 堆疊晶片100c，雙面皆設置接觸墊132&和 連接接觸塾l32a和⑽及各主動元件 ^層u後’包括形成層間介電層3ig20和 ¥電金屬盲孔330、360，以電性Hi% 接荖，再:笙- =t电『玍遷接正面的接觸墊132a， 接者再進订第一面的增層結構，包括形成層間介電層 S-7 13 201121375 710、内連線720和導電金屬盲孔73〇、76〇，以電性連接 背面的接觸墊132b。接著，後續進行sr和B/E製程，以 元成雙層或多層埋入式元件結構封農體的製作。 根據本發明所揭露的實施例’晶片上方的雙層複合結 構，主要以兩種以上之絕緣膜類為主。所述雙層複合結構 之计主要是為了抵銷造成基板形變的應力。若基板材料 向^彎曲’則複合材下方可使用較堅硬的材質，以抵抗向 下彎曲的應力。例如，藉由使用ABF與PI材料，由於π 經烘烤後較ABF更為堅硬，故可置於ABF下方，抵抗向 下變形的應力。再者，複合層結構所採用的兩種材料可視籲 基板的狀況而決定。例如’基板向上或向下彎曲，可決定 兩，緣材料的相對位置。絕緣材料的厚度以及種類，皆需 視貫際產品需求而決定，而以最佳化的實施方法進行。此 外’絕緣材料的種類可如一般電路板界所使用的絕緣材， 例如ABF、PP、或朽等，抑或者為高分子聚合物等材料， 如 PMMA、PVC 等。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範阖’任何所屬技術領域中具有通常知識者，在 φ 不脫離本發明之精神和範圍内，當可做些許的更動與潤 倚’因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 14 201121375 【圖式簡單說明】 第1〜11圖係顯示根據本發明之一實施例的複合埋入式 元件結構的製造方法，於各製程步驟的剖.面示意圖。 第12〜19圖係顯示根據本發明另一實施例的複合埋入 式元件結構的製造方法，於各製程步驟的剖面示意圖。 第20圖係顯示根據本發明之實施例的移除黏結層步 驟，使雙面封裝體分開成為兩個獨立的埋入式元件結構封 裝體200a和200b的剖面示意圖。 第21圖係顯示根據本發明之實施例採用採用三維堆疊 晶片具雙面增層結構的埋入式元件結構封裝體600的剖面 示意圖。 【主要元件符號說明】 100、100a、100b〜預封裝體； 110〜承截板； 122、122a、122b〜第一絕緣膜； 124、124a、124b〜第二絕緣膜； 130、130a、130b〜晶片； 132、132a、132b〜接觸墊； 135〜裁切步驟； 150、150a、150b〜開口； 200、200a、200b〜埋入式元件結構封裝體； 210、210a〜第一核心板； 21 Ob〜第三核心板； 215〜第一窗口； 220、220a〜第二核心板； 220b〜弟四核心板， IS. 15 201121375 225〜第二窗口； L〜複合承載板部分的寬度； Z〜晶片部分的寬度； 230、230a、230b〜黏結層； 228、 228a、228b〜空隙； 229、 229a、229b〜缝隙； 250、250a、250b〜光阻層； 260、260a、260b〜電鍍金屬； 270、270a、270b〜絕緣膜； 310、310a、310b〜層間介電層； 320、320a、320b〜内連線； 330、330a、330b、360、360a、360b〜導電金屬盲孔； 400〜埋入式元件結構封裝體； 410〜黏結層； 500〜導通孔結構； 510〜導電層； 520〜灌孔材料； 600〜埋入式元件結構封裝體； 650〜貫穿晶片的導通孔； 710〜層間介電層； 720〜内連線； 730、760〜導電金屬盲孔。Next, it is optional to form a via structure at the same time in the process of forming the build-up structure. Referring to FIG. 19, a via structure 500 is formed in a peripheral region of the chip package. The inner sidewall of the via structure 500 has a conductive layer 510, so that the upper and lower wafer stacks l〇〇a and i〇〇b can be used. The conductive layer 510 is electrically connected. The inside of the via hole is filled with an insulating material or a hole material 52〇S. Next, the SR and B/E processes are subsequently performed to complete the fabrication of the two-layer or multi-layer buried component structure package 400. On the other hand, it is also possible to select that no via structure is formed in the peripheral region of the chip package. That is, after the build-up structure is completed, the adhesive layer 41G is removed by physical stripping or chemical re-etching, and the package body is separated into two independent buried-type device package bodies 200a and 2〇〇b, such as Figure 2 is shown. Then, the SR and B/E steps are performed separately to complete the board fabrication. It should be noted that the wafers used in the embodiments disclosed in the present invention are not limited to soap-surface wafers, that is, the active components are not only fabricated on one side of the wafer, but also double-sided wafers or three-dimensional stacked wafers. Referring to FIG. 3, the process steps of the embodiment disclosed in FIGS. 1-11 are used; the three-dimensional stacked wafer 100c is used, and the contact pads 132 & and the connection contacts 32l32a and (10) and the active components are disposed on both sides. 'Including the formation of the interlayer dielectric layer 3ig20 and the electric metal blind holes 330, 360, with the electrical Hi% connection, and then: 笙 - = t electric "玍 接 正面 contact the front contact pad 132a, the receiver then order first The layered buildup structure includes forming an interlayer dielectric layer S-7 13 201121375 710, an interconnect 720 and conductive metal blind vias 73〇, 76〇 to electrically connect the back contact pads 132b. Then, the sr and B/E processes are subsequently carried out to form a double-layer or multi-layer embedded component structure to seal the agricultural body. According to the embodiment of the present invention, the two-layer composite structure above the wafer is mainly composed of two or more types of insulating films. The two-layer composite structure is mainly for offsetting the stress causing deformation of the substrate. If the substrate material is bent, a harder material can be used under the composite to resist the downward bending stress. For example, by using ABF and PI materials, since π is harder than ABF after baking, it can be placed under the ABF to resist the stress of downward deformation. Furthermore, the two materials used in the composite layer structure can be determined by the condition of the substrate. For example, the substrate is bent upwards or downwards to determine the relative position of the two edges. The thickness and type of the insulation material are determined by the requirements of the continuous product, and are carried out in an optimized implementation method. Further, the type of the insulating material may be, for example, an insulating material used in a general circuit board boundary, such as ABF, PP, or annihilation, or a material such as a polymer, such as PMMA or PVC. The present invention has been disclosed in the above preferred embodiments. However, it is not intended to limit the scope of the present invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. 14 201121375 [Brief Description of the Drawings] Figs. 1 to 11 are views showing a manufacturing method of a composite embedded element structure according to an embodiment of the present invention, and a schematic cross-sectional view of each process step. 12 to 19 are cross-sectional views showing the manufacturing method of the composite embedded element structure according to another embodiment of the present invention, in each process step. Figure 20 is a cross-sectional view showing the step of removing the bonding layer to separate the double-sided package into two separate buried component structure packages 200a and 200b according to an embodiment of the present invention. Fig. 21 is a cross-sectional view showing a buried element structure package 600 employing a three-dimensional stacked wafer having a double-sided build-up structure according to an embodiment of the present invention. [Description of main component symbols] 100, 100a, 100b to pre-package; 110 to receiving plate; 122, 122a, 122b to first insulating film; 124, 124a, 124b to second insulating film; 130, 130a, 130b~ Wafer; 132, 132a, 132b~ contact pad; 135~ cutting step; 150, 150a, 150b~ opening; 200, 200a, 200b~ buried component structure package; 210, 210a~ first core board; 21 Ob ~ third core board; 215 ~ first window; 220, 220a ~ second core board; 220b ~ brother four core board, IS. 15 201121375 225 ~ second window; L ~ composite carrier board part width; Z ~ wafer Partial width; 230, 230a, 230b~ bonding layer; 228, 228a, 228b~ void; 229, 229a, 229b~ slit; 250, 250a, 250b~ photoresist layer; 260, 260a, 260b~ electroplated metal; 270a, 270b~insulating film; 310, 310a, 310b~ interlayer dielectric layer; 320, 320a, 320b~internal line; 330, 330a, 330b, 360, 360a, 360b~ conductive metal blind hole; 400~ buried type Component structure package; 410~ bonding layer; 500~ via structure; 510~ Dielectric layer; 520~ grout material; 600~ embedded device package structure; 650~ through-wafer vias; 710~ interlayer dielectric layer; connecting the 720~; 730,760~ conductive metal vias.