201118892 六、發明說明： 【發明所屬之技術領域】 本發明涉及一種低電容積層型晶片變阻器，尤指晶片變阻器 的陶瓷主體的内外層具不同玻璃相組成的低電容積層型晶片變阻 器。 【先前技術】。 電子工業的趨勢是作鮮愈來愈高，尺寸愈來愈小。因此 在间頻範圍下使用低電容變阻器（i〇w capacitance varist〇r) 來保護1C不受過電壓破壞的需求，也就愈來愈大。 習知的變阻器（varistor)以氧化鋅或鈦酸錯為主體，並加 入氧化物燒結而成。以氧化鋅變阻器為例，是以氧化辞與則、也 、Si、Co、Μη、Cr等氧化物所組成。在1〇〇(rc以上的高溫下， 氧化叙與Co、Mn、Cr等氧化物會在氧化鋅粒子間形成一晶界層 ’微觀組織驗-種晶式電容器，所以，以此種材料製成的 變阻器具有較高電容值，在職下，其電容值由數十pF到數千 PF ;即使將上述材料做成積層型晶片變阻器，其電容值臟 下大約也有3PF職百PF。在高頻電路巾，保航件的電容值超 過3PF，便會使訊號失真，故上述保護元件不適用在高頻線路。 同樣的，由鈦_材料製作的保護讀，電容更超過數千^ 以上，也不適用在高頻線路。此外，傳輸頻率愈高，保護元件的 電谷值也要愈低’才不會使信號失真。 美國專利第5976·號發表一種具低電容且具高非線性指數 的積層型晶片變阻器’其材料組成主要是碳化雜，混合五種氧 201118892 * 化物Si02、Bi.2〇3' Pb0、聰、⑽t的任兩種氧化物含量共 、 〇·，再加入甲苯及黏結劑，球磨調成漿料後，刮成生^ ，經印内電極，疊層均壓、切割成小尺寸晶粒（chip)，在7〇〇 °C-11GG°C溫度下燒結後，制可耐靜電衝擊及抑制突波電壓且 非線性指數高達10到20的陶瓷積層型晶片變阻器。但由於此方 式做成的晶片，其電容值在1〇〜4〇pF，雖不是很高，仍遠超過 3pF，依然不適用在高頻線路。 美國專利第6251513號發表-種賴元件，其材料結構包括 • 錢粒徑小於1〇,的導體及半導體粒子，與做為絕緣材料的高 分子結合劑均勻混合，調成糊狀材料，於絕緣基板的同一平面上 印刷左右兩導體電極，在科體電極間隙中，填滿此糊狀材料後 -，烘乾而成。雖然其電容值極低，在紙下小於〇.獅，可作 •為高頻線路保護元件，但因絕緣材料係由高分子材料所組成，當 凡件使用時’’電衝擊或突波過電黯生的高熱，會使高分子 ;斗九化ie成保護元件導通，而失去對電子線路或元件的保護 籲作=’故以高分子材料為主的保護元件，不对靜電衝擊、壽命短 。若以8KV靜電直接衝擊，最多只能耐5〇〇次衝擊，即失效不能 ^請人在t華民國專利公開號_22153發表—種低電容積 1日片文阻為’體積小且電容極低，在1MHz下電容值小於0. 5 "有ί數千_人以上的8kv靜電衝擊的特性。該低電容積層型 曰日片變阻器包含一陶 _ 尤主體，且§亥陶瓷主體的内部設有内電極， 5只陶究主體的兩端設有外 ’卜電極。其中，陶瓷主體包含無機玻璃組 201118892 成3〜50wt%及粒徑大於〇_丄微米的微采或亞微米級半導體或導體 顆粒5G〜97wt%，其特點在於所述微米或亞财級半導體或導體顆 粒的表面包覆-層具厚度的高阻抗無機玻璃薄膜，燒結後， 在陶竟主體的半導體轉體顆粒之間形成耐高溫的無機破璃薄膜 ’可以耐靜電衝擊或突波過電壓產生的高熱；尤其，所述無機玻 璃薄膜内部含有許多二級分散(sec〇ndary⑴印⑽㈣粒徑更細 小的奈米級半導體微粒或導體微粒，微粒之間的間距極小，受到 異常過電壓時，會產生随道效應’故所製成的低電容積層型晶片 變阻器具有極佳的抑制過電壓及耐靜電能力且壽命長。但，這種 低電容積㈣W變阻器的缺點，卻在於機械強餘低及具有較 高觸發電壓，這個結果不符合商品的要求。 【發明内容】 因此’如何製作-個具有高機械強度且具有低觸發電壓的低 電容積層型晶>1變阻器，是本發明需要解決的課題。 本發明承襲所發表的低電容積層型晶片冑阻器的關鍵性技術 再提出改良，將低電容積層H變阻器的喊主體構成三明治 結構，包含内電極以内的内層陶瓷及内電極以外的外層陶瓷，且 内外層陶t的無機玻璃組成及導體或半導體顆粒的含量不同。所 以，經調配使用不同玻璃態組成及用4、不同料體或半導體含 量，就可以變更主體的内層陶竟與外層陶究的強度及導電性 ’進而獲得具有南機械強度和極佳的靜電防護效果及突波抑制能 力的低電容晶片型變阻器。 為此，本發明的主要目的在於提供一種低電容積層型晶片變 201118892 ' 阻益’包含-陶究主體、一對或一對以上内電極，左右交錯設於 〜 補莞主體的内部、及—對外電極，設於該陶-¾主體的兩端，其 /陶莞主體為二明治結構，包含内電極以内的内層陶莞及内 電極以外的外層陶究，且所述内層陶充包括無機玻璃組成3~5〇 ㈣及粒徑大於〇.1微米的半導體或導體顆粒50〜97 wt% ;所述 外層陶竟包括無機玻璃組成wt%及粒徑大於G i微米的半 導體或導體顆粒Μ wt% ;而且，所述的半導體或導體顆粒的 表面包覆一層無機玻璃態薄膜，無機玻璃態薄膜中含有許多二級 籲離散(secondary diSpersi0n)且粒徑小於丨微米的亞微米或奈米 級半導體微粒或導體微粒。 所述陶£主體的内層陶堯及外層陶竟，除了玻璃添加量的差 異外，可以分別使用不同的玻璃材料，但其玻璃成分基本上均屬 於石夕酸鹽玻璃、雜酸鹽玻璃、石朋酸鹽玻璃、鱗酸鹽玻璃或錯酸 鹽玻璃的其中一種或一種以上。 所述陶衫體的外層喊成分中，包含m卸、飢 Φ 和/或銻成分，以提升陶瓷主體的機械強度。 本發明的-種具極低電容值、低崩潰電壓的晶片型變阻器， 可以根據元件的觸發電壓值可以由陶究内層的生胚厚度、燒結溫 度、晶界玻_厚度、㈣或半導體顆粒的大小及二級離=用°: 米尺寸導體或半導體的添加量來控制。 不 本發明的日w型變阻器，其生胚外層與内層基本製作方式相 同，唯外層不貞責過電壓下_導通效應，因此含導體或铸體 的添加量較少，但因低雜的玻璃相成分較多，故整體晶片結構 201118892 強度較佳。 【實施方式】 如圖1所不’本發明的低電容積層型晶片變阻器1〇，以積層 技術(multilayer technology)製成，包含一陶究主體^，且該 陶究主體10的兩端設有外電極13及其内部設有内電極12。ν 本發明的喊主體1丨的微觀結構如圖2所示，具相當高比 例的孔隙17，故本發明_魅體u的電容值可以做到很小， 非常適用於製造極低電容㈣積層型晶片變阻[又本發明的陶 £主體11構成晶界絕緣層的材料為玻璃成分，因為玻璃成分對 溫度的穩定性高，故本發__主體u的壽命長。 尤其，本發明的陶瓷主體11是構成三明治結構，包含内電 極12以内的内層陶瓷Ha及内電極12以外的外層陶瓷llb。 其中，所述内層陶瓷11a含有3〜5〇 wt%低熔點玻璃相成分及 50〜97 wt°/。粒徑大於〇· 1微米的導體或半導體顆粒14。 所述外層陶瓷11b含有5〜50 wt%相同或類似所述内層陶瓷 lla的低熔點玻璃相成分及50〜95 wt%粒徑大於〇.1微米的導體 或半導體顆粒14。 — 為了提升所述陶瓷主體11燒結後的機械強度，所述陶瓷主 體11的外層陶瓷llb的玻璃相成分，除了使用相同或類似所述 陶瓷主體11的内層陶瓷11a的低熔點玻璃相成分外，為進一步 降低玻璃的权化點溫度，尚加入總重量〇. 1〜的低炫點成分， 例如’所述低熔點玻璃相成分中加入了硼、鋰、鈉、鉀、銻、鈒 等成分。 201118892 . 本發明的陶瓷主體11的内層陶瓷lla與外層陶瓷llb所使 、 用的半導體或導體微粒，可以使用相同成分，也可以使用不同成 刀而且，所述半導體或導體顆粒14的表面包覆一層具一定厚 度的财高溫、高阻抗無機玻璃薄膜15。尤其，所述無機玻璃薄膜 15可以進—步含雜徑小於1微糊二級分散的亞微米或奈米級 半導體微粒或導體微粒16。 本發明的低電容積層型晶片變阻器1〇，藉陶瓷主體u的微 米或亞微米鱗體或半導體顆粒14之間树高溫的無機玻璃薄 鲁膜15存在’可以耐靜電衝擊或突波過賴時離生的高熱。更 重要的是在無機朗_ 15巾含有許多二級離散（s_細 dispersion)的亞微米或奈米級半導體微粒或導體微粒16，而且 因為半導體彳政粒或導體微粒16之間的距離非常小，在受到異常 k電C4會產生隧道效應，故本發明所示的低電容積層型晶片 變阻器10具有極佳的抑制過電壓及耐靜電能力。 本發明的低電容積層型晶片變阻器1〇的製法，包括以下步 ▲ 驟： % 調製内層生胚混合液； (a) 用溶膠-凝膠方法製備預定的玻璃組成溶膠； 其中，玻璃組成可以是矽酸鹽破j离、矽鋁酸鹽玻璃、硼酸 鹽玻璃、磷酸鹽玻璃、或鉛酸鹽破螭，或混合其中的一種或 —種以上。 (b) 將奈米金屬微粒和/或半導體微粒均勻分散於玻璃組成的溶 膠中； 201118892 其中，奈米微粒的粒經小於麵奈米，且金屬微粒可選 自刪、鈀⑽、物、金⑽、鋁⑹、銀㈤、鎳 ㈤、銅㈣及其合金的其中—種或—種以上；半導體微粒 可選自碳化石夕⑽、氧化鋅⑽、氧化鈦⑽2)、氧化錫 (Sn〇2)夕錯Si-Ge合金、銻化錮、石申化鎵、磷化銦、 鱗化鎵、硫化鋅、石西化鋅、碌化鋅、鈦酸銘(SrTi〇3M鈦酸 鋇（BaTi〇3)的其中一種或一種以上。 ⑹將料體顆粒和/或導體顆粒均勻拌人上述分散有金屬微粒 、半導體微粒的溶膠f; 其中’半導體或導體顆粒的粒徑，是亞微米以或微米級， 其粒徑大於0. Ιμιη，且金屬顆粒可選自鉑（pt)、鈀(pd)、鎢 (W)、金(Au)、铭（A1)、銀(Ag)、鎳（Ni)、銅（〇i)及其合金 的其中一種或一種以上；半導體顆粒可選自碳化矽（SiC)、 氧化鋅（ZnO)、氧化鈦(Ti〇2)、氧化錫（Sn〇2)、矽、鍺、Si-Ge合金、錄化銦、钟化錁、攝化銦、罐化鎵、硫化鋅、祕化 鋅、碌化鋅、鈦酸錯(SrTi〇3)或鈦酸鋇（BaTi〇3)的其中一種 或一種以上。 2·調製外層生胚混合液； 用溶膠-凝膠方法製備預定的玻璃組成溶膠，且加入硼、鋰 、鈉、鉀、銻和/或釩元素外，重複調製内層生胚混合液的步驟 0 3.將製得兩種混合液經乾燥和適當的溫度煆燒（小於i〇〇〇°c)後， 再分別磨細成複合粉料； 201118892 4. 按砂積層技術將上述製制兩觀合粉料加餘細成裝料 ^ ，再分糊成厚度約1G〜5_軸層生㈣帶及外層生胚薄帶 } 5. 用數張外層生胚薄帶先疊好，再均縣約·_的下蓋。對所 述下騎刷上㈣極，烘乾後，再放置3_㈣生胚薄帶， 再印上内電極。如圖i所示，内層生胚薄帶的内電極和下蓋的 内電極以交錯印刷方式分別連接元件的左右端。内電極可以是 鉑（Pt)、把⑽、金⑽、銀(Ag)、錄㈤等金屬，或以上任 φ 兩種金屬所組成的合金。 再用數張外層生胚薄帶先叠好，均塵成約2〇_的上蓋。再 將上蓋放置於上述内層生胚薄帶的上方一起疊好，經均壓壓合 後’切割成生胚晶粒。再將生胚晶粒放入燒結爐中燒結，舞結 溫度約·麵。C。燒結後，對晶粒兩端沾上端電極;^ 600、900 C ’燒附後’即為製成具低容值、低電壓，能抑制突 波或靜電的積層型晶片變阻器產品。 犬 鲁 卩下列舉實施例說明本發明的製法，且所製得的低電容積屉 型曰曰片變阻器10的陶竟主體u為具不同玻璃相組成的内、外層 陶究所構成’該陶竟主體u具有低電容、低崩潰電壓及高機械 強度等優點，故所製得的低電容積層型“變阻器1Q具有極佳 的靜電防護效果及突波抑制能力。 貫施例 (a)内層生胚： 取粒徑在0·1〜20μιη範圍的碳化石夕（SiC)粉末及自行製備且 201118892 粒徑在〇1—2μΠ1範圍的奈米金顆粒，一起加入以溶膠凝膠 法製備的未含任何^納、鉀、鈒元素的奈米頻鹽玻^的 朦狀液内，，_均勻獅錢合液後，使碳切(SiC)粉末均句 包圍-層含賴成分有顧。依絲2所示的碳切粉、奈米翻 及玻璃的重量_，分觀得樣品丨及樣品2的⑽生胚混合液 〇 表1 樣品 SiC (碳化石夕） 重量°/。 金屬翻顆粒 重量％ 1 . - 丨 玻螭 重暑％ 1 100 1 1 β 2 100 2 --- 91 0 1 --- 將樣品1及樣品2 _層生胚混合舰乾獅成粉末，送到 煆燒爐以700°C煆燒，製成具包覆玻璃膜的Sic粉末。 煆燒粉末經粗磨及細磨後，添加溶劑（曱苯及正丁醇）、黏結 劑（聚乙烯縮丁盤）、分散劑後，一起放入球磨桶球磨，得到的聚 料，再以刮刀機刮成厚度3〇μιη的樣品1及樣品2内層生胚薄帶 〇 (b)外層生胚： 取粒徑在0.1〜20μπι範圍的碳化矽(si〇粉末及自行製備且 粒授在0· 01-2μιη耗圍的奈米金屬翻顆粒，一起加入以溶膠凝膠 法製備且添加了總量0· 1〜5wt%的哪、經、納、钾、訊元素的奈米 矽酸鹽玻璃的膠狀液内’經過均勻攪拌成混合液後，使碳化石夕 (SiC)粉末均勻包圍一層含玻璃成分有機膜。依照表2所示的碳 化矽粉、奈米鉑及玻璃的重量比例，分別取得樣品1及樣品2的 12BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-power-volume, layer-type wafer varistor, and more particularly to a low-capacity layer-type wafer varistor having a different glass phase composed of an inner and outer layer of a ceramic body of a wafer varistor. [Prior Art]. The trend in the electronics industry is that the freshness is getting higher and the size is getting smaller and smaller. Therefore, the use of low capacitance varistor (i〇w capacitance varist〇r) in the inter-frequency range to protect 1C from overvoltage damage is becoming more and more important. Conventional varistors are mainly made of zinc oxide or titanic acid and sintered by adding an oxide. Taking a zinc oxide varistor as an example, it is composed of oxides such as oxidized and sulphur, Si, Co, Μ, and Cr. At 1 〇〇 (high temperature above rc, oxidized oxides and oxides such as Co, Mn, and Cr form a grain boundary layer between the zinc oxide particles' microscopic structure-special crystal capacitors, so The varistor has a higher capacitance value, and its capacitance value ranges from tens of pF to several thousand PF. Even if the above material is made into a laminated wafer varistor, the capacitance value is about 3PF PF under dirty conditions. Circuit board, the capacitance value of the safety part exceeds 3PF, the signal will be distorted, so the above protection element is not suitable for high frequency lines. Similarly, the protection read by titanium material is more than several thousand ^, Not applicable to high-frequency lines. In addition, the higher the transmission frequency, the lower the electric potential of the protection element is, so that the signal will not be distorted. US Patent No. 5976·publishes a low-capacitance and high nonlinear index The laminated wafer varistor's material composition is mainly carbonized, mixed with five kinds of oxygen 201118892 * SiO2, Bi.2〇3' Pb0, Cong, (10)t of any two oxides, 〇·, then added toluene and bonding Agent, ball milled into slurry After that, it is scraped into a green ^, and the inner electrode is laminated, and the laminated pressure is divided into small-sized chips. After sintering at a temperature of 7 ° C to 11 GG ° C, the system is resistant to electrostatic shock and suppression. A ceramic laminated wafer varistor with a wave voltage and a nonlinearity index of up to 10 to 20. However, the capacitance of the wafer made by this method is 1 〇 to 4 〇pF, although it is not very high, it is still far more than 3 pF, which is still not applicable. In the high-frequency line, US Pat. No. 6,251,513, a material-based structure comprising: a conductor and a semiconductor particle having a particle size of less than 1 Å, uniformly mixed with a polymer binder as an insulating material, and adjusted into a paste. The material is printed on the same plane of the insulating substrate, and the left and right conductor electrodes are printed in the gap of the body electrode, and after filling the paste material, it is dried. Although the capacitance value is extremely low, it is less than 〇 under the paper. Lion, can be used as a high-frequency line protection component, but because the insulating material is composed of polymer materials, when the piece is used, the electric shock caused by electric shock or surge will cause the polymer; Ie into a protective element that turns on and loses the electron line The protection of the road or component is called = 'The protection element is mainly made of polymer material, it does not impact on static electricity and has a short life. If it is directly impacted by 8KV static electricity, it can only withstand 5 times of impact, that is, failure can not be tHuaguoguo Patent Publication No. _22153 published - a low-power volume 1 day piece of text resistance is 'small size and very low capacitance, the capacitance value at 1MHz is less than 0. 5 " there are thousands of people above 8kv electrostatic shock The low-capacity layer type 曰 片 varistor comprises a ceramic body, and the interior of the § hai ceramic body is provided with internal electrodes, and the ends of the five ceramic bodies are provided with external electrodes. Among them, the ceramic body 5G~97wt% of micro- or sub-micron semiconductor or conductor particles comprising inorganic glass group 201118892 and 3~50wt% and particle size larger than 〇_丄micron, characterized by the surface of the micron or sub-conductor semiconductor or conductor particles The high-impedance inorganic glass film with a thickness of the cladding layer is formed, and after sintering, a high-temperature resistant inorganic glass film is formed between the semiconductor rotating body particles of the ceramic body, which can resist the high heat generated by electrostatic shock or surge overvoltage; , The inorganic glass film contains a plurality of second-order semiconductor particles or conductor particles having a finer particle size, and the spacing between the particles is extremely small. When an abnormal overvoltage is applied, a channel effect is generated. The resulting low-power-volume layered wafer varistor has excellent overvoltage and static resistance and long life. However, the shortcomings of this low-capacity (four) W varistor are that the mechanical strength is low and the trigger voltage is high. This result does not meet the requirements of the commodity. SUMMARY OF THE INVENTION Therefore, how to fabricate a low-electric-volume layer-type crystal <1 varistor having high mechanical strength and having a low trigger voltage is a problem to be solved by the present invention. The present invention inherits the key technology of the disclosed low-capacity layer type chip varistor, and further improves the shunt body of the low-current-volume layer H varistor to form a sandwich structure, including an inner layer ceramic inside the inner electrode and an outer layer ceramic other than the inner electrode. Moreover, the inorganic glass composition of the inner and outer pottery t and the content of the conductor or the semiconductor particles are different. Therefore, by using different glass compositions and using 4, different material or semiconductor contents, it is possible to change the strength and conductivity of the inner ceramic layer and the outer ceramic material of the main body, thereby obtaining southern mechanical strength and excellent electrostatic protection. Low capacitance chip type varistor with effect and surge suppression capability. To this end, the main object of the present invention is to provide a low-power-volume layered wafer change 201118892 'blocking' including - ceramic body, one or more pairs of internal electrodes, staggered left and right in the interior of the body of the body, and - The external electrode is disposed at two ends of the ceramic body, and the main body of the pottery is a two-metal structure, including an inner layer of ceramics and an outer layer other than the inner electrode, and the inner layer of ceramic filler includes inorganic glass. Forming 3~5〇(4) and 50~97 wt% of semiconductor or conductor particles having a particle diameter larger than 1.1 μm; the outer layer of ceramics comprises inorganic glass composition wt% and semiconductor or conductor particles having a particle diameter larger than G i μm Further, the surface of the semiconductor or conductor particles is coated with an inorganic glassy film containing a plurality of sub-micron or nano-scale semiconductors having a second-order divergence and a particle size smaller than 丨micron. Particles or conductor particles. The inner pottery and the outer pottery of the main body of the pottery, in addition to the difference in the amount of glass added, can use different glass materials, respectively, but the glass components are basically belong to the stone powder, the acid salt glass, the stone. One or more of patelate glass, scaly glass or miscyanate glass. The outer layer of the ceramic body includes a component of m-unloading, hunger, and/or bismuth to enhance the mechanical strength of the ceramic body. The chip type varistor of the invention with extremely low capacitance value and low breakdown voltage can be obtained from the thickness of the raw layer of the inner layer, the sintering temperature, the grain boundary glass thickness, the (four) or the semiconductor particle according to the trigger voltage value of the element. Size and secondary separation = controlled by °: meter size conductor or semiconductor addition. Without the Japanese w-type varistor of the present invention, the outer layer of the green germ is basically produced in the same manner as the inner layer, and the outer layer is not blamed for the voltage-conducting effect, so the addition amount of the conductor or the cast body is small, but the low-misc glass phase The composition of the whole wafer structure 201118892 is better. [Embodiment] The low-capacity layer type wafer varistor 1 of the present invention is made of a multilayer technology, and includes a ceramic body, and both ends of the ceramic body 10 are provided. The outer electrode 13 and its inner portion are provided with an inner electrode 12. ν The microscopic structure of the shouting body 1丨 of the present invention is as shown in FIG. 2, and has a relatively high proportion of the apertures 17, so that the capacitance value of the present invention can be made small, and is very suitable for manufacturing extremely low capacitance (four) laminated layers. The varnish of the wafer is also a glass component. Since the stability of the glass component to temperature is high, the life of the main body u is long. In particular, the ceramic body 11 of the present invention is a sandwich structure, and includes an inner layer ceramic Ha inside the inner electrode 12 and an outer layer ceramic 11b other than the inner electrode 12. Wherein, the inner layer ceramic 11a contains 3 to 5 〇 wt% of a low-melting glass phase component and 50 to 97 wt ° /. Conductor or semiconductor particles 14 having a particle size greater than 〇 1 μm. The outer layer ceramic 11b contains 5 to 50% by weight of a low-melting glass phase component of the same or similar inner ceramic layer 11a and 50 to 95% by weight of the conductor or semiconductor particles 14 having a particle diameter larger than 0.1 μm. - in order to increase the mechanical strength of the ceramic body 11 after sintering, the glass phase component of the outer layer ceramic 11b of the ceramic body 11 is the same as the low-melting glass phase component of the inner layer ceramic 11a of the same or similar ceramic body 11, In order to further lower the weighting point temperature of the glass, a low-focus component having a total weight of 1.1 is added, for example, a component such as boron, lithium, sodium, potassium, rubidium or cesium is added to the low-melting glass phase component. 201118892. The semiconductor or conductor fine particles used for the inner layer ceramic 11a and the outer layer ceramic 11b of the ceramic body 11 of the present invention may be the same component, or may be formed using different knives, and the surface of the semiconductor or conductor particles 14 may be coated. A layer of high-temperature, high-impedance inorganic glass film with a certain thickness. In particular, the inorganic glass film 15 may further comprise submicron or nano-sized semiconductor particles or conductor particles 16 having a second-dispersion of less than 1 micro-paste. The low-capacity layer type wafer varistor of the present invention has a high temperature inorganic glass thin film 15 between the micro or sub-micron scales of the ceramic body u or the semiconductor particles 14 and can be resistant to electrostatic shock or surge. High heat from the birth. More importantly, the inorganic granules contain a number of sub-micron or nano-semiconductor particles or conductor particles 16 of secondary dispersion (s_fine dispersion), and because the distance between the semiconductor plaque or the conductor particles 16 is very Small, the tunneling effect is generated by the abnormal k electric current C4, so the low electric volume layer type wafer varistor 10 shown in the present invention has excellent suppression of overvoltage and static electricity resistance. The method for preparing a low-capacity layer type wafer varistor 1 of the present invention comprises the following steps: ???modulating an inner layer raw germ mixture; (a) preparing a predetermined glass composition sol by a sol-gel method; wherein the glass composition may be The bismuth citrate is broken, the strontium aluminate glass, the borate glass, the phosphate glass, or the lead acid salt is broken, or one or more of them are mixed. (b) uniformly dispersing the nano metal particles and/or the semiconductor particles in a sol composed of glass; 201118892 wherein the particles of the nano particles are smaller than the surface nano particles, and the metal particles may be selected from the group consisting of palladium, palladium (10), matter, gold (10), one or more of aluminum (6), silver (f), nickel (f), copper (four) and alloys thereof; the semiconductor particles may be selected from the group consisting of carbon carbide (10), zinc oxide (10), titanium oxide (10) 2), tin oxide (Sn〇2) Xixia Si-Ge alloy, bismuth telluride, bismuth sulphide, gallium phosphide, indium phosphide, gallium sulphide, zinc sulphide, zinc sulphate, zinc sulphate, titanate (SrTi〇3M barium titanate (BaTi〇3) (6) uniformly mixing the material particles and/or the conductor particles with the sol f in which the metal particles and the semiconductor particles are dispersed; wherein the particle size of the semiconductor or the conductor particles is submicron or micron , the particle size is greater than 0. Ιμιη, and the metal particles may be selected from platinum (pt), palladium (pd), tungsten (W), gold (Au), Ming (A1), silver (Ag), nickel (Ni), One or more of copper (〇i) and its alloys; the semiconductor particles may be selected from the group consisting of niobium carbide (SiC), zinc oxide (ZnO), and oxidation. Titanium (Ti〇2), tin oxide (Sn〇2), niobium, tantalum, Si-Ge alloy, indium, osmium, indium, cans, zinc sulfide, zinc, zinc , one or more of titanic acid (SrTi〇3) or barium titanate (BaTi〇3). 2. modulating the outer layer of raw germ mixture; preparing a predetermined glass composition sol by a sol-gel method, and adding boron In addition to lithium, sodium, potassium, rubidium and/or vanadium, the step of repeatedly preparing the inner layer raw germ mixture is as follows. 3. The two mixed solutions are prepared by drying and calcining at a suitable temperature (less than i〇〇〇°c). After that, it is separately ground into a composite powder; 201118892 4. According to the sand layer technology, the above two-made powder is added into the charging material ^, and then the thickness is about 1G~5_axis layer (4) Belt and outer layer of raw embryos} 5. Use several outer layers of raw embryonic strips to fold first, then the lower cover of the county. _. On the lower riding brush (four) pole, after drying, place 3_(four) raw The inner strip is reprinted with the inner electrode. As shown in Fig. i, the inner electrode of the inner layer of the raw layer and the inner electrode of the lower cover are respectively connected to the left and right ends of the element by staggered printing. The inner electrode may be Platinum (Pt), (10), gold (10), silver (Ag), recorded (five) and other metals, or the above two alloys of φ two alloys. Then use a number of outer layers of raw embryonic thin strips first, the dust is about 2 The upper cover of the 〇_. The upper cover is placed on the upper inner layer of the raw embryonic strip and stacked together, and after being pressure-pressed, it is cut into green embryo grains. Then the raw embryo grains are placed in a sintering furnace for sintering. The junction temperature is about the surface. C. After sintering, the terminal electrode is applied to both ends of the crystal grain; ^600, 900 C 'after burning, it is made into a layer with low capacitance and low voltage, which can suppress the surge or static electricity. Wafer varistor product. The following examples illustrate the manufacturing method of the present invention, and the ceramic body of the low-volume-volume type varistor 10 is made of inner and outer layers with different glass phases. The composition of the ceramic body has the advantages of low capacitance, low breakdown voltage and high mechanical strength. Therefore, the low electric volume layer type "varistor 1Q" has excellent electrostatic protection effect and surge suppression capability. Example (a) Inner layer green embryo: Take carbonized carbide (SiC) powder with a particle size in the range of 0·1~20μηη and self-prepared nano gold particles with a diameter of 181—2μΠ1 in 201118892, and add together The sol-gel method prepared in the sputum liquid of the nano-frequency salt glass containing no element of sodium, potassium and strontium, after the uniform lion money mixture, the carbon-cut (SiC) powder is surrounded by a layer There are ingredients for inclusion. According to the weight of carbon cut powder, nano-turned glass and glass as shown in Figure 2, the sample mixture and the (10) raw germ mixture of sample 2 are obtained. Table 1 Sample SiC (carbonized stone) weight ° /. Metal tumbling weight % 1 - 丨 螭 螭 1 1 1 100 1 1 β 2 100 2 --- 91 0 1 --- Sample 1 and sample 2 _ layer raw embryo mixed ship dry lion into powder, sent The crucible furnace was calcined at 700 ° C to prepare a Sic powder having a coated glass film. After rough grinding and fine grinding, the simmered powder is added with a solvent (nonyl benzene and n-butanol), a binder (polyethylene butyl slab), a dispersing agent, and then placed in a ball mill barrel ball mill to obtain a granule, and then The scraper is scraped into a sample of thickness 1 〇μιη1 and the inner layer of the inner layer of the sample 2 (b) outer layer of the embryo: a niobium carbide having a particle size of 0.1 to 20 μm (the si 〇 powder and self-prepared and granulated at 0) · 01-2μιη of nano-metal granules, together with the nano-silicate glass prepared by the sol-gel method and adding a total of 0·1~5wt% of the Na, Na, K, and Si In the colloidal liquid, after uniformly stirring into a mixed solution, the carbonized carbide (SiC) powder is uniformly surrounded by a glass-containing organic film. According to the weight ratio of niobium carbide powder, nano platinum and glass shown in Table 2, Obtain 12 of sample 1 and sample 2 respectively
201118892 ’外層生胚混合液。 表2 樣品 SiC (碳化石夕） 重量％ 金屬鉑顆粒 重量％ 玻螭 重量％ 1 "------ 100 0 19 2 100 0.05 23 — 重複上述製作内層生胚薄帶的步驟，製得厚度3_的樣品ι 及樣品2外層生胚薄帶。 义用數張外層生胚薄帶先疊好，s成約删卿的下蓋。 =刖述下蓋上’印上内電極，縣後，再放置娜m内層生胚薄 π，再印上内電極。如圖丨所示，内層生胚薄帶的㈣極和下層 内電極以交錯_方式分舰接元件的左右端。内電極材料可為 鉬（Pt)、銀或、或社任_金屬所組成的合金。 再用數張外層生胚薄帶先疊好，均壓成約雇哗的上蓋。 再將上蓋放置於上述内層生胚薄帶的上方—起疊好，經均壓壓合 後切割成長寬南為12 mmx〇 6mmx〇.6mm的生胚晶粒。再將生 胚s曰粒^燒結爐巾燒結，燒結溫度約咖〜丨咖t。燒結後，晶 粒的長寬馬為1.0 mmxQ 5mm吸5刪。將晶粒兩端沾上端電極， =00-_ C ’燒附後’即為具低容值、低電壓，能抑制突波或 #電的積層型晶片變阻器產品。 分別製得樣品丨及樣品2 _層型晶片變阻器之後，測量各 個積層型晶片變阻_潰電壓及經m靜電測試後的元件崩潰 電壓、電容值及推力強度，結果如表3所示。 13 f S: 1 201118892 表3 樣品 崩潰電壓 (VlmA) 電容值 (PF at ΙΜΗζΊ 1 125 ~~----- 0.16 2 118 0.23 一 ... 觸發電壓 187 174 1000次靜電後201118892 'Outer layer of embryonic mixture. Table 2 Sample SiC (Carbide) Weight % Metal Platinum Particle Weight % Glass Weight % 1 "------ 100 0 19 2 100 0.05 23 — Repeat the above steps for making the inner layer of raw embryonic strips Sample ι of thickness 3_ and outer layer of raw specimen of sample 2. The use of a number of outer layers of raw embryonic thin strips first folded, s into the lower cover of the Qing. = 刖 下 下 ’ ’ 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上As shown in Fig. ,, the (four) poles of the inner layer of the raw embryonic strip and the inner electrodes of the lower layer are separated in the staggered manner to the left and right ends of the component. The inner electrode material may be an alloy composed of molybdenum (Pt), silver or, or a metal. Then use a number of outer layers of raw embryos to fold them first, and press them into the upper cover of the employee. Then, the upper cover is placed on the upper layer of the inner layer of the raw embryo, and the stack is folded. After the pressure equalization, the green embryo grains of 12 mm×〇 6 mm×〇.6 mm are cut and widened. Then, the raw s granules are sintered, and the sintering temperature is about ca. After sintering, the length and width of the crystal grains are 1.0 mm x Q 5 mm. The ends of the die are immersed in the terminal electrode, and the =00-_ C 'b is attached, which is a laminated chip varistor product with low capacitance and low voltage, which can suppress surge or #电. After the sample 丨 and the sample 2 _ layer wafer varistor were separately prepared, the varistor-break voltage and the component collapse voltage, capacitance value and thrust strength after the m-electrostatic test were measured, and the results are shown in Table 3. 13 f S: 1 201118892 Table 3 Sample Crash Voltage (VlmA) Capacitance Value (PF at ΙΜΗζΊ 1 125 ~~----- 0.16 2 118 0.23 a ... Trigger Voltage 187 174 After 1000 Static Electricity
比較例： 樣品3的積層型晶片變阻器的陶变層，全部以樣 声 陶变成分來製作’其製作綠如樣品丨方法。 9内層 樣品4的輔型晶㈣阻^賴麵，全 陶变成分絲作，其製作方法如樣品丨方法。。^ 2的外層 表4 樣品 崩潰電壓 (VlmA) 3 128 4 248 電容值 (pF at 1MHz) 0. 17 0.22 測量比較例各個積層型晶片變阻器的崩潰電壓及經 測試後的兀件崩潰電壓、電容值及推力強度，結果如表4所八 觸發電壓 (V) 193 1000次靜電後 -2.2 367 -6.7Comparative Example: The ceramic layer of the laminated wafer varistor of Sample 3 was all made of the sample ceramic component. 9 inner layer The auxiliary crystal of the sample 4 (4) is resistant to the surface, and the whole ceramic composition is made of silk. The preparation method is as follows. . ^ 2 outer layer table 4 sample breakdown voltage (VlmA) 3 128 4 248 capacitance value (pF at 1MHz) 0. 17 0.22 Measure the breakdown voltage of each laminated chip varistor and the tested component breakdown voltage and capacitance value And thrust strength, the results are as shown in Table 4, the trigger voltage (V) 193 after 1000 static electricity -2.2 367 -6.7
結果 比較表3及表4的結果，本發明的積層型晶片變阻器具有降 低元件的觸發電壓及改善靜電衝擊時的驗電壓偏移量效果，同 時，具有不錯的機械強度且電容值極低，電容小於〇為f，林 發明的積層型晶片變阻H適合使用在高舰路的靜電保護上。 14 201118892 . 【圖式簡單說明】 . 圖1為本發明所示的低電容積層型晶片變阻器示意圖。 圖2為圖1的低電容積層型晶片變阻器的微觀結構示意圖。 【主要元件符號說明】 10···· ••積層型晶片變阻器 11···· ••陶瓷主體 11a . .....内層陶瓷 lib · ••…外層陶瓷 12.··· ••内電極 13.··· ••外電極 14……微米或亞微米級導體或半導體顆粒 15……無機玻璃薄膜 16……二級離散的奈米或亞微米級導體或半導體微粒 17……孔隙Results Comparing the results of Tables 3 and 4, the laminated wafer varistor of the present invention has the effects of reducing the trigger voltage of the device and improving the voltage offset when the electrostatic impact is applied, and has good mechanical strength and a very low capacitance value. Less than 〇 is f, the laminated wafer varistor H invented by Lin is suitable for use in electrostatic protection of high ships. 14 201118892 . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of a low-power-volume layered wafer varistor shown in the present invention. 2 is a schematic view showing the microstructure of the low-power-volume layered wafer varistor of FIG. 1. [Explanation of main component symbols] 10····••Multilayer wafer varistor 11····••Ceramic body 11a......Inner layer ceramic lib · ••...outer ceramics 12.··· •• Electrode 13.... External electrode 14...micron or submicron conductor or semiconductor particle 15...Inorganic glass film 16...Secondary discrete nano or submicron conductor or semiconductor particle 17...pore