201116177 六、發明說明： 【發明所屬之技術領域】 本發明是有關於-種印刷電路板，且 上之空間以進行繞線的佈局方法與電路板, 二ί參=!，其繪示習知之電路板之繞線示意圖。在習知 技術中，電路板_電_接於控㈣ 間，且包括第一接腳602 '第-接腳μ』 ，、，，、員不匸電路之 繞線區·。 帛―接物、晶片安置區與201116177 VI. Description of the Invention: [Technical Field] The present invention relates to a printed circuit board, and a space for winding a layout method and a circuit board, which is a conventional Schematic diagram of the winding of the board. In the prior art, the board_electric_ is connected between the control (four), and includes the first pin 602 'the first pin 』, ,,, and the winding area of the circuit.帛-接接, wafer placement area and
第-接腳602電_接至㈣器電路。第二接腳綱電性 箱接至顯不區電路。晶片安置區_用於設置 繞線區608包括第-部份電性通路_ 日曰 路612與614以及第三部份電性通路616。其中，帛一^份^ 性通路_係為電性搞接第一接腳6〇2與晶片安置區，第 二部份電性通路612與6Η係為電_接第二接腳6〇4盥晶片 =區_。第三部份電性通路616係為電性_第一接腳觀 與第二接腳604。 在習知之技術中，第一接腳602巾之一部分係在驅動晶片 女裝於晶片安置1 606上之後用於測試驅動晶片是否可正常 動作之用，因此’在第-部份電性通路61〇中亦包含有驅動晶 X測試用的繞線。在圖6中’由於第—接腳通均有連接至晶 月安置區6G6之第-部份電性通路⑽’因此第二部份電性』 路612與614將配置於第一部份電性通路61〇之下。但在驅動 曰曰片之接腳數日益增多的今天，此__輯勢必 電路板600之面積下無法完成繞線。 有吧的 【發明内容】 本發明的目的就是在提供一種佈局方法，其係可在不增加 r r 201116177 電路板面積之情況下增加繞線區域。 積更=:7目的是提供-種電路板’其係可以設計出面 本心明的又一目的是提供一種佈局方法，1~办 線的寬度以擴大散熱面積。利万U為加見電源 線設=::=:種電路板’其係可利用單側繞 電性局且方:二用::路板上。此電路板 腳以之：錄r板提供多個第二接 ^曰曰片，且提供繞線區以設置多個電性通路。其中 一部份電性通路的兩端分別電蝴妾於第 ： 二區:電性通路中的第二部分電性通路的兩端分別 第第二部分電性通路與 ., 者之間不扠置任一苐一部份電性通路。 電性魏Γ月的較佳實施例中，上述之電性通路中的第三部份 —路的_分別電性於第—接腳之—與第二接腳之 置於月Γ較佳實施例中，上述之第一部份電性通路係設 置於第一接腳與晶片安置區之第一侧之間。 小甘ί本發明的較佳實施例中，上述之第二部份電性通路之至 夕/、中之一係設置於第一接腳中的兩個第一接腳之間。 本發明再提出-種電路板，其係電_接於二電路 1路板包括多個第—接腳、多個第二接腳、晶片安置區與繞 、、區。上述之第一接腳係電性耦接至二電路之一。上述之第二 201116177 接腳係電性搞接至二電路之另一。上述之晶 ^電路晶片。上述之繞線區係用於設置多個電性通路。、直中， 接=路中的第一部份電性通路的兩端分別電性輕接於第— 接腳之-與晶片安置區，電性通路令的第二部分電 晶片安置區與第二接腳之一，第二部分電性 3與第—接腳其中至少—者之間不設置任—第—部份電性 齡ίΓΓ又提I種佈局方法，其係顧於電路板上。此電 =電f接於二電路之間’且佈局方法包括在電路板提供多 =-接腳以電性耗接至二電路之一，並在電路板提供多個第 以電性搞接至二電路之另一。其次’提供晶片安置區以 。又置電路W，並提供繞線區以設置多個電性通路。其中 性通路t的第-部份電性通路的兩端分別電 於、 =晶片|安/區之第一側，電性通路中的第二部分Ϊ性Ϊ 路的兩W別電_接於晶片安置區之第二側與第二 二而且第-部份電性通路t至少—電源 大散熱面積。 又仍^見Μ獷 本發明又提出—種電路板，其係電性祕於二電路之間。 =路板包括多個第—接腳'多個第二接腳、晶片安置區與繞 線區。上述之第-接腳係電性祕至二電路之—。 性搞接至二電路之另一。上述之晶片安置區係用於設 f路日日片。上述之繞線區係用於設置多個電性通路。直中， ^生通路中的第—部份電性通路的兩端分別電性減於第一 ，腳之-與晶片安置區之第一側，電性通路中的第二部分電性 ▼ ττ 不—辦 ’而且第-部份電性通路中至少—電源線的寬度被加寬以 ，路的兩端分別電性_於晶片安置區之第二側與第 之一· t « Λ* - 201116177 擴大散熱面積。 本發明因採用在第二部分電性通路與第一接腳其中至少 一者之間不設置任一第一部份電性通路，因此將可縮減第一部 分電性通路之範圍，並將空出之區域用於設置第二部分電性通 路，以達到空間的妥善利用。另外，又因將第一部份電性通路 中的電源線寬度加寬，因此可以擴大散熱面積。The first pin 602 is electrically connected to the (four) circuit. The second pin is connected to the display circuit. The wafer placement area _ for setting the winding area 608 includes a first partial electrical path _ 曰 612 and 614 and a third partial electrical path 616. Wherein, the first part of the path is electrically connected to the first pin 6〇2 and the chip placement area, and the second part of the electrical path 612 and 6 is electrically connected to the second pin 6〇4盥 Chip = Area _. The third partial electrical path 616 is electrically _ first pin view and second pin 604. In the prior art, a portion of the first pin 602 is used to test whether the driver wafer can operate normally after driving the wafer on the wafer placement 1 606, thus 'in the first partial electrical path 61. The winding also includes a winding for driving the crystal X test. In Fig. 6, 'because the first pin is connected to the first partial electrical path (10) of the crystal moon placement area 6G6', the second partial electrical path 612 and 614 will be arranged in the first part. Sexual pathways under 61〇. However, in today's increasingly popular number of pins for driving the cymbal, this __ series is bound to be able to complete the winding under the area of the circuit board 600. SUMMARY OF THE INVENTION It is an object of the present invention to provide a layout method which can increase a winding area without increasing the area of the circuit board of r r 201116177. Productivity =: 7 is intended to provide a kind of circuit board. The system can be designed to provide a layout method. Another purpose is to provide a layout method, 1~ the width of the line to expand the heat dissipation area. Liwan U is the power supply line setting =::=: kind of circuit board' can be used for one-side winding and the side: two:: on the road board. The board is provided with a plurality of second pads and a winding area for providing a plurality of electrical paths. The two ends of the electrical path are respectively electrically connected to the second: the second part: the second part of the electrical path is respectively connected to the second part of the electrical path and the second part of the electrical path is not crossed Set any part of the electrical path. In a preferred embodiment of the electrical Wei Yueyue, the third part of the electrical path is preferably implemented in the month of the first pin and the second pin. In the example, the first partial electrical path is disposed between the first pin and the first side of the wafer placement area. In a preferred embodiment of the invention, one of the second electrical paths of the second portion is disposed between the two first pins of the first pin. The invention further proposes a circuit board, which is electrically connected to the two circuits, and includes a plurality of first pins, a plurality of second pins, a wafer placement area and a winding area. The first pin is electrically coupled to one of the two circuits. The second 201116177 pin is electrically connected to the other of the two circuits. The above crystal circuit chip. The winding area described above is used to provide a plurality of electrical paths. In the middle, the two ends of the first part of the electrical path are electrically connected to the first-pin-to-wafer placement area, and the second part of the electrical path is placed in the second place. One of the two pins, the second part of the electrical 3 and the first leg are not provided with any - part of the electrical age and a layout method, which is on the circuit board. The electric=electric f is connected between the two circuits' and the layout method includes providing more than one pin on the circuit board to electrically consume one of the two circuits, and providing multiple electrical connections on the circuit board to The other of the two circuits. Secondly, the wafer placement area is provided. The circuit W is again placed and a winding area is provided to provide a plurality of electrical paths. The two ends of the first-part electrical path of the neutral path t are respectively connected to the first side of the = wafer|amplifier/area, and the second part of the electrical path is separated by two The second side of the wafer placement area and the second and second partial electrical paths t at least - the power supply has a large heat dissipation area. Still, the present invention also proposes a circuit board that is electrically connected to the two circuits. = The circuit board includes a plurality of first pins - a plurality of second pins, a wafer placement area and a winding area. The above-mentioned first pin is electrically connected to the second circuit. Sexually connect to the other of the two circuits. The above wafer placement area is used to set the f road day and day piece. The winding area described above is used to provide a plurality of electrical paths. In the straight middle, the two ends of the first part of the electrical path are electrically reduced to the first, the first side of the foot-and-wafer placement area, and the second part of the electrical path is electrically ττ Not-do' and at least the first part of the electrical path is widened by the width of the power line, and the two ends of the line are electrically _ on the second side of the wafer placement area and the first one t « Λ * - 201116177 Expand the heat dissipation area. The invention does not provide any first partial electrical path between at least one of the second partial electrical path and the first pin, thereby reducing the range of the first partial electrical path and vacating The area is used to set a second part of the electrical path to achieve proper use of space. In addition, since the width of the power supply line in the first partial electrical path is widened, the heat dissipation area can be increased.
為讓本發明之上述和其他目的、特徵和優點能更明顯易 僅，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 請參照圖1 ’其繪示本發明一實施例之電路板之繞線示意 圖。此電路板100係電性耦接於二電路之間，且包括多個第一 接腳102:多個第二接腳刚、晶片安置區1〇6與繞線區⑽。 其中:如熟習遠項技藝者可以輕易知曉，二電路可以分別例如 是顯示器之印刷電路板與顯示區電路，但均不以此為限。 在本實把例中’第一接腳1〇2係電性輕接至二電路之一， 知ί腳102係可以例如是銲塾（Pad)。第二接腳104係 另一 ’且第二接腳1〇4可以例如是用於測 常運作的接腳，因而在電路板100組裝 疋成後第一接腳104將被裁切掉。 晶片安置區106係用於設置電 可以輕易知曉，電路晶#可如熟以項技藝者 驅動晶片。 疋*，，、員不器的掃瞄線或資料線 繞線區108係包括笛_ An 112^ 第一。卩伤電性通路11〇、第二部份 通路112與114以及第三部 —Mi 電性通路11()的—端 ^^其中，第-奶 接收控制器所在之印刷電路-接腳102之部分，用^ 斤傳來之汛號（例如控制訊號^ 201116177 ==第:部份電性通路U〇的另-端係 片女置£ 106’用以將訊號輸出至晶片安置區 日曰 電性通路m與114的—端係電性祕於 份 -端:電性_於第二接物。第二部份電性二= 至顯不Μ路。第：部份電性通路116之—端係紐 = - =102,另-端則電性輕接於第二接腳1〇4,用以將押 L區::)所輸出至訊號透過第三部份電性通路116傳駐The above and other objects, features, and advantages of the present invention will become more apparent, [Embodiment] Referring to Figure 1 ', a schematic diagram of a winding of a circuit board according to an embodiment of the present invention is shown. The circuit board 100 is electrically coupled between the two circuits and includes a plurality of first pins 102: a plurality of second pins, a chip placement area 1〇6 and a winding area (10). Among them: those skilled in the art can easily know that the two circuits can be respectively, for example, the printed circuit board and the display area circuit of the display, but are not limited thereto. In the present embodiment, the first pin 1〇2 is electrically connected to one of the two circuits, and the leg 102 can be, for example, a pad. The second pin 104 is another and the second pin 1〇4 can be, for example, a pin for normal operation, so that the first pin 104 will be cut after the circuit board 100 is assembled. The wafer placement area 106 is used to set the electricity. It can be easily known that the circuit crystal can be driven by the skilled artisan.疋*,,, 员 的 scan line or data line The winding area 108 includes flute _ An 112 ^ first. The electrical circuit 11〇, the second partial passages 112 and 114, and the third-mi electrical passage 11 () end, wherein the first milk receiving controller is located in the printed circuit-pin 102 In part, the nickname transmitted by ^ ^ (for example, the control signal ^ 201116177 == the other part of the electrical path U 〇 - 系 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 The electrical end of the sexual pathways m and 114 is secretive to the part-end: electrical _ to the second junction. The second part of the electrical two = to the ambiguous path. Part: part of the electrical pathway 116 - The end system is replaced by - - = 102, and the other end is electrically connected to the second pin 1〇4 for transmitting the signal to the third partial electrical path 116 through the L-zone::)
由於在顯不器中的掃猫線與資料線日益增多，為 100上的m能有效_，因此將第—部份電性通路11〇中原 本用於測試购{或錢狀繞料以赚，亦即在第 分電性通路112與114與第-接腳1G2其中至少—者之間不設 置任-部份電性通路11〇。故，可減小第一部份電性通路 110之範圍，而將空餘出來之範圍用於第二部分電性通路112 與114的繞線。 在本發明之較佳實施例中，電路板100之面積可以比習知 ^電路板小，且電路板100所縮小的垂直尺寸（圖丨所示的節 省區域118的縱向寬度）略小於圖6中第二部分電性通路612 與614的上緣到第一接腳6〇2的下緣之間的距離。 在本發明之較佳實施例中，第一部份電性通路11〇係設置 於第一接腳102與晶片安置區1〇6之第一側之間。 在本發明之較佳實施例中，晶片安置區1〇6係例如是驅動 晶片之插槽或電路板1〇〇上為容納驅動晶片的多個貫孔。 請參照圖2 ’其係繪示本發明另一實施例之電路板之繞線 不意圖。為方便說明，圖2中與圖1相同之元件係給予相同之 201116177 編號’且功能相同之處則不再贅述。Since the sweeping cat line and the data line in the display device are increasing, the m on the 100 can be effective _, so the first part of the electrical path 11〇 is originally used for testing the purchase {or money-like material to earn That is, no part of the electrical path 11〇 is provided between at least the first of the first electrical paths 112 and 114 and the first leg 1G2. Therefore, the range of the first partial electrical path 110 can be reduced, and the vacant range can be used for the winding of the second partial electrical paths 112 and 114. In the preferred embodiment of the present invention, the area of the circuit board 100 can be smaller than that of the conventional circuit board, and the reduced vertical dimension of the circuit board 100 (the longitudinal width of the saving area 118 shown in FIG. The distance between the upper edge of the second partial electrical path 612 and 614 to the lower edge of the first pin 6〇2. In a preferred embodiment of the invention, the first portion of the electrical path 11 is disposed between the first pin 102 and the first side of the wafer placement region 〇6. In a preferred embodiment of the invention, the wafer placement area 〇6 is, for example, a slot for driving a wafer or a plurality of through holes for receiving a drive wafer on a circuit board. Referring to Figure 2, there is shown a winding of a circuit board according to another embodiment of the present invention. For convenience of explanation, the same components in Fig. 2 as those in Fig. 1 are given the same 201116177 number ' and the functions are the same, and will not be described again.
在本實施例中，圖2與圖i不同之處在於圖2係將原本用 於測試驅動晶ϋ或未使用之第—接腳1G2扣刪除，亦即僅保 留未來電路板100組裝完成後會使用到的第一接腳1〇2。如此 之設計可使得在某兩個第一接腳1〇2之間會有一未使用區 域，因此佈局人員則可將第二部分電性通路112盘ιι4配置於 此未使用區域’以達成空間充分利用之目❸。使用圖2所示之 配置方式而得的節省區域118的縱向寬度將略小於圖6中用以 放置第-接腳602的縱向寬度與第—部份電性通路_的 接著，請參照圖3，其係緣示本發明一實施例之佈局方法 之步驟流簡。其中，此佈局方法係可適用於圖…圖2之電 ^板。請合併參照圖i與圖3，在本實施例中首先係為在 電路板100上提供多個第-接腳102,以連接配置有控制器之 電路板（步驟S302)。其次’在電路板1〇〇 ±提供多個第二 接腳104,以連接顯示區電路（步驟S3〇4)。 接著，在電路板剛上提供晶片安置區，以容納驅動 並^疋於其上，用以與驅動晶片作電性耦接（步驟 =06)。然後’在轉板1〇〇上提供繞線區1〇8，以 電性通路（步驟S308)。 在步驟S308之後，則連接第—接腳撤與晶片安置區 1〇6 ’以形成第-電性通路110 (步驟S3i〇)。其:欠 ，接腳104與晶片安置區106，以形成第二電性通路ιΐ2與ιΐ4 (步驟S312)。而在第二部分電性通路ιΐ2及ιΐ4盘第 腳U)2其中至少-者之間不設置任—第—部份電性通 (步驟 S314)。 201116177 =參顧4 ’其鱗林發明又—實施例之電路板之繞線 。此電路板働係電性_於二電路之間，且包括多個 腳402、多個第二接腳4〇4與晶片安置區條。其中， =技藝者可以輕易知曉’二電路可以分別例如是顯示 裔之印刷電路板與顯示區電路，但均不以此為限。 在本實施例中，第一接腳搬係電性搞接至二電路之一， 電系可以例如是鲜塾（pad)。第二接腳404係 1電路;4二路之另—’且第二接腳4。4可以例如是用於測 S i 常運作的接腳’而在電路板_組裝完 成後，則第二接腳4〇4將被裁切掉。 用於設置電路晶片，如熟f該項技藝者 ::;片片可以例如是顯示器的掃瞄線或資料線 在本實施例中，t路板400係使用單 ίΓΓ曰=曰署片安置區406之間將形成第一部份電s路 通物在=Γ4(^接Γ4之間將形成第二電性 份電性通路：。ί: 404之間將形成第三部 Ύ 第一。Ρ伤電性通路410的一端係雷糾 接!7術之部分，用以接收控制器所在之印刷電路 =傳來之喊（例如控制訊號或時序訊號），第 ί 412 ^414 ^ 置區406，而另一端則電性輕接 Γ二f電性通路412與414之設置係用於 二所輸出之_訊號與資料訊號輸出至顯示區電路。第三 電性通路416之"'端係電性麵接於第-接腳402,另-端則^ 201116177 性耦接於第二接腳404，用以將控制器（未繪示）所輸出至訊 號透過第三部份電性通路416傳送至顯示區電路。 ° 第一部份電性通路410中係包括多個電源線42〇。為使電 源線420可充分散熱，因此電源線42〇之寬度被加寬，以增加 散熱面積。如此，電源線420將不會因為過熱而產生燒毀或故 障。 在本發明之較佳實施例中，電路板4〇〇之面積可以比習知 之電路板小，而縮減掉的節省區域418的縱向寬度則約略等同 於圖6中晶片安置區606的上緣到第二部分電性通路612與 • 614的上緣間的距離。 、 在本發明之較佳實施例中，晶片❹區4〇6係例如是驅動 晶片之插槽或電路板400上為容納驅動晶片的多個貫孔。 明參照圖5，其係繪不本發明又一實施例之佈局方法之步 驟机私圖。其令’此佈局方法係可適用於圖4之電路板働。 請合併參照圖4與圖5，在本實施例中首先係為在電路板働 上提供多個第一接腳402，以連接配置有控制器之電路板（步 驟S502)。其次，在電路板4〇〇上提供多個第二接腳4〇4，以 φ 連接顯示區電路（步驟S5〇4)。 曰接著，在電路板400上提供晶片安置區4〇6，以容納驅動 曰曰片並固疋於其上，用以與驅動晶片作電性耦接（步驟 S506)。然後，在電路板4〇〇上提供繞線區4〇8，以配置多個 電性通路（步驟S508)。 在步驟S508之後’則連接第一接腳4〇2與晶片安置區 4〇6，以形成第一電性通路41〇 (步驟S51〇)。其次連接第 接腳404與0日片女置區鄕，以形成第二電性通路4丨2 (步 驟S312)。加見第一電性通路41〇中之電源線42〇之寬度， 201116177 以增加散熱面積（步驟S514)。 在本發明之較佳實施例中’電路板1〇〇與400可以例如是 軟性印刷電路板。 在本發明之較佳實施例中，驅動晶片係經過測試無誤後， 才配置於晶片安置區1 〇6與406上。 綜上所述，在本發明之電路板與佈局方法因在第二部分電 性通路與第一接腳其中至少一者之間不設置任一第一部份電 性通路，因此將可縮減第一部分電性通路之範圍，並將空出之 區域用於設置第二部分電性通路，以達到空間的妥善利用。另 春外，又因將第一部份電性通路中的電源線寬度加寬，因此可以 擴大散熱面積。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍 内，當可作些許之更動與潤飾，因此本發明之保護範圍當視後 附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1繪示本發明一實施例之電路板之繞線示意圖。 • 圖2繪示本發明另一實施例之電路板之繞線示意圖。 圖3繪示本發明一實施例之佈局方法之步驟流程圖。 圖4繪示本發明又-實施例之電路板之燒線示意圖。 圖5綠示本發明又-實關之佈局方法之倾流程圖。 圖ό繪示習知之電路板之繞線示意圖。 【主要元件符號說明】 100、400、600 :電路板 102、402、602 :第一接腳區 104、404、604 :第二接腳區 11 201116177 106、406、606 :晶片安置區 108、608 :繞線區 110、410、610 :第一部份電性通路 112、114、412、612、614 :第二部份電性通路 116、416、616 :第三部份電性通路 118、418 :節省區域 S302〜S304 :各個步驟流程 S502〜S514 :各個步驟流程In this embodiment, FIG. 2 differs from FIG. 1 in that FIG. 2 removes the first pin 1G2 originally used for the test drive wafer or the unused one, that is, only after the assembly of the future circuit board 100 is completed. The first pin used is 1〇2. The design can be such that there is an unused area between the two first pins 1〇2, so the layout staff can arrange the second part of the electrical path 112 to the unused area to achieve sufficient space. Use of the target. The longitudinal width of the saving area 118 obtained by using the configuration shown in FIG. 2 will be slightly smaller than the longitudinal width of the first leg 602 and the first partial electrical path _ in FIG. 6, please refer to FIG. The relationship between the steps of the layout method of an embodiment of the present invention is simplified. Among them, this layout method can be applied to the electric board of Fig. 2 . Referring to FIG. 3 and FIG. 3, in the present embodiment, first, a plurality of first-pins 102 are provided on the circuit board 100 to connect the circuit board on which the controller is disposed (step S302). Next, a plurality of second pins 104 are provided on the circuit board 1 to connect the display area circuits (step S3〇4). Next, a wafer placement area is provided on the circuit board to accommodate the drive and be electrically coupled to the drive wafer (step = 06). Then, the winding area 1〇8 is provided on the rotating plate 1 to electrically connect (step S308). After the step S308, the first pin is disconnected from the wafer seating area 1〇6' to form the first electrical path 110 (step S3i). It is: owed, the pin 104 and the wafer placement area 106 to form the second electrical paths ι 2 and ι 4 (step S312). On the other hand, at least one of the second partial electrical path ιΐ2 and the ιΐ4 pin footer U)2 is not provided with any of the first partial electrical contacts (step S314). 201116177 = Refer to 4''''''''''''' The circuit board is electrically connected between the two circuits and includes a plurality of legs 402, a plurality of second pins 4〇4 and a wafer placement strip. Among them, the skilled artisan can easily know that the two circuits can be respectively displayed on the printed circuit board and the display area circuit of the display, but are not limited thereto. In this embodiment, the first pin is electrically coupled to one of the two circuits, and the electrical system can be, for example, a pad. The second pin 404 is a 1 circuit; the other 2 and the second pin 4. 4 can be, for example, a pin for measuring the operation of the S i, and after the board is assembled, the second Pin 4〇4 will be cut. For setting up a circuit chip, as the skilled person:: the chip can be, for example, a scan line or a data line of the display. In this embodiment, the t-way board 400 is used by a single tablet. Between the 406, a first portion of the electrical s-way will be formed between = Γ 4 (the junction 4 will form a second electrical electrical path: ί: 404 will form a third portion Ύ first. One end of the electrical path 410 is a lightning correction! The part of the 7 is used to receive the printed circuit of the controller = the incoming call (such as a control signal or a timing signal), and the ί 412 ^414 ^ area 406, The other end is electrically connected to the second electrical path 412 and 414 for the output of the two signals and the signal signal output to the display circuit. The third electrical path 416 " The other end is connected to the first pin 402, and the other end is coupled to the second pin 404 for transmitting the signal outputted by the controller (not shown) through the third partial electrical path 416. To the display area circuit. ° The first part of the electrical path 410 includes a plurality of power lines 42. In order to make the power line 420 sufficiently dissipate heat, the electricity is The width of the source line 42 is widened to increase the heat dissipation area. Thus, the power line 420 will not be burnt or broken due to overheating. In a preferred embodiment of the invention, the area of the board 4 can be compared The conventional circuit board is small, and the reduced longitudinal extent of the reduced area 418 is approximately equivalent to the distance from the upper edge of the wafer seating area 606 of FIG. 6 to the upper edge of the second partial electrical path 612 and 614. In the preferred embodiment of the present invention, the wafer buffer region 4〇6 is, for example, a slot for driving a chip or a plurality of through holes for receiving a driving wafer on the circuit board 400. Referring to FIG. 5, it is not shown in FIG. A step-by-step private diagram of the layout method of an embodiment. This allows the layout method to be applied to the circuit board of FIG. 4. Referring to FIG. 4 and FIG. 5 together, in the present embodiment, it is first in the circuit board. A plurality of first pins 402 are provided to connect the circuit board configured with the controller (step S502). Secondly, a plurality of second pins 4〇4 are provided on the circuit board 4〇〇 to connect the display area circuit with φ (Step S5〇4). Next, provided on the circuit board 400 The chip placement area 4〇6 is adapted to receive the driving blade and is fixed thereon for electrically coupling with the driving chip (step S506). Then, the winding area is provided on the circuit board 4〇〇. 8. Arranging a plurality of electrical paths (step S508). After step S508, the first pin 4〇2 and the wafer placement area 4〇6 are connected to form a first electrical path 41〇 (step S51〇). Next, the first pin 404 and the 0-day female device are connected to form a second electrical path 4丨2 (step S312). The width of the power line 42〇 in the first electrical path 41〇 is added, 201116177 To increase the heat dissipation area (step S514). In the preferred embodiment of the invention, the circuit boards 1 and 400 may be, for example, flexible printed circuit boards. In a preferred embodiment of the invention, the driver wafers are placed on the wafer placement areas 1 〇 6 and 406 after being tested. In summary, the circuit board and the layout method of the present invention are not provided with any first partial electrical path between at least one of the second partial electrical path and the first pin, and thus the A part of the range of the electrical path, and the vacated area is used to set the second part of the electrical path to achieve the proper use of space. In addition, in addition to the spring, the width of the power line in the first part of the electrical path is widened, so that the heat dissipation area can be enlarged. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a winding of a circuit board according to an embodiment of the present invention. FIG. 2 is a schematic view showing the winding of a circuit board according to another embodiment of the present invention. 3 is a flow chart showing the steps of a layout method according to an embodiment of the present invention. 4 is a schematic view showing a firing line of a circuit board according to still another embodiment of the present invention. Fig. 5 is a green flow chart showing the layout method of the present invention. The figure shows a schematic diagram of the winding of a conventional circuit board. [Main component symbol description] 100, 400, 600: circuit board 102, 402, 602: first pin area 104, 404, 604: second pin area 11 201116177 106, 406, 606: wafer placement area 108, 608 : winding area 110, 410, 610: first partial electrical path 112, 114, 412, 612, 614: second partial electrical path 116, 416, 616: third partial electrical path 118, 418 : Saving area S302~S304: each step flow S502~S514: each step flow
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