201115632 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種碳化矽半導體裝置之製造方法，尤 其關於一種將不純物離子注入碳化矽基板後之活化熱處 理。 【先前技術】 相較於矽半導體，因爲碳化矽半導體具有下列優異的 特徵—絕緣破壞電壓較大、能隙（band gap)較廣，另外，熱 傳導係數較高等，期待應用於發光元件、大電力功率裝置、 耐高溫元件、耐放射性元件、高頻元件等。 爲了使用上述碳化矽半導體而形成元件（SiC半導體元 件），例如，在碳化矽基板（SiC基板）上形成作爲半導體 兀件之活性區域的晶晶成長層’在此晶晶成長層所選擇的 區域，控制導電型或載子濃度將成爲必要。因此，藉由將 不純物摻雜原子部分注入活性區域之磊晶成長層中而形成 P型或η型之各種不純物摻雜區域，使構成電晶體或二極 體等之半導體元件將成爲可能。 然而，爲了使碳化矽基板之活性區域中所注入的不純 物活化，必須進行非常高溫下之退火處理（例如，1600°C 〜2000°C )。已知藉由於此高溫下之退火處理，碳化矽基 板表面之Si原子將氣化而使表面碳（以下記錄爲C )形成 活化（rich)，表面不平整或堆積將發生，對元件之特性造成 不良影響。因而，使用如此之表面碳化矽基板即使形成電 晶體或二極體，也具有難以得到從SiC原本優越之物性而 得到如所期待的電特性之問題。 -4- 201115632 因此’提出一種能夠抑制碳化矽基板之表面不平整的 高溫退火處理方法（專利文獻1〜3)。具體而言，於專利 文獻1中’揭示一種高溫退火處理方法，其係藉由將類鑽 碳（DLC )膜或有機膜作爲保護膜，堆積於成爲活性區域 之磊晶層上而進行活化退火（活化熱處理）來抑制SiC基 板之表面不平整。 於專利文獻2中，揭示一種高溫退火處理方法，其係 藉由使形成於活性區域上之阻抗層碳化後之膜，將該膜作 爲保護膜而進行活化退火，來防止表面不平整之發生。 另外，於專利文獻3中，揭示一種高溫退火處理方法， 其係藉由在活性區域上形成因濺鍍所得到的碳膜而作爲保 護膜使用，且規定此碳膜之純度來防止因活化退火所造成 的表面不平整之發生。 專利文獻1 :日本專利特開2001 -68428號公報 專利文獻2 :日本專利特開2007-28 1005號公報 專利文獻3 :日本專利特開2005 -35 377 1號公報 【發明內容】 發明所欲解決之技術問題 在上述之專利文獻1〜3中所揭示的發明中，於活化熱 處理的高溫退火處理之前，僅在碳化矽基板之表面（活化 面或矽磊面）長成保護膜。然而，此情形下，僅在碳化矽 基板之表面側存在起因於保護膜與碳化矽基板之熱膨脹係 數不同的熱應力；在背面則不存在如此之熱應力。另外， 201115632 雖然碳化矽基板之表面側受到保護膜的殘留應力（內部應 力）之影響，在無保護膜之背面側則無如此之影響。如此 方式，僅在碳化矽基板之表面長成保護膜之情形下，由於 因成膜所造成的應力非對稱地存在於基板之雙面，起因於 此，於高溫之活化退火時基板之彎曲將發生。另外，如後 所詳述，僅在碳化矽基板之表面側具有保護膜之情形，由 於在碳化矽基板之表面與背面所加熱的形態不同，在表面 與背面發生溫差，此溫差導致熱膨脹之差，成爲基板彎曲 之起因。尤其，基板之彎曲係基板越大口徑化會變得越顯 著。 再者，如碳化矽基板之背面電極等，背面也發揮作爲 元件之功能而利用之情形，必須也抑制碳化矽基板背面側 之表面不平整。 因爲本發明係有鑑於上述事實所完成者，目的在於提 供一種碳化矽半導體裝置之製造方法，其不僅抑制因高溫 之退火處理所造成的表面不平整及堆積，也抑制基板之彎 曲，一面保持高的不純物活化率，也一面具有較習知還平 滑之碳化矽的表面。 解決問題之技術手段 於第1圖，針對僅在碳化矽基板之單面具有保護膜（碳 膜）之情形及在雙面具有之情形，因輻射熱所導致的基板 加熱之槪念圖。 於第1圖，符號1係具備保護膜之碳化矽基板，符號 201115632 2係基座，符號2A係基座主體，符號2B係基座蓋，符號 2a係試料台。 在退火爐內，熱處理碳化矽基板1之際，僅在單面形 成有保護膜之情形，在具有保護膜之面（表面）上，來自 基座2之輻射熱首先被保護膜所吸收而使保護膜加熱，藉 由來自此所加熱的保護膜之熱傳導而使表面被加熱。針對 於此，無保護膜之面（背面）之情形，由於碳化矽基板1 係半透明，輻射熱將穿透背面。因此，背面之加熱係從表 面經由基板內而傳導的熱所進行。如此方式，在有或無碳 化矽基板1的保護膜之面所加熱的形態不同，使得起因於 此而在雙面產生溫差。因爲按照此溫差而使各自面側的熱 膨脹產生差異，如上所述成爲於高溫退火時基板彎曲之起 因。 另一方面，在碳化矽基板1之雙面具有保護膜之情 形’因爲藉由面所進行的加熱形態無差異，使基板之均一 加熱成爲可能。 本發明係提供以下之手段：（1 ) 一種碳化矽半導體裝 置之製造方法，其係在碳化矽基板之表面具備不純物摻雜 區域的碳化矽半導體裝置之製造方法，其特徵爲依序實 施：在碳化矽基板之表面注入不純物離子之步驟；在該碳 化矽基板之表面與背面長成碳膜之步驟；將該碳膜作爲保 護膜而活化熱處理該碳化矽基板之步驟；及於進行該活化 熱處理之步驟後，去除該表面與背面的碳膜之步驟。（2) 201115632 揭示於該（η之碳化矽半導體裝置之製造 膜爲藉由濺鍍法或CVD法所成膜的碳膜、 膜、或是碳化有機膜而形成的碳膜中任一; 該（1)或（2)之碳化矽半導體裝置之製 活化熱處理係加熱溫度爲1600〜2000 °C下 於該（1)至（3)中任一項之碳化矽半導 法，其中該活化熱處理係依照高頻加熱法 空熱電子撞擊法中任一種所進行的加熱。 (5 )揭示於該（1 )至（4 )中任一項 裝置之製造方法，其中於氬氣環境或1x10 環境中進行該活化熱處理。 [發明之效果] 將不純物離子注入碳化矽基板後，即 化熱處理，基板之彎曲將受到抑制。此效 基板特別有效。另外，因爲基板之背面也 而爲平滑，如背面電極等，背面也能夠發 而使用。 【實施方式】 以下，針對適用本發明之一實施形態 裝置的製造方法，利用圖面而詳加說明。 說明中所用之圖面係爲了容易了解特徵， 大成爲特徵的部分之情形，各構造要件之 際不一定相同。 方法，其中該碳 DLC (類鑽碳） 重。（3 )揭示於 造方法，其中該 進行。（4 )揭示 體裝置之製造方 、燈加熱法、真 之碳化矽半導體 —2Pa以下之減壓 使進行高溫之活 果對於大口徑之 抑制表面不平整 揮作爲元件功能 的碳化矽半導體 還有，於以下之 方便上而具有放 尺寸比例等與實 201115632 第2 ( a )〜（d )圖係顯示本實施形態之碳化矽半導體 裝置的製造方法之步驟剖面圖。本實施形態之碳化矽半導 體裝置的製造方法係具備下列步驟所槪略構成：在碳化矽 基板之表面注入不純物離子之步驟（不純物注入步驟）、 在碳化矽基板之雙面長成碳膜之步驟（保護膜形成步驟）、 將碳膜作爲保護膜而活化熱處理碳化矽基板之步驟（活化 熱處理步驟）、及去除碳膜之步驟（保護膜去除步驟）； 依序實施此等之步驟，製造在碳化矽基板之表面具備不純 物摻雜區域之碳化矽半導體裝置之方法。 (不純物注入步驟） 首先’於不純物注入步驟中，將不純物注入碳化矽基 板之表面。具體而言，首先如第2(a)圖所示，將使η型 磊晶層2成長於η +型碳化矽基板3上的磊晶基板1作爲碳 化矽基板使用。此磊晶基板1較佳爲例如Ra < 1 nm以下之 表面粗糙度小的平滑表面。 接著’在磊晶層之表面上形成不純物離子注入用之遮 罩。此遮罩係覆蓋磊晶層之表面的一部分，藉由不純物離 子注入而在欲形成p型區域（不純物區域）之區域設置有 開口部。然後，爲了從此開口部所露出的磊晶層之表面層 中形成P型區域之不純物離子，例如使用6種加速電壓而 多段注入鋁（A1)離子6。具體而言，進行將加速電壓設爲 240kV、150kV、95kV、5 5kV、27kV、10kV 之合計 6 段的離 子注入（6段注入法）。另外，所注入的A1濃度，例如設 201115632 爲2xl019cnT 3或2xl02°cnT 3。藉由如此之不純物注入步驟， 如圖所示形成不純物離子注入層。 (保護膜形成步驟） 接著，如第2(b)圖所示，於保護膜形成步驟中，在 磊晶基板（碳化矽基板）之表面及背面長成碳膜4、5。具 體而言，首先去除用於不純物離子注入之遮罩。接著，將 作爲保護膜之碳膜形成於磊晶基板之表面及背面的雙面。 作爲保護膜之碳膜4、5能夠使用藉由濺鍍法或CVD 法所進行的成膜、或是藉高頻電漿CVD法等所得到的DLC (類鑽碳）膜所進行的成膜、或是使用使阻劑等之有機膜 碳化之碳膜等。 於藉由濺鍍法或CVD法所進行的成膜中，碳膜之膜厚 較佳爲10〜500nm，更佳爲30〜200nm，特別理想爲50〜 150nro。若碳膜之膜厚低於10nm時，於所後述之活化熱處 理步驟中，由於作爲保護膜之機能不充分而不佳。另外， 若碳膜之膜厚超過500nm時，由於基板中發生彎曲或裂開 而不佳。再者，由於所後述的保護膜去除步驟中，碳膜之 去除將變得困難而不佳。另一方面，若碳膜之膜厚爲上述 範圍的話，由於活化熱處理之際，基板中不會發生彎曲或 裂開，能夠抑制從磊晶基板1之表面的Si原子的昇華，同 時也於保護膜去除步驟中，使去除變得容易而較佳。 碳膜4、5係例如進行如下之方式，成膜於磊晶基板（碳 化矽蕋板）之表面及背面。 -10- 201115632 藉由濺鍍法所進行的長成碳膜之情·形，最 板1之表面側朝向濺鍍源側，將背面側連接於 的方式來設置，在表面側長成碳膜。之後，反 背面側朝向濺鎪源側，將表面側連接於基板載 來設置，在背面側進行成膜。 藉由CVD法所進行的長成碳膜之情形，最 板1之表面側朝向氣相反應氣體環境側（電 側），將背面側連接於基板載置側的方式來設 側長成碳膜。之後，反轉基板而將背面側朝向 體環境側（電漿氣體環境側），將表面側連接 側的方式來設置，在背面側進行成膜。 另外，使阻劑等之有機膜碳化的碳膜之情 基板1之表面側與背面側的雙面，將有機膜塗辛 利用既定之條件進行烘烤，之後，於氬氣環境之 利用既定之加熱條件進行碳膜形成。 (活化熱處理步驟） 接著，如第2 ( c )圖所示，將碳膜4、5作 膜，進行磊晶基板1之活化熱處理而形成不 域。活化熱處理係藉由低於1 X 1 〇_ 2Pa之真空退 行。加熱溫度較佳爲1 600〜2000 °C之範圍，更 1 900°C之範圍，最好爲1700〜1 8 50t之範圍。 低於1 600°C時，所注入的不純物之活化將變得 佳。另外，若超過2000°C時，即使具有保護膜 1之表面也將碳化，由於具有表面不平整之可倉Ϊ 初將磊晶基 基板載置側 轉基板而將 置側的方式 初將晶晶基 獎氣體環境 置，在表面 氣相反應氣 於基板載置 形’在晶晶 ί成約3μπΐ， .加熱爐中， 爲雙面保護 純物摻雜區 火方式來進 佳爲1 700〜 若加熱溫度 不充分而不 •晶晶基板 j性而不佳。 -11 - 201115632 另外，加熱時間較佳爲以1〜1 0分鐘進行，更佳爲以1 〜7分鐘進行，特別理想爲以1〜5分鐘進行。若加熱時間 少於1分鐘時，由於不純物之活性化變得不充分而不佳。 另外，若加熱時間超過1 0分鐘時，即使具有保護膜，磊晶 基板之表面也將碳化，由於具有表面不平整之可能性而不 佳。 (保護膜去除步驟） 接著’如第2(d)圖所示，去除作爲保護膜使用之碳 膜。碳膜之去除係藉由氧氣環境之熱氧化而灰化碳膜來去 除。具體而言，將基板設置於熱氧化爐內，例如，藉由供 應流量3.5L/min之氧氣，利用1 125°C、加熱90分鐘之條 件，能夠去除磊晶層2及不純物離子注入層7上的碳膜4 及磊晶基板背面的碳膜5。 還有，磊晶基板1能夠在氧化爐內之基板載置上（石 英小舟等），使基板雙面充分曝露於氧氣環境的方式來設 置，同時灰化基板雙面之碳膜而去除。還有，於本實施形 態中，鋁之活化率約爲8 0 %，進行充分之活化。藉由如此 之保護膜去除步驟，能夠具有如第1圖所示之高活化率的 不純物摻雜層8，同時也製造表面爲平滑之碳化矽半導體 基板（晶圓）。然後，在含有如此表面的碳化矽半導體基 板上_藉由形成例如蕭特基（Schottky )二極體而能夠製造 碳化矽半導體基板。 -12- 201115632 還有，本發明之技術範圍並不受上述實施形態 定，於不脫離本發明主旨之範圍內，增加各種的變更 能。例如，於本實施形態中，雖使用減壓方式之加熱 進行活化熱處理步驟，也可以使用氬（Ar )等之惰性 環境的加熱爐。另外，加熱方式可以使用燈加熱或高 式，也可以使用電子線加熱方式。 另外，於本實施形態中，雖然利用熱氧化而去除碳 藉由使用氧之電漿處理或臭氧處理也能夠去除碳膜。 [實施例1] 以下，利用實施例而具體說明本發明之效果。還 本發明並不受此等實施例所限定。 對S i C單晶晶圓之磊晶膜的成長係使用高頻感應 方式之橫型 CVD( Chemical Vapor Deposition:化學氣 積）裝置而進行。 具體而言，將S i C單晶晶圓水平配置於基座上 200mbar之氫氣減壓環境中，升溫直到1 620°C，長成 8μηι之SiC磊晶膜。將氫氣作爲載氣使用，將SiH4與 之混合氣體作爲原料氣體使用。 進行如此方式，在直徑3吋且厚度3 80μιη之SiC 基板上，製作成膜厚度8 μιη之磊晶膜的磊晶基板。 接著，在此直徑3吋之SiC磊晶基板上，進行A1 之注入。A1離子之注入條件係利用6段注入法（加速 240k V ' 150kV、95kV、55kV' 27kV、10 kV 之合計 6 段 所限 爲可 爐而 氣體 頻方 膜， 有， 加熱 相沉 ，於 厚度 C3H8 單晶 離子 電壓 匕）0 -13- 201115632 還有，注入後之A1濃度爲2xl019cnT3。 A1離子之注入後，藉由使阻劑塗布膜碳化之碳膜而將 碳膜成膜於上述SiC基板之表面及背面的雙面。上述條件 係最初在SiC基板之表面塗布約3μιη之阻抗膜後，進行烘 烤處理，接著，在SiC基板之背面塗布約3μιη之阻抗膜後， 進行烘烤處理。 其後，利用以下之條件而進行碳化處理。 碳化處理之條件係於氬氣環境中，於1小時內，使溫 度從室溫升溫直到80(TC，接著於800°C保持10分鐘，之 後，使其降溫約7小時而直到室溫爲止。 接著，使用真空退火爐而減壓至5xl0_4〜5xlO_3Pa以 下，利用溫度1 830°C、保持時間5分鐘之條件下，進行不 純物之活化熱處理。最後，藉由氧氣環境之熱氧化（1125 t、90分鐘），去除灰化碳膜，製造實施例1之碳化矽半 導體裝置。 (基板之彎曲的結果） 針對上述實施例1之3吋碳化矽半導體裝置（本發 明）、與利用相同於實施例1的製造條件而僅在單面具有 碳膜之3吋碳化矽基板（習知例），藉由基板平坦度測定 器（製造商名：Corning Tropel公司、裝置名：Ultra Sort)， 測定「彎曲」及「WARP」。於第3圖，顯示實施例1之結 果0 -14- 201115632 於習知例中，相對於退火前之「彎曲」及「WARP」分 別爲 26.215μιη、27·215μιη，退火後則分別爲 76.293 μιη、 76.377 μιη，確認退火前後之基板的彎曲。 另一方面，本實施例之情形，退火前之「彎曲」及 「WARP」分別爲1 5.593 μπι、14.408μιη，退火後則分別爲 1 6.49 8 μιη、14.001μηι，能夠確認已抑制於退火前後之基板 的彎曲。 (基板表面及背面之表面狀態的結果） 將依照上述實施例1之3吋碳化矽半導體裝置之表面 與背面的原子力顯微鏡（AFM )觀察所得到的表面形態 (Rins )之結果顯示於第 4圖。第 4圖之掃描面積爲 2μιη>:2μιη。另外，高度之尺寸已揭示於圖中。基板之表面 及背面的Rms任一種皆爲0.3nm以下，針對背面，能夠確 認與表面同程度之表面不平整抑制效果》 [產業上利用之可能性] 本發明之碳化矽半導體裝置的製造方法能夠利用於碳 化矽半導體裝置之製造，其不僅抑制因高溫退火處理所造 成的表面不平整及堆積，也抑制基板之彎曲，一面保持高 的不純物活化率，一面具有較習知還平滑之碳化矽的表 面。尤其，因爲相對於大口徑之基板，於活化熱處理後也 能夠保持無基板彎曲之狀態，特別有效於使用大口徑基板 之碳化矽半導體裝置的製造。另外，也能夠利用於碳化矽 基板之背面也發揮作爲元件機能所利用的碳化矽半導體裝 置之製造。 -15- 201115632 【圖式簡單說明】 第1圖係針對僅在碳化矽基板之單面長成保護膜之情 形、與在雙面成膜之情形，因輻射熱所導致的基板加熱之 槪念圖。 第2 ( a )〜（d )圖係顯示本實施形態之碳化矽半導體裝 置的製造方法之步驟剖面圖。 第3圖係顯示3吋碳化矽基板之退火前後的彎曲與WARP 的測定結果之圖形。 第4圖係顯示碳化矽基板之表面與背面之藉由原子力顯 微鏡（AFM )觀察所得到的表面形態結果$ ® ° 【主要元件符號說明】 1 磊晶基板 2 磊晶層 3 碳化矽基板 4 表面之碳膜 5 背面之碳膜 6 不純物離子 7 不純物離子注入層 B 不純物摻雜層 -16 -BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a tantalum carbide semiconductor device, and more particularly to an activation heat treatment after ion implantation of impurities into a tantalum carbide substrate. [Prior Art] Compared with germanium semiconductors, tantalum carbide semiconductors have the following excellent characteristics: large dielectric breakdown voltage, wide band gap, and high heat transfer coefficient, etc., and are expected to be applied to light-emitting elements and large power. Power devices, high temperature resistant components, radioactive components, high frequency components, etc. In order to form an element (SiC semiconductor element) using the above-described tantalum carbide semiconductor, for example, a crystal growth layer as an active region of a semiconductor element is formed on a tantalum carbide substrate (SiC substrate), and a region selected by the crystal growth layer is selected. It is necessary to control the conductivity type or carrier concentration. Therefore, by implanting the impurity-doped atomic portion into the epitaxial growth layer of the active region to form various impurity-doped regions of the P-type or the n-type, semiconductor elements constituting the transistor or the diode or the like are made possible. However, in order to activate the impurities implanted in the active region of the tantalum carbide substrate, annealing treatment at a very high temperature (for example, 1600 ° C to 2000 ° C) must be performed. It is known that by the annealing treatment at this high temperature, Si atoms on the surface of the tantalum carbide substrate will be vaporized to cause surface carbon (hereinafter referred to as C) to form a rich (rich) surface unevenness or accumulation, which causes a characteristic of the element. Bad effects. Therefore, even if a crystal or a diode is formed using such a surface tantalum carbide substrate, it is difficult to obtain a desired electrical property from the original physical properties of SiC. -4- 201115632 Therefore, a high-temperature annealing treatment method capable of suppressing surface unevenness of the tantalum carbide substrate has been proposed (Patent Documents 1 to 3). Specifically, in Patent Document 1, a high-temperature annealing treatment method is disclosed which performs activation annealing by depositing a diamond-like carbon (DLC) film or an organic film as a protective film on an epitaxial layer which becomes an active region. (Activation heat treatment) to suppress surface unevenness of the SiC substrate. Patent Document 2 discloses a high-temperature annealing treatment method in which a film which is carbonized by a resistive layer formed on an active region is used as a protective film to perform activation annealing to prevent surface unevenness from occurring. Further, Patent Document 3 discloses a high-temperature annealing treatment method which is used as a protective film by forming a carbon film obtained by sputtering on an active region, and specifies the purity of the carbon film to prevent activation annealing. The resulting surface irregularities occur. Patent Document 1: Japanese Laid-Open Patent Publication No. 2001-68428 Patent Document 2: Japanese Patent Laid-Open Publication No. Hei No. Hei. No. Hei. No. Hei. Technical Problem In the inventions disclosed in the above-mentioned Patent Documents 1 to 3, the protective film is formed only on the surface (activated surface or surface of the tantalum carbide) of the tantalum carbide substrate before the high-temperature annealing treatment of the activation heat treatment. However, in this case, only the thermal stress due to the thermal expansion coefficient of the protective film and the tantalum carbide substrate is present on the surface side of the tantalum carbide substrate; such thermal stress does not exist on the back surface. In addition, 201115632, although the surface side of the tantalum carbide substrate is affected by the residual stress (internal stress) of the protective film, there is no such influence on the back side of the non-protective film. In this way, in the case where the surface of the tantalum carbide substrate is grown into a protective film, since the stress caused by the film formation is asymmetrically present on both sides of the substrate, the bending of the substrate at the time of the high-temperature activation annealing will be caused. occur. Further, as will be described in detail later, in the case where the protective film is provided only on the surface side of the tantalum carbide substrate, the temperature difference between the surface and the back surface is different due to the difference in the form of heating on the surface and the back surface of the tantalum carbide substrate, and the temperature difference causes the difference in thermal expansion. It becomes the cause of the bending of the substrate. In particular, the larger the diameter of the curved substrate of the substrate, the more remarkable the diameter. Further, in the case where the back surface of the tantalum carbide substrate or the like is used as a function of the element, it is necessary to suppress unevenness of the surface on the back side of the tantalum carbide substrate. The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for manufacturing a niobium carbide semiconductor device which not only suppresses surface unevenness and deposition due to annealing treatment at a high temperature, but also suppresses bending of a substrate while maintaining high The rate of impure activation is also on the surface of a conventionally smoother tantalum carbide. Means for Solving the Problem In the first embodiment, a case where the protective film (carbon film) is provided on one side of the tantalum carbide substrate and the case where it is provided on both sides, the substrate is heated due to radiant heat. In Fig. 1, reference numeral 1 denotes a ruthenium carbide substrate provided with a protective film, a symbol 201115632 2 pedestal, a symbol 2A pedestal body, a symbol 2B pedestal cover, and a symbol 2a is a sample stage. In the annealing furnace, when the tantalum carbide substrate 1 is heat-treated, a protective film is formed only on one side, and on the surface (surface) having the protective film, the radiant heat from the susceptor 2 is first absorbed by the protective film to protect The film is heated and the surface is heated by heat conduction from the heated protective film. For this reason, in the case of the surface (back side) without the protective film, since the tantalum carbide substrate 1 is translucent, radiant heat will penetrate the back surface. Therefore, the heating of the back surface is performed by the heat conducted from the surface through the inside of the substrate. In this manner, the form of heating on the surface of the protective film with or without the ruthenium carbide substrate 1 is different, so that a temperature difference occurs on both sides due to this. Since the difference in thermal expansion between the respective surface sides is caused by this temperature difference, as described above, the substrate is bent at the time of high temperature annealing. On the other hand, in the case where the both sides of the tantalum carbide substrate 1 have a protective film, since there is no difference in the heating form by the surface, uniform heating of the substrate is possible. The present invention provides the following means: (1) A method of manufacturing a niobium carbide semiconductor device, which is a method for manufacturing a niobium carbide semiconductor device having an impurity doped region on a surface of a tantalum carbide substrate, which is characterized in that: a step of implanting impurities on the surface of the tantalum carbide substrate; a step of growing a carbon film on the surface and the back surface of the tantalum carbide substrate; a step of activating the heat treatment of the tantalum carbide substrate by using the carbon film as a protective film; and performing the activation heat treatment After the step, the carbon film on the surface and the back surface is removed. (2) 201115632 discloses that (the production film of the yttrium carbide semiconductor device is any one of a carbon film formed by a sputtering method or a CVD method, a film, or a carbonized organic film; The activation heat treatment of the tantalum carbide semiconductor device of (1) or (2) is a carbonization germanium semiconducting method according to any one of (1) to (3), wherein the activation heat treatment is performed at a heating temperature of 1600 to 2000 °C. A heating method according to any one of the high-frequency heating method, wherein the apparatus of any one of (1) to (4) is disclosed in an argon atmosphere or a 1x10 environment. [The effect of the invention] When the impurity is ion-implanted into the tantalum carbide substrate, the heat treatment is performed, and the bending of the substrate is suppressed. This effect substrate is particularly effective. In addition, since the back surface of the substrate is also smooth, such as the back electrode [Embodiment] Hereinafter, a manufacturing method to which an apparatus according to an embodiment of the present invention is applied will be described in detail with reference to the drawings. The drawings used in the description are for easy understanding of features, and are large. In the case of a part of the feature, the structural elements are not necessarily the same at the time. The method wherein the carbon DLC (the diamond-like carbon) is heavy. (3) is disclosed in the method of manufacture, wherein the process proceeds. (4) The manufacturer of the device is disclosed. , the lamp heating method, the true carbonization of the ruthenium semiconductor - the decompression of 2Pa or less, the high-temperature effect of the fruit for the suppression of the large-diameter surface unevenness as a component of the function of the niobium carbide semiconductor, also has the following size In the second embodiment, the second embodiment of the present invention is a cross-sectional view showing the method of manufacturing the niobium carbide semiconductor device of the present embodiment. The method for manufacturing the niobium carbide semiconductor device of the present embodiment has the following steps. Slightly configured: a step of implanting impurity ions on the surface of the tantalum carbide substrate (impurity injection step), a step of growing a carbon film on both sides of the tantalum carbide substrate (protective film forming step), and a carbon film as a protective film to activate heat treatment carbonization a step of ruthenium substrate (activation heat treatment step), and a step of removing carbon film (protective film removal step); a method of manufacturing a niobium carbide semiconductor device having an impurity-doped region on a surface of a tantalum carbide substrate. (Impurity Injection Step) First, in the impurity injecting step, impurities are implanted into the surface of the tantalum carbide substrate. Specifically, first, As shown in Fig. 2(a), the epitaxial substrate 1 on which the n-type epitaxial layer 2 is grown on the η + -type tantalum carbide substrate 3 is used as a tantalum carbide substrate. The epitaxial substrate 1 is preferably Ra < A smooth surface with a small surface roughness of 1 nm or less. Next, a mask for imperfect ion implantation is formed on the surface of the epitaxial layer. This mask covers a portion of the surface of the epitaxial layer, and is implanted by impurity ion implantation. An area in which a p-type region (impurity region) is to be formed is provided with an opening portion. Then, in order to form impurity ions of the P-type region from the surface layer of the epitaxial layer exposed from the opening, for example, aluminum (A1) ions 6 are implanted in multiple stages using six kinds of accelerating voltages. Specifically, ion implantation (six-stage injection method) in which the acceleration voltage is set to a total of six stages of 240 kV, 150 kV, 95 kV, 55 kV, 27 kV, and 10 kV is performed. Further, the injected A1 concentration is, for example, 201115632 being 2xl019cnT 3 or 2xl02°cnT 3 . By such an impurity injecting step, an impurity ion implantation layer is formed as shown. (Protective film forming step) Next, as shown in Fig. 2(b), in the protective film forming step, the carbon films 4 and 5 are grown on the surface and the back surface of the epitaxial substrate (tantalum carbide substrate). Specifically, the mask for impurity ion implantation is first removed. Next, a carbon film as a protective film is formed on both surfaces of the front and back surfaces of the epitaxial substrate. The carbon films 4 and 5 which are protective films can be formed by film formation by a sputtering method or a CVD method, or by a DLC (Drilling Carbon) film obtained by a high frequency plasma CVD method or the like. Or a carbon film obtained by carbonizing an organic film such as a resist or the like. In the film formation by the sputtering method or the CVD method, the film thickness of the carbon film is preferably from 10 to 500 nm, more preferably from 30 to 200 nm, particularly preferably from 50 to 150 nro. When the film thickness of the carbon film is less than 10 nm, it is not preferable because the function as a protective film is insufficient in the activation heat treatment step to be described later. Further, when the film thickness of the carbon film exceeds 500 nm, it is not preferable because bending or cracking occurs in the substrate. Further, in the protective film removing step to be described later, the removal of the carbon film becomes difficult. On the other hand, when the film thickness of the carbon film is in the above range, bending or cracking does not occur in the substrate during the activation heat treatment, and sublimation of Si atoms from the surface of the epitaxial substrate 1 can be suppressed and protected. In the film removing step, the removal is made easy and preferable. The carbon films 4 and 5 are formed on the surface and the back surface of an epitaxial substrate (carbonized silicon carbide), for example, in the following manner. -10- 201115632 The shape of the carbon film formed by the sputtering method is such that the surface side of the top plate 1 faces the sputtering source side, and the back side is connected to the surface side, and the carbon film is formed on the surface side. . Thereafter, the reverse back side faces the sputter source side, the front side is connected to the substrate, and the film is formed on the back side. In the case where the carbon film is formed by the CVD method, the surface side of the uppermost plate 1 faces the gas phase reaction gas environment side (electric side), and the back surface side is connected to the substrate mounting side to form a side carbon film. . Thereafter, the substrate is reversed, and the back side is placed toward the body environment side (plasma gas environment side), and the front side is connected to the side, and film formation is performed on the back side. In addition, the carbon film which is made of a carbon film such as a resist is used for the both sides of the front side and the back side of the substrate 1, and the organic film is baked by a predetermined condition, and then used in an argon atmosphere. The carbon film is formed under heating conditions. (Activating heat treatment step) Next, as shown in Fig. 2(c), the carbon films 4 and 5 are used as a film, and the epitaxial substrate 1 is subjected to activation heat treatment to form a region. The activation heat treatment is carried out by a vacuum of less than 1 X 1 〇 2 Pa. The heating temperature is preferably in the range of 1 600 to 2000 ° C, more preferably in the range of 1 900 ° C, preferably in the range of 1700 to 1 8 50 t. Below 1 600 ° C, the activation of the implanted impurities will be better. In addition, when it exceeds 2000 ° C, even if the surface of the protective film 1 is carbonized, the surface of the epitaxial base substrate is placed on the side-transferred substrate, and the side is placed on the substrate. The base gas is placed in the gas environment, and the gas phase reaction gas on the surface is placed on the substrate. The crystal is formed in a crystal crystal of about 3μπΐ. In the heating furnace, the double-sided protective pure doping zone is fired in a manner of preferably 1 700~ if heating temperature Insufficient without the crystal substrate j is not good. -11 - 201115632 Further, the heating time is preferably from 1 to 10 minutes, more preferably from 1 to 7 minutes, and particularly preferably from 1 to 5 minutes. If the heating time is less than 1 minute, it is not preferable because the activation of impurities is insufficient. Further, when the heating time exceeds 10 minutes, even if a protective film is provided, the surface of the epitaxial substrate is carbonized, which is not preferable because of the unevenness of the surface. (Protective film removing step) Next, as shown in Fig. 2(d), the carbon film used as the protective film is removed. The removal of the carbon film is removed by oxidizing the carbon film by thermal oxidation of the oxygen environment. Specifically, the substrate is placed in a thermal oxidation furnace. For example, the epitaxial layer 2 and the impurity ion implantation layer 7 can be removed by supplying oxygen at a flow rate of 3.5 L/min and heating at 190 ° C for 90 minutes. The upper carbon film 4 and the carbon film 5 on the back surface of the epitaxial substrate. Further, the epitaxial substrate 1 can be placed on a substrate in an oxidizing furnace (such as a stone boat), and the substrate can be sufficiently exposed to the oxygen atmosphere, and the carbon film on both sides of the substrate can be removed. Further, in the present embodiment, the activation rate of aluminum is about 80%, and sufficient activation is performed. By such a protective film removing step, it is possible to have the impurity-doped layer 8 having a high activation ratio as shown in Fig. 1, and to manufacture a silicon carbide semiconductor substrate (wafer) having a smooth surface. Then, on a tantalum carbide semiconductor substrate having such a surface, a tantalum carbide semiconductor substrate can be manufactured by forming, for example, a Schottky diode. In addition, the technical scope of the present invention is not limited to the above-described embodiments, and various modifications can be added without departing from the spirit of the invention. For example, in the present embodiment, the activation heat treatment step is carried out by heating under reduced pressure, and a heating furnace in an inert environment such as argon (Ar) may be used. In addition, the heating method may be a lamp heating or a high type, or an electron beam heating method. Further, in the present embodiment, carbon is removed by thermal oxidation. The carbon film can be removed by plasma treatment using oxygen or ozone treatment. [Example 1] Hereinafter, the effects of the present invention will be specifically described using examples. The invention is also not limited by these examples. The growth of the epitaxial film of the Si C single crystal wafer was carried out using a high frequency induction type horizontal CVD (Chemical Vapor Deposition) apparatus. Specifically, the SiC single crystal wafer was horizontally placed on a susceptor in a hydrogen decompression atmosphere of 200 mbar, and heated up to 1,620 ° C to grow into a SiC epitaxial film of 8 μm. Hydrogen gas was used as a carrier gas, and a mixed gas of SiH4 and the like was used as a material gas. In this manner, an epitaxial substrate having an epitaxial film having a film thickness of 8 μm was formed on a SiC substrate having a diameter of 3 Å and a thickness of 3 80 μm. Next, an implantation of A1 was performed on the SiC epitaxial substrate having a diameter of 3 Å. The injection condition of A1 ion is limited to 6 burners (acceleration 240k V '150kV, 95kV, 55kV' 27kV, 10 kV total 6 segments is limited to furnace and gas frequency square film, there is, heating phase sink, thickness C3H8 Single crystal ion voltage 匕) 0 -13- 201115632 Also, the A1 concentration after injection is 2xl019cnT3. After the injection of the A1 ions, the carbon film is formed on both surfaces of the surface and the back surface of the SiC substrate by a carbon film in which the resist coating film is carbonized. The above conditions were carried out by first applying a resist film of about 3 μm on the surface of the SiC substrate, followed by baking, and then applying a resist film of about 3 μm on the back surface of the SiC substrate, followed by baking treatment. Thereafter, the carbonization treatment was carried out under the following conditions. The conditions of the carbonization treatment were carried out under an argon atmosphere, and the temperature was raised from room temperature to 80 (TC, followed by maintaining at 800 ° C for 10 minutes in 1 hour, after which it was allowed to cool for about 7 hours until room temperature. Then, using a vacuum annealing furnace, the pressure was reduced to 5×10 −4 to 5×10 −3 Pa or less, and the activation heat treatment of the impurities was carried out under the conditions of a temperature of 1,830° C. and a holding time of 5 minutes. Finally, thermal oxidation by an oxygen atmosphere (1125 t, 90) Minutes), the carbonized carbon film was removed, and the tantalum carbide semiconductor device of Example 1 was produced. (Result of bending of the substrate) The tantalum carbide semiconductor device (invention) of the above-described Example 1 was used in the same manner as in Example 1. The manufacturing conditions were only 3 吋 吋 具有 substrate (conventional example) having a carbon film on one side, and the "bending" was measured by a substrate flatness measuring device (manufacturer name: Corning Tropel, device name: Ultra Sort). And "WARP". In Figure 3, the results of Example 1 are shown in 0 - 14 - 201115632. In the conventional example, the "bending" and "WARP" before annealing are 26.215 μιη, 27·215 μηη, annealing, respectively. Then, 76.293 μm and 76.377 μm, respectively, were used to confirm the bending of the substrate before and after annealing. On the other hand, in the case of the present embodiment, the "bending" and "WARP" before annealing were respectively 1.593 μπι, 14.408 μιη, respectively, after annealing, respectively It is confirmed that the curvature of the substrate before and after the annealing is suppressed by the results of the measurement of the surface state of the substrate before and after the annealing. (Results of the surface state of the surface of the substrate and the back surface) The surface and the back surface of the tantalum carbide semiconductor device according to the above-described Embodiment 1 will be used. The results of the surface morphology (Rins) obtained by atomic force microscopy (AFM) observation are shown in Fig. 4. The scanning area of Fig. 4 is 2 μηη>: 2 μιη. In addition, the height dimension has been disclosed in the figure. Any of Rms is 0.3 nm or less, and it is possible to confirm the surface unevenness suppression effect with respect to the surface on the back surface. [Industrial Applicability] The method for producing a niobium carbide semiconductor device of the present invention can be utilized for a niobium carbide semiconductor The manufacture of the device not only suppresses surface unevenness and deposition caused by high temperature annealing treatment, but also suppresses the substrate Bending, while maintaining a high degree of impurity activation, on the one hand, has a surface that is more conventionally smooth and smoother. In particular, since the substrate with a large diameter can maintain the state of no substrate bending after the activation heat treatment, it is particularly effective for use. The production of the niobium carbide semiconductor device of the large-diameter substrate can also be used for the production of the niobium carbide semiconductor device used as the element function on the back surface of the tantalum carbide substrate. -15- 201115632 [Simplified illustration] Fig. 1 It is a concept for heating the substrate due to radiant heat in the case where the protective film is formed on only one side of the tantalum carbide substrate and in the case where the film is formed on both sides. 2(a) to 2(d) are cross-sectional views showing the steps of the method of manufacturing the niobium carbide semiconductor device of the present embodiment. Fig. 3 is a graph showing the results of the bending before and after annealing of the 3 吋 吋 substrate and the measurement results of WARP. Fig. 4 shows the surface morphology results obtained by atomic force microscopy (AFM) observation of the surface and the back surface of the tantalum carbide substrate. $ ® ° [Key element symbol description] 1 Epitaxial substrate 2 Epitaxial layer 3 Surface of the tantalum carbide substrate 4 Carbon film 5 Carbon film on the back side 6 Impurity ions 7 Impurity ion implantation layer B Impurity doped layer-16 -