TW201108601A - Buffer amplifier - Google Patents

Abstract

A buffer amplifier includes an input stage circuit, an output stage circuit and a bias circuit, providing a buffered output signal at an output terminal according to an input signal applied to a first input terminal. The input stage circuit generates four control signals in response to the input signal when the logic level of the buffered output signal is opposite to that of the input signal. The output stage circuit includes four output transistors, wherein the first and second output transistor of a first type are provided for discharge in response to a first control signal and a second control signal, and the third and fourth output transistor of a second type are provided for charge in response to a third control signal and a fourth control signal. The bias circuit is used for determining the first, second, third and fourth control signal.

Description

201108601 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to buffer amplifiers, and more particularly to buffer amplifiers used with source drivers for display panels. [Prior Art] A flat panel display panel, such as a liquid crystal display panel, is widely used in electronic devices due to its thinness and low power consumption. In general, the gate driver and the source driver are configured to drive the liquid crystal display panel through a plurality of gate lines and source lines. The gate driver continuously supplies the turn-on voltage to its corresponding gate line, and then the source driver provides the gray scale voltage associated with the image data to be displayed to the corresponding source line. In addition, the source driver usually includes an output buffer amplifier for driving each panel negative according to the corresponding gray scale voltage, for example, the load capacitance of the display panel, for charging and discharging to a desired state. However, as the display resolution of the display panel continues to increase, the capacitance value added by each load capacitor will greatly reduce the charge-discharge capability of the wheel-out buffer amplifier, resulting in the rising time and falling of the load capacitance. The falling time increases unexpectedly. As a result, the deterioration of the fall time adversely affects the conversion time required to charge and discharge the load capacitance. Therefore, for the source driver of a large-size display panel, it is necessary to use an improved and optimized buffer driver, which is driven into the source: 201108601 The driving capability of the actuator, and shortens the charge and discharge required for each load capacitor. - rise time and fall time. SUMMARY OF THE INVENTION According to an embodiment of the present invention, a buffer amplifier is provided having a first input terminal, a second input terminal, and an output terminal, including: an input stage circuit, an output stage circuit, and a bias current. road. The output end is coupled to the second input end for generating a buffered output signal at the output end according to the input signal Φ number applied to the first input end. The input stage circuit is coupled between the input end and the output end, and when the logic level of the buffer output signal is opposite to the logic level of the input signal, the fourth control corresponding to the input signal is generated. Signal. The output stage circuit is coupled to the input stage circuit and has a first output transistor and a second output transistor of a first type, and a third output transistor and a fourth output of a second type. Transistor. The first and second output transistors include: a source for receiving a first supply voltage, and a gate for receiving a first control signal and a second control signal, and are coupled to the gate The drain of the output. The third and fourth output transistors include: a source for receiving a second supply voltage, a gate for receiving a third control signal and a fourth control signal, and a common coupling to the output The end of the bungee. The bias circuit is coupled between the input stage circuit and the output stage circuit, and has a plurality of current mirror circuits for determining the first, second, third and fourth control signals. The above described objects, features and advantages of the present invention will become more apparent from the following description. [Embodiment] The following is a preferred embodiment of the present invention. It is intended that the general principles of the present invention are not intended to limit the invention. The scope of protection of the present invention is subject to the definition of the patent application. Fig. 1 is a schematic view showing a display system 1 according to an embodiment of the present invention. The display system 1 shown in Fig. 1 includes a source driver 1 〇 2, a gate driver 1G4, a timing controller 12G, and a display panel, such as a thin film transistor liquid crystal display (TFT_LCD) panel. According to this embodiment, the display panel 106 has a plurality of display units, such as the display unit 108' being arranged in the row formed by the gates 'Gi, G2, ... Gm, and the source lines si, S2... The intersection of the columns formed by the SN is used to form a display array. In operation, the timing controller 12 provides timing signals 132 and 134 to the source driver 1〇2 and the gate driver 1〇4, respectively. For example, the clock signal 132 corresponding to the timing controller 120 is related to the horizontal clock signal H__cl〇ck and the horizontal synchronization signal H_sync, and the image data to be displayed will be sequentially transmitted through the source driver 102. Writes to the display units 108 in succession. In addition to this, the display unit 1 8 includes a liquid crystal cell 122, a thin film transistor TFT, and a storage capacitor Cs. As shown in Fig. 1, the gate and source of the transistor TFT are respectively connected to the idle line gm and the source line ^ of the 201108601. In this case, the transistor wT is like the same switch, and is controlled by the open source I applied by the source driver 102 to the gate line to allow the corresponding gray scale voltage from the source driver 1〇2 to be written. To the liquid crystal cell 122. The gray scale voltage is related to the image data to be displayed. Each of the cs is used as a load capacitor, corresponding to the voltage difference between the gray line and the common voltage VC0M of the source line, for selectively charging or Electricity. Further, according to other embodiments, the capacitance may not be converted to the common voltage vCOM. The liquid crystal cell 122 is coupled in parallel to the memory valley cs. Therefore, the liquid crystal cell 122 displays a shadow corresponding to the voltage difference. The second diagram shows the source driver 2〇2 _ in accordance with the embodiment of Fig. 1. ^ Referring to FIG. 2, the source driver 2〇2 includes: a shift register mode sensitive 216, an latch (iatch; module) 218, a level shifter, and a digital to _ • ratio (D/A) converter. 222 and the balance amplifier 23 〇. In operation, the shift register module 216 has a plurality of shift registers, according to the clock controller no, such as the first! As shown, the output clock signal 132 is used to continuously generate the shift pulse 232 required for the RGB signal, wherein the RGB signal 214 is associated with the image data to be displayed. According to this embodiment, the clock signal 132 includes a horizontal clock signal H-cl〇ck and a horizontal sync signal. The latch module 218 has a set of sample latches for latching the RGB signal 214 to synchronize with the shift 201108601 pulse 23.2. The latch module 218 has a set of hold latches that further latch the latched RGB signal 214 to synchronize with the hold signal 234. Next, the level converter 220 converts the output level of the latch module 218 into a high voltage digital signal by a low voltage digital signal. Then, the digital to analog (D/A) converter 222 generates a analog signal Sdata according to the digital signal transmitted by the level converter 220. Thereafter, the analog signal Sdata is supplied to the buffer amplifier 230. After receiving the analog signal Sdata, the buffer amplifier 230 generates the buffered output signal Sout and supplies it to the corresponding source line. For example, as shown in FIG. 1, the buffer amplifier 230 is used to increase the driving capability of the analog signal sdata. The panel load of each of the display units can be successfully driven, and the image data to be displayed is written. In one embodiment, the buffered output signal Sout is used to drive the display unit 108 of the figure to a logic level, which is substantially the same as the logic level of the signal Sdata. In this case, the display unit 108 can switch between a high logic level, a low logic level, or between two levels. In particular, for a large-sized or high-resolution display panel 1〇6, the buffer amplifier 230 enables the charging and discharging to be performed more quickly when the display unit 1G8 is switched from low to high or high to low, (4) Improve the characteristics of the fall time. Fig. 3 is a diagram showing the buffer amplifier 33 shown in Fig. 2 and the original example of the + * 2 figure. 201108601 Please refer to FIG. 3, the buffer amplifier 330 has a first input terminal INP, a second input terminal 1 and a transmission and output terminal OUT. The output terminal OUT is coupled back to the second input terminal INN′ and generates a buffered output signal s〇ut at the output terminal OUT according to the signal embedding applied to the first input terminal INp. In this embodiment, the buffer amplifier 330 includes: Input stage circuit 302, output stage circuit 304 and bias circuit 306. It is worth noting that the buffer amplifier 33 is configured as a unity-gain buffer amplifier. That is, the buffered output signal Sout is substantially equal to the signal Sdata, and the monthly b is sufficient to save unnecessary driving power. As shown in FIG. 3, the wheel-in stage circuit 3〇2 is coupled between the two input terminals INp, INN' and the output terminal OUT. When the logic level of the buffered output signal Scmt of the output terminal OUT is opposite to the logic level of the signal sdata of the first input terminal INP, the input stage circuit 302 will generate four control signals 310, 312, 314 and 316'. The signal Sdata corresponding to the first input terminal INP. The further step input circuit 302 includes three input transistors PI, P2 and INVP1 'as p-type MOS transistors (pM〇s), and three input transistors Nb N2 and INVN2, N Type MOS semiconductor electric Japanese body (NM 〇 S). In operation, the input transistors P1 and INVP1 are used to control the output transistors N10 and DN10, respectively, and the two NMOS input transistors and 1NVN2 are used to control the output transistors P10 and DP1, respectively. The sources of the input transistors P1 and INVP1 collectively receive a supply voltage ', for example, vDD', which has a gate common reception signal Sdata, and its drain, 201108601, is coupled to the gates of the output transistors N10 and DN10, respectively. Similarly, the drains of the input transistors N1 and INVN2 are respectively coupled to the gates of the output transistors P1.0 and DP10, the gates of which collectively receive the signal Sdata, and the sources of which collectively receive another supply voltage, such as Vss. The sources of the input transistors N2 and P2 each receive the supply voltages Vss and VDD' and their gates receive the buffered output signal s〇m of the second input terminal INN. It is to be noted that the input transistors P1 and P2 have the same size (e.g., aspect ratio)' and are larger than the size of the input transistor INVP1. In addition, the input transistors N1 and N2 also have the same size and are larger than the size of the input transistor INVN2. Furthermore, the output stage circuit 304 is coupled to the input stage circuit 302. According to the embodiment of Figure 3, the output stage circuit 304 is a class AB push-pull amplification stage and has a first NMOS output transistor.

The body N10, a second NMOS output transistor DN10, a third PMOS output transistor P10 and a fourth PMOS output transistor DP10.

More specifically, NMOS transistors N10 and DN10, and PMOS transistors P10 and DP10 are arranged in a push-pull configuration. In detail, the sources of the first and second output transistors N10 and DN10 collectively receive the supply voltage Vss', the gates of which respectively receive the first and second control signals 310 and 312, and the drains of which are commonly coupled to the output terminal OUT . Similarly, the sources of the third and fourth output transistors P10 and DP10 collectively receive the supply voltage VDD, wherein the * gates respectively receive the third and fourth control signals 314 and 316, and the drains of the diodes 201108601 are coupled to the output. End out. It is worth noting that in Figure 3 the 'supply voltage vss is set to the lower voltage supply rail (,0wer-voltage supply rail) whose value is less than the supply voltage set to the uPPer-voltage supply rail.

VdD° therefore the buffer amplifier 330 is operable between the supply voltages of the rail-to-rail (rail_t0_rail). Further, according to the embodiment of FIG. 3, the bias circuit 306 is coupled between the input stage circuit 302 and the output stage circuit 304, and includes a first current mirror circuit 322 and a second current mirror circuit 324. The first, second, third, and fourth control signals 310, 312, 314, and 316 are determined. In this case, current mirror circuits 322 and 324 are used to individually adjust the voltage at the wheel terminal. Further illustrating the bias circuit 306, a set of NMOS transistors N4, N5 and INVN1 form a current mirror circuit 324, and another set of PMOS transistors P4, P5 and INVP2 constitute a current mirror circuit 322. The sources of the transistors N4, N5 and INVN1 collectively receive the supply voltage Vss, the gates of which together receive a bias voltage and the drains of which are respectively coupled to the drain of the input transistor P2 and the wheel at the output defect point VN. The pole of the input transistor pi and the drain of the input transistor INVPi on the output node INV1. The sources of the transistors p4, p5 and INVP2 collectively receive the supply voltage Vdd, the gates of which together receive the bias voltage, and the drains of which are respectively coupled to the drain of the input transistor N2, the input transistor located at the output node INV2 The pole of N1 and the drain of the input transistor INVN2 located on the turn-out node VP. 11 201108601 It is worth noting that the above fields are generated by one way, the electric PMOS transistors P8 and P9, and the NM〇s transistors m and _ are used to receive the external input voltages P and VB〇N, thereby allowing the buffer 330 operates in different voltage ranges. Further, the two transistors N3 are powered by external input voltages VBP and v_ to provide stability: bias current. In one embodiment, 'four additional transistors _, gang, purchased and ND3 are used as four switches, according to the two switching signals, to simultaneously start or close the input stage circuit 3 〇 2, the waste circuit 3 〇 6 With the output stage circuit 3〇4. The operation of the buffer amplifier 330 will be described in detail below. According to an embodiment, assuming that the load capacitance of the display unit 1〇8 has been fully charged, the buffer wheel output signal s〇ut of the output terminal OUT is a high logic level and is fed back to the second round. Incoming INN. When a relative -L LOW level is applied to the first input terminal INP, the input transistors P1 and INVP1 are respectively turned on. Thereafter, the control signals 310 and 312 are individually adjusted based on the voltage drops across the transistors N5 and IIsfVN1 coupled across the output terminals VN and INV1. More specifically, the current through the electric crystal N5 is increased, so that the drain-source voltage Vds of the transistor N5 is increased. Similarly, the current increase through the transistor INVN1 causes the gate-source voltage vDS of the transistor INV1Sii to increase substantially. The two output nodes VN and INVi are thus pulled high to a high logic level. As a result, the transistors N10 and DN1 are both turned on, and the load capacitance 12 201108601 of the display unit 108 is discharged. In this way, the two discharge paths will cause the load capacitance to discharge quickly, thereby improving the buffer-down time characteristic of the buffer amplifier 330. When the load capacitance at the output terminal OUT gradually changes from a high logic level to a low logic level, that is, when the discharge conversion is completed, the input transistor P2 is turned on. At this time, since the sizes of the input transistors P1 and P2 are both larger than the size of the input transistor INVP1, the current through the input transistor INVP1 is smaller than φ. According to another embodiment, when the load capacitance of the display unit 108 is discharged. In this case, the buffered output signal s of the output terminal OUT is a low logic level and is fed back to the second input terminal INN. At the first input terminal INP, since the signal Sdata is at a high logic level, the input transistors N1 and INVN2 are turned on. In this embodiment, the control signals 314 and 316 are individually adjusted based on the voltage drops across the transistors P5 and INPV2 coupled to the output nodes VP and INV2. More specifically, input transistors N1 and INVN2 will be turned on to increase the current through transistors P5 and INVP2. At this time, the drain-source voltage VDS of the transistors P5 and INVP2 increases. In this way, because the voltage across the transistors P5 and INVP2 increases, the two output nodes VP and INV2 are pulled low to a low logic level. In this way, both output transistors P10 and DP10 are turned on, causing the load capacitance of display unit 108 to be charged. In this way, the increased dynamic current further reduces the rise time characteristic of the buffer amplifier 330. When the load capacitance at the output terminal OUT gradually changes from the low logic level to the high logic level 13 201108601 bit, that is, when the charge conversion is completed, the input transistor N2 is turned on. The size of the input transistor, N1-- or N2 is larger than the size of the input transistor INVN2-, so the current through the input transistor INVN2 is small. Therefore, the buffer amplifier of the present invention allows the load capacitance of the display unit to be charged or discharged more quickly during charge-discharge switching. Therefore, for a large-sized or high-resolution display panel, when the signal Sdata is converted, the time and driving ability of the control will be greatly reduced. Furthermore, the buffer amplifier of the present invention can also avoid unnecessary power consumption after the charge and discharge process is completed in the load capacitor. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

14 201108601 [Simplified description of the drawings] II - Fig. 1 is a schematic view showing a display system according to an embodiment of the present invention. Fig. 2 is a schematic view showing a source driver according to the embodiment of Fig. 1. Fig. 3 is a view showing a buffer amplifier according to the embodiment of Fig. 2. [Main component symbol description] 10~ display system; φ 1〇2, 2〇2~source driver; 104~gate driver; 106~ display panel; 108~ display unit; 120~ timing controller; 122~liquid crystal unit 132, 134~ timing signal; spring G1, G〗... Gm~ gate line;

Si, S2...Sn~source line, TFT~film transistor;

Cs~ storage capacitor;

Vc〇M ~ common voltage; 214~RGB signal; 216~ shift register module; 218~latch module; 15 201108601 220~bit level converter; 222~digit to analog converter; - - 230, 330~ buffer amplifier; 232~ shift pulse; 2 34~ hold signal; 302~ input stage circuit; 3 04~ output stage circuit; 306~bias circuit; 310, 312, 314, 316~ control signal; , 324~ current mirror circuit;

Sdata ~ analog signal; S〇ut ~ buffer output signal; SW, SWB ~ switching signal; VP, VN, INV2, INV1 ~ node;

Vdd, Vss~ supply voltage, VBP, VBN, VBOP, VBON~ external input voltage; and P10, DP10, PI, P2, P3, P4, P5, P8, P9, INVP1, INVP2, PD2, PD3, N10, DN10, m, N2, N3, N4, N5, N8, N9, INVN1, INVN2, ND2, ND3~ transistor.

16

Claims (1)

201108601 VII. Patent application scope: An If-type buffer amplifier has a first input end, a second input end and an output end, wherein the output end is coupled back to the second input end, and according to An input signal is applied to the first input terminal, and a buffer output signal is generated at the output end. The buffer amplifier includes: an input stage circuit coupled between the input end and the output end, when the buffer output is When the logic level of the signal is opposite to the logic level of the input signal φ, four control signals corresponding to the input signal are generated; an output stage circuit coupled to the input stage circuit has one of the first types An output transistor and a second output transistor, and a second output transistor of a second type and a fourth output transistor, wherein the first and second output transistors comprise a common receiving a source of a supply voltage, a gate for receiving a first control signal and a second control signal, and a drain coupled to the output terminal, wherein the third and fourth inputs The transistor includes a source for receiving a second supply voltage, a gate for receiving a third control signal and a fourth control signal, and a drain coupled to the output terminal; and a bias The voltage circuit is coupled between the input stage circuit and the output stage circuit, and has a plurality of current mirror circuits for determining the first, second, third and fourth control signals. 2. The buffer amplifier of claim 1, wherein the input stage circuit comprises: 17 201108601 a first input transistor and a second input transistor having the second type and including receiving the same a source for the voltage source, a gate for receiving the input signal, and a drain, each coupled to the gates of the first and second output transistors; a third input transistor and a fourth An input transistor having the first type and including a source for coupling to the gates of the third and fourth output transistors, for collectively receiving the gate of the input signal, and for receiving the same a drain of a first supply voltage; a fifth input transistor having the second type and including a drain, a source for receiving the second supply voltage, and a buffer for receiving the buffer from the second input a gate of the output signal; and a sixth input transistor having the first type and including a drain, a source for receiving the first supply voltage, and a buffer output for receiving the second input Signal gate . 3. The buffer amplifier of claim 1, wherein the bias circuit comprises: a first set of transistors comprising three transistors having the first type, the first set of transistors The source receives the first supply voltage, the gates collectively receive a bias voltage, and the drains are respectively coupled to the drain of the first input transistor at a first output node. a second output node coupled to the drain of the second input transistor and a drain coupled to the fifth input transistor; and 201108601 a second set of transistors, including three having the second type The transistor, the source of the second-group-transistor is connected in common to receive the second supply voltage. The gates are coupled to the drain of the third input transistor and coupled to the fourth output node at a third output node. a drain of the fourth input transistor and coupled to the sum of the sixth input transistor, wherein the voltage drop across the para-conductor coupled to the first and second output nodes is used Adjusting the first and second control signals respectively, and wherein the third and fourth control signals are respectively adjusted according to a voltage drop across the transistors coupled to the third and fourth output nodes . 4. The buffer amplifier of claim 1, further comprising: a plurality of switches for simultaneously activating or deactivating the input stage circuit, the bias circuit and the output stage circuit. 5. The buffer amplifier of claim 1, wherein the first supply voltage is a lower voltage supply rail, the second supply voltage is an upper voltage supply rail, and the first supply voltage is less than the first Two supply voltages. 6. The buffer amplifier of claim 1, wherein the output stage circuit is an Class AB amplifier stage. 7. The buffer amplifier of claim 1, wherein the first type of transistor is an N-type MOS transistor, and the second type of transistor is a P-type MOS semiconductor Crystal. The amplifier of claim 1, wherein the τ first and fifth input transistors have the same size and are larger than the size of the second input transistor, and wherein The third and sixth input transistors have the same size and are larger than the size of the fourth input transistor. -20