201021427 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種直接數位頻率合成裝置及用於直接數 位頻率合成之位移式拋物線方程式之參數計算方法。 【先前技術】 在習知的技術中，直接數位頻率合成器主要可分為有唯 讀把憶體與無唯讀記憶體（ROM-less)之頻率合成器兩類。 有唯讀記憶體的直接頻率合成器是使用唯讀記憶體來儲存 正弦波（和/或）餘弦波的值，並使用查表的方式產生出數位 弦波（參考美國專利第4，134,072號及美國專利第6,615,398 B2號）。然而隨著相位的解析度增加，唯讀記憶體的使用 以及每個字元的長度亦跟隨增加，產生大面積與速度慢的 缺點。 無唯讀記憶體之頻率合成器則是利用特殊演算法來減少 所需記憶的參數值（參考美國專利第5,644,6〇2號及本國專 利第1284802號），大幅改善了由於相位解析度的增加而造 ^ 成唯讀記憶體的使用量’但是所付出的代價則為無法達到 像使用有唯讀記憶體的直接頻率合成器一樣的無寄生動態 範圍（spurious-free dynamic range, SFDR)。因此近來在無 唯讀記憶體之頻率合成器的研究文獻上，皆是朝向可以兼 具速度且又能擁有優異的無寄生動態範圍值為目標。例如 拋物線内插法（參考先前技術文獻，係將一完整周期為 2π rad的弦波相位等分切成”段，每段都利用拋物線方程式 + 去近似弦波，並且利用此拋物線方程式去做内插的 133588.doc 201021427 動作，產生出此段中其他的近似弦波振幅值（參考圖1)，此 方法在振幅接近0的地方誤差值會較大（參考圖2,該圖為 將四分之一週期等分切四段產生出的近似弦波振幅與理想 弦波振幅之間的誤差絕對值），其輸出弦波波形利用快速 傅立葉轉換後的頻譜，無寄生動態範圍（spurious-free dynamic range, SFDR)為 59.1 dBc(參考圖 3)。 先前技術文獻P]提出類線性内插法（參考圖4)，係將振 幅接近0處，改用更接近弦波的直線，因此降低了誤差值 • (參考圖5,該圖為將四分之一週期等分切四段產生出的近 似弦波振幅與理想弦波振幅之間的誤差絕對值），其輸出 弦波波形利用快速傅立葉轉換後的頻譜，無寄生動態範圍 為65.7 dBc(參考圖6)。然而這些習知技術所產生之無寄生 動態範圍（spurious-free dynamic range, SFDR)不夠大，難 以產生高純度弦波。 因此，有必要提供一種創新且具進步性的直接數位頻率 合成裝置，以解決上述問題。 〇 先前技術文獻： [1] A. M. Sodagar, and G. R. Lahihi, "A novel architecture for ROM-less sin-output direct digital frequency synthesizers by using the 2nd-order parabolic approximation," in Proc. IEEE/EIA Inter. Frequency Control Symp. and Exhibition, pp. 284-289, June 2000.201021427 IX. Description of the Invention: [Technical Field] The present invention relates to a direct digital frequency synthesizing device and a parameter calculating method for a displacement parabolic equation for direct digital frequency synthesis. [Prior Art] In the prior art, the direct digital frequency synthesizer can be mainly classified into two types: a frequency synthesizer having a read-only memory and a ROM-less memory. A direct frequency synthesizer with read-only memory uses a read-only memory to store the value of a sine wave (and/or) cosine wave, and uses a look-up table to generate a digital sine wave (refer to U.S. Patent No. 4,134,072). And U.S. Patent No. 6,615,398 B2). However, as the resolution of the phase increases, the use of read-only memory and the length of each character also increase, resulting in the disadvantage of large area and slow speed. The frequency synthesizer without read-only memory is a special algorithm to reduce the parameter value of the required memory (refer to U.S. Patent No. 5,644,6, 2 and the national patent No. 1284802), which greatly improves the phase resolution. The increase in the amount of read-only memory is used, but the price paid is that the spurious-free dynamic range (SFDR) like the direct frequency synthesizer with read-only memory cannot be achieved. Therefore, in recent research literature on frequency synthesizers without read-only memory, the goal is to have both speed and spurious-free dynamic range values. For example, parabolic interpolation (refer to the prior art literature, the sine wave phase of a complete period of 2π rad is equally divided into segments), each of which uses a parabolic equation + to approximate the sine wave, and uses this parabolic equation to do the inner Insert the 133588.doc 201021427 action to generate other approximate sine wave amplitude values in this segment (refer to Figure 1). This method will have a larger error value when the amplitude is close to 0 (refer to Figure 2, which will be four points). One cycle equally divides the absolute value of the error between the approximate sine wave amplitude and the ideal sine wave amplitude generated by the four segments, and the output sine wave waveform utilizes the fast Fourier transformed spectrum, without spurious-free dynamic range (spurious-free dynamic Range, SFDR) is 59.1 dBc (refer to Figure 3). The prior art document P] proposes a linear interpolation method (refer to Figure 4), which uses the amplitude close to 0 and uses a line closer to the sine wave, thus reducing the error. Value • (Refer to Figure 5, which is the absolute value of the error between the approximate sine wave amplitude and the ideal sine wave amplitude produced by dividing the quarter period into four segments), and the output sine wave waveform using fast Fourier In the modified spectrum, the parasitic dynamic range is 65.7 dBc (refer to Figure 6). However, the spurious-free dynamic range (SFDR) generated by these prior art techniques is not large enough to generate high-purity sine waves. It is necessary to provide an innovative and progressive direct digital frequency synthesizer to solve the above problems. 〇 Previous technical literature: [1] AM Sodagar, and GR Lahihi, "A novel architecture for ROM-less sin-output direct Digital frequency synthesizers by using the 2nd-order parabolic approximation," in Proc. IEEE/EIA Inter. Frequency Control Symp. and Exhibition, pp. 284-289, June 2000.
[2] A. Ashrafl, and R. Adhami, "A direct digital frequency synthesizer utilizing quasi-linear interpolation method," in Proc. of IEEE 37th Southeastern Symp. on System Theory, pp. 114-118, Mar. 2005. 【發明内容】 133588.doc 201021427 本發明提供一種直接數位頻率合成裝置，包括：一計數 電路、一相位截斷電路、一對稱電路、一相位位移電路、 一相位弦波轉換電路及一符號電路。該計數電路接收一外 部頻率控制訊號以進行重覆計數，而產生一弦波取樣位址 訊號。該相位截斷電路係將該弦波取樣位址訊號經過部分 位元捨棄（truncate)，得到一相位位址訊號。該對稱電路用 以將相位截斷電路輸出之相位位址訊號進行對稱運算，以 得到一對稱相位位址訊號。該相位位移電路用以將該對稱 相位位址訊號進行相位位移，以得到一位移相位位址訊 號°該相位弦波轉換電路用以將位移相位位址訊號進行拋 物線逼近，得到一弦波轉換預測訊號。該符號電路將該弦 波轉換預測訊號做符號運算，以得到一直接數位頻率合成 弦波訊號。 本發明另提供一種用於直接數位頻率合成之位移式拋物 線方程式之參數計算方法，包括以下步驟：（1)將複數個弦 波取樣位址（Xi)以及所對應之複數個弦波振幅值（yi)代入到 一位移式拋物線方程式中，得到一方程組，其中該位移式 拋物線方程式為（yi=a*(d+Xi)2+c)，a為第一參數組；c為第 二參數組；d為位移參數組；（2)設定任意值為位移參數組 之初始值，並帶入該位移式拋物線方程式中；（3)利用最小 平方近似法’得到該第一參數組及該第二參數組之值並 帶入該位移式拋物線方程式中，以取得複數個近似弦波振 幅值；（4)依據該等近似弦波振幅值及理想弦波值，使得該 等近似弦波值與理想弦波值之誤差平方和最小，以計算得 133588.doc 201021427 該位移參數組之調整值；及（5)將該位移參數組之調整值帶 入該位移式拋物線方程式，再利用最小平方近似法，得到 該第一參數組及該第二參數組之調整值。 因此，利用本發明直接數位頻率合成裝置可產生高純度 之弦波，且具有高無寄生動態範圍。並且本發明用於直接 數位頻率合成之位移式拋物線方程式（yi=a*(d+Xi)2+c)之參 數計算方法，可用以計算位移式拋物線方程式中之a、c、 d參數，使得利用位移式拋物線方程式所計算之近似弦波 ® 值與理想弦波值之誤差平方和降低。 【實施方式】 參考圖7，其顯示本發明用於直接數位頻率合成之位移 式拋物線方程式之參數計算方法之流程示意圖。本發明用 於直接數位頻率合成之位移式拋物線方程式 (yi-a*(d+Xi) +c)之參數計算方法’係用以計算位移式拋物 線方程式中之a、C、d參數，其中a為第一參數組；^為第 二參數組；d為位移參數組。 參考步驟S71 ’首先將複數個弦波取樣位址（Xi)以及所對 應之複數個弦波振幅值（yi)代入到該位移式拋物線方程式 (yeaYd+Xif+c)中’得到一方程組，該位移式拋物線方程 式以矩陣方式表示如下式（1): yi" '(x,+d)2 f y2 = (x2+d)2 1 ' η a c y«n. (xm+d)2 1 133588.doc 201021427 再没疋任意值為位移參數組d之初始值並帶入該位移 式拋物線方程式中◊並利用最小平方近似法，計算得到該 第一參數組a及該第二參數組(；之值。在本實施例中該最 小平方近似法係包括以下步驟，在該料形式之位移式抛 物線方程式同乘以一轉置矩陣，如步驟S72，其表示如下 式（2):[2] A. Ashrafl, and R. Adhami, "A direct digital frequency synthesizer utilizing quasi-linear interpolation method," in Proc. of IEEE 37th Southeastern Symp. on System Theory, pp. 114-118, Mar. 2005 SUMMARY OF THE INVENTION The present invention provides a direct digital frequency synthesizing apparatus comprising: a counting circuit, a phase truncating circuit, a symmetrical circuit, a phase shift circuit, a phase sine wave converting circuit and a symbol circuit. The counting circuit receives an external frequency control signal for repeated counting to generate a sine wave sampling address signal. The phase truncation circuit discards the sine wave sampling address signal through a partial bit to obtain a phase address signal. The symmetrical circuit is used to symmetrically calculate the phase address signal outputted by the phase cutoff circuit to obtain a symmetric phase address signal. The phase shift circuit is configured to phase shift the symmetric phase address signal to obtain a displacement phase address signal. The phase sine wave conversion circuit is configured to parabolically approximate the displacement phase address signal to obtain a sine wave conversion prediction. Signal. The symbol circuit performs a symbol operation on the sine wave conversion prediction signal to obtain a direct digital frequency synthesis sine wave signal. The invention further provides a parameter calculation method for a displacement parabolic equation for direct digital frequency synthesis, comprising the following steps: (1) sampling a plurality of sine wave sampling addresses (Xi) and corresponding plurality of sine wave amplitude values ( I) substituting into a displacement parabolic equation to obtain a system of equations, where the displacement parabolic equation is (yi=a*(d+Xi)2+c), a is the first parameter group; c is the second parameter Group; d is the displacement parameter group; (2) setting the arbitrary value as the initial value of the displacement parameter group, and bringing it into the displacement parabolic equation; (3) using the least square approximation method to obtain the first parameter group and the first The value of the two parameter group is taken into the displacement parabolic equation to obtain a plurality of approximate sine wave amplitude values; (4) according to the approximate sine wave amplitude values and the ideal sine wave values, such approximate sine wave values are The sum of the squares of the ideal sine wave values is the smallest, to calculate the adjustment value of the displacement parameter group of 133588.doc 201021427; and (5) bring the adjustment value of the displacement parameter group into the displacement parabolic equation, and then use the least square approximation law Obtaining an adjustment value of the first parameter group and the second parameter group. Therefore, with the direct digital frequency synthesizing device of the present invention, a high-purity sine wave can be generated with a high parasitic dynamic range. And the parameter calculation method for the displacement parabolic equation (yi=a*(d+Xi)2+c) of the direct digital frequency synthesis of the present invention can be used to calculate the a, c, d parameters in the displacement parabolic equation, so that The sum of the squared errors of the approximate sine wave® value calculated from the displacement parabolic equation and the ideal sine wave value is reduced. [Embodiment] Referring to Fig. 7, there is shown a flow chart showing a parameter calculation method of a displacement parabolic equation for direct digital frequency synthesis of the present invention. The parameter calculation method for the displacement parabolic equation (yi-a*(d+Xi) +c) for direct digital frequency synthesis is used to calculate the a, C, and d parameters in the displacement parabolic equation, where a It is the first parameter group; ^ is the second parameter group; d is the displacement parameter group. Referring to step S71 'first, a plurality of sine wave sampling addresses (Xi) and corresponding plurality of sine wave amplitude values (yi) are substituted into the displacement parabolic equation (yeaYd+Xif+c) to obtain a system of equations. The displacement parabolic equation is expressed in matrix as follows (1): yi" '(x,+d)2 f y2 = (x2+d)2 1 ' η acy«n. (xm+d)2 1 133588. Doc 201021427 No further arbitrary value is the initial value of the displacement parameter group d and is brought into the displacement parabolic equation ◊ and the least square approximation method is used to calculate the value of the first parameter group a and the second parameter group (; In the present embodiment, the least square approximation method includes the following steps: the displacement parabolic equation in the form of the material is multiplied by a transposed matrix, as shown in step S72, which represents the following equation (2):
(Xi+d)2 1' (x2+d)2 1 • · • · T >ι' y2 (Χι+d)2 Γ (x2+d)2 1 ♦ · T (Xi+d)2 1· (x2 +d)2 1 • · _(xm+d)2 1_ ♦ I _(xm+d)2 1 • • . _(xm+d)2 1 (2) 參考步驟S73，再經移項整理，可計算得到該第一參數 組a及該第二參數之值如下式（？）： (x!+d)2 Γ (x2 +d)2 1 • . • . T (Xi+d)2 Γ (x2 +d)2 1 • . • . \-1 (χ,+d)2 1Ί (x2+d)2 1 • · T "yi" y2 丄(Xm+d)2 1_ • . ,(Xm+d)2 1 / • · _(xm+d)2 1_ ym. (3)(Xi+d)2 1' (x2+d)2 1 • · • · T >ι' y2 (Χι+d)2 Γ (x2+d)2 1 ♦ · T (Xi+d)2 1· (x2 +d)2 1 • · _(xm+d)2 1_ ♦ I _(xm+d)2 1 • • . _(xm+d)2 1 (2) Referring to step S73, after shifting, The value of the first parameter group a and the second parameter can be calculated as follows (?): (x!+d)2 Γ (x2 +d)2 1 • . • . T (Xi+d)2 Γ ( X2 +d)2 1 • . • . \-1 (χ,+d)2 1Ί (x2+d)2 1 • · T "yi" y2 丄(Xm+d)2 1_ • . , (Xm+ d) 2 1 / • · _(xm+d)2 1_ ym. (3)
將第一參數組a及該第二參數組^之值帶入該位移式拋物 線方程式，如上式（1)中，以取得複數個近似弦波振幅值， 如步驟S74所示。 依據該等近似弦波振幅值及理想弦波值，使得該等近似 弦波值與理想弦波值之誤差平方和最小，以計算得該位移 參數組d之調整值，如步驟S75及S76。 再將該位移參數組之調整值帶入該位移式拋物線方程 式’再利用最小平方近似法，如上述之式（3)，以計算得到 133588.doc 201021427 該第一參數組a及該第二參數組〇之調整值，如步驟871、 S72、S73。則上述之調整值為該位移式拋物線方程式之該 第參數組a、該第二參數組c及該位移參數組d之值。 本發明用於直接數位頻率合成之位移式拋物線方程式 O^Ad+xy+c)之參數計算方法，可用以計算位移式拋物 線方程式中之a、c、d參數，使得利用位移式拋物線方程 式所計算之近似弦波值與理想弦波值之誤差平方和降低。 參考圖8，其顯示本發明直接數位頻率合成裝置之示意 圖，參考圖11，其顯示本發明直接數位頻率合成裝置電路 示意圖。配合參考圖8及圖u，本發明直接數位頻率合成 裝置80包括.一计數電路81、一相位截斷電路82、一對稱 電路83、一相位位移電路84、一相位弦波轉換電路“及一 符號電路86。 該計數電路81接收一外部頻率控制訊號以進行重覆計 數，而產生一弦波取樣位址訊號。在本實施例中，該計數 電路81係為一相位累加器，其包括一第一加法器811及一 第一暫存器812;該第一加法器811用以將所接收之該外部 頻率控制訊號FCW與該第一暫存器812所暫存之内容做加 總運算，再把加總運算之結果儲存到該第一暫存器812， 以輸出該弦波取樣位址訊號。在本實施例中，該弦波取樣 位址訊號係為33位元之訊號。該第一暫存器812接收一外 部重置訊號Reset，以決定該第一暫存器812之重置動作， 並且依據一外部參考時脈Ref clk以決定該第一暫存器Η〗 輸出該弦波取樣位址訊號之時序。 133588.doc -11- 201021427 該相位截斷電路82係將該弦波取樣位址訊號經過部分位 元捨棄（truncate) ’得到一相位位址訊號。該相位截斷電路 係將該弦波取樣位址訊號之最低複數個位元捨棄；在本實 施例中，該相位截斷電路82係將33位元之弦波取樣位址訊 號之最低13位元捨棄，輸出一 20位元之相位位址訊號《經 過相位捨棄後’可降低後續電路所需之硬體成本，而又仍 可以保持所需求的弦波頻譜的純度。 該對稱電路83用以將相位截斷電路82輸出之相位位址訊 號進行對稱運算，以得到一對稱相位位址訊號。在本實施 例中’該對稱電路83係為一反相器，用以依據該相位位址 訊號中之次高位元（2nd MSB)，將相位位址訊號之部分位元 進行相位反相’以得到該對稱相位位址訊號。在本實施例 中’該對稱電路83將相位位址訊號最低18個有效位元利用 該反相器83進行反相運算，輸出一丨8位元之對稱相位位址 訊號。 該相位位移電路84用以將該對稱相位位址訊號進行相位 位移以得到一位移相位位址訊號。在本實施例中，該相 位位移電路84包括一第一多工器841、複數個第二暫存器 842及一第二加法器845。該等第二暫存器842用以儲存複 數個位移參數，在本實施例中，該等第二暫存器所暫 存之值是將四分之一弦波相位等分切成16段，每段係利用 月J述位移式撤物線方程式（yi=a*(d+Xi)2+c)之參數計算方法 所計算得之位移參數值d。 該第一多工器841係根據對稱電路輸出之該對稱相位位 133588.doc •12- 201021427 址訊號中複數個最高有效位元，以切換控制該等第一暫存 器，輸出該等位移參數。在本實施例中，該第一多工器 841係根據該對稱電路83輸出之該對稱相位位址訊號中最 高4個有效位元，切換該等第二暫存器842。該第二加法器 845用以將該對稱相位位址訊號與該等位移參數進行加總 運算，以輸出一22位元之位移相位位址訊號，亦即為前述 位移式拋物線方程式（yi=a*(d+Xi)2+c)中之（d+Xi)。 該相位弦波轉換電路85用以將位移相位位址訊號進行拋 物線逼近，得到一弦波轉換預測訊號。在本實施例中，該 相位弦波轉換電路85包括：一平方器851、一位移器Μ〗、 複數個第三暫存器853、一第二多工器8S4及一第三加法器 組855。該平方器851用以將該位移相位位址訊號進行平方 運算，產生一平方訊號，亦即為前述位移式拋物線方程式 (yfaYd+xOhe)中之（d+Xi)2。在本實施例中，該平方訊號 為一 44位元訊號。 該位移器852用以將該平方訊號，根據一第一參數組， 進行位移運算，產生-位移訊號。在本實施例中，該位移 器852包括複數個第四暫存器856及複數個第三多工器 857。該等第四暫存器856用以儲存該第一參數組在本實 施例中，該等第四暫存器856所暫存之值是將四分之一弦 波相位等分切成16段’每段係利用前述位移式拋物線方程 式（Ρ*(<1+Χί)2+〇之參數計算方法所計算得之第一參數值 a。該等第三多工器857係根據對稱電路輸出之該對稱相位 位址訊號中複數個最高有效位元（在本實施例中為4個最高 133588.doc -13- 201021427 有效位元），以切換控制該等第三暫存器856，輸出該位移 訊號’該位移訊號為24位元訊號》 該等第三暫存器853用以儲存一第二參數組，在本實施 例中’該等第i暫存器853所暫存之值是將四分之一弦波 相位等分切成16段，每段係利用前述位移式拋物線方程式 (y产a*(d+Xi)2+c)之參數計算方法所計算得之第二參數值 c。第二多工器854用以依據對稱相位位址訊號中最高複數 個位元（在本實施例中為5個最高有效位元），將所儲存之該 • 帛二參數組進行訊號切換，產生-切換訊號。第三加法器 組855用以將該切換訊號及該位移訊號進行加總運算，以 產生該弦波轉換預測訊號，亦即為前述位移式拋物線方程 式（yeaYd+x^+c)之yi。在本實施例中，該第三加法器組 855包括複數個加法器，成一管線式架構。 該符號電路86將該弦波轉換預測訊號做符號運算，以得 到一直接數位頻率合成弦波訊號。在本實施例中，該符號 ❷ 電路86係為一反相器，用以依據該相位位址訊號中最高位 元，將該弦波轉換預測訊號進行相位反相後輸出，以輸出 一 24位元之直接數位頻率合成弦波訊號。 參考圖9，其顯示利用本發明較佳實施例將四分之—週 期等分切四段產生出的近似弦波振幅與理想弦波振幅之間 的誤差絕對值圖。明顯地，本發明較佳實施例利用位移式 拋物線内插法，將四分之一週期等分切四段產生出的近似 弦波振幅與理想弦波振幅之間的誤差絕對值，其優於習知 技術（參考圖2、圖5)。 133588.doc 14· 201021427 〃考圖0纟顯不利用本發明產生之弦波頻譜圖。明顯 地，將本發明輸出弦波波形利用快速傅立葉轉換後的頻譜 圖’其無寄生動態範圍為8〇·71 dBe，亦優於習知技術（參 考圖3、圖6)。 為了進一步顯示本發明之優越性，纟發明之實施例以台 灣積體電路製造公司提供之。13 um lp8M cm〇s製程來實 文參考圖12’其顯示本發明之時域模擬結果示意圖。其 中"相位累加器輸出[32:0]"為相位累加器的輸出結果波 形經過將最低13位元捨棄後得到的輸出為"相位戴斷電 路輸出[32:13]"，使得後續電路的複雜度可以降低，又仍 可以保持所需求的弦波頻譜的純度。接著根據"相位累加 器輸出第二最高有效位元"訊號，將"相位累加器輸出 [32.13]利用1的補數轉換成左右對稱的訊號供給下一級的 相位弦波轉換電路。最後根據”相位累加器輸出最高有效 位儿"訊號，將相位弦波轉換電路之輸出結果利用2的補數 φ 產生出所要的數位弦波波形。圖12下方亦顯示，在切換所 需要的輸出頻率時’訊號是立即的切換，且相位在切換時 亦疋連續的’不像先前文獻與技術所示會有一段設定時間 (settling time)以及不連續的相位。 參考圖13’其顯示上述圖12之弦波頻譜圖。將上述圖12 之輸出弦波波形利用快速傅立葉轉換後的頻譜，其無寄生 動態範圍（spurious-free dynamic range，SFDR)可高達 Π7 dBc，明顯地優於習知技術之效果。參考圖14，其顯示本 發明之實體晶片量測Shmoo Plot圖。在工作電壓為1 2V時 133588.doc -15- 201021427 最南之參考時脈為161 MHz。 因此’利用本發明直接數位頻率合成裝置可產生高純度 之弦波’且具有尚無寄生動態範圍。並且本發明用於直接 數位頻率合成之位移式拋物線方程式（yi=a*(d+Xi)2+c)之參 數計算方法，可用以計算位移式拋物線方程式中之a、c、 d參數，使得利用位移式拋物線方程式所計算之近似弦波 值與理想弦波值之誤差平方和降低。 惟上述實施例僅為說明本發明之原理及其功效，而非限 • 制本發明。因此，習於此技術之人士對上述實施例進行修 改及變化仍不脫本發明之精神。本發明之權利範圍應如後 述之申請專利範圍所列。 【圖式簡單說明】 圖1顯示利用習知技術拋物線内插法產生之近似弦波示 意圖； 圖2顯示利用習知技術拋物線内插法產生弦波與理想弦 ^ 波之絕對誤差示意圖； 圖3顯示利用習知技術拋物線内插法產生近似弦波之頻 譜圖； 圖4顯示利用習知技術類拋物線内插方法產生近似弦波 示意圖； 圖5顯示利用習知技術類拋物線内插方法產生弦波與理 想弦波之絕對誤差示意圖； 圖6顯示利用習知技術類拋物線内插方法產生近似弦、皮 之頻譜圖； 133588.doc -16· 201021427 圖7顯不本發明用於直接數位頻率合成之位移式拋物線 方程式之參數計算方法之流程示意圖；及 圖8顯示本發明直接數位頻率合成裝置之示意圖； 圖9顯示利用本發明產生之近似弦波振幅與理想弦波振 幅間的絕對誤差示意圖； 圖Π顯示本發明直接數位頻率合成裝置電路示意圖； 圖12顯示本發明之時域模擬結果示意圖； 圖13顯示上述圖12之弦波頻譜圖；及 . 圖14顯示本發明之實體晶片量測shmoo Plot圖。 【主要元件符號說明】 80 本發明直接數位頻率合成裝置 81 計數電路 82 相位截斷電路 83 對稱電路 84 相位位移電路 85 相位弦波轉換電路 86 符號電路 811 第一加法器 812 第一暫存器 841 第一多工器 842 第二暫存器 845 第二加法器 851 平方器 852 位移器 133588.doc -17- 201021427 853 854 855 856 857 第三暫存器 第二多工器 第三加法器組 第四暫存器 第三多工器 133588.doc -18-The values of the first parameter set a and the second parameter set ^ are brought into the displacement parabolic equation, as in the above equation (1), to obtain a plurality of approximate sine wave amplitude values, as shown in step S74. According to the approximate sine wave amplitude value and the ideal sine wave value, the sum of squared errors of the approximate sine wave values and the ideal sine wave values is minimized to calculate the adjustment value of the displacement parameter group d, as in steps S75 and S76. Then, the adjustment parameter of the displacement parameter group is brought into the displacement parabolic equation 'reuse least square approximation method, as in the above formula (3), to calculate 133588.doc 201021427 the first parameter group a and the second parameter The adjustment value of the group is as shown in steps 871, S72, and S73. Then, the adjustment value is the value of the parameter group a, the second parameter group c and the displacement parameter group d of the displacement parabolic equation. The parameter calculation method of the displacement parabolic equation O^Ad+xy+c) for direct digital frequency synthesis can be used to calculate the a, c, and d parameters in the displacement parabolic equation, so that the displacement parabolic equation is used to calculate The sum of the squares of the approximate sine wave value and the ideal sine wave value decreases. Referring to Figure 8, there is shown a schematic diagram of a direct digital frequency synthesizing apparatus of the present invention, and with reference to Figure 11, there is shown a circuit diagram of the direct digital frequency synthesizing apparatus of the present invention. Referring to FIG. 8 and FIG. u, the direct digital frequency synthesizing device 80 of the present invention comprises: a counting circuit 81, a phase blocking circuit 82, a symmetrical circuit 83, a phase shift circuit 84, a phase sine wave converting circuit "and a The symbol circuit 86. The counting circuit 81 receives an external frequency control signal for repeated counting to generate a sine wave sampling address signal. In this embodiment, the counting circuit 81 is a phase accumulator, which includes a a first adder 811 and a first register 812; the first adder 811 is configured to perform a total operation on the received external frequency control signal FCW and the content temporarily stored in the first register 812. The result of the total operation is stored in the first register 812 to output the sine wave sampling address signal. In this embodiment, the sine wave sampling address signal is a 33-bit signal. A register 812 receives an external reset signal Reset to determine a reset action of the first register 812, and outputs the sine wave according to an external reference clock Ref clk to determine the first register Η The timing of the sampled address signal. 133588. Doc -11- 201021427 The phase truncation circuit 82 obtains a phase address signal by truncate the sine wave sampling address signal. The phase truncation circuit is the lowest of the sine wave sampling address signal. The plurality of bits are discarded; in the embodiment, the phase truncation circuit 82 discards the lowest 13 bits of the 33-bit sine wave sampling address signal, and outputs a 20-bit phase address signal. The latter can reduce the hardware cost required for the subsequent circuit, while still maintaining the purity of the required sine wave spectrum. The symmetrical circuit 83 is used to symmetrically calculate the phase address signal outputted by the phase cutoff circuit 82 to obtain A symmetric phase address signal. In the present embodiment, the symmetrical circuit 83 is an inverter for locating a portion of the phase address signal according to the second highest bit (2nd MSB) of the phase address signal. The element performs phase inversion ' to obtain the symmetric phase address signal. In the embodiment, the symmetrical circuit 83 uses the inverter 83 to perform the inversion operation using the lowest effective bit of the phase address signal. The symmetrical 8-bit symmetrical phase address signal is output. The phase shift circuit 84 is configured to phase shift the symmetrical phase address signal to obtain a displacement phase address signal. In this embodiment, the phase shift circuit 84 A first multiplexer 841, a plurality of second temporary registers 842, and a second adder 845. The second temporary registers 842 are configured to store a plurality of displacement parameters. In this embodiment, the first The value of the temporary storage of the second register is to divide the phase of the quarter wave into 16 segments, and each segment uses the displacement equation of the displacement (yi=a*(d+Xi)2+ c) The parameter calculation method calculates the displacement parameter value d. The first multiplexer 841 is based on the symmetrical phase of the symmetric circuit output 133588.doc • 12- 201021427 address signal of the plurality of most significant bits, Switching controls the first registers to output the displacement parameters. In this embodiment, the first multiplexer 841 switches the second registers 842 according to the highest four valid bits of the symmetric phase address signals output by the symmetrical circuit 83. The second adder 845 is configured to perform a total operation of the symmetric phase address signal and the displacement parameters to output a 22-bit displacement phase address signal, that is, the displacement parabolic equation (yi=a). *(d+Xi)2+()(d+Xi). The phase sine wave conversion circuit 85 is configured to parabolically approximate the displacement phase address signal to obtain a sine wave conversion prediction signal. In this embodiment, the phase sine wave conversion circuit 85 includes: a squarer 851, a shifter 、, a plurality of third temporary registers 853, a second multiplexer 8S4, and a third adder group 855. . The squarer 851 is used to square the displacement phase address signal to generate a square signal, which is (d+Xi)2 in the displacement parabola equation (yfaYd+xOhe). In this embodiment, the square signal is a 44-bit signal. The shifter 852 is configured to perform a displacement operation on the square signal according to a first parameter group to generate a displacement signal. In the present embodiment, the shifter 852 includes a plurality of fourth registers 856 and a plurality of third multiplexers 857. The fourth register 856 is configured to store the first parameter group. In the embodiment, the temporary storage value of the fourth register 856 is to divide the quarter wave phase into 16 segments. 'Each segment is the first parameter value a calculated by the above-mentioned displacement parabolic equation (Ρ*(<1+Χί)2+ parameter calculation method. The third multiplexer 857 is based on the symmetrical circuit output. The plurality of most significant bits (in this embodiment, the four highest 133588.doc -13 - 201021427 valid bits) in the symmetric phase address signal are used to switch control the third temporary registers 856, and output the The displacement signal 'the displacement signal is a 24-bit signal'. The third temporary register 853 is configured to store a second parameter set. In this embodiment, the value temporarily stored in the i-th register 853 is The quarter-wave phase is equally divided into 16 segments, each segment is calculated by the parameter calculation method of the displacement parabola equation (y*(d+Xi)2+c). The second multiplexer 854 is configured to use the highest number of bits in the symmetric phase address signal (in this embodiment, the five most significant bits) And storing the stored parameter group to generate a signal to be switched. The third adder group 855 is configured to add the switching signal and the displacement signal to generate the sine wave prediction signal. That is, the aforementioned displacement parabolic equation (yeaYd+x^+c) yi. In this embodiment, the third adder group 855 includes a plurality of adders into a pipelined architecture. The symbol circuit 86 The sine wave conversion prediction signal is subjected to a symbol operation to obtain a direct digital frequency synthesis sine wave signal. In this embodiment, the symbol 电路 circuit 86 is an inverter for determining the highest bit in the phase address signal. The sine wave conversion prediction signal is phase-inverted and output to output a 24-bit direct digital frequency synthesis chord signal. Referring to FIG. 9, there is shown a quarter-cycle, etc., using a preferred embodiment of the present invention. An absolute value plot of the error between the approximated sinusoidal amplitude and the ideal sinusoidal amplitude produced by the four segments. Obviously, the preferred embodiment of the invention utilizes a displacement parabolic interpolation method that will take a quarter of a cycle. The absolute value of the error between the approximate sine wave amplitude and the ideal sine wave amplitude produced by the equally divided four segments is superior to the conventional technique (refer to Fig. 2, Fig. 5). 133588.doc 14· 201021427 〃考图0纟The sinusoidal spectrum diagram generated by the present invention is obviously not used. Obviously, the spectrum of the output sine wave waveform of the present invention is fast-Fourier-transformed, and its spurious-free dynamic range is 8〇·71 dBe, which is also superior to the prior art ( Referring to Figures 3 and 6), in order to further demonstrate the advantages of the present invention, an embodiment of the invention is provided by Taiwan Integrated Circuit Manufacturing Co., Ltd. 13 um lp8M cm 〇s process, with reference to Figure 12', which shows the present invention. A schematic diagram of the time domain simulation results. Where "phase accumulator output [32:0]" is the output of the phase accumulator. The waveform is discarded after the lowest 13 bits are discarded. The phase is the output of the phase [32:13]" This allows the complexity of subsequent circuits to be reduced while still maintaining the purity of the required sine wave spectrum. Then, according to the "phase accumulator outputting the second most significant bit "signal, the "phase accumulator output [32.13] is converted into a left-right symmetric signal by the 1's complement signal to the next stage phase sine wave conversion circuit. Finally, according to the "phase accumulator output most significant bit" signal, the output of the phase sine wave conversion circuit is used to generate the desired digital sine wave waveform by using the 2's complement φ. The lower part of Fig. 12 also shows the need for switching. At the output frequency, the 'signal is an immediate switch, and the phase is also continuous when switching'. Unlike the previous literature and technology, there will be a settling time and a discontinuous phase. Referring to Figure 13', the above is shown. The sinusoidal spectrum diagram of Figure 12. Using the fast Fourier-converted spectrum of the output sine wave waveform of Figure 12 above, the spurious-free dynamic range (SFDR) can be as high as Π7 dBc, which is significantly better than the conventional one. Effect of the Technology. Referring to Figure 14, there is shown a solid wafer measurement Shmoo Plot diagram of the present invention. At the operating voltage of 12 V, 133588.doc -15-201021427, the southernmost reference clock is 161 MHz. The direct digital frequency synthesizing device can generate a high-purity sine wave 'and has no spurious dynamic range. And the present invention is applied to a displacement parabola for direct digital frequency synthesis. The parameter calculation method of the equation (yi=a*(d+Xi)2+c) can be used to calculate the a, c, and d parameters in the displacement parabolic equation, so that the approximate sine wave value calculated by the displacement parabolic equation is The sum of the squared errors of the ideal sine wave values is reduced. However, the above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the invention. Therefore, those skilled in the art will be able to modify and change the above embodiments. Without departing from the spirit of the invention, the scope of the invention should be as set forth in the appended claims. FIG. 1 shows a schematic diagram of an approximate sine wave generated by a parabolic interpolation method of the prior art; A conventional parabolic interpolation method produces a schematic diagram of the absolute error of a sine wave and an ideal chord wave; FIG. 3 shows a spectroscopic diagram of an approximate sine wave generated by a parabolic interpolation method of the prior art; FIG. 4 shows a parabolic interpolation using a conventional technique. The method produces an approximate sine wave diagram; FIG. 5 shows a schematic diagram of the absolute error of generating a sine wave and an ideal sine wave by a parabolic interpolation method of the prior art; The parabolic interpolation method of the technology produces a spectrum diagram of approximate chord and skin; 133588.doc -16· 201021427 Figure 7 shows a schematic flow chart of the parameter calculation method of the displacement parabolic equation for direct digital frequency synthesis; and Fig. 8 A schematic diagram showing a direct digital frequency synthesizing device of the present invention; FIG. 9 is a schematic diagram showing an absolute error between an approximate sine wave amplitude and an ideal sine wave amplitude generated by the present invention; FIG. 12 is a circuit diagram showing the direct digital frequency synthesizing device of the present invention; A schematic diagram of the time domain simulation results of the present invention; Figure 13 shows the sine wave spectrum diagram of Figure 12 above; and Figure 14 shows a solid wafer measurement shmoo Plot diagram of the present invention. [Description of main component symbols] 80 Direct digital frequency synthesizing device 81 of the present invention Counting circuit 82 Phase cutoff circuit 83 Symmetric circuit 84 Phase shift circuit 85 Phase sine wave conversion circuit 86 Symbol circuit 811 First adder 812 First register 841 A multiplexer 842 second register 845 second adder 851 squarer 852 shifter 133588.doc -17- 201021427 853 854 855 856 857 third register second multiplexer third adder group fourth Register third multiplexer 133588.doc -18-