201029130 六、發明說明： 【發明所屬之技術領域】 本發明係關於_種無如職基韻觀方法，特別 於一種利用可移除式臨時核心層進行增層製程之盔核心 基板的製造方法。 …、 衣 【先前技術】 現今，半導體封裝產業為了滿足各種高密度封裝之需求， 逐漸發展出各種不同型式之封裝構造，其中常見具有基板 (substrate)之封裝構造包含球格陣列封裝構造(Μ grid ， BGA)、針腳陣列封裝構造恤gri(j航砂，pGA)、接點陣列封 裝構造(land grid airay，LGA)或基板上晶片封裝構造加加〇n chip ’ BOC)等。在上述封裝構造中，該基板之一上表面承載有 至夕、日曰片’並經由打線(wire bonding)或凸塊(bumping)製程 將晶>ί的數個接墊電性連接至該基板之上表面的數個焊墊。同 時，該基板之一下表面亦必需提供大量的焊墊，以焊接數個輸 出端。通常，該基板係一多層電路板，其除了在上、下表面提 供表面電路層以形成所需焊墊之外，其内部亦具有至少一内電 © 路層及數個導通孔，以重新安排上、下表面的焊墊之連接關 係。因此，如何製造具有多層電路之封裝用基板，亦為封裝產 業之一重要關鍵技術。 舉例而言，請參照第1圖所示，其揭示一種習用封裝基板 10之構、ie ’其中該封裝基板1〇係以一核心層(core layer)l 1為 中心，並藉由增層法(build-up)在該核心層η之兩侧分別向外 依序形成一第一電路層12、一第一介電層13、一第二電路層 14、一第二介電層15、一表面電路層16及一防谭層17。再者， 在增層期間，該核心層11另可能形成數個電鍍通孔(plating through hole)lll貫穿其間，以電性連接兩侧之該第一電路層 12。該第一介電層13可能形成數個導通孔(conductive via)i31 201029130 U其間’以電性連接該第—及第二電路層12、14。該 ί 形成數瓣通孔151貫穿其間，以電性連“ _電路層14及表面電路層16。最後，該防焊層16形成數 2開口 161 ’以裸露一部分的絲面電路層16，以提供數個焊 垃16/立置）’以便結合金屬、線、凸塊或錫球等電性連 接構造(未緣示）。 上述習用封裝基板10大量應用在目前之半導體封裝製程 中。然而，為了符合半導體封裝之小型化需求，因此有必要進 一步設法減少該封裝基板10的整體厚度。然而，該封裝基板 10在增層細不可避免的必需使用具有足解度的該核心層 1卜以確保能提供足夠的支撐強度，及防止因熱應力(thermal stress)不均勻所發生的勉曲等(warpage)缺陷。但是，使用該核 心層11卻也會佔用過多厚度空間，導致不利於降低該封 板的整體厚度。另一方面，當整體厚度不變時，也難以藉 由減少該核心層11之厚度，以將省下來的厚度空間用來增加 電路層的總層數，因此使用該核心層U亦不利於提高電路集 成度。 、 故，有必要提供一種封裝基板的製造方法，以解決習知技 術所存在的問題。201029130 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for making a baseless view, and particularly to a method for manufacturing a helmet core substrate using a removable temporary core layer for a build-up process. ..., [Previous Technology] Nowadays, in order to meet the needs of various high-density packaging, the semiconductor packaging industry has gradually developed various types of package structures. Among them, a package structure with a substrate includes a grid array package structure (Μ grid , BGA), pin array package structure shirt gri (j aeronautical sand, pGA), contact array package structure (land grid airay, LGA) or substrate package structure plus 'n chip 'BOC). In the above package structure, one of the upper surfaces of the substrate carries the slabs and the plurality of pads of the crystals are electrically connected to the slabs by wire bonding or bumping processes. A number of pads on the surface above the substrate. At the same time, a large number of pads must be provided on the lower surface of the substrate to solder several outputs. Generally, the substrate is a multi-layer circuit board, which has a surface circuit layer on the upper and lower surfaces to form a desired pad, and has at least one internal circuit layer and a plurality of via holes therein to re Arrange the connection relationship of the pads on the upper and lower surfaces. Therefore, how to manufacture a package substrate with a multilayer circuit is also an important key technology in the packaging industry. For example, please refer to FIG. 1 , which discloses a structure of a conventional package substrate 10 , wherein the package substrate 1 is centered on a core layer 11 and is grown by a layering method. Forming a first circuit layer 12, a first dielectric layer 13, a second circuit layer 14, a second dielectric layer 15, and a second outwardly on the two sides of the core layer η. The surface circuit layer 16 and an anti-tank layer 17. Moreover, during the layering, the core layer 11 may further form a plurality of plating through holes 111 therebetween to electrically connect the first circuit layers 12 on both sides. The first dielectric layer 13 may form a plurality of conductive vias i31 201029130 U to electrically connect the first and second circuit layers 12, 14. The ί is formed with a plurality of through-holes 151 extending therebetween to electrically connect the "- circuit layer 14 and the surface circuit layer 16. Finally, the solder resist layer 16 forms a number of openings 161' to expose a portion of the surface circuit layer 16 to A plurality of soldering strips 16/stand-ups are provided for bonding metal, wires, bumps or solder balls, etc. (not shown). The above-mentioned conventional package substrate 10 is widely used in current semiconductor packaging processes. In order to meet the miniaturization requirements of the semiconductor package, it is necessary to further reduce the overall thickness of the package substrate 10. However, it is inevitable that the package substrate 10 is inevitably used to ensure the core layer 1 having a sufficient degree of stability. It can provide sufficient support strength and prevent warpage defects caused by uneven thermal stress. However, the use of the core layer 11 also takes up too much thickness space, which is not conducive to reducing the seal. The overall thickness of the board. On the other hand, when the overall thickness is constant, it is also difficult to reduce the thickness of the core layer 11 to increase the total thickness of the circuit layer. Number, the use of the core layer nor U help improve the integrated circuit degree., It is necessary to provide a method for manufacturing a package substrate, in order to solve the conventional technical problem exists.
【發明内容】 本發明之主要目的在於提供一種無核心封裝基板的製造方 法，其係利用臨時核心層在增層期間提供足夠支撐強度，並可 在增層後移除臨時核心層，進而有利於降低基板厚度及提高電 路集成度。 本發明之次要目的在於提供一種無核心封裝基板的製造方 法’其係利用臨時核心層進行增層，以同時在其兩侧製做二組 無核心封裝基板，進而提高生產速度、降低製造成本及確保增 層良率。 本發明之另一目的在於提供一種無核心封裝基板的製造方 4 201029130 法’其係利用臨時核心層進行增層，臨時核心層的表面具有可 撕除之金屬箔層’可直接轉用做為無核心封裝基板的表面電路 層’進而簡化增層製程、提高增層效率及降低備料成本。 、為達上述之目的，本發明提供一種無核心封裝基板的製造 方法’其包含：提供一臨時核心層；在該臨時核心層之二侧分 別依序堆疊一第一金屬箔層、一第一介電層及第二金屬箔層， 其中該第一金屬箔層具有一平坦表面及一粗糙表面，該平坦表 面朝向該臨時核心層，及該粗糙表面朝向該第一介電層；對每 二該第二金屬箔層進行圖案化，以分別形成一第二電路層；在 每一該第二電路層外堆疊至少一增層結構，該增層結構包含一 增層介電層及一增層金屬箔層；以及，移除該臨時核心層，以 得到二無核心封裝基板，每一該無核心封裝基板至少包含該第 一金屬箔層、第一介電層、第二電路層及至少一增層結構。 在本發明之一實施例中，在提供該臨時核心層之步驟中， 該臨時核心層係為含有B階段熱固性樹脂之核心層。 在本發明之一實施例中，在提供該臨時核心層及壓合該第 一金屬箔層之步驟中，該臨時核心層之每一侧具有一臨時黏性 表面，以結合於該第一金屬箔層之平坦表面。 在本發明之一實施例中，在堆疊該第一金屬箔層、第一介 ❹ 電層及第二金屬箔層之步驟後，進行加熱處理，以永久性去除 該臨時核心層之臨時黏性表面的黏性。 在本發明之一實施例中，在提供該臨時核心層及壓合該第 一金屬箔層之步驟中，該臨時核心層之每一侧具有一金屬支稽 層’該金屬支撐層具有一粗糙表面及一平坦表面，該金屬支撐 層之粗糖表面結合於該臨時核心層之表面，及該金屬支樓層之 平坦表面結合於該第一金屬箔層之平坦表面。 在本發明之一實施例中，該臨時核心層之金屬支撐層的厚 度大於該第一金屬箔層之厚度。 在本發明之一實施例中，在堆疊該增層結構之步驟後及移 除該臨時核心層之步驟前，另對該增層結構之增層介電層及增 5 201029130 ，以形成數個導通孔及— 層金屬箔層進行鑽孔、填孔及圖案化 增層電路層。 /在本發明之一實施例中，在得到該無核心封裝基板之步驟 後’另對該無核心封裝基板之第一金屬箔層及第一介電層進行 鑽孔、填孔及圖案化，以形成一第一電路層及數個導通孔。 在本發明之一實施例中，在形成該第一電路層之步驟後， 在該第一電路層上形成一防焊層(solder mask)，並對該防焊層 進行圖案化，以形成數個開口，裸露一部分的該第一電路層， 以提供數個焊墊。SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a coreless package substrate, which utilizes a temporary core layer to provide sufficient support strength during layer buildup, and which can remove the temporary core layer after layer buildup, thereby facilitating Reduce substrate thickness and increase circuit integration. A secondary object of the present invention is to provide a method for manufacturing a coreless package substrate, which utilizes a temporary core layer for layering to simultaneously form two sets of coreless package substrates on both sides thereof, thereby improving production speed and manufacturing cost. And to ensure the increase in yield. Another object of the present invention is to provide a method for manufacturing a coreless package substrate. The method of the present invention is to use a temporary core layer for layering, and the surface of the temporary core layer has a peelable metal foil layer, which can be directly used as The surface circuit layer of the coreless package substrate simplifies the build-up process, increases the layering efficiency, and reduces the cost of stock preparation. For the purpose of the present invention, the present invention provides a method for manufacturing a coreless package substrate, which comprises: providing a temporary core layer; sequentially stacking a first metal foil layer on each of the two sides of the temporary core layer, a first a dielectric layer and a second metal foil layer, wherein the first metal foil layer has a flat surface and a rough surface, the flat surface faces the temporary core layer, and the rough surface faces the first dielectric layer; The second metal foil layer is patterned to form a second circuit layer, and at least one build-up structure is stacked outside each of the second circuit layers, the build-up structure comprising a build-up dielectric layer and a build-up layer a metal foil layer; and removing the temporary core layer to obtain two core package substrates, each of the coreless package substrates including at least the first metal foil layer, the first dielectric layer, the second circuit layer, and at least one Layered structure. In an embodiment of the invention, in the step of providing the temporary core layer, the temporary core layer is a core layer containing a B-stage thermosetting resin. In an embodiment of the present invention, in the step of providing the temporary core layer and pressing the first metal foil layer, each side of the temporary core layer has a temporary adhesive surface for bonding to the first metal The flat surface of the foil layer. In an embodiment of the invention, after the step of stacking the first metal foil layer, the first dielectric layer and the second metal foil layer, heat treatment is performed to permanently remove the temporary viscosity of the temporary core layer. The viscosity of the surface. In an embodiment of the present invention, in the step of providing the temporary core layer and pressing the first metal foil layer, each side of the temporary core layer has a metal branch layer. The metal support layer has a roughness. a surface and a flat surface, the rough sugar surface of the metal support layer is bonded to the surface of the temporary core layer, and the flat surface of the metal support floor is bonded to the flat surface of the first metal foil layer. In one embodiment of the invention, the metal support layer of the temporary core layer has a thickness greater than the thickness of the first metal foil layer. In an embodiment of the present invention, after the step of stacking the build-up structure and before the step of removing the temporary core layer, the additional dielectric layer of the build-up structure is increased by 5 201029130 to form a plurality of The via hole and the layer of metal foil are drilled, filled and patterned to form a circuit layer. In an embodiment of the present invention, after the step of obtaining the coreless package substrate, the first metal foil layer and the first dielectric layer of the coreless package substrate are drilled, filled, and patterned. To form a first circuit layer and a plurality of via holes. In an embodiment of the invention, after the step of forming the first circuit layer, a solder mask is formed on the first circuit layer, and the solder resist layer is patterned to form a number An opening exposes a portion of the first circuit layer to provide a plurality of pads.
❹ /在本發明之一實施例中’在得到該無核心封裝基板之步驟 後’另對該增層結構之增層介電層及增層金屬箔層進行鑽孔、 填孔及圖案化，以形成數個導通孔及一增層電路層。 在本發明之一實施例中’在形成該增層電路層之步驟後， 在該增層電路層上形成一防烊層，並對該防焊層進行圖案化， 以形成數個開口，裸露一部分的該增層電路層，以提供數個焊 墊。 在本發明之一實施例中，在形成該防焊層及焊墊之步驟 後，在該焊墊之表面形成一助焊層。 在本發明之一實施例中，該助焊層選自電鍍鎳層、電鍍金 層、無電链錄化金層(electroless Ni/Au)、浸鍍銀（immersion silver )、浸鍵錫（immersion tin )或有機保護膜(organic solderability preservatives，0SP)。 在本發明之一實施例中，該第一金屬箔層、第二金屬箔層 及增層金屬箔層之厚度實質介於10至35微米之間。 在本發明之一實施例中，該第一介電層及增層介電層之厚 度實質介於30至55微米之間。 【實施方式】 為了讓本發明之上述及其他目的、特徵、優點能更明顯易 懂，下文將特舉本發明較佳實施例，並配合所附圖式，作詳細 201029130 說明如下。 «月參照第2A至圖戶斤示，本發明第一實施例之無核心封 裝基板的製造方法主要包含下列步驟：提供一臨時核心層2〇 ; 在該臨時核心層20之二側分別依序堆疊一第一金屬箔層21、 具有一平坦表面211及一粗糖表面212，該平坦表面211朝向 該臨時核心層20，及該粗糙表面212朝向該第一介電層22 ; 對每-該第二金屬騎23進行圖案化，以分別形成一第二電 路層230;在每一該第二電路層230外堆疊至少一增層結構 30，該增層結構30包含一增層介電層31及一增層金屬箔層 32，以及，移除該臨時核心層2〇 ,以得到二無核心封裝基板 200，每一該無核心封裝基板2〇〇至少包含該第一金屬箔層 21、第一介電層22、第二電路層230及至少一增層結構3〇。 凊參照第2A圖所示，本發明第一實施例之無核心封裝基 板的製造方法第一步驟係：提供一臨時核心層2〇。在本步驟 中，該臨時核心層20較佳係選自含有B階段熱固性樹脂 (B-stage thermosetting resin)之核心層，例如含有B階段環氧樹 脂之核心層，另外亦可能含有雙順丁烯二酸醯亞胺三氮樹脂 (bismaleimidetriazine ’ BT)等熱固性樹脂。上述含有b階段熱 參 固性樹知之核心層係藉由將玻璃纖維(glass fiber)布等填充;^ 料預浸在生漆(varnish)狀態的A階段熱固性樹脂半乾後並經加 熱軟化所製成。因此’該臨時核心層2〇之每一侧皆且有一臨 時黏性表面201、202 ’以提供一預定程度之臨時黏性。在本 實施例中，該臨時核心層20可選自玻纖布基材環氧樹脂銅箔 基板’例如FR-4或FR-5等’但並不限於此。該臨時核心層 20用以提供增層製程所需之足夠支撐強度，因此必需具備足 夠厚度’但在具備足夠支撲強度的前題下，本發明並不限制該 臨時核心層20之厚度範圍。 μ 請再參照第2Α圖所示，本發明第一實施例之無核心封裝 基板的氣造方法第二步驟係：在該臨時核心層2〇之二侧分別 7 201029130 ❹ 依序堆疊一第一金屬箔層21、一第一介電層22及第二金屬猪 層23。在本步驟中，該第一金屬箔層21及第二金屬箔層23 係可預先藉由電鍍法(electroplating)或輾軋法(rolling)加以製成 備用，其中至少該第一金屬箔層21必需具有一平坦表面211 及一粗縫表面212 ’該平坦表面211朝向該臨時核心層20，及 該粗糙表面212朝向該第一介電層22。上述堆疊排列關係之 作用將另於下文加以詳細說明。再者，該第一金屬箔層21及 第二金屬箔層23可取材自銅、銘、鎳、金、銀等金屬或合金， 但並不限於此。該第一金屬箔層21及第二金屬箔層23之厚度 較佳實質介於10至35微米之間。值得注意的是，當該臨時核 心層20選用FR_4或FR_5等玻纖布基材環氧樹脂銅箔基板 時’該臨時核心層2〇每一侧的臨時黏性表面2〇1、2〇2已預先 =有-平坦表面朝内之金屬騎，其可直接用以做為該第一 ^屬箔層21，因而有利於減少備料成本或簡化堆疊步驟。該 二層22實質包含具娜_性之®階段顏性樹脂等 B 樹脂錢順了烯三麵亞胺三 im，必要時，亦可加入玻璃纖維布等填充材料。該 厚度較佳實質介於3〇至55微米之間。在進 第時’可在完成堆#之後，進行加熱處理，使 ，日巧心層20之臨時黏性表面2〇1、2 性。此時，該臨時黏性表面2〇丨、·^又性云除具黏 ^ 21 表面212蔣合七a u· a ^第金屬v白層21之粗糖 時該第二金 板的實=之無核心封裝基 藉由現有的塗佈雜、光^ _在本步齡’本發明可 金屬落層23進行圓案化，以去該第二 23，因而形成該第二電路層⑽。必要時，本; 8 201029130 化之前(或之後），選擇進行鑽孔及填孔的製程，以在該第一 電層22中形成數個導通孔(未繪示），該鑽孔製程可選自 或機械鑽孔，而該填孔製程係藉由電鍍方式加以完成。惟，在 本實施例中，本發明係在第五步驟之後，才在該第一介電 22中形成數個導通孔221(如帛2G圖所示）。上述導通孔的形 成時機並非用以限制本發明。 請參照第2C、2D及2E圖所示，本發明第一實施例之無核 〜封裝基板的製造方法第四步驟係：在每一該第二電路層230 外堆疊至少一增層結構30、40。在本實施例中，本發明係設 置二組該增層結構30、40，但其數量並不限於此，其亦可設 置一組、二組或三組以上。該增層結構3〇包含一增層介電層 31及一增層金屬箔層32。該增層介電層31實質相同於該第一 ^電層22 ’同樣實質包含具備臨時黏性之3階段熱固性樹脂 等絕緣材料’及其厚度較佳實質介於3〇至55微米之間。該增 層金屬箔層32實質相同於該第二金屬箔層23，同樣可取材自 ，、鋁、鎳、金、銀等金屬或合金，及其厚度較佳實質介於 〇至35微米之間。在本實施例中，如第2C圖所示，本發明 土在每一該第二電路層230外堆疊該增層結構30，並適當加 熱處理，以vf吏該增層介電層31結合於該第二電路層23〇，並 使該增層金屬荡層32朝向外侧。接著，如第2D圖所示，對 該增層結構30之增層介電層31及增層金屬箔層32進行鑽 孔、填孔及圖案化等處理，以形成數個導通孔311及一增層電 =層320。再者’如第2E圖所示，以類似第％圖的做法，進 :步在每一該增層電路層320外再堆疊另-該增層結構40， ^增層結構40包含一增層介電層41及一增層金屬箔層42， ，實質相同於該增層介電層31及增層金屬箔層32。必要時， 發明亦可在對該增層介電層41及增層金屬箔層42選擇進行 —孔、填孔及圖案化的製程，以形成數個導通孔(未繪示)及另 ^層(未繪示）。惟，在本實施例中，為了使堆叠結構 、有對稱性以防止熱應力(^επη&ι stress)不均勻造成翹曲 9 201029130 (warpage)缺陷’本發明係在第五步驟之後，才使該增層介電層 41及增層金屬箔層42形成數個導通孔411及另一增層電路層 420(如第2G圖所示）。 請參照第2F、2G及2H圖所示，本發明第一實施例之無核 心，裝基板的製造方法第五步驟係：移除該臨時核心層2〇， 以得到二無核心封裴基板2〇〇。在本實施例中，該臨時核心層 20之臨時黏性表面2(U、202已在上述數次堆疊加熱過程中永 久性去除其黏性。此時，該平坦表面211與臨時黏性表面2〇卜 202的最終結合強度將明顯小於該粗糖表面2丨2與第一介電層 22之最終結合強度。因此，如第2F圖所示，本發明可輕易藉 由人工或簡易機具移除該臨時核心層2〇,並留下二組該無核 心封裝基板200，其中每一該無核心封裝基板2〇〇至少包含該 第一金屬箔層21、第一介電層22、第二電路層230及至少一 增層結構30、40。在本實施例中，每一該無核心封裝基板2〇〇 包含二組該增層結構30、40，但並不限於此。接著，如第2〇 圖所示，在移除該臨時核心層20之後，可對每一該無核心封 裝基板200之第一金屬箔層21及第一介電層22進行鑽孔、填 孔及圖案化，以形成一第一電路層；21〇及數個導通孔221。同 ，，對該增層結構40之增層介電層41及增層金屬箔層42進 G 行鑽孔、填孔及圖案化，以形成數個導通孔411及一增層電路 層420。隨後，如第2H圖所示，則可在該第一電路層21〇上 形成一防焊層(solder mask)50，並對該防焊層50進行圖案化， 以形成數個開口 51 ,裸露一部分的該第一電路層21〇，以提供 數個焊塑·(未標示）。同時，在該增層電路層42〇上形成另一防 谭層50，並對該防焊層50進行圖案化，以形成數個開口 51， 裸露一部分的該增層電路層42〇，以提供數個焊墊(未標示）。 最後，依產品需求’選擇性的在該第一電路層21〇(或增層電路 層420)之焊墊的表面形成一助焊層6〇，該助焊層6〇係可選自 電錢鎳層、電錢金層、無電錄錄化金層(elec加lessNi/Au)、浸 鍵銀（immersionsilver)、浸鑛錫（immersiontin)或有機保護 201029130 膜(organic solderability preservatives，OSP)。 藉由上述第一至第五步驟’本發明第一實施例即可利用該 臨時核心層20提供足夠支撐強度，以便順利進行增層製程f 並可在增層後移除該臨時核心層2〇,故有利於降低該無核心 封裝基板200的整體厚度及提高該無核心封裝基板2〇〇的電路 集成度。由於可同時在該臨時核心層20的兩侧製做二組無核 心封裝基板200 ’因此不但可相對提高生產速度及降低製造成 本’亦可藉由二側對稱進行增層，以確實防止熱應力不均勻所 造成的翹曲缺陷’進而確保增層良率。 φ 請參照第3圖所示，本發明第二實施例之無核心封裝基板 的製造方法係相似於本發明第一實施例，但該第二實施例使用 之臨時核心層70不同於該第一實施例之臨時核心層2〇。在第 二實施例中，在預先製備該臨時核心層7〇時，該臨時核心層 70之每一侧已具有一金屬支撐層71及一第一金屬箔層72。例 如’該臨時核心層70可選用特殊之FR_4或FR-5等玻纖布基 材環氧樹脂銅箔基板，亦即該臨時核心層7〇每一侧的表面已 預先依序黏附有該金屬支撐層71及第一金屬箔層72，因而有 利於減少備料成本或簡化堆疊步驟。更詳言之，該金屬支播層 71具有一粗糙表面711及一平坦表面712,同時該第一金屬箔 層72具有平坦表面721及一粗糖表面722。在本發明中， 該金屬支撐層71之粗糙表面711結合於該臨時核心層7〇，其 中該臨時核心層70可具有臨時黏性表面(未標示），但亦可不 具有臨時黏性表面。再者，該金屬支撐層71之平坦表面712 結合於該第一金屬箔層72之平坦表面721，該第一金屬箔層 72之粗糙表面722則用以依序堆疊結合一第一介層電π及一 第二金屬箔層74。因此，該金屬支撐層71與臨時核心層7〇 之最終結合強度會大於該金屬支撐層71與第一金屬箔層72之 最終結合強度。當第二實施例完成增層並欲移除該臨時核心層 7〇時’該臨時核心層70將連同該金屬支撐層71 一起被移除， 僅由該第-金屬羯層72、第一介層電73、第二金属荡層％及 201029130 至少層結構(未繪示)構成二組無核心封裝基板(未繪示）。 值f导注意的是，由於該臨時核心層70之金屬支撐層71僅 用以提供支撐作用，因此本發明並不限制該金屬支撐層71之 厚度丄但其厚度較佳大於該第一金屬箔層72之厚度。該第一 金屬箔層72之厚度較佳實質介於10至35微米之間。除了該 臨時核〜層7G的構造不同之外，該第二實施例之無核心封裝 基板的製造方法係實質相同於該第一實施例，故本發明不再另 予詳細說明該第二實施例之各個步驟。❹ In one embodiment of the present invention, after the step of obtaining the coreless package substrate, drilling, filling and patterning the build-up dielectric layer and the build-up metal foil layer of the build-up structure are further performed. To form a plurality of vias and a build-up circuit layer. In an embodiment of the present invention, after the step of forming the build-up circuit layer, a ruthenium-proof layer is formed on the build-up circuit layer, and the solder resist layer is patterned to form a plurality of openings, exposed A portion of the build-up circuit layer provides a plurality of pads. In an embodiment of the invention, after the step of forming the solder resist layer and the pad, a solder layer is formed on the surface of the pad. In an embodiment of the invention, the soldering layer is selected from the group consisting of an electroplated nickel layer, an electroplated gold layer, an electroless Ni/Au, an immersion silver, and an immersion tin. Or organic solderability preservatives (0SP). In one embodiment of the invention, the thickness of the first metal foil layer, the second metal foil layer, and the build-up metal foil layer is substantially between 10 and 35 microns. In one embodiment of the invention, the thickness of the first dielectric layer and the build-up dielectric layer is substantially between 30 and 55 microns. The above and other objects, features and advantages of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The manufacturing method of the coreless package substrate according to the first embodiment of the present invention mainly comprises the following steps: providing a temporary core layer 2〇; respectively, on the two sides of the temporary core layer 20, respectively. Stacking a first metal foil layer 21 having a flat surface 211 and a rough sugar surface 212, the flat surface 211 facing the temporary core layer 20, and the rough surface 212 facing the first dielectric layer 22; The two metal rides 23 are patterned to form a second circuit layer 230, and at least one build-up structure 30 is disposed outside each of the second circuit layers 230. The build-up structure 30 includes a build-up dielectric layer 31 and An additional metal foil layer 32 is removed, and the temporary core layer 2 is removed to obtain two core package substrates 200, each of the coreless package substrates 2 including at least the first metal foil layer 21, first The dielectric layer 22, the second circuit layer 230, and at least one build-up structure 3A. Referring to Fig. 2A, the first step of the method for manufacturing a coreless package substrate according to the first embodiment of the present invention is to provide a temporary core layer. In this step, the temporary core layer 20 is preferably selected from a core layer containing a B-stage thermosetting resin, such as a core layer containing a B-stage epoxy resin, and may also contain a bis-butene. A thermosetting resin such as bismaleimidetriazine 'BT. The above-mentioned core layer containing the b-stage thermal refractory tree is prepared by preliminarily filling a glass fiber cloth or the like into a varnish state, and then heating and softening the A-stage thermosetting resin. to make. Thus, each of the temporary core layers 2 has a temporary viscous surface 201, 202' to provide a predetermined degree of temporary adhesion. In the present embodiment, the temporary core layer 20 may be selected from a fiberglass cloth substrate epoxy copper foil substrate 'e.g., FR-4 or FR-5, etc.' but is not limited thereto. The temporary core layer 20 is used to provide sufficient support strength for the build-up process and therefore must be of sufficient thickness 'but with the premise of having sufficient puff strength, the present invention does not limit the thickness range of the temporary core layer 20. The second step of the gas-making method of the coreless package substrate according to the first embodiment of the present invention is as follows: on the two sides of the temporary core layer 2, respectively, 7 201029130 ❹ sequentially stacking a first A metal foil layer 21, a first dielectric layer 22 and a second metal pig layer 23. In this step, the first metal foil layer 21 and the second metal foil layer 23 may be prepared in advance by electroplating or rolling, wherein at least the first metal foil layer 21 is used. It is necessary to have a flat surface 211 and a rough surface 212 'the flat surface 211 facing the temporary core layer 20, and the rough surface 212 faces the first dielectric layer 22. The role of the above stacked arrangement relationship will be described in detail below. Further, the first metal foil layer 21 and the second metal foil layer 23 may be made of a metal or an alloy such as copper, indium, nickel, gold or silver, but are not limited thereto. The thickness of the first metal foil layer 21 and the second metal foil layer 23 is preferably substantially between 10 and 35 microns. It is worth noting that when the temporary core layer 20 is made of a fiberglass cloth substrate epoxy resin copper foil substrate such as FR_4 or FR_5, the temporary adhesive surface of each temporary core layer 2 is 2〇1, 2〇2 It has been previously = there is a metal ride with a flat surface facing inward, which can be used directly as the first foil layer 21, thereby facilitating the reduction of the stock cost or the simplification of the stacking step. The second layer 22 substantially contains a B resin such as a naphthalene resin, and a tri-aniline im im, and if necessary, a filler such as a glass fiber cloth. The thickness is preferably substantially between 3 and 55 microns. At the time of the advancement, the heat treatment may be performed after the completion of the pile #, so that the temporary adhesive surface of the core layer 20 is 2〇1 and 2nd. At this time, the temporary viscous surface 2〇丨,·^又性云除粘2 21 surface 212 Jiang Heqiu au· a ^ metal v white layer 21 of raw sugar when the second gold plate is true = The core package base is rounded by the existing coating miscellaneous, photo-forming layer 23 of the present invention to form the second circuit layer (10). If necessary, before; 201028130 (or after), the process of drilling and filling is selected to form a plurality of via holes (not shown) in the first electrical layer 22, and the drilling process is optional. Self- or mechanical drilling, and the filling process is completed by electroplating. However, in the present embodiment, the present invention forms a plurality of via holes 221 (shown in FIG. 2G) in the first dielectric 22 after the fifth step. The timing of forming the via holes described above is not intended to limit the present invention. Referring to FIGS. 2C, 2D, and 2E, the fourth step of the method for manufacturing a coreless-package substrate according to the first embodiment of the present invention is: stacking at least one build-up structure 30 outside each of the second circuit layers 230, 40. In the present embodiment, the present invention provides two sets of the build-up structures 30, 40, but the number is not limited thereto, and one, two or more sets may be provided. The build-up structure 3A includes a build-up dielectric layer 31 and a build-up metal foil layer 32. The build-up dielectric layer 31 is substantially identical to the first electrical layer 22' and substantially comprises an insulating material such as a three-stage thermosetting resin having a temporary viscosity, and the thickness thereof is preferably substantially between 3 Å and 55 μm. The build-up metal foil layer 32 is substantially identical to the second metal foil layer 23, and may also be obtained from a metal or alloy such as aluminum, nickel, gold, silver, etc., and the thickness thereof is preferably between 〇 and 35 microns. . In the present embodiment, as shown in FIG. 2C, the soil of the present invention is stacked on the outer surface of each of the second circuit layers 230, and is heated appropriately, and is bonded to the layered dielectric layer 31 by vf. The second circuit layer 23 is turned on and the build-up metal layer 32 is directed outward. Next, as shown in FIG. 2D, the build-up dielectric layer 31 and the build-up metal foil layer 32 of the build-up structure 30 are subjected to drilling, hole filling, patterning, etc. to form a plurality of vias 311 and a Layering = layer 320. Furthermore, as shown in FIG. 2E, in a similar manner to the first graph, steps are further stacked outside each of the build-up circuit layers 320. The build-up structure 40, the build-up structure 40 includes a build-up layer. The dielectric layer 41 and the build-up metal foil layer 42 are substantially identical to the build-up dielectric layer 31 and the build-up metal foil layer 32. If necessary, the invention may also select a process of performing a hole, a hole filling, and a patterning on the build-up dielectric layer 41 and the build-up metal foil layer 42 to form a plurality of via holes (not shown) and another layer. (not shown). However, in the present embodiment, in order to make the stacked structure and symmetry to prevent thermal stress (^επη &ι stress) unevenness, warpage 9 201029130 (warpage) defect is caused by the present invention after the fifth step. The build-up dielectric layer 41 and the build-up metal foil layer 42 form a plurality of vias 411 and another build-up circuit layer 420 (as shown in FIG. 2G). Referring to FIGS. 2F, 2G, and 2H, the fifth step of the method for manufacturing a substrate without a core according to the first embodiment of the present invention is: removing the temporary core layer 2〇 to obtain a second coreless package substrate 2 Hey. In the present embodiment, the temporary adhesive surface 2 of the temporary core layer 20 (U, 202 has permanently removed its viscosity during the above-mentioned several stack heating processes. At this time, the flat surface 211 and the temporary adhesive surface 2 The final bond strength of the slab 202 will be significantly less than the final bond strength of the raw sugar surface 2丨2 to the first dielectric layer 22. Thus, as shown in Figure 2F, the present invention can be easily removed by manual or simple implements. The temporary core layer 2〇, and leaving two sets of the coreless package substrate 200, wherein each of the coreless package substrates 2 includes at least the first metal foil layer 21, the first dielectric layer 22, and the second circuit layer 230 and at least one build-up structure 30, 40. In this embodiment, each of the coreless package substrates 2A includes two sets of the build-up structures 30, 40, but is not limited thereto. Next, as in the second As shown in the figure, after the temporary core layer 20 is removed, the first metal foil layer 21 and the first dielectric layer 22 of each coreless package substrate 200 may be drilled, filled, and patterned to form a first circuit layer; 21 turns and a plurality of vias 221. Similarly, the buildup structure 40 The build-up dielectric layer 41 and the build-up metal foil layer 42 are drilled, filled and patterned into G rows to form a plurality of vias 411 and a build-up circuit layer 420. Subsequently, as shown in FIG. 2H, A solder mask 50 may be formed on the first circuit layer 21, and the solder resist layer 50 is patterned to form a plurality of openings 51, and a portion of the first circuit layer 21 is exposed. To provide a plurality of solder moldings (not shown). At the same time, another anti-solder layer 50 is formed on the build-up circuit layer 42, and the solder resist layer 50 is patterned to form a plurality of openings 51, A portion of the build-up circuit layer 42 is exposed to provide a plurality of pads (not labeled). Finally, the pads of the first circuit layer 21 (or build-up circuit layer 420) are selectively selected according to product requirements. The surface of the solder layer 6 is formed, and the solder layer 6 can be selected from the group consisting of a nickel-nickel layer, an electric gold layer, an electroless gold layer (elec plus lessNi/Au), and an immersion silver (immersionsilver). Immersion tin or organic solderability preservatives (OSP). By the first to fifth steps described above The first embodiment of the present invention can utilize the temporary core layer 20 to provide sufficient support strength to smoothly carry out the build-up process f and remove the temporary core layer 2 after the build-up, thereby facilitating the reduction of the coreless package substrate. The overall thickness of the 200 and the circuit integration of the coreless package substrate 2 are improved. Since two sets of coreless package substrates 200 can be fabricated on both sides of the temporary core layer 20, the production speed can be relatively increased and the speed can be reduced. The manufacturing cost can also be layered by two-sided symmetry to surely prevent warpage defects caused by uneven thermal stress, thereby ensuring the build-up yield. φ Referring to FIG. 3, the manufacturing method of the coreless package substrate according to the second embodiment of the present invention is similar to the first embodiment of the present invention, but the temporary core layer 70 used in the second embodiment is different from the first embodiment. The temporary core layer of the embodiment is 2〇. In the second embodiment, when the temporary core layer 7 is prepared in advance, each side of the temporary core layer 70 has a metal supporting layer 71 and a first metal foil layer 72. For example, the temporary core layer 70 may be made of a special fiberglass cloth substrate epoxy resin foil substrate such as FR_4 or FR-5, that is, the surface of each side of the temporary core layer 7 has been adhered to the metal in advance. The support layer 71 and the first metal foil layer 72 are thus advantageous in reducing the cost of stock preparation or simplifying the stacking step. More specifically, the metal support layer 71 has a rough surface 711 and a flat surface 712, while the first metal foil layer 72 has a flat surface 721 and a raw sugar surface 722. In the present invention, the rough surface 711 of the metal support layer 71 is bonded to the temporary core layer 7, wherein the temporary core layer 70 may have a temporary adhesive surface (not shown), but may not have a temporary adhesive surface. Furthermore, the flat surface 712 of the metal supporting layer 71 is bonded to the flat surface 721 of the first metal foil layer 72, and the rough surface 722 of the first metal foil layer 72 is used to sequentially stack and bond a first dielectric layer. π and a second metal foil layer 74. Therefore, the final bonding strength of the metal supporting layer 71 and the temporary core layer 7〇 is greater than the final bonding strength of the metal supporting layer 71 and the first metal foil layer 72. When the second embodiment completes the buildup and wants to remove the temporary core layer 7〇, the temporary core layer 70 will be removed along with the metal support layer 71, only by the first metal layer 72, the first Layer layer 73, second metal layer % and 201029130 at least layer structure (not shown) constitute two sets of coreless package substrates (not shown). The value f indicates that since the metal supporting layer 71 of the temporary core layer 70 is only used to provide support, the present invention does not limit the thickness of the metal supporting layer 71, but the thickness thereof is preferably larger than the first metal foil. The thickness of layer 72. The thickness of the first metal foil layer 72 is preferably substantially between 10 and 35 microns. The manufacturing method of the coreless package substrate of the second embodiment is substantially the same as the first embodiment except that the configuration of the temporary core layer 7G is different. Therefore, the second embodiment of the present invention will not be described in detail. Each step.
如上所述，相較於第1圖之習用封裝基板10在增層時使用 該核心層11，導致不利於降低整體厚度或提高電路集成度等 缺點，第/A至2H及3圖之本發明利用該臨時核心層2〇在增 層期間提供足触翻度’並可在增層後移除賊時核心^ 20’因而有利於降低該無核心封裝基板2〇〇的整體厚度及提高 該無核心封裝基板200的電路集成度。再者，由於可同時在^ 臨時核心層20的兩側製做二組無核心封裝基板2〇〇，因此不 ，可相對提高生產速度及降低製造成本，亦可藉由二侧對稱進 行增層，以確實防止熱應力不均勻所造成的翹曲缺陷，進而確 保增層良率。此外，如第3圖所示，當該臨時核心層7〇的表 面具有可撕除之第一金屬箔層72時，該第一金屬箔層72可直 接轉用做為後續無核心封裝基板的表面電路層，因此能簡化與 層製程、提高增層效率及降低備料成本。 曰 雖然本發明已以較佳實施例揭露，然其並非用以限制本發 任何熟習此項技藝之人士，在不脫離本發明之精神和範圍 ，當可作各種更動與修飾，因此本發明之保護範圍當視後 之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖：習用封裝基板之示意圖。 第2A至2H圖：本發明第-實施例之無核心封裝基板的 方法之流程示意圖。 12 201029130 " 第3圖：本發明第二實施例之無核心封裝基板的製造方法之示 意圖。 【主要元件符號說明】 10封裝基板 111電鍍通孔 13第一介電層 14第二電路層 151導通孔 11核心層 12第一電路層 131導通孔 15第二介電層 16表面電路層 161 開口 _ 20臨時核心層 17防焊層 200無核心封裝基板 201臨時黏性表面 202臨時黏性表面 21第一金屬箔層 211平坦表面 22第一介電層 23第二金屬箔層 30增層結構 311導通孔 320增層電路層 φ 41增層介電層 42增層金屬猪層 210第一電路層 212粗糙表面 221導通孔 230第二電路層 31 增層介電層 32增層金屬箔層 40增層結構 411導通孔 420增層電路層 50防焊層 60助焊層 71金屬支撐層 Ή2平坦表面 721平坦表面 73第一介層電 51開口 70 臨時核心層 711粗糙表面 72第一金屬箔層 722粗糙表面 74第二金屬箔層 13As described above, the use of the core layer 11 in the build-up of the conventional package substrate 10 of FIG. 1 results in disadvantages such as reduction in overall thickness or improvement in circuit integration, and the invention of FIGS. AA to 2H and 3 Utilizing the temporary core layer 2 to provide foot flipping during the layering period and removing the thief core layer 20' after the layering is added, thereby facilitating reducing the overall thickness of the coreless package substrate 2 and improving the The degree of circuit integration of the core package substrate 200. Furthermore, since two sets of coreless package substrates 2 can be fabricated on both sides of the temporary core layer 20, the production speed and the manufacturing cost can be relatively increased, and the layers can be layered by two sides. In order to prevent warpage defects caused by uneven thermal stress, and to ensure the formation yield. In addition, as shown in FIG. 3, when the surface of the temporary core layer 7 has a peelable first metal foil layer 72, the first metal foil layer 72 can be directly used as a subsequent coreless package substrate. The surface circuit layer can simplify the layer process, increase the layering efficiency and reduce the cost of stock preparation. The present invention has been disclosed in its preferred embodiments, and it is not intended to limit the scope of the present invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. The scope of protection shall be subject to the definition of the scope of the patent application. [Simple description of the drawing] Fig. 1: Schematic diagram of a conventional package substrate. 2A to 2H are views showing a flow chart of a method of the coreless package substrate of the first embodiment of the present invention. 12 201029130 &3; Fig. 3 is a view showing a method of manufacturing a coreless package substrate according to a second embodiment of the present invention. [Main component symbol description] 10 package substrate 111 plated through hole 13 first dielectric layer 14 second circuit layer 151 via hole 11 core layer 12 first circuit layer 131 via hole 15 second dielectric layer 16 surface circuit layer 161 opening _ 20 temporary core layer 17 solder resist layer 200 without core package substrate 201 temporary adhesive surface 202 temporary adhesive surface 21 first metal foil layer 211 flat surface 22 first dielectric layer 23 second metal foil layer 30 buildup structure 311 Via 320 layer build-up circuit layer φ 41 build-up dielectric layer 42 build-up metal pig layer 210 first circuit layer 212 rough surface 221 via 230 second circuit layer 31 build-up dielectric layer 32 build-up metal foil layer 40 increase Layer structure 411 via hole 420 build-up circuit layer 50 solder mask layer 60 solder layer 71 metal support layer 平坦 2 flat surface 721 flat surface 73 first interlayer electricity 51 opening 70 temporary core layer 711 rough surface 72 first metal foil layer 722 Rough surface 74 second metal foil layer 13