CN103579009A - Package substrate, manufacturing method of the package substrate, chip packaging structure and manufacturing method of the chip packaging body - Google Patents

Abstract

A packaging substrate, which includes a copper foil substrate, a sputtered copper layer, a plurality of conductive contacts, a dielectric layer and a conductive circuit layer, the sputtered copper layer is formed on the surface of the copper foil substrate, and the plurality of conductive contacts Formed on the surface of the sputtered copper layer away from the copper foil substrate, the dielectric layer is located between the conductive circuit layer and the sputtered copper layer, and a plurality of conductive lines are formed in the dielectric layer. A plurality of conductive blind holes corresponding to the contacts one by one, the conductive line layer includes a plurality of conductive lines electrically connected to the plurality of conductive blind holes one by one and a plurality of connection pads electrically connected to the plurality of conductive lines one by one, Each conductive contact is electrically connected to each other through a corresponding conductive blind hole, a corresponding conductive line and a corresponding connection pad. The invention also provides a manufacturing method of the packaging substrate, a packaging structure and a manufacturing method of a chip packaging body.

Description

Package substrate and manufacturing method thereof, chip packaging structure and chip package manufacturing method

technical field

The invention relates to the technical field of chip packaging, in particular to a packaging substrate and a manufacturing method thereof, a chip packaging structure and a manufacturing method of a chip packaging body.

Background technique

The packaging substrate can provide electrical connection, protection, support, heat dissipation, assembly and other functions for the chip to achieve multi-pin, reduce the volume of packaged products, improve electrical performance and heat dissipation, ultra-high density or multi-chip modularization.

In the process of packaging the chip with the packaging substrate, when the thickness of the packaging substrate is small, it is necessary to use a rigid carrier plate for support. In the prior art, usually the front and back substrates are manufactured at the same time for encapsulation, and the carrier board is arranged between the two substrates. In order to separate the front and back chip packages obtained after packaging, it is usually necessary to use a special copper foil as the part connecting the carrier board and the package substrate. The special copper bowl has a structure in which an adhesive layer is sandwiched between two layers of copper foil, and the thickness of the two layers of copper foil is different. Such copper foil is expensive, which increases the cost of chip packaging.

Contents of the invention

Therefore, it is necessary to provide a packaging substrate and a manufacturing method thereof, a chip packaging structure and a manufacturing method of a chip packaging body, so as to reduce the cost of chip packaging.

A packaging substrate, which includes a copper foil substrate, a sputtered copper layer, a plurality of conductive contacts, a dielectric layer and a conductive circuit layer, the sputtered copper layer is formed on the surface of the copper foil substrate, and the plurality of conductive contacts Formed on the surface of the sputtered copper layer away from the copper foil substrate, the dielectric layer is located between the conductive circuit layer and the sputtered copper layer, and a plurality of conductive lines are formed in the dielectric layer. A plurality of conductive blind holes corresponding to the contacts one by one, the conductive line layer includes a plurality of conductive lines electrically connected to the plurality of conductive blind holes one by one and a plurality of connection pads electrically connected to the plurality of conductive lines one by one, Each conductive contact is electrically connected to each other through a corresponding conductive blind hole, a corresponding conductive line and a corresponding connection pad.

A method for manufacturing a packaging substrate, comprising the steps of: providing a first copper foil substrate, a film, and a second copper foil substrate, and pressing the film between the first copper foil substrate and the second copper foil substrate to obtain a carrier substrate, the The carrier substrate has opposite first surface and second surface; a first sputtered copper layer is formed on the first surface, and a second sputtered copper layer is formed on the second surface; a second sputtered copper layer is formed on the first sputtered copper layer. A plurality of first conductive contacts are formed by electroplating on the layer, and a plurality of second conductive contacts are formed by electroplating on the second sputtered copper layer; a first conductive contact is pressed on the plurality of first conductive contacts and the first sputtered copper layer. A dielectric layer and a first conductive layer, the second dielectric layer and the second conductive layer are laminated on a plurality of the second conductive contacts and the second sputtered copper layer; the first dielectric layer and the first conductive layer A plurality of first conductive blind holes corresponding to the plurality of first conductive contacts are formed in the layer, and the first conductive layer is fabricated to form a first conductive circuit layer, and the first conductive circuit layer includes a plurality of first conductive circuit layers. Blind holes—a plurality of first conductive lines that are electrically connected one by one and a plurality of first connection pads that are electrically connected to the plurality of first conductive lines one by one, so that each first conductive contact passes through a corresponding first conductive blind The hole, a corresponding first conductive line and a corresponding first connection pad are electrically connected to each other, forming a plurality of second conductive blind holes in the second dielectric layer and the second conductive layer, and forming the second conductive layer A plurality of second conductive lines and a plurality of second connection pads, each second conductive contact is electrically connected to the second connection pad through the corresponding second conductive blind hole and the second conductive line, thereby obtaining a multilayer substrate; and The multilayer substrate is divided between the first copper clad substrate and the second copper clad substrate, and the film between the first copper clad substrate and the second copper clad substrate is removed, so as to obtain two mutually separated packaging substrates.

A chip packaging structure, which includes a copper foil substrate, a sputtered copper layer, a plurality of conductive contacts, a dielectric layer, a conductive circuit layer, a solder resist layer and a chip, and the sputtered copper layer is formed on the surface of the copper foil substrate , the plurality of conductive contacts are formed on the surface of the sputtered copper layer away from the copper foil substrate, the dielectric layer is located between the conductive circuit layer and the sputtered copper layer, the dielectric layer There are a plurality of conductive blind holes corresponding to a plurality of conductive contacts one by one, and the conductive line layer includes a plurality of conductive lines electrically connected to the plurality of conductive blind holes and electrically connected to the plurality of conductive lines. A plurality of connection pads are connected, each conductive contact is electrically connected to a corresponding connection pad through a corresponding conductive blind hole, a corresponding conductive line, and the solder resist layer covers the surfaces of the multiple conductive lines and from The surface of the dielectric layer exposed by the wire line layer exposes the plurality of connection pads, a gold layer is formed on the surface of each connection pad, the chip is arranged on the surface of the solder resist layer, and is connected to each connection pad through a bonding wire. The gold layer on the surface of the connection pad is electrically connected.

A method for manufacturing a chip package, comprising the steps of: providing the package substrate;

Package a chip on the package substrate so that the chip is electrically connected to the connection pad of the conductive circuit layer; separate the copper foil substrate in the package substrate from the surface of the sputtered copper layer; remove the sputtered copper layer in each package substrate to expose forming the plurality of conductive contacts; and forming a solder ball on each conductive contact in the packaging substrate, thereby obtaining a chip package.

A method for manufacturing a chip package, comprising the steps of: providing the package structure;

separating the copper foil substrate in the packaging structure from the surface of the sputtered copper layer; removing the sputtered copper layer to expose the plurality of conductive contacts; and forming a solder ball on each conductive contact in the package structure, thereby A chip package is obtained.

A method for manufacturing a chip package, comprising the steps of: providing two copper foil substrates and a film, and pressing the film between the two copper foil substrates to obtain a carrying substrate, the carrying substrate has two opposite Sputtered surfaces; each sputtered surface is sputtered to form a layer of sputtered copper; each layer of sputtered copper is formed by electroplating a plurality of conductive contacts;

A dielectric layer and a conductive layer are laminated on both sides of the carrier substrate, and the dielectric layer is in contact with a plurality of conductive contacts and a sputtered copper layer; the dielectric layer and the conductive layer on each side Form a plurality of conductive blind holes corresponding to a plurality of conductive contacts one by one, and make the conductive layer to form a conductive circuit layer, the conductive circuit layer includes a plurality of conductive circuits electrically connected to the plurality of conductive blind holes and The plurality of conductive lines are electrically connected to a plurality of connection pads, so that each conductive contact is electrically connected to each other through a corresponding conductive blind hole, a corresponding conductive line and a corresponding connection pad, thereby obtaining a multilayer substrate; The multi-layer substrate is divided between two copper foil substrates, and the film between the two copper foil substrates is removed, so as to obtain two mutually separated package substrates, each package substrate includes one of the copper foil A substrate, a sputtered copper layer sputtered on the surface of the copper foil substrate, a plurality of conductive contacts on the surface of the sputtered copper layer, a layer of the sputtered copper layer pressed on the surface of the sputtered copper layer a dielectric layer and a layer of the conductive circuit layer laminated on the surface of the dielectric layer;

Package a chip on each package substrate so that the chip is electrically connected to the connection pad of the conductive circuit layer; separate the copper foil substrate in each package substrate from the surface of the sputtered copper layer; remove the sputtered copper in each package substrate layer to expose the plurality of conductive contacts; and

A solder ball is formed on each conductive contact in each packaging substrate, thereby obtaining a chip package.

Compared with the prior art, during the manufacturing process of the packaging substrate provided by this technical solution, a sputtered copper layer is formed on the surface of the carrier substrate, and the sputtered copper layer has electroplatability and strippability, and the sputtered copper layer Electroplating on the layer forms a conductive pattern for subsequent fabrication of the packaging substrate. During the process of packaging chips with the packaging substrate, the supporting part in the packaging substrate can be easily removed. Therefore, the manufacturing method of the packaging substrate and the chip package provided by the technical solution can avoid the use of a relatively expensive special copper foil structure, thereby reducing the manufacturing cost of the packaging substrate and the chip package. The packaging substrate provided by the technical solution has the characteristics of small size and easy fabrication.

Description of drawings

Fig. 1 is a schematic cross-sectional view of the first copper foil substrate, the first copper foil, the film, the second copper foil and the second copper foil substrate provided by the embodiment of the technical solution.

Fig. 2 is a schematic cross-sectional view of the carrier substrate obtained after laminating the first copper foil substrate, the first copper foil, the film, the second copper foil and the second copper foil substrate according to the embodiment of the technical solution.

3 is a schematic cross-sectional view of two surfaces of the carrier substrate in FIG. 2 after the first sputtered copper layer and the second sputtered copper layer are respectively formed.

FIG. 4 is a schematic cross-sectional view of the carrier substrate in FIG. 2 after forming a first tool hole.

FIG. 5 is a schematic cross-sectional view of forming a first photoresist pattern on the first sputtered copper layer and forming a second photoresist pattern on the second sputtered copper layer in FIG. 4 .

FIG. 6 is a schematic cross-sectional view of FIG. 5 after the first conductive pattern is formed in the first photoresist pattern and the second conductive pattern is formed in the second photoresist pattern.

FIG. 7 is a schematic cross-sectional view of FIG. 6 after removing the first photoresist pattern and the second photoresist pattern.

FIG. 8 is a schematic cross-sectional view of the first dielectric layer and the first conductive layer laminated on the first conductive pattern in FIG. 7 and the second dielectric layer and the second conductive layer laminated on the second conductive pattern.

FIG. 9 is a schematic cross-sectional view of forming a first conductive blind hole in the first dielectric layer and the first conductive layer and forming a second conductive blind hole in the second dielectric layer and the second conductive layer in FIG. 8 .

10 is a schematic cross-sectional view of a multi-layer substrate obtained after the first conductive layer in FIG. 9 is fabricated to form a first conductive circuit layer, and the second conductive layer is fabricated to form a second conductive circuit layer.

Figure 11 is the first solder resist layer formed on the first conductive line in Figure 10, the first gold layer formed on the first connection pad, the second solder resist layer formed on the second conductive line, and the second gold layer formed on the second connection pad sectional schematic diagram.

FIG. 12 is a schematic cross-sectional view of cutting the multi-layer substrate of FIG. 11 .

FIG. 13 is a schematic cross-sectional view of the first packaging substrate and the second packaging substrate obtained after cutting the multilayer substrate in FIG. 12 .

FIG. 14 is a schematic cross-sectional view of the packaging substrate of FIG. 13 after packaging chips.

FIG. 15 is a schematic cross-sectional view of the packaging substrate in FIG. 14 after removing the first copper foil substrate.

FIG. 16 is a schematic cross-sectional view of the package substrate in FIG. 15 after removing the first sputtered copper layer.

FIG. 17 is a schematic cross-sectional view of a chip package obtained after packaging provided by the technical solution.

Description of main component symbols

Carrier substrate 10 The first copper foil substrate 11 Second copper foil substrate 12 first copper foil 13 Second copper foil 14 film 15 first tool hole 16 second tool hole 17 first sputtered copper layer twenty one Second sputtered copper layer twenty two first contact pattern 31 second contact pattern 32 first photoresist pattern 41 Second Photoresist Pattern 42 first dielectric layer 51 second dielectric layer 52 The first conductive blind via 53 Second Conductive Blind Via 54 first conductive layer 61 second conductive layer 62 first conductive circuit layer 63 second conductive line layer 64 first solder mask 71 first gold layer 72 Second solder mask 81 second gold layer 82 first packaging substrate 100a Second Package Substrate 100b Chip package structure 100c first surface 101 second surface 102 product area 103 waste area 104 incision 105 multilayer substrate 110a Central District 151 marginal area 152 first conductive contact 311 second conductive contact 321 first conductive line 631 first connection pad 632 second conductive line 641 chip 200 Bonding wire 210 Packaging material 220 solder ball 240 chip package 300

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

Detailed ways

The manufacturing method of the packaging substrate provided by the technical solution comprises the following steps:

The first step, referring to FIG. 1 , is to provide a first copper foil substrate 11 , a second copper foil substrate 12 , a first copper foil 13 , a second copper foil 14 and a film 15 .

Both the first copper foil substrate 11 and the second copper foil substrate 12 are double-sided adhesive-backed copper foil substrates, and both include upper and lower copper foil layers and an insulating layer between the two copper foil layers.

The shape and size of the first copper foil substrate 11 , the second copper foil substrate 12 and the film 15 are the same. The shape of the first copper foil 13 and the second copper foil 14 is the same as that of the first copper foil substrate 11 , and the size of the first copper foil 13 and the second copper foil 14 is smaller than that of the first copper foil substrate 11 . Specifically, the cross-sectional area of the first copper foil 13 and the second copper foil 14 is smaller than the cross-sectional area of the first copper foil substrate 11 . The film 15 includes a central area 151 and an edge area 152 surrounding the central area 151 . The shape of the central area 151 is the same as that of the first copper foil 13 and the second copper foil 14 , and the size is equal.

In this embodiment, the insulating layers of the first copper clad substrate 11 and the second copper clad substrate 12 are both made of FR4 epoxy glass cloth laminated board. Film 15 is FR4 epoxy glass cloth prepreg film.

The second step, please refer to Figure 2, stack and press the first copper foil substrate 11, the first copper foil 13, the film 15, the second copper foil 14 and the second copper foil substrate 12 in sequence to form a whole to obtain the carrier substrate 10.

When stacking the first copper foil substrate 11, the first copper foil 13, the film 15, the second copper foil 14 and the second copper foil substrate 12, the first copper foil substrate 11, the first copper foil 13, the film 15, The centers of the second copper foil 14 and the second copper foil substrate 12 are aligned with each other. Because the size of the first copper foil 13 and the second copper foil 14 is smaller than the first copper foil substrate 11, the second copper foil substrate 12 and the size of the film 15, the first copper foil 13 and the second copper foil 14 are respectively in contact with the center of the film 15. Area 151 corresponds. When pressing, the two sides of the edge area 152 of the film 15 are respectively combined with the first copper foil substrate 11 and the second copper foil substrate 12, and the two sides of the central area 151 of the film 15 are respectively connected with the first copper foil 13 and the second copper foil substrate 12. The second copper foil 14 is combined with each other, and the central area 151 of the film 15 is not combined with the first copper foil substrate 11 and the second copper foil substrate 12 .

The carrier substrate 10 has an opposite first surface 101 and a second surface 102, wherein the first surface 101 is the surface of a copper foil layer of the first copper foil substrate 11, and the second surface 102 is a copper foil layer of the second copper foil substrate 12. surface of the foil layer.

The carrier substrate 10 has a product area 103 and a non-product area 104 surrounding the product area 103 . The cross-sectional area of the product area 103 is smaller than that of the first copper foil 13 . The orthographic projection of the product area 103 on the surface of the first copper foil substrate 11 is located within the orthographic projection of the first copper foil 13 on the surface of the first copper foil substrate 11 .

It can be understood that the carrier substrate 10 may not include the first copper foil 13 and the second copper foil 14 , and the first copper foil substrate 11 and the second copper foil substrate 12 are bonded by an adhesive film 15 .

The third step, please refer to FIG. 3 , is to form a first sputtered copper layer 21 on the first surface 101 of the carrier substrate 10 , and form a second sputtered copper layer 22 on the second surface 102 of the carrier substrate 10 .

In this embodiment, the thicknesses of the formed first sputtered copper layer 21 and the second sputtered copper layer 22 are both less than 1 micron. Preferably, the thickness of the first sputtered copper layer 21 and the second sputtered copper layer 22 is 0.1 micron to 1 micron. Since the first sputtered copper layer 21 and the second sputtered copper layer 22 are formed by sputtering copper, the first sputtered copper layer 21 and the second sputtered copper layer 22 have good electroplatability and peelability. The first sputtered copper layer 21 and the second sputtered copper layer 22 can be formed by using existing copper sputtering technology.

One method of sputtering copper is as follows: the copper target is arranged on the cathode of the vacuum sputtering device, the carrier substrate 10 is opposite to the cathode, and the carrier substrate 10 is arranged on the vacuum sputtering device. anode of the device. Vacuumize and preheat the vacuum sputtering device, and after filling inert gas, apply a high-voltage direct current between the copper target and the carrier substrate 10 to form the first sputtered copper layer on both sides of the carrier substrate 10 respectively 21 and the second sputtered copper layer 22. In this embodiment, the pressure inside the vacuum sputtering device is about 1.3×10 ⁻³ Pa, and the temperature is about 60° C. After the argon gas is filled into the vacuum sputtering device through the gas supply device, the electrons generated by the glow discharge (glow discharge) excite the argon gas to generate plasma, which blasts the atoms of the copper target and deposits them on the carrier substrate 10 surfaces. The thicknesses of the first sputtered copper layer 21 and the second sputtered copper layer 22 can be controlled by adjusting the sputtering time.

Referring to FIG. 4 , in this embodiment, after forming the first sputtered copper layer 21 and the second sputtered copper layer 22 , a step of forming a plurality of first tool holes 16 in the carrier substrate 10 may also be included. The opening position of the formed first tool hole 16 corresponds to the edge area 152 of the film 15 . That is, the first tool hole 16 runs through the edge region 152 of the film 15 and the first copper foil substrate 11 , the first copper foil 13 , the second copper foil 14 and the second copper foil substrate 12 corresponding to the edge region 152 . The first tool hole 16 is used for positioning in the next step.

The fourth step, referring to FIGS. 5 to 7 , is to form a first contact pattern 31 on the first sputtered copper layer 21 , and form a second contact pattern 32 on the second sputtered copper layer 22 . The first contact pattern 31 includes a plurality of first conductive contacts 311 , and the second contact pattern 32 includes a plurality of second conductive contacts 321 .

The formation of the first contact pattern 31 and the second contact pattern 32 can adopt the following methods:

First, a first photoresist pattern 41 is formed on the surface of the first sputtered copper layer 21 , and a second photoresist pattern 42 is formed on the surface of the second sputtered copper layer 22 . Specifically, a photoresist layer covering the entire first sputtered copper layer 21 and the second sputtered copper layer 22 may be formed by laminating dry films or printing liquid photosensitive ink. Then, a part of the photoresist layer is selectively removed by exposure and development to form a first photoresist pattern 41 and a second photoresist pattern 42 .

Then, form the first contact pattern 31 on the surface of the first sputtered copper layer 21 exposed from the first photoresist pattern 41 by electroplating, and form the first contact pattern 31 on the surface of the second sputtered copper layer 21 exposed from the second photoresist pattern 42. A second contact pattern 32 is formed on the surface of the copper plating layer 22 .

Finally, the first photoresist pattern 41 and the second photoresist pattern 42 are removed. In this embodiment, the stripping solution can be used to react with the first photoresist pattern 41 and the second photoresist pattern 42, so that the first photoresist pattern 41 is sputtered with copper from the first The surface of the layer 21 is detached, and the second photoresist pattern 42 is detached from the surface of the second sputtered copper layer 22 .

Both the first contact pattern 31 and the second contact pattern 32 are located in the product area 103 . The fifth step, please refer to FIG. 8, laminate the first dielectric layer 51 and the first conductive layer 61 on the surface of the first sputtered copper layer 21 and the first contact pattern 31, and the second sputtered copper layer 22 and the first contact pattern 31. The surface of the two contact pattern 32 is laminated with a second dielectric layer 52 and a second conductive layer 62 .

Wherein, the first dielectric layer 51 and the first conductive layer 61 may be an integral structure, that is, a single-sided copper-clad substrate composed of the first dielectric layer 51 and the first conductive layer 61 . The second dielectric layer 52 and the second conductive layer 62 may also be an integral structure, that is, a single-sided copper-clad substrate composed of the second dielectric layer 52 and the second conductive layer 62 .

After this step, it may also include forming a second tool hole 17 in the first dielectric layer 51 , the first conductive layer 61 , the carrier substrate 10 , the second dielectric layer 52 and the second conductive layer 62 that are pressed together. , the second tool hole 17 may coincide with the first tool hole 16 . The second tool hole 17 is used for positioning during subsequent outer layer fabrication.

The sixth step, please refer to FIG. 9 and FIG. 10, form a plurality of first conductive blind holes 53 in the first conductive layer 61 and the first dielectric layer 51, and form a plurality of first conductive blind holes 53 in the second conductive layer 62 and the second dielectric layer 52 Form a plurality of second conductive blind holes 54, and make the first conductive layer 61 to form the first conductive circuit layer 63, make the second conductive layer 62 to form the second conductive circuit layer 64, and the first conductive contacts 311 pass through the first conductive circuit layer. The blind hole 53 is electrically connected to the first conductive circuit layer 63 , and the second conductive contact 321 is electrically connected to the second conductive circuit layer 64 through the second conductive blind hole 54 to obtain the multilayer substrate 110 a.

The formation of the first conductive blind hole 53 can adopt the following method:

Firstly, a first hole 55 is formed in the first conductive layer 61 and the first dielectric layer 51 by laser ablation, and the first contact pattern 31 is exposed from the bottom of the first hole 55 .

Then, a conductive metal layer 56 is formed on the inner wall of the first hole 55 and the first contact pattern 31 exposed from the first hole 55 , so as to obtain the first conductive blind hole 53 . The conductive metal layer 56 can be formed by electroless copper plating or electroplating copper. It can be understood that the conductive metal layer 56 can also be formed on the entire first conductive layer 61 to increase the thickness of the first conductive layer 61 .

The forming method of the second conductive blind hole 54 may be the same as that of the first conductive blind hole 53 .

The first conductive circuit layer 63 and the second conductive circuit layer 64 can be formed by an image transfer process and an etching process. In this embodiment, the first conductive circuit layer 63 includes a plurality of first conductive circuits 631 and a plurality of first connection pads 632 . The first conductive line 631 is electrically connected between the first conductive blind hole 53 and the first connection pad 632 . The second conductive circuit layer 64 includes a second conductive circuit 641 and a second connection pad 642 . The second conductive circuit 641 is electrically connected between the second conductive blind hole 54 and the second connection pad 642 . It can be understood that the number of the first conductive lines 631 and the number of the first connection pads 632 can be set according to the chip to be packaged, when the chip to be packaged needs to be connected to a plurality of first connection pads 632, The first conductive circuit layer 63 can be provided with a plurality of first conductive circuits 631 and a plurality of first connection pads 632 . Similarly, the number of the second connection pads 642 and the second conductive lines 641 can be multiple.

In the seventh step, please refer to FIG. 11 , a first solder resist layer 71 is formed on the first conductive circuit 631 , and a first gold layer 72 is formed on the first connection pad 632 . A second solder resist layer 81 is formed on the second conductive circuit 641 , and a second gold layer 82 is formed on the second connection pad 642 .

The first solder resist layer 71 and the second solder resist layer 81 can be formed by printing liquid solder resist ink and then baking and solidifying. The first gold layer 72 and the second gold layer 82 can be formed by nickel-gold plating.

The eighth step, referring to FIG. 12 and FIG. 13 , is to cut the multilayer substrate 110a along the boundary line between the product area 103 and the non-product area 104 to form an annular cutout 105, thereby obtaining the first packaging substrate 100a and the first package substrate 100a separated from each other. The second package substrate 100b.

In the product area 103, the first copper foil 13 and the second copper foil 14 are combined with the film 15, the first copper foil substrate 11 and the second copper foil substrate 12 are not combined with the film 15, when along the product area 103 When the multilayer substrate 110a is cut at the boundary line with the non-product area 104, the first copper foil substrate 11 and the second copper foil substrate 12 are separated from the film 15, thereby obtaining two first packaging substrates 100a separated from each other. and the second packaging substrate 100b.

When the first copper foil substrate 11 and the second copper foil substrate 12 are not provided with the first copper foil 13 and the second copper foil 14, the first copper foil substrate 11 and the second copper foil 15 can be cut The foil substrates 12 are separated from each other, thereby obtaining a first package substrate 100a and a second package substrate 100b separated from each other.

Referring to FIG. 13 , the structure of the first packaging substrate 100 a is the same as that of the second packaging substrate 100 b. Wherein, the first packaging substrate 100 a includes a first copper foil substrate 11 , a first sputtered copper layer 21 , a first dielectric layer 51 and a first conductive circuit layer 63 arranged in sequence. The first conductive circuit layer 63 includes a first conductive circuit 631 and a first connection pad 632 . A plurality of first conductive contacts 311 are formed on the first sputtered copper layer 21, and a first conductive blind hole 53 is formed in the first dielectric layer 51, and each first conductive contact 311 passes through the first conductive blind hole 53 It is electrically connected with the first conductive circuit 631 . A first solder resist layer 71 is formed on the first conductive circuit 631 , and a first gold layer 72 is formed on the first connection pad 632 .

The second packaging substrate 100 b includes a second copper foil substrate 12 , a second sputtered copper layer 22 , a second dielectric layer 52 and a second conductive circuit layer 64 arranged in sequence. The second conductive circuit layer 64 includes a second conductive circuit 641 and a second connection pad 642 . A plurality of second conductive contacts 321 are formed on the second sputtered copper layer 22, and a plurality of second conductive blind holes 54 are formed in the second dielectric layer 52, and each second conductive contact 321 passes through a second conductive The blind hole 54 is electrically connected to a second conductive circuit 641 and the second connection pad 642 . A second solder resist layer 81 is formed on the second conductive circuit 641 , and a second gold layer 82 is formed on the second connection pad 642 .

The technical solution also provides a chip packaging method, comprising the steps of:

The first step, please refer to FIG. 13 , is to provide the packaging substrate prepared by the above method. In this embodiment, the first packaging substrate 100a is taken as an example for illustration.

The second step, please refer to FIG. 14 , is to package the chip 200 on the first package substrate 100 a to obtain the chip package structure 100 c.

A traditional chip packaging method can be used to package the chip 200 on the first packaging substrate 100a, specifically:

First, the chip 200 is attached to the first packaging substrate 100a. In this embodiment, the chip 200 is pasted on the first solder resist layer 71 . During bonding, an adhesive layer may be provided between the first solder resist layer 71 and the chip 200 , so that the chip 200 is more stably bonded to the first solder resist layer 71 .

Then, a wire bonding method is used to connect each electrode pad of the chip 200 to a corresponding first connection pad 632 to form a bonding wire 210 .

Finally, the packaging material 220 is formed on the chip 200 and the first packaging substrate 100a, so that the chip 200, the bonding wire 210 and the first solder resist layer 71 and the first connection pad 632 of the first packaging substrate 100a are completely covered by the packaging material. 220 covered. The encapsulation material 220 can be a thermosetting resin, such as polyimide resin, epoxy resin or silicone resin.

The third step, please refer to FIG. 15 , is to remove the first copper foil substrate 11 from the chip packaging structure 100c.

Since the thickness of the first sputtered copper layer 21 is very small, the bonding force with the first copper foil substrate 11 and the first dielectric layer 51 is relatively small, so the first sputtered copper layer 21 has the property of being peelable. Under the action of external force, the first copper foil substrate 11 can be separated from the first sputtered copper layer 21 , so that the first copper foil substrate 11 can be removed from the chip packaging structure 100c.

The fourth step, please refer to FIG. 16 , is to remove the first sputtered copper layer 21 adhered on the first dielectric layer 51 .

In this embodiment, the partly adhered first sputtered copper layer 21 on the first dielectric layer 51 is removed by micro-etching. The micro-etching chemical solution is used to react with the partially adhered first sputtered copper layer 21 on the first dielectric layer 51, so that the remaining partially adhered first sputtered copper layer 21 of the first dielectric layer 51 is removed. dissolving and removing from the surface of the first dielectric layer 51 , so that each first conductive contact 311 is exposed.

In the fifth step, referring to FIG. 17 , a solder ball 240 is formed on each first conductive contact 311 to obtain a chip package 300 .

Please refer to FIG. 17, the chip package 300 provided by this technical solution includes a first dielectric layer 51, a first contact pattern 31, a first conductive circuit layer 63, a chip 200, a plurality of bonding wires 210 and packaging materials arranged in sequence. 220. The first contact pattern 31 and the first conductive circuit layer 63 are located on opposite sides of the first dielectric layer 51 . The first contact pattern 31 includes a plurality of first conductive contacts 311 . The first conductive circuit layer 63 includes a first conductive circuit 631 and a first connection pad 632 . A first conductive blind hole 53 is disposed in the first dielectric layer 51 . Each first conductive contact 311 is electrically connected to the first conductive circuit 631 through a corresponding first conductive blind hole 53 . Each bonding wire 210 is correspondingly connected to an electrode pad of the chip 200 and a first connection pad 632 is formed with a first solder resist layer 71 on the first conductive line 631, and a solder resist layer 71 is formed on the first connection pad 632. The first gold layer 72 . The encapsulation material 220 is in contact with the surface of the first dielectric layer 51 formed with the first conductive circuit layer 63 , so that the first conductive circuit layer 63 , the chip 200 , and the plurality of bonding wires 210 are completely inside the encapsulation material 220 . Each solder ball 240 is formed on a first conductive contact 311 .

During the manufacturing process of the packaging substrate provided by this technical solution, a sputtered copper layer is formed on the surface of the carrier substrate, and the sputtered copper layer has electroplatability and strippability, and the sputtered copper layer is electroplated to form a contact pattern. Subsequent fabrication of the packaging substrate is carried out. During the process of packaging chips with the packaging substrate, the supporting part in the packaging substrate can be easily removed. Therefore, the manufacturing method of the packaging substrate and the chip package provided by the technical solution can avoid the use of a relatively expensive special copper foil structure, thereby reducing the manufacturing cost of the packaging substrate and the chip package. The package substrate and chip package body provided by the technical solution have the characteristics of small size and easy manufacture.

It can be understood that those skilled in the art can make various other corresponding changes and modifications according to the technical concept of the present invention, and all these changes and modifications should belong to the protection scope of the claims of the present invention.

Claims (14)

1. A method for manufacturing a packaging substrate, comprising the steps of: Provide a first copper foil substrate, a film, and a second copper foil substrate, and press the film between the first copper foil substrate and the second copper foil substrate to obtain a carrier substrate, the carrier substrate has an opposite first surface and a second copper foil substrate. two surfaces; forming a first sputtered copper layer on the first surface, and forming a second sputtered copper layer on the second surface; a plurality of first conductive contacts are formed by electroplating on the first sputtered copper layer, and a plurality of second conductive contacts are formed by electroplating on the second sputtered copper layer; The first dielectric layer and the first conductive layer are pressed on the plurality of first conductive contacts and the first sputtered copper layer, and the first dielectric layer and the first conductive layer are pressed on the plurality of second conductive contacts and the second sputtered copper layer. a second dielectric layer and a second conductive layer; A plurality of first conductive blind holes corresponding to the plurality of first conductive contacts are formed in the first dielectric layer and the first conductive layer, and the first conductive layer is fabricated to form a first conductive circuit layer, the first The conductive circuit layer includes a plurality of first conductive circuits electrically connected to the plurality of first conductive blind holes and a plurality of first connection pads electrically connected to the plurality of first conductive circuits, so that each first The conductive contacts are electrically connected to each other through a corresponding first conductive blind hole, a corresponding first conductive line and a corresponding first connection pad, forming a plurality of second conductive blind holes in the second dielectric layer and the second conductive layer. hole, and the second conductive layer is fabricated to form a plurality of second conductive lines and a plurality of second connection pads, and each second conductive contact is electrically connected to the second connection pad through the corresponding second conductive blind hole and the second conductive line. through, thereby obtaining a multilayer substrate; and The multi-layer substrate is divided between the first copper clad substrate and the second copper clad substrate, and the film between the first copper clad substrate and the second copper clad substrate is removed, thereby obtaining two mutually separated packaging substrates . 2. The method for manufacturing a packaging substrate according to claim 1, further comprising the steps of: forming a first solder resist layer on the first conductive circuit layer, so that the first solder resist layer covers the surfaces of the plurality of first conductive circuits and the surface of the first dielectric layer exposed from the first conductive circuit layer, and exposing the plurality of first connection pads; forming a second solder resist layer on the second conductive circuit layer, so that the second solder resist layer covers the surfaces of the plurality of second conductive circuits and the surface of the second dielectric layer exposed from the second conductive circuit layer, and expose the plurality of second connection pads. 3. The manufacturing method of the packaging substrate according to claim 2, wherein after forming the first solder resist layer, a first gold layer is also formed on the surface of the first connection pad, and after forming the second solder resist layer, A second gold layer is also formed on the surface of the second connection pad. 4. The manufacturing method of the packaging substrate according to claim 1, wherein when providing the first copper foil substrate, the film and the second copper foil substrate, the first copper foil and the second copper foil are also provided, and the The cross-sectional areas of the first copper foil substrate, the film and the second copper foil substrate are the same, the cross-sectional areas of the first copper foil and the second copper foil are the same, and the cross-sectional area of the first copper foil is smaller than the cross-sectional area of the film Area, the film includes a central area and an edge area surrounding the central area, the cross-sectional area of the central area is equal to the cross-sectional area of the first copper foil; when the film is pressed on the first copper foil substrate and the second copper foil When between the substrates, press the first copper foil between the film and the first copper foil substrate at the same time, press the second copper foil between the film and the second copper foil substrate, the first copper foil and the first copper foil The two copper foils are all in contact with the central area of the film, and the orthographic projection of the first copper foil on the surface of the first copper foil substrate and the orthographic projection of the second copper foil on the surface of the first copper foil substrate are all in line with the center area on the first copper foil substrate surface. The orthographic projections of the surfaces of the copper-clad substrates overlap, so that the first copper-clad substrate and the second copper-clad substrate are bonded together only by the edge regions of the film. 5. The manufacturing method of the packaging substrate according to claim 4, wherein the carrier substrate includes a product area and a waste area surrounding the product area, the product area corresponds to the central area of the film, and the product area The orthographic projection of the area on the surface of the first copper foil substrate is located within the orthographic projection of the central area on the surface of the first copper foil substrate, and the multilayer substrate is carried out between the first copper foil substrate and the second copper foil substrate. When dividing, the multilayer substrate is cut along the boundary line between the product area and the waste area, so that the product area is separated from the waste area, and the first copper foil substrate in the product area is naturally separated from the first copper foil, and the product The second copper foil substrate in the product area is naturally separated from the second copper foil, and the first copper foil, the second copper foil and the film in between are removed in the product area, thereby obtaining two package substrates separated from each other. 6. A packaging substrate, which includes a copper foil substrate, a sputtered copper layer, a plurality of conductive contacts, a dielectric layer and a conductive circuit layer, the sputtered copper layer is formed on the surface of the copper foil substrate, and the plurality of Conductive contacts are formed on the surface of the sputtered copper layer away from the copper foil substrate, the dielectric layer is located between the conductive circuit layer and the sputtered copper layer, and the dielectric layer is formed with multiple A plurality of conductive blind holes corresponding to a plurality of conductive contacts one by one, the conductive line layer includes a plurality of conductive lines electrically connected to the plurality of conductive blind holes one by one and a plurality of connections electrically connected to the plurality of conductive lines one by one. Each conductive contact is electrically connected to a corresponding connection pad through a corresponding conductive blind hole, a corresponding conductive line and a corresponding connection pad. 7. The package substrate according to claim 6, wherein a first solder resist layer is formed on the conductive circuit layer, so that the first solder resist layer covers the surfaces of the plurality of conductive circuits and is exposed from the conductive circuit layer. The surface of the exposed dielectric layer is exposed, and the plurality of connection pads are exposed, and the gold layer is formed on the connection pads. 8 . The package substrate according to claim 6 , wherein the sputtered copper layer has a thickness of 0.1 micron to 1 micron. 9. A chip packaging structure, comprising a copper foil substrate, a sputtered copper layer, a plurality of conductive contacts, a dielectric layer, a conductive circuit layer, a solder resist layer and a chip, and the sputtered copper layer is formed on the copper foil The surface of the substrate, the plurality of conductive contacts are formed on the surface of the sputtered copper layer away from the copper foil substrate, the dielectric layer is located between the conductive circuit layer and the sputtered copper layer, the dielectric layer A plurality of conductive blind holes corresponding to a plurality of conductive contacts are formed in the electrical layer, and the conductive line layer includes a plurality of conductive lines electrically connected to the plurality of conductive blind holes and a plurality of conductive lines connected to the plurality of conductive lines. A plurality of connection pads electrically connected, each conductive contact is electrically connected to each other through a corresponding conductive blind hole, a corresponding conductive line and a corresponding connection pad, and the solder resist layer covers the surface of the plurality of conductive lines And the surface of the dielectric layer exposed from the wire line layer, and expose the plurality of connection pads, each connection pad surface is formed with a gold layer, the chip is arranged on the surface of the solder resist layer, and is connected with the bonding wire through the bonding wire The gold layer on the surface of each connection pad is electrically connected. 10. A method for manufacturing a chip package, comprising the steps of: providing the package substrate as claimed in claim 6; Encapsulating a chip on the packaging substrate, so that the chip is electrically connected to the connection pad of the conductive circuit layer; Separating the copper foil substrate in the packaging substrate from the surface of the sputtered copper layer; removing the sputtered copper layer in each package substrate to expose the plurality of conductive contacts; and A solder ball is formed on each conductive contact in the packaging substrate, thereby obtaining a chip package. 11. A method for manufacturing a chip package, comprising the steps of: Provide the chip package structure as claimed in claim 9; Separate the copper foil substrate in the packaging structure from the surface of the sputtered copper layer; removing the sputtered copper layer to expose the plurality of conductive contacts; and A solder ball is formed on each conductive contact in the packaging structure, thereby obtaining a chip package. 12. A method for manufacturing a chip package, comprising the steps of: Provide two copper foil substrates and a film, and press the film between the two copper foil substrates to obtain a carrier substrate, the carrier substrate has two opposite sputtering surfaces; A layer of sputtered copper is sputtered on each sputtered surface; forming a plurality of conductive contacts by electroplating on each sputtered copper layer; Pressing one layer of dielectric layer and one layer of conductive layer on both sides of the carrier substrate, and making the dielectric layer contact with multiple conductive contacts and sputtered copper layer; A plurality of conductive blind holes corresponding to a plurality of conductive contacts are formed in the dielectric layer and the conductive layer on each side, and the conductive layer is made into a conductive circuit layer, and the conductive circuit layer includes a plurality of conductive blind holes. A plurality of electrically conductive lines and a plurality of connection pads electrically connected to the plurality of conductive lines one by one, so that each conductive contact passes through a corresponding conductive blind hole, a corresponding conductive line and a corresponding connection pad are electrically connected to each other to obtain a multi-layer substrate; The multi-layer substrate is divided between two copper foil substrates, and the film between the two copper foil substrates is removed, so as to obtain two mutually separated package substrates, each package substrate includes one of the copper foil A substrate, a sputtered copper layer sputtered on the surface of the copper foil substrate, a plurality of conductive contacts on the surface of the sputtered copper layer, a layer of the sputtered copper layer pressed on the surface of the sputtered copper layer a dielectric layer and a layer of the conductive circuit layer laminated on the surface of the dielectric layer; Encapsulating a chip on each packaging substrate, so that the chip is electrically connected to the connection pad of the conductive circuit layer; separating the copper foil substrate in each package substrate from the surface of the sputtered copper layer; removing the sputtered copper layer in each package substrate to expose the plurality of conductive contacts; and A solder ball is formed on each conductive contact in each packaging substrate, thereby obtaining a chip package. 13. The method for manufacturing a chip package according to any one of claims 10 to 12, wherein packaging the chip on a packaging substrate comprises the steps of: Bond the chip to the packaging substrate insulatedly; forming a bonding wire between each electrode pad of the chip and a corresponding one of the connection pads; and The encapsulation material is formed on the chip and the encapsulation substrate, so that the chip, the bonding wire and the first conductive circuit layer of the encapsulation substrate are completely covered by the encapsulation material. 14. The method for manufacturing a chip package according to any one of claims 10 to 12, wherein the sputtered copper layer adhered to the dielectric layer is removed by means of micro-etching.

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