201015264 九、發明說明： 【發明所屬之技術領域】 尤指一 本發明係指-種用於-電子裝置之電源穩壓電路， 種可以提供大負載一穩定電壓之電源穩壓電路。 ， 【先前技術】 ❹ 在電子中’賴麵電路可提供電路運料穩定 電塵。在正“雜況下，電源麵電路吻定額雷 壓值，並提供足夠的電流給被供電的電路。然 ^ …、叩，不完善的電源 穩壓電路可能使電路在運作過程中出現電壓不穩的現象， 統當機或使計算出現錯誤的結果。 導致系 傳統的電源穩壓電路需在其所屬之積體電路之外附加一具有 ❹較大電容值之外部電容，以確保電源穩壓電路的穩定性。請參考 第1圖’第1圖為習知-電源穩壓電路K)之示意圖。電源^壓電 路10係由一 p型金氧半（PM0S)電晶體M1、一運算放大器i㈨ 及電阻iU、R2所組成，用以根據一參考電壓vref，將一輸入電 壓VIN轉換為適當大小的一輸出電壓ν〇υτ，並輸出至一負載 - 1〇2。其中，為了確保電源穩壓電路1〇的穩定性，電源穩壓電路 10的輸出端（及PMOS電晶體Ml的汲極）另耦接於一外部電容 CEXT。當負載1〇2在瞬間汲取大電流時，外部電容CEXT可用來 201015264 防止輸出電壓νουτ發生太大的瞬間發。然而，&電1載力 大時，電_壓電路Κ)的域點會輸出電流增U高鮮 動，造成電路不穩定’並失去正#功能。也狀說，大負載電流 是造成電源穩壓電路U)發生不歡現象的主要成因。除此之外_， 為了儲存足_電能，以·輸㈣鮮觀發生過大的瞬間落 差’通常需翻具較大f容值料㈣容CEXT，目*需耗費 路板空間。 近來’為節省電路板的空間，習知技術已發展出不需在積體 電路之外附加外部電容的電源穩壓電路。請參考第2圖，第2圖 係習知_電雜壓電路2G之示意目。電雜壓魏2G不需附加 外部電容，其包含有㈣金氧半（NMOS)電晶體M2、M3、-運算放大器200、電阻R卜R2、R。及一電容CL，用以根據參考 電壓VREF ’將輸入電壓viN轉換為適當大小的輸出電壓ν〇υτ， 並輸出至一負載202。其中’電容CL為一電容值較小的内部電容。 當負載202瞬間汲取大電流時，電容CL中所儲存之電荷被迅速用 來提供負載202瞬間所需的電流，同時，電晶體M3的源 極電壓也隨之下降。然而，由於_〇3電晶體M3的源極與閘極 之間存在電谷值相當大的一寄生電容CgS，當輸出電壓νουτ發 生變化時，寄生電容Cgs會將輸出電壓ν〇υτ驟降現象，耦接至 運算放大器200的輸出端電晶體M2的閘極之間，使 NMOS電晶體M2的閘級電壓下降，進而降低NM〇s電晶體]^2 的導通電流，致使源級電壓下降。緊接著，NMOS電晶體M2的 201015264 源級電壓，經由電阻R1及R2所建構的回授機制，傳導至運算放 大器200的負端’經放大誤差訊號後，促使電晶體M2的 閘級電壓挺而’使NMOS電晶體]V12的源級電壓回到原先之位準， 進而使NMOS電晶體M3的源，級輸出電壓回到原先之位準。換言 之，當負載202 _波取大電流時，電源麵電路2〇的輸出電壓 VOUT係呈現_下降再回升的抖動現象。此抖滅象主要肇因 於系統頻寬不足’輸出端瞬間抽取大電流的反應速度不足所導 ❹致。這些都是電源穩壓電路20較為明顯的缺點。 【發明内容】 因此，本發明的主要目的即在於提供一種用於一電子裝置 之電源穩壓電路。 ❹201015264 IX. Description of the invention: [Technical field to which the invention pertains] In particular, the invention refers to a power supply voltage stabilization circuit for an electronic device, and a power supply voltage stabilization circuit capable of providing a large load and a stable voltage. [Prior Art] ❹ In the electronic field, the circuit can provide stable circuit dust. Under the circumstance, the power supply circuit kisses the rated lightning pressure value and provides enough current to the circuit to be powered. However, the imperfect power supply voltage regulator circuit may cause the voltage to appear during the operation of the circuit. Steady phenomenon, the result of the error or the calculation of the error. The traditional power supply voltage regulator circuit needs to add an external capacitor with a larger capacitance value outside the integrated circuit to ensure the power supply voltage regulation. The stability of the circuit. Please refer to Figure 1 'Figure 1 for the conventional-power supply voltage regulator circuit K. The power supply voltage circuit 10 is composed of a p-type gold oxide half (PM0S) transistor M1, a operation The amplifier i (9) and the resistors iU and R2 are configured to convert an input voltage VIN into an output voltage ν〇υτ of an appropriate size according to a reference voltage vref, and output it to a load -1〇2. The stability of the voltage stabilizing circuit 1,, the output end of the power voltage stabilizing circuit 10 (and the drain of the PMOS transistor M1) is coupled to an external capacitor CEXT. When the load 1〇2 draws a large current in an instant, the external capacitor CEXT can be used for 201015264 The output voltage νουτ occurs too much instantaneously. However, when the electric load of 1 is large, the domain point of the electric_voltage circuit 会) will increase the current and increase the current, causing the circuit to be unstable and losing the positive # Function. It is also said that the large load current is the main cause of the unsatisfactory phenomenon of the power supply voltage regulator U. In addition, _, in order to store the foot _ electric energy, to lose (four) fresh view occurs too large instantaneous drop 'usually Need to turn over a large f-capacity material (four) capacity CEXT, the head * need to consume the space of the board. Recently, in order to save the space of the circuit board, the conventional technology has developed a power supply that does not need to add an external capacitor outside the integrated circuit. Pressure circuit. Please refer to Figure 2, Figure 2 is a schematic diagram of the conventional _ electric hybrid circuit 2G. The electric miscellaneous Wei 2G does not need to add an external capacitor, which contains (4) gold oxide half (NMOS) transistor M2 The M3, the operational amplifier 200, the resistor R, R2, R, and a capacitor CL are used to convert the input voltage viN into an appropriately sized output voltage ν〇υτ according to the reference voltage VREF', and output it to a load 202. 'Capacitor CL is an internal capacitor with a small capacitance value. When the load 202 is instantaneous When a large current is taken, the charge stored in the capacitor CL is quickly used to supply the current required for the load 202 instantaneously, and at the same time, the source voltage of the transistor M3 is also lowered. However, due to the source of the _3 transistor M3 A parasitic capacitance CgS having a relatively large electric valley between the pole and the gate, when the output voltage νουτ changes, the parasitic capacitance Cgs will suddenly drop the output voltage ν〇υτ, and is coupled to the output of the operational amplifier 200. Between the gates of the crystal M2, the gate voltage of the NMOS transistor M2 is lowered, thereby lowering the on current of the NM〇s transistor ^2, causing the source voltage to drop. Then, the 201015264 source level of the NMOS transistor M2 The voltage is transmitted to the negative terminal of the operational amplifier 200 via the feedback mechanism constructed by the resistors R1 and R2. After the amplified error signal, the gate voltage of the transistor M2 is promoted and the source voltage of the NMOS transistor V12 is made. Returning to the original level, the source and output voltages of the NMOS transistor M3 are returned to the original level. In other words, when the load 202 _ wave takes a large current, the output voltage VOUT of the power supply surface circuit 2 呈现 exhibits a jitter phenomenon of falling and then rising. This dimming image is mainly caused by insufficient system bandwidth, and the reaction speed of the output terminal instantaneously extracting a large current is insufficient. These are the disadvantages of the power supply voltage regulator circuit 20. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a power supply voltage regulator circuit for an electronic device. ❹
本發明揭露-種電源穩壓電路，包含有—前級電路，包知 -比較單S’包含有-第-端_於—外部參考電壓一第二端 及-=三端，用來比較該第1及該第二端之電壓差，以由則 j輸出-比較結果；-驅動單元，包含有—第—端祕U 流電源，-第二端祕鱗元之該第三端 該驅動單元用來根據該第二端 矛—碼 $端之峨，導通該第-端至該第三对 一升壓單元，包含有一第一 一第二端，用來提高該第二 端輕接於該驅動單元之該第三端及 端至該第一端之電壓；以及一配壓單 201015264 元’搞接至該比較單元與該升壓單元，用來根據該升壓單元之該 第二端之電壓’輸出—回授峨至該比鮮元；-緩衝級電路f 耦接於該驅動單元之該第三端，用來根據該驅動單元之該第三端 的電壓大小’輸出—調節訊號；以及—輸出級電路，耗接於該緩 衝級電路及該電源接收端，用來根據該調節訊號，輸出該直 源。 ❹ 【實施方式】 請參考第3圖，第3圖為本發明實施例用於一電子裝置之— 電«壓電路30之示意圖。電源讎電路3〇可提供穩定電壓， 其包含一電源接收端32、一前級電路3〇〇、一緩衝級電路3〇2、_ 輸出級電路304及-電壓輸出端34。電源麵電路3〇用以由電源 接收端32接收一直流電源，並經前級電路3〇〇、緩衝級電路 〇 302及輸出級電路3〇4之處理後，由電壓輸出端34輪出一輸 v 壓 VOUT。 請繼續參考第4圖，第4圖為前級電路300之示意圖。前級 電路300 &含有一參考輸入端4〇、一比較單元4〇〇、一驅動單元 4〇2、-升壓單元4〇4及一配壓單元·。參考輸入端㈣接於一 電，產生器（未緣於第4圖中），用以接收一參考電壓權F。比 較單元4〇〇輕接於參考輸入端40、配壓單元4〇6及驅動單元4〇2， 用以比較參考電壓VREF及配壓單元所輸出之―回授訊號 9 201015264 大小’並將比較結果輸出至鷄單元402。驅動單元4〇2 _，電源接收端32、比較單元·及升壓單元彻，用來根據 比較單元4GG所輸出之比較結果，控制電源接收端％至升壓單元 4〇4之電流大小’以輸出一驅動訊號微¥。升壓單元耦接於 驅動單元402雜壓單元侧之間，用來提高配壓單元條至驅 動單元402之電壓位準’關於加入升壓單元4〇4之原目將詳述於 後文。最後，配壓單元406輕接於升壓單元4〇4、比較單元4〇〇 ❹及一地端GND ’用來根據升壓單元4〇4之電壓位準，輸出回授訊 號VFB至比較單元4〇〇。 簡5之，在刖級電路3〇〇中，比較單元4〇〇比較參考電壓 VREF與回授訊號VFB，以控制驅動單元4〇2的輸出電流大小， 從而產生驅動訊號VDRV。同時，透過米勒麵法，使前級電路 300能得到更穩定的操作。 特別注意的是，第4圖所示為前級電路3〇〇之實施例示意圖， 本湏域具通常知識者當可據以做不同之修飾，而不限於此。舉例 來說，請參考第5圖，第5圖為前級電路，之較佳實施例示意 圖。在第5圖中，一運算放大器500用以實現比較單元400 ; 一 PMOS電晶體MP1及一補償元件CM1用以實現驅動單元4〇2 ; NMOS電sb體MN2及MN3 用以實現升壓單元4〇4;以及電阻R1、 R2用以實現配壓單元406。運算放大器500可比較參考電壓vref 和電阻R1、R2所提供的之回授訊號WB，以控制1>]^〇3電晶體 201015264 MP1之導通。同時，NMOS電晶體MN2及MN3係為二極體聯結 (diode-connected)形式，用以提供一固定之電壓差，以提高pM〇s 電晶體MP1在操作時的電壓基準。如此一來，pM〇s電晶體Mpl 之沒極電壓可於一較高之電壓基準輸出驅動訊號VDRV，使得下 一級的緩衝級電路302和輸出級電路304也在較高之電壓基準上 操作。因此，前級電路300係將電晶體Μρ!汲極電壓的擾動經由 電阻R1、R2回授到運算放大器5〇〇，以控制電晶體刪的導通， ❹從而抵銷電晶體MPU及極電壓的擾動，使電晶體刪沒極的電 壓迅速回復到原先的平衡狀態。另外，電容㈤麵接於pM〇s 電晶體MP1的閘極及没極之間，用來提供頻率補償。依照電路設 计中之米勒補償法，作為頻率補償用的電容(：]^1，其跨接於具有 訊號放大功能賴極及祕之間，可使原先的主極齡離為一個 較為低頻賴主極點與-較為高_新極點， 離㈤es_ng)。經由米勒補償法的極點分離功能 ❹跨齡PMOS電晶體廳的閘極及沒極之間，可產生一個較為低 頻且更為穩定的新主極點，以增進系統穩定度。 針對前級電路300中的驅動單元4〇2，電晶體咖的頻率 償方式可加以變化而得到等同的功效，例如，以串聯之一電六〇 與一電阻RM取代電容CM1，如第6A圖所示。在第6a圖合中， 第之間。其中’電容CM2係透過米勒補償法 疋的新主極點，而電阻則可產生新的零點，進—步改 201015264 電路300的頻率響應。需注意的是，驅動單元術中補償元件係 ㈣使原先的雄齡離為—個較為錢騎雄賴—較為高 頻的新極點，明_統穩定度’而補償元件的連接方式與實現 方式當可根據不同系統而變化，而不限於此。 舉例來說’睛參考第6B圖，第6b圖為前級電路3〇〇之一實 施例示意圖。比較第6B圖與第5圖可知，第6B圖與第5圖所示 ❹之實施例的差異，在於第4圖中PMOS電晶體刪係由第6B圖 中-NMOS電晶體_所取代’因此運算放大器之連接方 式亦隨之改變。在此情形下…電容CC _接於電晶體麵的 間極與地端_之間，用來提供頻率麵，以增進系統穩定度。 口月參考第7圖’第7圖為緩衝級電路3〇2之實施例示意圖。 緩衝級電路302係由KM〇s電晶體麵4及画5所組成。顧〇§ 冑日曰體麵4之作用為一緩衝開關’用來根據前級電路300所輸出 之驅動訊號VDRV，決定電源接收端32至輸出級電路3〇4的電流 大小，以輸出一調節訊號VREG至輸出級電路3〇4qNM〇s電晶 體MN5之作用為-電流源，其閘極輕接於一固定偏壓值的電壓源 VBW吏NMOS電晶體麵5得以提供固定電流給醒〇8電晶體 MN4使用。在第7圖十，麵〇8電晶體丽4可提供一低輸出阻 抗，使此低輸出阻抗所對應的極點可由低頻移往高頻，以增進系 統的穩定性及增加系統的頻寬。除此之外，匪〇8電晶體細4 所提供的低輸出阻抗也有效阻絕了輸出級電路3〇4的電壓抖動對 12 201015264 月’J級電路300的影響。值得注意的是’麵〇8電晶體咖在提供 低輸出随賴時，將使其位於__出電壓下降—特定值。 為了補償NMOS電晶體_4的源極電壓，因而在前級電路_ 了升壓單元4G4 ’使得繼0S電晶體丽4的輸έίί端(源極) 相，於輸人端(_)暇賴降現象，可在驗魏3⑻的升 壓單元404中予以補償。 ❹ 赫考第8圖’第8圖為輸出級電路3〇4之實施例示意圖。 輸出級電路304包含有nm0s電晶體顧6、顧7及一電容cl。 麵〇S電晶體娜之作用為一功率開關’用來根據緩衝器電路 3〇2所輸出之調節訊號，決歧極至職之電流大小，以控 制輸出電壓V0UT的大小。NM〇s電晶體丽7之作用為一電流 源，其間極輕接於-固定偏壓值的電壓源爾，使顧〇§電晶體 丽7得以提供固定電流給NM〇s電晶體麵6使用。輸出級電路 ❹ 304另包含一電容CL，耦接於電壓輸出端％與地端gnd之間， 用來儲存電荷。值得注意的是，醒⑽電晶體續6的源極與閉極 之間存有-電容值相當大的寄生電容Cgs，寄生電容Cgs可將輪 出端的電壓抖動現象，耦接至NMOS電晶體mn6的閘極。在此 情形下，緩衝級電路302中NMOS電晶體MN4所提供的低輸出 阻抗可有效阻絕輸出級電路304的電壓抖動現象對前級電路3⑻ 的影響。另外，NM〇S電晶體麵6的聯結方式將使其位於源極的 輸出電壓下降一特定值。同樣的，在前級電路300中的升壓單元 404可提供電壓升壓功能，以補償電壓下降。 13 201015264 結合第5圖、第7圖及第8圖，則為電源穩壓電路3〇之較佳 實施例，如第9圖所示。如前所述，依照米勒補償法，運算放大 器500的輸出端產生一低頻的新主極點，以增進系統穩定性。緩 衝級電路302中的NMOS電晶體mn4的低輸出阻抗驅使所對應 的極點由低頻移往高頻，以增進系統的穩定性及增加系統頻寬， 並可阻絕輸出級電路304因寄生電容而影響前級電路3〇〇。此外， ❹一極體聯結之NMOS電晶體MN2、MN3可補償因使用nm〇§電 晶體_4及MN6所發生的壓降現象，使電源穩壓電路3〇兼具穩 定性與快速反應的優點。 一般而言，輸出級電路304的NMOS電晶體_6存在大電 谷值的寄生電容Cgs。當外部負載瞬間汲取大電流時，將導致輸出 電壓VOUT下降，使NMOS電晶體MN6增加導通能力，以迅速 , 提供負載所需的電荷。此外’緩衝級電路302所具備的低輸出阻 抗特性’使輸出電壓VOUT的變化不會影響前級電路300的操作。 前級電路300經米勒補償法，得到一個較為低頻且不隨輸出電流 移位的新主極點。而NMOS電晶體MN4及NMOS電晶體MN6 的輸出電壓下降現象亦由前級電路3〇〇的升壓單元404予以等量 的補償。因此’本發明可兼顧增進穩定性與反應速度，使輸出電 壓VOUT能維持所需的電壓位準。 综上所述，習知電源穩壓電路雖然去除了必須外加電容的限 14 201015264 仍需解決電路系騎生的*穩定與反應速度*足的現象。相 較之下’本發明彻内加—提供低輸出阻抗的緩衝級電路使輸出 級電路的電;1波動不致影響前級電路的運作。並且，經由對前級 電路的驅動單元提供頻率補償及提升操作電壓，本發明之電源穩 壓電路得以妥善解決系統補定與反應速度不足關題，提供大 電流負載一穩定之電壓源。 © 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知一電源穩壓電路的示意圖。 第2圖為習知一電源穩壓電路示意圖。 第3圖為本發明實施例一電源穩壓電路之示意圖。 ◎ 第4圖為第3圖中一前級電路之示意圖。 第5圖、第6A圖及第6B圖為第4圖之前級電路之實施例示意圖。 第7圖為第3圖中一緩衝級電路之實施例示意圖。 第8圖為第3圖中一輸出級電路之實施例示意圖。 弟9圖為本發明電源穩壓電路之一較佳實施例示意圖。 【主要元件符號說明】 30 電源穩壓電路 201015264 32 電源接收端 34 電壓輸出端 102'202 負載 302 緩衝級電路 304 輸出級電路 300 前級電路 400 比較單元 Ο 402 驅動單元 404 升壓單元 406 配壓單元 100、200、500 運算放大器 VIN 直流電源 VOUT 輸出電壓 CL 電容 Cgs ❹ 寄生電容 CEXT 外部電容 CM1 ' CM2 > CC 電容 Ro ' R1 ' R2 ' RM 電阻 M2、M3、MN1、MN2、MN3 ' NMOS電晶體 、MN4、MN5、MN6、MN7 Ml ' MP1 PMOS電晶體 GND 地端 VDRV 驅動訊號 16 201015264 調節訊號 參考電壓 電壓源 VREG VREF VB1 ' VB2 ❹The invention discloses a power supply voltage stabilizing circuit comprising a pre-stage circuit, and the packet-same-single S' includes a -first-end_--external reference voltage, a second end and a -= three end, for comparing the The voltage difference between the first end and the second end is outputted by the j-comparison result; the drive unit includes a first-end U-stream power supply, and the third end of the second-end secret scale element is the drive unit The second end of the boosting unit is connected to the third end of the boosting unit according to the second end spear-code $ end, and includes a first and a second end for improving the second end to be connected to the And the voltage of the third end of the driving unit to the first end; and a voltage distribution unit of 201015264 yuan is connected to the comparing unit and the boosting unit for using the second end of the boosting unit The voltage output is outputted to the third element of the driving unit, and is configured to output an output signal according to the voltage of the third end of the driving unit; An output stage circuit that is connected to the buffer stage circuit and the power receiving end for adjusting the signal according to the The source of the straight.实施 [Embodiment] Please refer to FIG. 3, which is a schematic diagram of an electric «voltage circuit 30 for an electronic device according to an embodiment of the present invention. The power supply circuit 3A can provide a stable voltage, and includes a power receiving terminal 32, a front stage circuit 3A, a buffer stage circuit 3'2, an output stage circuit 304, and a voltage output terminal 34. The power supply circuit 3 is configured to receive the DC power from the power receiving terminal 32, and is processed by the voltage output terminal 34 after being processed by the preamplifier circuit 3, the buffer stage circuit 302, and the output stage circuit 3〇4. The v voltage is VOUT. Please continue to refer to FIG. 4, which is a schematic diagram of the front stage circuit 300. The pre-stage circuit 300 & includes a reference input terminal 4〇, a comparison unit 4〇〇, a drive unit 4〇2, a boost unit 4〇4, and a press unit. The reference input terminal (4) is connected to an electric generator (not shown in FIG. 4) for receiving a reference voltage F. The comparison unit 4 is lightly connected to the reference input terminal 40, the voltage regulating unit 4〇6 and the driving unit 4〇2 for comparing the reference voltage VREF and the “return signal 9 201015264 size” output by the voltage regulating unit and will compare The result is output to the chicken unit 402. The driving unit 4〇2_, the power receiving end 32, the comparing unit and the boosting unit are configured to control the current magnitude of the power receiving end % to the boosting unit 4〇4 according to the comparison result output by the comparing unit 4GG. Output a drive signal micro ¥. The boosting unit is coupled between the side of the miscellaneous unit of the driving unit 402 for increasing the voltage level of the regulating unit strip to the driving unit 402. The details of the step of adding the boosting unit 4〇4 will be described later. Finally, the voltage regulating unit 406 is connected to the boosting unit 4〇4, the comparing unit 4〇〇❹, and a ground terminal GND' for outputting the feedback signal VFB to the comparing unit according to the voltage level of the boosting unit 4〇4. 4〇〇. In the fifth stage circuit, the comparison unit 4 〇〇 compares the reference voltage VREF with the feedback signal VFB to control the magnitude of the output current of the driving unit 4〇2, thereby generating the driving signal VDRV. At the same time, the front stage circuit 300 can be operated more stably by the Miller surface method. It is to be noted that FIG. 4 is a schematic diagram of an embodiment of the pre-stage circuit 3, which is generally modified by a person skilled in the art, and is not limited thereto. For example, please refer to FIG. 5, which is a schematic diagram of a preferred embodiment of a pre-stage circuit. In FIG. 5, an operational amplifier 500 is used to implement the comparison unit 400; a PMOS transistor MP1 and a compensation component CM1 are used to implement the driving unit 4〇2; and the NMOS sb bodies MN2 and MN3 are used to implement the boosting unit 4 〇4; and resistors R1, R2 are used to implement the pressure regulating unit 406. The operational amplifier 500 can compare the reference voltage vref with the feedback signal WB provided by the resistors R1, R2 to control the conduction of the transistor 1 20101264 MP1. At the same time, the NMOS transistors MN2 and MN3 are in a diode-connected form to provide a fixed voltage difference to improve the voltage reference of the pM〇s transistor MP1 during operation. As a result, the gate voltage of the pM〇s transistor Mpl can output the drive signal VDRV at a higher voltage reference such that the next stage of the buffer stage circuit 302 and the output stage circuit 304 also operate on a higher voltage reference. Therefore, the pre-stage circuit 300 returns the disturbance of the transistor Μρ!汲 voltage to the operational amplifier 5〇〇 via the resistors R1 and R2 to control the conduction of the transistor, thereby offsetting the transistor MPU and the pole voltage. Disturbance, the voltage of the transistor is quickly restored to the original equilibrium state. In addition, the capacitor (five) is connected between the gate and the gate of the pM〇s transistor MP1 to provide frequency compensation. According to the Miller compensation method in the circuit design, as the frequency compensation capacitor (:]^1, it is connected between the signal amplification function and the secret, which can make the original main pole age a relatively low frequency. Lai main pole and - relatively high _ new pole, away (five) es_ng). Pole separation function via Miller compensation method Between the gate and the immersion of the PMOS transistor hall, a new low-frequency and more stable main pole can be generated to improve system stability. For the driving unit 4〇2 in the pre-stage circuit 300, the frequency compensation mode of the transistor can be changed to obtain an equivalent effect, for example, replacing the capacitor CM1 with a series of electric hexels and a resistor RM, as shown in FIG. 6A. Shown. In the 6a picture, the first. Where 'capacitor CM2 passes through the new main pole of Miller's compensation method, and the resistor can generate a new zero point, and the frequency response of the circuit of 201015264 is changed. It should be noted that the compensation component of the drive unit is (4) to make the original male age be a more expensive rider - a new pole with higher frequency, a stable stability, and the connection mode and implementation mode of the compensation component. It can vary depending on the system, and is not limited to this. For example, reference is made to Figure 6B, and Figure 6b is a schematic diagram of an embodiment of the pre-stage circuit 3〇〇. Comparing FIGS. 6B and 5, the difference between the embodiment shown in FIG. 6B and FIG. 5 is that the PMOS transistor in FIG. 4 is replaced by the -NMOS transistor _ in FIG. 6B. The way the op amp is connected is also changed. In this case, the capacitor CC _ is connected between the interpole and the ground of the transistor surface to provide a frequency plane to improve system stability. Figure 7 is a schematic view of an embodiment of the buffer stage circuit 3〇2. The buffer stage circuit 302 is composed of a KM〇s transistor face 4 and a picture 5. Gu 〇 胄 胄 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰The signal VREG to the output stage circuit 3〇4qNM〇s transistor MN5 acts as a current source, and its gate is lightly connected to a fixed bias voltage source VBW 吏 NMOS transistor surface 5 to provide a fixed current to wake up 8 The transistor MN4 is used. In Fig. 7, the transistor 8 can provide a low output impedance, so that the pole corresponding to the low output impedance can be shifted from the low frequency to the high frequency to improve the stability of the system and increase the bandwidth of the system. In addition, the low output impedance provided by 匪〇8 transistor fine 4 also effectively blocks the effect of the voltage jitter of the output stage circuit 3〇4 on the 12 201015264 'J-level circuit 300. It is worth noting that the 'face 〇 8 transistor coffee will provide a low output lag when it is placed at the __ output voltage drop - a specific value. In order to compensate the source voltage of the NMOS transistor _4, the booster unit 4G4' in the pre-stage circuit makes the input 源ίί (source) phase of the NMOS transistor 4, at the input end (_) The drop phenomenon can be compensated in the boost unit 404 of the test 3 (8).赫 Herac Fig. 8' Fig. 8 is a schematic diagram of an embodiment of the output stage circuit 3〇4. The output stage circuit 304 includes an nm0s transistor, a cell 7, and a capacitor c1. The function of the surface 〇S transistor is a power switch ’ used to control the output voltage V0UT according to the adjustment signal outputted by the snubber circuit 3〇2. The function of NM〇s transistor Li 7 is a current source, which is extremely lightly connected to the voltage source of the fixed bias value, so that the battery can provide a fixed current to the NM〇s transistor surface 6. . The output stage circuit ❹ 304 further includes a capacitor CL coupled between the voltage output terminal % and the ground terminal gnd for storing the charge. It is worth noting that there is a parasitic capacitance Cgs with a large capacitance value between the source and the closed end of the awake (10) transistor. The parasitic capacitance Cgs can couple the voltage jitter phenomenon at the wheel terminal to the NMOS transistor mn6. The gate. In this case, the low output impedance provided by the NMOS transistor MN4 in the buffer stage circuit 302 can effectively block the influence of the voltage jitter phenomenon of the output stage circuit 304 on the pre-stage circuit 3(8). In addition, the coupling of the NM〇S transistor face 6 will cause its output voltage at the source to drop by a specific value. Similarly, boost unit 404 in preamp circuit 300 can provide a voltage boost function to compensate for voltage drops. 13 201015264 In combination with FIG. 5, FIG. 7, and FIG. 8, a preferred embodiment of the power supply voltage regulator circuit 3 is shown in FIG. As previously mentioned, in accordance with the Miller compensation method, the output of operational amplifier 500 produces a low frequency new main pole to improve system stability. The low output impedance of the NMOS transistor mn4 in the buffer stage circuit 302 drives the corresponding pole from low frequency to high frequency to improve system stability and increase system bandwidth, and can prevent the output stage circuit 304 from being affected by parasitic capacitance. The pre-stage circuit is 3〇〇. In addition, the NMOS transistors MN2 and MN3 of the ❹-polar body can compensate for the voltage drop phenomenon caused by the use of nm 电 _4 and MN6, so that the power supply voltage regulator circuit 3 has both stability and rapid response advantages. . In general, the NMOS transistor _6 of the output stage circuit 304 has a parasitic capacitance Cgs of a large valley. When the external load instantaneously draws a large current, it will cause the output voltage VOUT to drop, which will increase the conduction capability of the NMOS transistor MN6 to quickly provide the charge required by the load. Further, the low output impedance characteristic ' provided by the buffer stage circuit 302' causes the change of the output voltage VOUT to not affect the operation of the pre-stage circuit 300. The pre-stage circuit 300 is subjected to the Miller compensation method to obtain a new main pole which is relatively low frequency and does not shift with the output current. The output voltage drop phenomenon of the NMOS transistor MN4 and the NMOS transistor MN6 is also compensated by the boosting unit 404 of the preceding stage circuit 3 by an equal amount. Therefore, the present invention can achieve both stability and reaction speed, and the output voltage VOUT can maintain the required voltage level. In summary, although the conventional power supply voltage regulator circuit has removed the limit of the capacitor must be added 14 201015264 still need to solve the phenomenon of the circuit system riding * stability and reaction speed * sufficient. In contrast, the present invention provides a buffer stage circuit that provides a low output impedance to the power of the output stage circuit; 1 fluctuations do not affect the operation of the pre-stage circuit. Moreover, by providing frequency compensation and boosting the operating voltage to the driving unit of the pre-stage circuit, the power supply voltage stabilizing circuit of the present invention can properly solve the problem of insufficient system compensation and reaction speed, and provides a stable current source with a large current load. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. [Simple Description of the Drawing] Fig. 1 is a schematic diagram of a conventional power supply voltage stabilizing circuit. Figure 2 is a schematic diagram of a conventional power supply voltage regulator circuit. FIG. 3 is a schematic diagram of a power supply voltage stabilization circuit according to an embodiment of the present invention. ◎ Figure 4 is a schematic diagram of a pre-stage circuit in Figure 3. Fig. 5, Fig. 6A and Fig. 6B are schematic views showing an embodiment of the circuit of the previous stage of Fig. 4. Figure 7 is a schematic diagram of an embodiment of a buffer stage circuit in Figure 3. Figure 8 is a schematic diagram of an embodiment of an output stage circuit in Figure 3. Figure 9 is a schematic diagram of a preferred embodiment of the power supply voltage regulator circuit of the present invention. [Main component symbol description] 30 power supply voltage regulator 201015264 32 power receiving terminal 34 voltage output terminal 102'202 load 302 buffer stage circuit 304 output stage circuit 300 front stage circuit 400 comparison unit Ο 402 drive unit 404 boost unit 406 Unit 100, 200, 500 Operational amplifier VIN DC power supply VOUT Output voltage CL Capacitance Cgs 寄生 Parasitic capacitance CEXT External capacitance CM1 ' CM2 > CC capacitance Ro ' R1 ' R2 ' RM Resistance M2, M3, MN1, MN2, MN3 ' NMOS Crystal, MN4, MN5, MN6, MN7 Ml ' MP1 PMOS transistor GND Ground VDRV drive signal 16 201015264 Adjust signal reference voltage source VREG VREF VB1 ' VB2 ❹
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