201003874 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置，特別係有關於一 種無外引腳式半導體封裝構造。 【先前技術】 伴隨著半導體產品輕薄短小之發展趨勢，傳統具有 外引腳之導線架因其由產品的側邊外露延伸並無法滿 足趨勢，因此發展出一種無外引腳式半導體封裝構造， 其是一種能符合小尺寸封裝與低成本的導線架基底半 導體封裝構造，以引腳的下表面外露於封膠體底面以供 對外表面接合，故能取代由封膠體側面延伸並彎折成形 之外引腳，能符合低外形輪廓、重量輕之需求，並可縮 小整體封裝構造的體積以及提高訊號傳遞的速度。然習 知之無外引腳式半導體封裝構造仍會有可靠度降低之 問題。 請參閱第1圖所示，為一種習知無外引腳式半導體 封裝構造之截面示意圖。該無外引腳式半導體封裝構造 1 0 0主要包含複數個引腳1 1 0、一晶片1 2 0、複數個銲 線1 3 0以及一封膠體1 4 0。該些引腳1 1 0係排列在該封 膠體140之底面兩側或周邊，但不具有由該封膠體140 之側面往外延伸彎折的外引腳。利用一黏晶膠1 5 1，如 膠帶（tape)或環氧膠，將該晶片120黏設於一晶片承座 1 5 0上，而該晶片承座1 5 0通常是與該些引腳1 1 0為相 同金屬材質並形成於同一導線架。該晶片1 20之主動面 5 201003874 上係設有複數個電極1 2 1，例如銲墊。該些銲線1 3 0係 利用打線製程所形成，以連接該晶片 1 2 0之該些電極 1 2 1至相對應之該些引腳1 1 0之上表面1 1 1。該封膠體 140係以壓模（transfer molding)製程形成，以密封該些 引腳1 1 0、該晶片1 2 0與該些銲線1 3 0，但顯露該些引 腳1 1 0之下表面1 1 2與該晶片承座1 5 0之下表面在該封 膠體1 40之底面，以供對外接合。由於該些引腳1 1 0的 顯露面積過大，在熱循環試驗中，受到熱應力作用容易 造成該些引腳1 1 0與該封膠體1 40的接合界面產生分 層，特別是由該些引腳1 1 0之顯露切割後端1 1 3開始發 生，導致引腳脫落與水氣侵入之問題，使得產品的可靠 度低落。 再者，在應用上，該無外引腳式半導體封裝構造1 00 應以表面接著（SMT)技術安裝至一印刷電路板（圖未繪 出）。其係利用銲錫材料將該些引腳 1 1 0之下表面1 1 2 焊固於該印刷電路板上相對應之接墊，以達到電性導通 與增進散熱之目的。銲錫材料不同於一般半導體封裝構 造，如球柵陣列封裝所設置之銲球或是外接端子，在回 焊時過於柔軟不足以維持封裝構造的表面接合縫隙。因 此，習知無外引腳式半導體封裝構造1 00舆被表面接合 印刷電路板之間的表面接合缝隙顯得更小且無法控 制，甚至水平度也有誤差。這將導致在某一引腳110下 的銲錫接點易於受到熱應力的集中作用，而產生焊點斷 裂之問題。 6 201003874 此外’該些引腳11 0之切割德诚Η 7+ 傻知11 3顯露在該封膠 體14〇之側面亦會引起金屬氧化耸„ Bs ^ ^ 〇 乳1匕寻問題，並容易產生天 線效應（a n t e η n a e f f e c t)等高頻却轴·工 馮汛旒干擾，使外部之雜散 電荷累積在該些引腳1 10上，卄推 止^ ^ 亚進一步破壞内部晶片 120。 【發明内容】 有鑒於此，本發明之主要目的总 戈曰的係在於提供一種無外 引腳式半導體封裝構造，利用丨 用弓丨腳之凸點彎曲組合方式 可以防止引腳脫落與水氣侵入， 以達到尚可靠度。並可 維持封襄構造的表面接合縫隙，I i 甚至可以達到節省銲球 或外接端子之設置’以避免焊點斷裂。 本發明的目的及解決其技術p卩靖θ M m ^ 仅術問題是採用以下技術方 案來實現的。依據本發明所揭示 丨判不之一種無外接腳式半導 體封裝構造，主要包含複數個第一引腳、一第一晶片、 複數個第—銲線以及一封膠體。每一第一引腳係具有一 第-水平接指、一第一凸點彎曲及—相對遠離該第一水 平接指之後端，其中該些第一水平接指係形成於一第一 平面，該些第一凸點彎曲係突出至一第二平面，並且該 第一平面與該第二平面為平行。該第一晶片係具有複數 個第一電極。該些第一銲線係連接該第一晶片之該些第 一電極與該些第一引腳之該些第一水平接指。該封膠體 係密封該第一晶片、該些第一銲線、該些第一引腳之該 些第一水平接指與該些第一引腳之後端，該封膠體係具 有一底面’其係平行形成在該第一平面與該第二平面之 7 201003874 間，以使該些第一引腳僅有該些第一凸點彎曲為突出外 露在該底面。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述無外接腳式半導體封裝構造中，該封膠體之 該底面至該第二平面之距離係可不大於該些第一凸點 彎曲之厚度，以使該些第一凸點彎曲之内表面被該封膠 體密封。 在前述無外接腳式半導體封裝構造中，可另包含一 晶片承座，用以承載該第一晶片。 在前述無外接腳式半導體封裝構造中，可另包含一 黏晶膠，其係黏接該第一晶片與該晶片承座。 在前述無外接腳式半導體封裝構造中，可另包含一 膠帶，係黏附該第一晶片至該些第一水平接指。 在前述無外接腳式半導體封裝構造中，該些第一凸 點彎曲係可為圓弧形截面。 在前述無外接腳式半導體封裝構造中，該些第一凸 點彎曲係可為v形截面。 在前述無外接腳式半導體封裝構造中，可另包含複 數個第二引腳、一第二晶片以及複數個第二銲線。每一 第二引腳係具有一第二水平接指及一第二凸點彎曲，其 中該些第二凸點彎曲係可接合至該些第一引腳。該第二 晶片係可設置於該第一晶片上並具有複數個第二電 極。該些第二銲線係可連接該第二晶片之該些第二電極 8 201003874 與該些第二引腳之該些第二水平接指。 在前述無外接腳式半導體封裝構造中 線膠層’係形成於該第一晶匕3-覆 第-銲線。 X第—曰曰片並局部包覆該些 在前述無外接腳式半導體封裝構造中， 之被密封後端係可具有非平面端面。 二第-引腳 在刖述無外接腳式半導體封裝構造中，該 之被密封後端係可為分叉狀或鑛齒狀。 。弟-引腳 在前述無外接腳式半導體封褒 點彎曲之至少-個係可位在該第—曰…些第—凸 由以上技術方案可以看出，本 覆盍£。 導體封裝構造，具有以下優點與錢：之無外接腳式半 -、藉由：腳只有突出於封膠體底面之 路，可以^引㈣^與水氣侵人，^為外 度。 Λ建到向可靠 —、利用引腳之凸點彎曲的突 表面接合縫碎，甚至=能維持封裂構造的 之設置，以避免焊點斷裂。 秦^子 三、藉由引腳形成之凸點彎曲可做為該無外 體封裝構造之一體化外接 1 +導 成本。 于以即名封裝步騍與 四：體密封引腳之後端’避免天線效應 干擾，以增進封裝產品之可靠度。 員吼蜆 五、藉由引腳之被密封後端形成為^叉狀或鑛齒狀，。 9 201003874 增進引腳在封膠體内之咬合度。 【實施方式】 依據本發明之第一具體實施例，一種無外接腳式半 導體封裝構造舉例說明於第2圖之截面 接腳式半導體封裝構造㈣主要包含複數個 2 10 第一晶片22〇、複數個第一銲線no以及—封 膠體240201003874 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to an external lead type semiconductor package structure. [Prior Art] With the trend of thin and light semiconductor products, the conventional lead frame with external leads has not been able to meet the trend due to the extension of the side of the product. Therefore, an external lead type semiconductor package structure has been developed. The utility model relates to a lead frame base semiconductor package structure which can meet the small package and low cost, and the lower surface of the lead is exposed on the bottom surface of the seal body for the external surface to be joined, so that it can be replaced by the side surface of the sealant and bent and formed. The foot can meet the requirements of low profile and light weight, and can reduce the volume of the overall package structure and improve the speed of signal transmission. However, there is still a problem of reduced reliability in the conventional lead-type semiconductor package construction. Referring to Figure 1, there is shown a cross-sectional view of a conventional leadless semiconductor package construction. The external lead type semiconductor package structure 100 mainly includes a plurality of pins 1 10 0, a wafer 1 2 0 , a plurality of bonding wires 1 30 0, and a colloid 1 40. The pins 110 are arranged on both sides or the periphery of the bottom surface of the sealant 140, but do not have external pins that are bent outwardly from the side of the sealant 140. The wafer 120 is adhered to a wafer holder 150 by a glue, such as tape or epoxy, and the wafer holder 150 is usually associated with the pins. 1 1 0 is made of the same metal and formed on the same lead frame. The active surface 5 201003874 of the wafer 1 20 is provided with a plurality of electrodes 1 2 1, such as solder pads. The bonding wires 1 30 are formed by a wire bonding process to connect the electrodes 1 2 1 of the wafer 120 to the corresponding surface 1 1 1 of the pins 110. The encapsulant 140 is formed by a transfer molding process to seal the pins 110, the wafer 120 and the bonding wires 1 30, but expose the pins 1 1 0 The surface 1 1 2 and the lower surface of the wafer holder 150 are on the bottom surface of the sealant 140 for external bonding. Since the exposed area of the pins 110 is too large, in the thermal cycle test, the thermal stress is likely to cause delamination of the bonding interface between the pins 110 and the encapsulant 140, especially by the The exposed end of the pin 1 1 0 1 1 3 begins to occur, causing pinout and moisture intrusion problems, making the product less reliable. Furthermore, in application, the leadless semiconductor package structure 100 should be mounted to a printed circuit board (not shown) by surface-to-surface (SMT) technology. The soldering material is used to solder the lower surface 1 1 2 of the pins 110 to the corresponding pads on the printed circuit board to achieve electrical conduction and heat dissipation. The solder material is different from the general semiconductor package structure, such as solder balls or external terminals provided in the ball grid array package, which is too soft during reflow to maintain the surface joint gap of the package structure. Therefore, the conventional lead-free semiconductor package structure 100 舆 is surface-bonded. The surface joint gap between the printed circuit boards is smaller and uncontrollable, and even the level is inaccurate. This will result in solder joints under a certain pin 110 being susceptible to thermal stress concentration, which can cause solder joint breakage. 6 201003874 In addition, 'the pin 11 0's cut Decheng Η 7+ silly know 11 3 exposed on the side of the sealant 14 亦 will also cause metal oxidation „ Bs ^ ^ 〇 milk 1 匕 problem, and easy to produce The antenna effect (ante η naeffect) and the like are high-frequency, but the external stray charges are accumulated on the pins 1 10 , and the internal wafer 120 is further destroyed. In view of this, the main purpose of the present invention is to provide an external lead type semiconductor package structure, which can prevent pin drop and moisture intrusion by using a bump bending combination of the bow and the foot. Reliable reliability is achieved. The surface joint gap of the sealing structure can be maintained, and I i can even save the solder ball or the arrangement of the external terminals to avoid solder joint breakage. The object of the present invention is to solve the technical problem. The problem is only achieved by the following technical solution. According to the invention, an external pinless semiconductor package structure mainly includes a plurality of first pins, a first chip, a plurality of first wire bonds and a gel body. Each of the first pins has a first-level finger, a first bump bend, and a relatively long distance from the rear end of the first horizontal finger, wherein the first The horizontal finger is formed on a first plane, the first bump bending system protrudes to a second plane, and the first plane is parallel to the second plane. The first wafer has a plurality of first electrodes The first bonding wires are connected to the first electrodes of the first chip and the first horizontal fingers of the first pins. The sealing system seals the first wafer, the first solders The first horizontal fingers of the first pins and the rear ends of the first pins, the encapsulation system has a bottom surface that is formed in parallel with the first plane and the second plane. Between 201003874, the first pins are only bent to protrude from the first bumps to protrude from the bottom surface. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the semiconductor package structure, the bottom surface of the sealant The distance from the second plane may not be greater than the thickness of the first bumps, so that the inner surfaces of the first bumps are sealed by the sealant. In the foregoing external strapless semiconductor package structure, Further comprising a wafer holder for carrying the first wafer. In the external pedestal-free semiconductor package structure, an adhesive may be further included, which bonds the first wafer and the wafer holder. In the external strapless semiconductor package structure, an adhesive tape may be further included to adhere the first wafer to the first horizontal fingers. In the foregoing external strapless semiconductor package structure, the first bump bending systems may be In the above-described external pinless semiconductor package structure, the first bump bending systems may have a v-shaped cross section. In the foregoing external pinless semiconductor package structure, a plurality of second pins, a second wafer, and a plurality of second bonding wires may be further included. Each of the second leads has a second horizontal finger and a second bump bend, wherein the second bump bends are engageable to the first pins. The second wafer can be disposed on the first wafer and has a plurality of second electrodes. The second bonding wires are connected to the second electrodes 8 201003874 of the second chip and the second horizontal fingers of the second pins. In the pedestal-free semiconductor package structure described above, a line of glue layer is formed on the first wafer-over-weld wire. The X-thin film is partially covered and partially covered. In the aforementioned pedestal-free semiconductor package structure, the sealed back end may have a non-planar end face. Two-Phase-Pin In the non-external-pin semiconductor package construction described above, the sealed back end may be bifurcated or mineral-toothed. . The younger-pin is at least one of the above-mentioned bends without the external-pin type semiconductor sealing point, which can be located in the first-thickness---the above-mentioned first convexity can be seen from the above technical solution. The conductor package structure has the following advantages and money: there is no external pin half--, by: the foot only protrudes from the bottom surface of the sealant, which can be used to induce (4)^ with water and gas intrusion, and ^ is external. Λ 到 向 向 可靠 、 、 、 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用Qinzizi 3. The bump bending formed by the pin can be used as the integrated external connection cost of the external package structure. In the case of the name package step and the fourth: body seal pin rear end to avoid antenna interference, to improve the reliability of the packaged product.吼蚬 、 5. By the sealed back end of the pin is formed into a fork shape or a mineral tooth shape. 9 201003874 Improves the bite of the pin in the sealant. [Embodiment] According to a first embodiment of the present invention, a cross-leg type semiconductor package structure illustrated in FIG. 2 is exemplified by a plurality of 2 10 first wafers 22 〇, plural First bonding wire no and sealing body 240
如第2圖所示，該些第—引腳21〇係形成於該無外 I腳式半導體封裝構造200之兩側邊或四周側邊。該些 第一引腳21G係為-導線架之—部份，其材f可為導電 性金屬材質，例如銅。每一第一引腳21〇係具有一第一As shown in FIG. 2, the first leads 21 are formed on both sides or on the sides of the outer-less semiconductor package structure 200. The first pins 21G are part of the lead frame, and the material f can be made of a conductive metal such as copper. Each first pin 21 has a first
2平接指211、一第一凸點彎曲212及一相對遠離該第 一水平接指211之後端213。該些第一水平接指211係 供打線接合。在本實施例中，該些第一水平接指係 L伸至β亥第—晶片22〇之下方，用以承載該第一晶片 22〇,而為—種晶片在引腳上（COL，ChiP-〇n_Lead)之封裝形 態。其中’該些第一水平接指2丨丨係形成於一第一平面 P1，該些第一凸點彎曲212係突出至一第二平面p2， 並且该第一平面pl與該第二平面P2係為平行。因此， 如第2圖所示，該些第一凸點彎曲212係遠離該第一平 面P1而往下彎曲至該第二平面P2。 具體而言，如第3圖所示，該些第一凸點彎曲2 j 2 係可利用沖壓方式形成，其係將該些第一引腳21〇放置 在一模板10上，該模板10係具有複數個與上述該些第 10 201003874 -凸點f肖212相同形狀之凹槽"，再利用複數 有相對該些凹槽U形狀之沖壓具2〇往下沖壓該些 引腳210而形成該些第一凸點彎曲212。兮些第二 21〇之厚度可被薄化而具有良好可加工性能了以形 些第-凸點彎曲212，通常其厚度約在數十微米。 實施例中，該些第—凸點彎#212係可為圓藏形截 以模擬習知的銲球更具有與引腳-體化之優點。但 局限地’該些第―凸點f曲212之截面亦可為各 狀…形(第5圖所示）、矩形或其他形狀。並且 鄰之第-引腳210之該些第一凸點彎曲212可為交 列設置’以分散焊接凸點’並增加與外界電性連接 輸入/輸出連接端點，以增加與外部印刷電路板之 性二此，該些第-凸點·彎曲⑴的形成不需要繁 驟與附加額外元件#於报# 件便此形成，可作為—體化外接端 以替代辉球(容後詳述)。該些第-引腳川可放置 模板或承載板上進行半導體封裝作業。 φ :第2圖所示’該第-晶片22。係具有複數個 ’例如銲墊’其係位於該第-晶片220之 面：可利用該些第一銲線23 0電性連接該第一晶片 第-電極221與該些第一引腳21〇之該些第 平接私2 1 1。該些第一銲線23 〇可利用打線製程 成’其材質可為金。該些第一銲線23 〇之兩端打線 占々元成方式係可採用超音波接合、熱壓接合或熱 波接°等方式’以電性連接該第一晶片220與該些 個具 第一 引腳 成該 在本 1面， 不受 種形 ，相 錯排 用之 固著 複步 子， 於該 第一 主動 220 一水 所形 接合 超音 第一 201003874 引腳21 0。此外，如第2圖所示，該無外接腳式半導體 封裝構造200可另包含一膠帶250，例如雙面ΡΙ膠帶， 係黏附該第一晶片220至該些第一水平接指2 1 1，用以 固定該第一晶片22 0並且不使該些第一水平接指2 1 1電 性接觸至該第一晶片220之背面。 如第2圖所示，該封膠體240係為一種内含矽氧填 充物的絕緣性熱固性樹脂，如環氧模封化合物（EMC, epoxy molding compound)，可利用模封（或稱轉移成形） / 1 方法形成。該封膠體240係密封該第一晶片220、該些 第一銲線23 0、該些第一引腳2 1 0之該些第一水平接指 2 1 1與該些第一引腳2 1 0之後端2 1 3，以使該些内部元 件與外界氣密隔離而免受外界衝擊或污染。具體而言， 該封膠體240係具有一底面24 1，其係平行形成在該第 一平面P1與該第二平面P2之間，以使該些第一引腳 2 1 0僅有該些第一凸點彎曲 2 1 2為突出外露在該底面 f 241。較佳地，如第2圖所示，該封膠體240之該底面 24 1至該第二平面P2之距離係可不大於該些第一凸點 彎曲2 1 2之厚度，以使該些第一凸點彎曲2 1 2之内表面 被該封膠體240密封，故在封膠時，該封膠體240係一 併充填入該些第一凸點彎曲2 1 2之内表面空間，可強化 該些第一凸點彎曲2 1 2之強度。該封膠體2 4 0由該底面 24 1至該第一平面P 1的封膠縫隙可利用一下模具具有 複數個深度小於該些第一凸點彎曲 212的凹坑定義 之，而上述封膠模具之形狀可大致與第3圖所示的模具 12 201003874 1 0相同，但凹坑的深度小於該模具1 〇之凹槽11之深 度，並在凹坑内設有吸盤或夾具以在封膠時固定該些第 一引腳210。 因此，上述的無外接腳式半導體封裝構造200具有 以下幾點主要功效。由於該些第一引腳2 1 0只有第一凸 點彎曲212是突出地外露於該封膠體240之底面24 1， 該些第一引腳2 1 0之其餘部位皆被密封在該封膠體240 内，特別是在該封膠體240之側面不會有引腳外露之切 割後端。故在熱循環試驗或實際運算中，可以防止第一 引腳2 1 0的脫落與水氣侵入，以達到高可靠度。 再者，利用該些第一引腳2 1 0之第一凸點彎曲2 1 2 的突出高度能維持該無外接腳式半導體封裝構造200 的表面接合縫隙，甚至可以達到節省銲球或外接端子之 設置，以避免焊點斷裂。故該些第一凸點彎曲2 1 2做為 該無外接腳式半導體封裝構造 200之一體化外接端 子，以節省封裝步驟與成本。 此外，由於該些第一引腳2 1 0僅有該些第一凸點彎 曲2 12外露，其餘係密封在該封膠體240内，故能避免 該些第一引腳2 1 0受到天線效應等高頻訊號干擾，以防 止破壞該第一晶片220或内部元件，以增進封裝產品之 可靠度。 較佳地，如第4Α圖所示，在一實施例中，該些第一引腳 2 1 0之被密封後端2 1 3係可具有非平面端面，例如分叉狀。 如第4Β圖所示，在另一變化實施例中，該些第一引腳210 13 201003874 之被密封後端213’係可為鋸齒狀。因此，在被該封膠體24〇 密封該些被密封後端213、213’之後’可增進該些第一引腳 210在該封膠體240内之緊密咬合度。 依據本發明之弟二具體實施例’另一種無外接腳式 半導體封裝構造說明於第5圖之截面示意圖。主要元件 係與第一具體實施例相同並以相同圖號表示之，故可以 理解亦具有上述功效。每一第一引腳210係具有一第— 水平接指2 1 1、複數個第一凸點彎曲2 1 2及—相對遠離 1 該第一水平接指211之後端213。其中，在本實施例中， 該些第一凸點彎曲2 1 2係為V形截面，可具有端子穿刺 之功效。每一第一引腳210的第一凸點彎曲212的數量 增加可以增加與外界電性連接的機率。至少一或部份之 該些第一凸點彎曲2 12可位在該第一晶片22〇之底部覆 蓋區，可以增進表面接合縫隙的維持精準度並提供良好 的打線支撐。在本實施例中，該膠帶250可為完整平貼 在該第一晶片220之背面，用以電性絕緣該第一晶片 22〇並固定該些第一引腳210之第一水平接指211。 依據本發明之第三具體實施例，另一種無外接腳式 半導體封裝構造說明於第6圖之截面示意圖。該無外接 腳式半導體封裝構造300主要包含複數個第一引腳 2 1 0、一第一晶片2 2 0、複數個第一輝線2 3 〇以及一封 膠體240。其中與第一實施例相同的主要元件將以相同 符5虎標不’不再予以資述。 請參閱第6圖所示，該無外接腳式半導體封裝構造 14 201003874 300可另包含一晶片承座350，用以承載該第—晶片 220’並提供導熱與散熱，以使該無外接腳式半導體封 裝構造300具有較佳之散熱效率，並使該些第一水平接 指2 1 1可不延伸到該第一晶片2 2 0之下方。並可利用_ 黏晶膠351黏接該第一晶片220與該晶片承座35〇，以 使亥第一晶片220固著於該晶片承座350上。具體而 言，該黏晶膠3 5 1係可利用網印或針筒點膠、貼附等方 法开> 成在該晶片承座3 5 0上。該黏晶膠3 5 1係可選自於 Β階膠體、液態膠或聚亞醯胺（ΡΙ)膠帶之其中之一。較 佳地’該晶片承座3 50係具有一凸點彎曲352，其係突出 外露在該封膠體240之該底面241，其突出高度可與該些第 一凸點彎曲212大致相同，也就可以提供在該底面241中央 的表面接合縫隙的維持效果。 依據本發明之第四具體實施例，另一種無外接腳式 半導體封裝構造說明於第7圖之截面示意圖。該無外接 腳式半導體封裝構造400主要包含複數個第一引腳 2l〇 第一晶片22〇、複數個第一銲線230以及一封 臉體240。其中與第一實施例相同的主要元件將以相同 符號標示，不再予以贅述。該無外接腳式半導體封裝構 邊400另包含一晶片承座45〇，用以承載該第一晶片 220，並提供導熱與散熱。 如第7圖所示，該無外接腳式半導體封裝構造4〇0 <運用多晶片堆疊，另包含複數個第二引腳46〇、一第 〆日日片470以及複數個第一鲜線480。該此第二引腳460 15 201003874 係對應排列在該些第一引腳21〇上方。每_第二引腳 460係具有—第二水平接指461及—第二凸點彎曲 462 ’其中該些第二凸點f曲—係可接合至該些第一 引腳2 1 0而達到上下引腳的電性導通。該第二晶月4 7 〇 係可》又置於β亥第一晶片22〇上並具有複數個第二電極 47卜該些第二銲線48〇係可連接該第二晶片指之該 些第二電極471與該些第二引腳46〇之該些第二水平接 指4 6 1，以逹到電性連接。 更具體地，該無外接腳式半導體封裝構造4〇〇中， 可另包含一覆線膠層490,係形成於該第一晶片22〇與該第 一晶片470之間並局部包覆該些第一銲線23〇，可用以承載 該第U470並可^該些第—銲線23〇之晶片端。 …因此’在本實施例中，該無外引腳式半導體封裝構造糊 可以不需額外設置内邻雷柯# 2 直円。卩電性端子，便能達到 疊之電性連接目的，廿0丁< 卜日日斤率 „ 並且不文限地，可依此架構往上堆 疊更多晶片與引腳。 苒任上隹 以上所述’僅是本發明的較佳實施例而已 本發明作任何形式上沾Βρ生, 並非對 所附申請專利範圍Α坐7 v 圍虽依 、一範圍為準。任何熟悉本專業的技術 利用上述揭不的枯化 6 貝了 忖内谷作出些許更動或修 變化的等效實施例，佃 為等同 但凡疋未脫離本發明技術方 容，依據本發明的技術眚折 ^ 莱的内 议術貫貝對以上實施例所作 單修改、等同變化鱼收麻 ^ J任何簡 更化與修飾，均仍屬於本發明 範圍内。 町方案的 16 201003874 【圖式簡單說明】 第1圖：習知無外引腳式半導體封裝構造之截面示意圖。 第2圖：為依據本發明第一具體實施例的一種無外接腳 式半導體封裝構造之截面示意圖。 第3圖：繪示依據本發明第一具體實施例的該無外引腳 式半導體封裝構造的第一凸點彎曲形成方法 之截面示意圖。 第4A及4B圖：為依據本發明第一具體實施例的該無 外引腳式半導體封裝構造的第一引腳在不同 變化例之俯視圖。 第5圖：為依據本發明第二具體實施例的一種無外接腳 式半導體封裝構造之截面示意圖。 第6圖：為依據本發明第三具體實施例的一種無外接腳 式半導體封裝構造之截面示意圖。 第7圖：為依據本發明第四具體實施例的一種無外接腳 . 式半導體封裝構造之截面示意圖。 【主要元件符號說明】 P1 第一平面 P2 第二平面 10 模板 11 凹槽 20 沖壓具 100 無外接腳式半導體封裝構造 110 引腳 111 上表面 112下表面 113 外露後端 120 晶片 121 電極 130 銲線 140 封膠體 17 201003874 150 200 210 212 220 230 250 300 350 400 45 0 460 470 480 490 晶片承座 1 5 1黏晶膠 無外接腳式半導體封裝構造 第一引腳 211第一水平接指 第一凸點彎曲2 1 3後端 2 1 3 ’後端 第一晶片 221第一電極 第一銲線 240封膠體 241底面 膠帶 無外接腳式半導體封裝構造 晶片承座 351黏晶膠 352凸點彎曲 無外接腳式半導體封裝構造 晶片承座 第二引腳 461第二水平接指 462第二凸點彎曲 第二晶片 471第二電極 第二銲線 覆線膠層 182 flat fingers 211, a first bump bend 212 and a rear end 213 relatively far from the first horizontal joint 211. The first horizontal fingers 211 are for wire bonding. In this embodiment, the first horizontal fingers L extend below the β-first wafer 22〇 to carry the first wafer 22〇, and the wafer is on the pin (COL, ChiP). -〇n_Lead) package form. Wherein the first horizontal fingers 2 are formed on a first plane P1, the first bumps 212 are protruded to a second plane p2, and the first plane pl and the second plane P2 The system is parallel. Therefore, as shown in Fig. 2, the first bump bends 212 are bent downward to the second plane P2 away from the first plane P1. Specifically, as shown in FIG. 3, the first bump bends 2 j 2 can be formed by stamping, and the first pins 21 are placed on a template 10, and the template 10 is a plurality of grooves having the same shape as the above-mentioned 10th 201003874-bumps 212, and then punching the pins 210 with the plurality of punches 2 of the grooves U shape The first bumps are bent 212. The thickness of the second 21 turns can be thinned to have good processability to form a first-bump bend 212, typically having a thickness of about tens of microns. In an embodiment, the first bumps #212 can be circularly shaped to simulate the advantages of conventional solder balls with pin-body. However, the cross section of the first-bump f curve 212 may be a shape of a shape (shown in Fig. 5), a rectangle or the like. And the first bump bends 212 of the adjacent first-pin 210 may be set to 'distribute the solder bumps' for the intersection and increase the input/output connection terminals electrically connected to the outside to increase the external printed circuit board. Therefore, the formation of the first-bump-bend (1) does not need to be complicated and additional additional components are formed. This can be used as a body-like external terminal instead of a glow ball. . These first-pin can be placed on a stencil or carrier board for semiconductor packaging operations. φ : 'the first wafer 22' shown in Fig. 2 . The first wafer electrode 221 and the first pins 21 are electrically connected to the first wafer 221 by using the first bonding wires 230. The first flats are private 1 1 1 . The first bonding wires 23 can be made by a wire bonding process, and the material thereof can be gold. The first bonding wires 23 are electrically connected to the first wafer 220 and the plurality of wires by means of ultrasonic bonding, thermocompression bonding or thermal wave bonding. A pin is formed on the first side of the body, and is not subjected to the seed shape, and the phase shifting step is used for the fixing step, and the first active 220 water-shaped joint supersonic first 201003874 pin 21 0. In addition, as shown in FIG. 2, the pedestal-free semiconductor package structure 200 may further include a tape 250, such as a double-sided tape, for adhering the first wafer 220 to the first horizontal fingers 2 1 1 . The first wafer 22 is fixed and the first horizontal fingers 21 1 are not electrically connected to the back surface of the first wafer 220. As shown in FIG. 2, the encapsulant 240 is an insulating thermosetting resin containing an oxygen-filled filler, such as an epoxy molding compound (EMC), which can be molded (or transferred). / 1 method is formed. The encapsulant 240 seals the first wafer 220, the first bonding wires 230, the first horizontal fingers 2 1 1 of the first pins 2 1 0 and the first pins 2 1 0 after the end 2 1 3, so that the internal components are airtightly isolated from the outside from external impact or pollution. Specifically, the encapsulant 240 has a bottom surface 24 1 formed in parallel between the first plane P1 and the second plane P2, so that the first pins 2 1 0 are only the first A bump bend 2 1 2 is exposed to the bottom surface f 241. Preferably, as shown in FIG. 2, the distance from the bottom surface 24 1 of the encapsulant 240 to the second plane P2 may not be greater than the thickness of the first bumps 2 1 2 to make the first The inner surface of the bump bend 2 1 2 is sealed by the sealant 240. Therefore, when the sealant is sealed, the sealant 240 is filled into the inner surface space of the first bump bends 2 1 2 to strengthen the inner surface space. The first bump bends the strength of 2 1 2 . The sealant gap of the sealant 240 from the bottom surface 24 1 to the first plane P 1 can be defined by a plurality of recesses having a depth smaller than the first bump bends 212, and the sealant mold is used. The shape may be substantially the same as the mold 12 201003874 1 0 shown in FIG. 3, but the depth of the dimple is smaller than the depth of the groove 11 of the mold 1 and a suction cup or a jig is provided in the dimple to be fixed at the time of sealing. The first pins 210. Therefore, the above-described external-less semiconductor package structure 200 has the following main effects. Since the first bumps 201 are only exposed to the bottom surface 24 of the encapsulant 240, the remaining portions of the first pins 2 10 are sealed in the encapsulant. Within 240, in particular, there is no lead-exposed cutting back end on the side of the encapsulant 240. Therefore, in the thermal cycle test or the actual calculation, the fall of the first pin 210 and the intrusion of moisture can be prevented to achieve high reliability. Moreover, the protrusion height of the first bump bend 2 1 2 of the first pins 2 1 0 can maintain the surface joint gap of the pedestal-free semiconductor package structure 200, and even save the solder ball or the external terminal. Set to avoid solder joint breakage. Therefore, the first bumps are bent 2 1 2 as the integrated external terminals of the external semiconductor package structure 200 to save packaging steps and costs. In addition, since the first pins 2 1 0 are only exposed by the first bumps 2 12 , the rest are sealed in the encapsulant 240 , so that the first pins 2 1 0 can be prevented from being subjected to the antenna effect. The high frequency signal interferes to prevent damage to the first wafer 220 or internal components to enhance the reliability of the packaged product. Preferably, as shown in FIG. 4, in an embodiment, the sealed rear end 2 1 3 of the first pins 210 may have a non-planar end face, such as a bifurcated shape. As shown in FIG. 4, in another variant embodiment, the sealed rear end 213' of the first pins 210 13 201003874 may be serrated. Therefore, after the sealed back ends 213, 213' are sealed by the sealant 24, the tightness of the first pins 210 in the sealant 240 can be improved. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Another embodiment of a semiconductor package having no external pin type is illustrated in a cross-sectional view of FIG. The main components are the same as those of the first embodiment and are represented by the same reference numerals, so that it is understood that the above-mentioned effects are also obtained. Each of the first pins 210 has a first horizontal finger 2 1 1 , a plurality of first bumps 2 1 2 and a relatively long distance 1 rear end 213 of the first horizontal finger 211. In the embodiment, the first bump bends 2 1 2 are V-shaped cross sections, and may have the effect of terminal puncture. The increase in the number of first bump bends 212 of each of the first pins 210 can increase the probability of electrical connection to the outside. At least one or a portion of the first bump bends 2 12 can be positioned in the bottom cover region of the first wafer 22 to improve the maintenance accuracy of the surface bond gap and provide good wire bonding support. In this embodiment, the tape 250 may be completely affixed to the back surface of the first wafer 220 to electrically insulate the first wafer 22 and fix the first horizontal fingers 211 of the first pins 210. . In accordance with a third embodiment of the present invention, another pedestal-free semiconductor package construction is illustrated in cross-section in Figure 6. The external strapless semiconductor package structure 300 mainly includes a plurality of first pins 2 10 0, a first wafer 2 2 0 , a plurality of first glow lines 2 3 〇, and a colloid 240. The main elements in which the same elements as the first embodiment will be the same will not be described. As shown in FIG. 6, the external-footless semiconductor package structure 14 201003874 300 may further include a wafer holder 350 for carrying the first wafer 220' and providing heat conduction and heat dissipation so that the external type is not provided. The semiconductor package structure 300 has better heat dissipation efficiency, and the first horizontal fingers 21 1 may not extend below the first wafer 2 2 0 . The first wafer 220 and the wafer holder 35 are bonded by the adhesive 351 to fix the first wafer 220 to the wafer holder 350. Specifically, the adhesive layer 3 5 1 can be opened on the wafer holder 350 by means of screen printing or syringe dispensing or attaching. The adhesive 3 1 1 may be selected from one of a ruthenium colloid, a liquid glue or a polyamidene (ruthenium) tape. Preferably, the wafer holder 3 50 has a bump bend 352 protruding from the bottom surface 241 of the seal body 240, and the protrusion height is substantially the same as the first bump bends 212. The maintenance effect of the surface joint gap at the center of the bottom surface 241 can be provided. In accordance with a fourth embodiment of the present invention, another pedestal-free semiconductor package construction is illustrated in cross section in Figure 7. The external-less semiconductor package structure 400 mainly includes a plurality of first pins 21 〇 a first wafer 22 , a plurality of first bonding wires 230 , and a face 240 . The same elements as those in the first embodiment will be designated by the same reference numerals and will not be described again. The pedestal-free semiconductor package edging 400 further includes a wafer holder 45 用以 for carrying the first wafer 220 and providing heat conduction and heat dissipation. As shown in FIG. 7, the pedestal-free semiconductor package structure 4 〇 0 < uses a multi-wafer stack, and further includes a plurality of second pins 46 〇, a second day 470, and a plurality of first fresh lines 480. The second pin 460 15 201003874 is correspondingly arranged above the first pins 21 。. Each of the second pins 460 has a second horizontal finger 461 and a second bump bend 462 ′, wherein the second bumps f are coupled to the first pins 2 1 0 to reach The upper and lower pins are electrically connected. The second crystal 4 7 can be placed on the first wafer 22 of the β-ray and has a plurality of second electrodes 47. The second bonding wires 48 can be connected to the second wafer. The second electrode 471 and the second horizontal fingers 46 of the second pins 46 are electrically connected. More specifically, the pedestal-free semiconductor package structure can further include a coating layer 490 formed between the first wafer 22 and the first wafer 470 and partially covered. The first bonding wire 23〇 can be used to carry the U-th and the wafer ends of the first bonding wires 23〇. Therefore, in the present embodiment, the external-lead type semiconductor package structure paste can be disposed without the need to additionally set the inner Neco #2 straight.卩Electrical terminals can achieve the purpose of electrical connection of stacks, 廿0丁< 卜日日斤 rate „ and, without limitation, stack more wafers and pins upwards according to this architecture. The above description is merely a preferred embodiment of the present invention and has been in any form of the present invention, and is not intended to be in accordance with the scope of the appended claims. The equivalent embodiment of the invention is not limited to the technical scope of the present invention, and the technique according to the present invention is not considered to be unconstrained from the technical scope of the present invention. The single modification of the above embodiment, the equivalent change of fish, and any modification and modification of the fish are still within the scope of the present invention. 16 of the town plan 201003874 [Simple description of the figure] Figure 1: Conventional FIG. 2 is a schematic cross-sectional view showing a structure of a semiconductor package without external pins according to a first embodiment of the present invention. FIG. 3 is a first embodiment of the present invention. real FIG. 4A and FIG. 4B are diagrams showing the first bump bending method of the external lead type semiconductor package structure. FIG. 4A and FIG. 4B are diagrams showing the first leadless semiconductor package structure according to the first embodiment of the present invention. A top view of a pin in different variations. FIG. 5 is a cross-sectional view of a non-external pin type semiconductor package structure in accordance with a second embodiment of the present invention. FIG. 6 is a third embodiment of the present invention. A cross-sectional view of a semiconductor package structure without an external pin. Fig. 7 is a schematic cross-sectional view showing a semiconductor package structure without external pins according to a fourth embodiment of the present invention. [Description of main components] P1 first plane P2 Second Plane 10 Template 11 Groove 20 Stamping Tool 100 No External Pin Type Semiconductor Package Construction 110 Pin 111 Upper Surface 112 Lower Surface 113 Exposed Rear End 120 Wafer 121 Electrode 130 Solder Wire 140 Sealant 17 201003874 150 200 210 212 220 230 250 300 350 400 45 0 460 470 480 490 Wafer holder 1 5 1 adhesive crystal without external pin semiconductor package construction Pin 211 first horizontal joint first bump bend 2 1 3 rear end 2 1 3 'back end first wafer 221 first electrode first bond wire 240 sealant 241 bottom surface tape no external foot semiconductor package structure wafer bearing Block 351 adhesive 352 bump bending without external foot semiconductor package structure wafer holder second pin 461 second horizontal finger 462 second bump bending second wafer 471 second electrode second bonding wire coating layer 18