TWI286831B - A chip package structure - Google Patents

Abstract

A chip package structure comprises a substrate, a chip, several conductive lines, a piece of heat sink and a compound. The substrate has a surface in which a chip area, a connecting area and a heat-spread area located thereon, the chip thereby is located on the chip area and the conductive lines are coupled to the chip and the connects on the connecting area. The piece of heat sink is located on the heat-spread area to increase efficiency of heat dissipation of the chip package. The compound covers the chip, the conductive lines and a part of the piece of heat sink. In addition, within the surface of the substrate, a grounding pad located on the heat-spread area is electrically connected to the piece of heat sink, for providing shielding of electromagnetic radiation.

Description

1286831 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a 曰H &#目钍Μ> s type of solar package structure, and in particular to a chip package having a heat dissipation structure structure. Prior Art In the half/body/industry, integrated circuits (Integrated Circuit,

The life of 1C) can be divided into three stages: integrated circuit design (IC d=lgn), integrated circuit fabrication (IC pr〇cess), and integrated circuit package (IC = kage). Therefore, the die is soldered through the wafer % η, the circuit is set to +, the strike is shorter than the first cover, and the wafer is cut. Bonding or flip-chip bonding mP chw b〇nding), etc., electrically connecting the bare die to a carrier = arrier, such as a leadframe or a substrate (substrata 荨, such as a bonding pad of a bare die) Rewiring (redlstribUti〇n) to the periphery of the wafer or the active surface of the wafer: Take the wire bonding structure of the wire bonding type as an example, when the bare wafer is backed to the t carrier, then The bonding method is electrically connected to the green attack, and then the bare crystal line is coated with a sealing material (m), to protect the bare wafer and the wires, etc., to prevent the bare wafer from being wet-rolled again. The effect while providing good thermal performance to the bare die. Figure. Ί1 失 Λ Λ Λ Λ Λ Λ 示意 示意 示意 示意 示意 示意 示意 示意 示意 示意 示意 示意 示意 示意 示意 示意 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 Ii 4,. The substrate 110 has a top surface 11 2 and a top surface 112 of the corresponding back substrate 110 and a back surface 114 respectively have a plurality of top connections

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Page 5 1286831 V. DESCRIPTION OF THE INVENTION (2) Point 11 6 a and bottom contact 116b ' and wafer 120 is disposed on top surface 112 ′ of substrate 1 1 Q and upper surface 122 of wafer 120 has a plurality of solder bumps 124 The wires 130 are electrically connected to the top contacts 1 16a of the top surface 1 12 of the substrate 1 1 respectively. 9 In addition, the 'sealing material 140 is coated with the wafer 120 and the wire 1 30, and the bottom contact 1 16b of the bottom surface 11 4 of the substrate 1 1 q can be made by the solder ball 1 18 and the external circuit, respectively. Electrical connection. Fig. 2 is a view showing a conventional wafer package structure of a flip chip bonding type. Referring to FIG. 2, the conventional flip chip bonding type wafer package structure is mainly composed of a substrate 210, a wafer 220, a plurality of solder balls 23A, and a primer 240. The substrate 21A has a top surface 212 and a corresponding back surface 214, and the top surface 212 and the back surface 214 of the substrate 210 respectively have a plurality of top contacts 2163 and bottom contacts 2161}, and the wafer 22 is disposed on the substrate 21〇. The top surface 212 of the wafer 220 has a plurality of pads 224, and the bumps 226 are electrically connected to the top contacts 216a of the top surface 212 of the substrate 21, and the bottom paste 240 is filled with The wafer 22 is sandwiched between the substrate 22 and the substrate 21 and covered with solder balls 230. In addition, the bottom contact of the bottom surface 214 of the substrate 21 is electrically connected to an external circuit by a solder ball 2300.曰 It is worth noting that - Tian Hao is in the heart of the heart to open a large amount of energy, once the heat can not effectively dissipate into the external environment, the combined == body circuit can not function properly due to overheating, :Yi: Energy, is an important subject in the field of chip packaging. The important task is to reduce the wafers from being subjected to external semiconductor chips, such as Multlple Chip M〇duie (mcm). Sealed dry =

1286831 The purpose of the wafer, the multi-sided, and the top sheet is disposed on the top of the substrate. The heat dissipation structure is described. The top surface of the wafer and the wafer area board are disposed on the base wafer.

In Package, SIP) Small, so easy to influence the correctness of individual wafers in the purpose of proposing a heat dissipation structure, using ipat ions. A heat dissipation structure for a wafer is proposed, and the heat dissipation structure encloses a contact region of the strip conductor of the present invention having a top surface of the substrate. In addition, the invention description (3) or the system package (the distance between the system slices may be magnetically disturbed, and thus the invention is directed to the heat dissipation disposed on the surface of the substrate in the present invention (heat diss The surface of the first mesh is provided with at least one material, and the wafer is provided with a shielding effect. In order to achieve the above structure, the substrate comprises a substrate and a glue. The substrate has a top field and a heat dissipation region, and the crystal wires are respectively connected to the wafer and Arranging on the top surface, the line and at least part of the substrate

In order to achieve the invention, the __L structure includes a substrate and a top surface, and the top mask is disposed in a joint manner in the base f', and the sheet-like heat dissipation structure further has a glue, which is f-shaped, etc. An electric book operation is generated between the two chips. a chip package structure for accelerating a package structure of a chip package structure, wherein the material of the substrate structure is in a space of conduction, for generating a chip package junction heat dissipation structure and a wafer area and a contact area The wafer area, the lead area, and the sheet-like heat sink, the seal-coated wafer, and the present invention propose another chip-package junction heat structure, the substrate has a region, the wafer is a flip-chip wafer region, and is electrically connected to The heat dissipation area of the top surface of the substrate. In addition, and at least part of the sheet-like heat dissipation structure. One piece and one heat

Page 7 1286831, the invention description (4) According to a preferred embodiment of the present invention, the substrate further has at least one ground pad disposed on the top surface of the substrate, and the ground pad is located in the heat dissipation region, and is in contact with the heat dissipation The surface of the structure, and the material of the sheet-like heat dissipation structure can be a conductive material to create a shielding effect. According to a preferred embodiment of the present invention, a cap-shaped heat dissipating structure is further encased in the crystal > 1 ' and the periphery of the cap-shaped heat dissipating structure is connected to the sheet-like heat dissipating structure, and the % encapsulant is filled in the cap-shaped heat dissipating structure and The space enclosed by the substrate. The above described objects, features, and advantages of the present invention will become more apparent and understood from the following description. A top view and a cross-sectional view of a chip package structure according to a first embodiment of the present invention are shown. The chip package structure 3 includes a substrate 310, a wafer 320, a plurality of wires 330, a sheet-like heat dissipation structure 340, and an adhesive 350. The substrate 310 has a top surface 312, and the top surface 312 is roughly divided into a wafer area 312a, a contact area 3 12b and a heat dissipation area 312c. The wafer area 31 2a is located, for example, in the central area of the substrate 3 1 . The dot area 31 2b is distributed around the wafer area 31 2a for arranging a plurality of contacts 3丨6a, and the sheet heat dissipation structure 340 has an opening 341 to expose the contact area 312b' and the heat dissipation area 3 12c is located The wafer area 3丨2a and the top surface 312 other than the contact area 312b, and a portion of the heat dissipation area 312c are located between the wafer area 3 12a and the contact area 3 12b. In addition, the wafer 32 is disposed on the wafer region 312a of the top surface 312 of the substrate 310, and the upper surface 322 of the wafer 320 has a plurality of pads 324, and the pads 324 are respectively connected to the contact regions by wires 330.

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The σ on the domain 312b, 4 01 Λ s occupies 31 6a. In addition, the sheet-like heat dissipation structure 340 is disposed on the heat dissipation region 312c of the base, and the sealant 350 is coated with the chip=the small and part of the sheet-shaped heat dissipation structure 340, and the bottom surface of the substrate 310, " 6b, which is electrically connected to the outside by a solder ball 3 8 (bal 1) (or a pin). 2 >" 4, which is a schematic view showing another crystal package structure of a first embodiment of the present invention. The chip package structure 30 0 includes a substrate 310, a die 320, a ridge wire “ο, a sheet heat dissipation structure 34Q, and a glue 35 〇. Further, a cover heat dissipation structure 342 is selectively disposed. The chip package structure 3'0' and the cap-shaped heat dissipation structure 342 covers the wafer 32〇 and the wire coffee, and the periphery of the heat dissipation structure 342 is connected to the sheet heat dissipation structure 34. The other 2 'sealing 350 is filled in The cover heat dissipation structure 342 and the space surrounded by the substrate 31, and the sealant 350 can cover a portion of the cover heat dissipation structure 342. As shown in Fig. 4, the chip package structure 3 is configured in a sheet shape. The heat dissipation structure 340 and the optional cover heat dissipation structure 342, and the material of the sheet heat dissipation structure 34 and the cover heat dissipation structure 342 can be metal materials with high thermal conductivity, such as aluminum, copper and alloys thereof. The heat dissipation effect of the chip heat dissipation structure 34 and the cover heat dissipation structure 342 is better than that of the sealant 350, so the heat generated by the wafer 310 can be generated by the sheet heat dissipation member 340 and the cover heat dissipation member 342. Thermal energy is rapidly conducted to the surface of the chip package structure 300. As shown in the figure, since the sheet-shaped heat dissipating structure 340 and the cap-shaped heat dissipating structure 342 are composed of a conductive material of an alloy such as aluminum or copper, the wafer 32 is disposed in the sheet-like heat dissipating structure 340 and the cap-shaped heat dissipating structure 342. In the space, the sheet heat dissipation structure 340 and the cover heat dissipation structure 342 will form a shield.

10229twf.ptd Page 9 1286831 V. INSTRUCTIONS (6) Function' is used to prevent external electromagnetic interference from being generated by the chip 300. Referring to FIGS. 3B and 4, the present invention can further configure a ground pad 315 on the top surface 312 of the substrate 3 10, which is located within the heat dissipation region 312c, and the periphery of the sheet heat dissipation structure 300 is correspondingly bonded to The bonding heat dissipation structure 340 and the cap-shaped heat dissipation structure 342 are electrically connected to the grounding of the chip package structure 300 (c 〇mm ο ngr 〇und) via the bonding pad 31 5 . To provide the shielding effect of the chip package structure 300. Referring to FIG. 5, a schematic diagram of still another wafer package structure according to a first embodiment of the present invention is shown. The chip package structure 3 includes a substrate 31, a die 320, a plurality of wires 330, a sheet-like heat dissipation structure 34, and a glue 350. The bottom surface of the chip heat dissipation structure 340 has a heat conducting plug 344, and the substrate 310 has a corresponding hole 311' so that the heat conducting plug 344 can penetrate the through hole 311 to reach the bottom surface 314 of the substrate 310, and the bottom surface of the substrate 31 314, for example, has a bottom trace pattern 316 that forms bond pads 316b and a bottom trace 316, and thermally conductive plugs 344 are coupled to bond pads 3161 via bottom traces 316c. Since the thermal plug 344 can transfer the wafer 32 to the thermal energy of the sheet-like heat dissipating structure 34, the upper surface 312 of the substrate 310 is transferred to the lower surface 314, and then the thermal energy is further conducted to the thermal conduction by the bottom line 3 16c and the bonding pad 3 16b. The solder ball 318 is finally transferred to the external environment by the heat conduction #球3 1 8 , and the chip package structure is increased. The efficiency of the government is such that the thermal energy of the wafer 3 2 不会 is not excessively concentrated on the wafer 3 2 〇上. A liquid crystal package structure, a schematic view of a second embodiment of the present invention. The chip package structure 400 includes a substrate 41, a wafer 42 0, an I dry bulb 430, a sheet heat dissipation structure 44, and a cap heat dissipation structure 442.

Page 10 1286831 V. Description of invention (7) and a glue 450. The wafer 42 is disposed on the top surface 412 of the substrate 410 by flip chip bonding, and the top surface 412 is roughly divided into a wafer region 41 2a and a heat dissipation region 412b, wherein the wafer region 4 12a is located, for example, in the center of the substrate 410. The region ' has a plurality of contacts 416a, and the heat dissipation regions 4 12b are located on the top surface 412 other than the wafer region 41 2a. In addition, the wafer 420 is disposed on the wafer region 4 1 2 a of the top surface 41 of the substrate 41 0 , and the lower surface 42 2 of the wafer 410 has, for example, a plurality of pads 424 , and the pads 424 are protruded by the bumps 424 . Block 426 is coupled to contact 414 of wafer region 412a, respectively, and underfill 428 is filled between wafer 420 and substrate 410' and overlies solder bumps 426. In addition, the bottom surface 414 of the substrate 4 10 further has a plurality of contacts 416b electrically connected to the outside by solder balls 430, respectively. Referring to FIG. 6, the chip heat dissipation structure 470 is disposed on the heat dissipation region 412c of the top surface 412 of the substrate 410, and the cover heat dissipation structure 442 and the sealant 450 are optional. On the sheet-like heat dissipation structure 440, the sealant 450 covers the wafer 420' and fills the space surrounded by the cover-shaped heat dissipation structure 424 and the substrate 410, and the sealant 450 is further covered. Cover heat dissipation structure 442. In this way, when the thermal energy generated by the wafer 42 is transmitted to the encapsulant 45 〇 and the substrate 41 ,, the thermal energy can be quickly transferred to the chip package structure 400 by the sheet heat dissipation structure 404 and the cap-shaped heat dissipating member 424. surface. Referring to FIG. 6 on the top surface 412 of the substrate 410, a ground pad 415 is disposed, which is also located in the heat dissipation region 412b, and the periphery of the sheet heat dissipation structure 44 is further joined to the ground pad 415. Thus, the wafer 420 is disposed in a shielded region surrounded by the sheet-like heat dissipation structure 408 and the cap-shaped heat dissipation structure 442 to achieve an electromagnetic interference prevention effect. . In summary, the chip package structure of the present invention has at least the following advantages:

1286831 V. INSTRUCTION OF THE INVENTION (8) 1 The wafer of the present invention is provided with a cap-shaped heat dissipating structure' sheet-like heat dissipating structure and a surface of a cap. 2. The effect of the magnetic structure of the wafer of the present invention on the thermal structure and the cover heat dissipation. Although the present invention has been limited to the present invention, in any of the familiar ranges, the patentable 10229 twf.ptd package structure can be configured to make the wafer in, rich & sheet heat dissipation structure and electrification The thermal energy generated during operation can be quickly transmitted to the w-package package structure by means of the member, by placing the structure around the stagnation/=?- In order to achieve anti-electricity - the preferred embodiment is disclosed above, and the person skilled in the art is obsessed with the art; the present invention is modified and retouched. Therefore, the scope of the invention is defined by the scope of the invention. /, ° vine range page 12 1286831 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional wafer bonding structure of a wire bonding type, and FIG. 2 is a schematic view showing a conventional chip bonding structure of a flip chip bonding type; 3A to 3B are a plan view and a cross-sectional view showing a chip package structure according to a first embodiment of the present invention, and FIG. 4 is a schematic view showing another chip package structure according to a first embodiment of the present invention; A schematic diagram of still another chip package structure according to a first embodiment of the present invention; and FIG. 6 is a schematic view showing a chip package structure according to a second embodiment of the present invention. Description of the figure: 1 0 0, 2 0 0, 3 0 0, 4 0 0 : chip package structure 1 1 0, 2 1 0, 3 1 0, 4 1 0 : substrate 112, 212, 312, 412: top Faces 114, 214, 314, 414: bottom faces 116a, 116b, 216a, 216b, 316a, 316b, 416a, 416b: contacts '1 18, 230, 430: solder balls 3 1 8 : thermally conductive solder balls 120, 2 2 0, 3 2 0 , 42 0 : wafers 122, 222, 322, 422: surface

10229twf.ptd Page 13 1286831 Brief description of the diagram 124, 224, 324, 424: pads 1 3 0, 3 3 0: wires 140, 35 0, 45 0: sealant 2 2 6 , 4 2 6 : bumps 240, 428: primer 3 1 1 : through holes 312a, 412a: wafer area 312b: contact area 312c, 412b: heat dissipation area 3 1 5, 4 1 5 : ground pad 3 1 6 : bottom line pattern 3 1 6 c : bottom line 340, 440: sheet heat dissipation structure 342, 442: cover heat dissipation structure 344: heat conduction plug

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Claims (1)

1286831 1 . A chip package structure comprising: a substrate having a top surface, wherein the top mask has a wafer area, a contact area and a heat dissipation area; a wafer | the wafer disposed on the top surface of the substrate a plurality of wires respectively connected to the top contact region of the wafer and the substrate; j @ a heat dissipation structure disposed on the top surface of the substrate; and a rubber coating The wafer, the wires and at least a portion of the sheet-like heat dissipation structure. The chip package structure of claim 1, wherein at least a portion of the far heat dissipation region is located between the wafer region and the joint region. 3. The chip package structure of claim 1, wherein the material of the chip heat dissipation structure is a conductive material, and the substrate further has at least one ground pad disposed on the top surface of the substrate, and The ground pad is located within the heat dissipation region and contacts the surface of the sheet heat dissipation structure. The wafer package structure of claim 1, wherein the substrate further has a bottom surface and at least one bonding pad, wherein the bottom surface of the substrate corresponds to the top surface of the substrate, and the bonding pad is Disposed on the bottom surface of the substrate, and the sheet heat dissipation structure further has at least one heat conducting plug extending from the surface of the sheet heat conductive structure and penetrating the substrate, and the bonding pad connected to the bottom surface of the substrate . 5. The chip package structure according to claim 4, wherein the 6-well substrate further has a bottom line pattern, which constitutes the bonding pad and a bottom line 10229twf.ptd 1286831 6. Patent application range, and the thermal plug is connected to the bonding pad via the bottom line. The chip package structure of claim 1, further comprising a cap-shaped heat dissipating structure that encloses the chip and the wires, and a periphery of the cap-shaped heat dissipating structure is connected to the chip heat dissipating structure, The sealant is filled in the space surrounded by the cover-shaped heat dissipation structure and the substrate. A chip package structure comprising: a substrate having a top surface, wherein the top mask has a wafer area and a heat dissipation area; and a wafer is disposed on the top surface of the substrate by flip chip bonding The wafer area is electrically connected to the substrate; and a planar heat dissipation structure is disposed on the heat dissipation area of the top surface of the substrate. 8. The wafer package structure of claim 7, further comprising a glue covering the wafer and at least a portion of the sheet heat dissipation structure. 9. The chip package structure of claim 7, wherein the material of the chip heat dissipation structure is a conductive material, and the substrate further has at least one grounding layer disposed on the top surface of the substrate, and The grounding raft is located within the heat dissipating region and contacts the surface of the sheet-like heat dissipating structure. 10. The wafer package structure of claim 7, wherein the substrate further has a bottom surface and at least one bonding pad, wherein the bottom surface of the substrate corresponds to the top surface of the substrate, and the bonding pad Disposed on the bottom surface of the substrate, and the sheet heat dissipation structure further has a thermal plug that extends from the surface of the sheet heat conductive structure and is connected to the bottom surface of the substrate. The bonding pad. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The tether is connected to the bond pad via the bottom line. 12. The chip package structure of claim 7, further comprising a cap-shaped heat dissipating structure and an adhesive covering the wafer, and a periphery of the cap-shaped heat dissipating structure is connected to the sheet-like heat dissipating structure, The sealant is filled in the space surrounded by the cover-shaped heat dissipation structure and the substrate. 13. The wafer package structure of claim 12, wherein the sealant further covers at least a portion of the cap-shaped heat dissipation structure. 10229twf.ptd Page 17