201001662 九、發明說明： 【發明所屬之技術領域】 種嵌埋 本發明係有關於-種電路板及其製法，尤指一 半導體元件之電路板及其製法。 【先前技術】 隨著電子產業的蓬勃發展，雷 一 x软电千產品亦朝輕、薄、短、 小、高集積度、多功能化方向笋屏。&v上、& _ J 士展為滿足半導體封裝件 局積集度（Integration)以及微型化⑻心㈣加 的封裝需求，半導體晶片之封I形逐漸由單—晶片之球拇 陣列（BGA)封裝或覆晶式（F1 ip Ghip，F(：)封裝演進到模组 化封裝形態，使得封裝結構有SIp(Systern Inte_ed201001662 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a circuit board and a method of manufacturing the same, and more particularly to a circuit board of a semiconductor element and a method of manufacturing the same. [Prior Art] With the rapid development of the electronics industry, Lei Yi x soft electric products are also light, thin, short, small, high accumulation, multi-functional direction. &v, & _ J show to meet the packaging requirements of semiconductor package integration and miniaturization (8) heart (four) plus packaging, semiconductor chip I shape gradually from the single-chip ball thumb array ( BGA) package or flip chip (F1 ip Ghip, F (:) package evolved into a modular package form, so that the package structure has SIp (Systern Inte_ed
Package)及 SiB(System in Board)等多種形式。 惟，该些模組化封裝形態係為覆晶技術（flip chip) 或打線技術（wire bonding)，而將單一半導體晶片電性連 接至封裝基板上，抑或使用表面黏貼技術（SMT)黏貼於基 板表面’惟该半導體晶片係設置於基板上，因而不利於模 組化結構尺寸之縮小及性能的提高。 為此’遂有業界提出將半導體元件埋入基板之製法； 請參閱第1A至1D圖所示之習知嵌埋半導體元件之基板之 製法示意圖。 如第1A圖所示’提供一第一承載板π ’於該第一承 載板11上接置有一第二承載板12，且該第二承載板12 具有相對之第一表面12a及第二表面12b，並於該第二承 載板12中形成至少一貫穿該第一表面12a及第二表面 5 110851 201001662 ‘ 12b之開π 120’使該第二承載板12之第二表自取接合 •於該第一承載板U上，並封住該第二承載板i 120 的一端。 * 如苐1B圖所示，提供一丰莫㈣ 杈仏牛蛉肢晶片13,該半導體晶 、 具有相對之作用面…及非作用自13b，於 .面…上具有複數電極塾131，且藉 ： 半導體晶片13之非竹围品杜 有日Μ將該 隹作用面13b接置於該第二承载板12 之開口⑽中的第—承載板u上。 載板Μ 13之作：所不，於該第二承載板12及半導體晶片 a上形成有介電層15,且該介電層15並填 ^弟一承載板12之開口 m與半導體晶片^之間的間 進該半導體晶片13固定於該開口㈣惟該 曰片心^熱壓時’因為壓力不均，易造成該半導體 3於該開σ 120中產生偏移差e。 且二所示’於該介電層15上形成有線路層16’ (接該；盲孔161，以電性連 電層時該半導體曰片=但由於熱壓形成該介 孔⑻連接㈣ 發生偏移差e，造成該導電盲 益法帝性遠I:極塾131之對位偏差，甚至因偏差過大而 …、忐电性連接該電極墊131。 於知，該半導體晶片13雖以該黏著層14接置Package) and SiB (System in Board) and other forms. However, the modular package forms are flip chip or wire bonding, and the single semiconductor wafer is electrically connected to the package substrate, or the surface mount technology (SMT) is adhered to the substrate. The surface 'only the semiconductor wafer is disposed on the substrate, which is disadvantageous for the size reduction of the modular structure and the improvement of performance. To this end, the industry has proposed a method of embedding a semiconductor element in a substrate; please refer to the schematic diagram of a conventional substrate for embedding a semiconductor element as shown in Figs. 1A to 1D. As shown in FIG. 1A, a first carrier plate π' is provided with a second carrier plate 12 on the first carrier plate 11, and the second carrier plate 12 has a first surface 12a and a second surface opposite to each other. 12b, and forming at least one opening π 120' extending through the first surface 12a and the second surface 5 110851 201001662 ' 12b in the second carrier 12 to self-pick the second surface of the second carrier 12 The first carrier U is mounted on the first carrier U. * As shown in Fig. 1B, a yak (4) yak limb wafer 13 is provided, the semiconductor crystal having a relative action surface... and a non-action surface 13b having a plurality of electrodes 塾131 on the surface : The non-bamboo product of the semiconductor wafer 13 has a crucible action surface 13b attached to the first carrier plate u in the opening (10) of the second carrier plate 12. The carrier layer 13 is formed: a dielectric layer 15 is formed on the second carrier 12 and the semiconductor wafer a, and the dielectric layer 15 is filled with the opening m of the carrier 12 and the semiconductor wafer. The intervening semiconductor wafer 13 is fixed to the opening (4). However, when the chip core is hot pressed, the semiconductor 3 is liable to cause an offset difference e in the opening σ 120 because of uneven pressure. And the second layer is formed on the dielectric layer 15 with a wiring layer 16' (connected thereto; the blind via 161, the semiconductor germanium when electrically connected to the layer = but the mesoporous (8) connection due to hot pressing (4) occurs The offset difference e causes the conductive blind method to be far away: the alignment deviation of the pole 131, even if the deviation is too large, and electrically connects the electrode pad 131. It is known that the semiconductor wafer 13 Adhesive layer 14 is attached
…/弟一承载板12之開口 U 形成該介電層15並填人該半導體7；= 12之 亍令體日日片13及弟一承載板 之間的間隙時，仍然會造成容置於該開口 110851 6 201001662 120 =的半導體晶片13產生偏移；目此，該半導體晶片 °亥開〇 12〇中產生偏移’導致該導電盲孔161連接 ，㈣極塾131之對位偏差，甚至因偏差過大而無法電性連 接》亥宅極墊131，進而影響電性連接之可靠度。 ' 〃 口此如何提出一種嵌埋半導體元件之電路板，以避 免:知之電路板嵌埋製程中，容置於核心板開口中的半導 體兀件產生偏移，實以成為目前業界亟待克服之課題。 【發明内容】 鑒於上述習知技術之種種缺失，本發明之主要目的在 於提供-種嵌埋半導體元件之電路板及其製法，能將半導 體晶片有效地固定於核心板開口中，以避免產生偏移。 為達上揭目的，本發明提供一種嵌埋半導體元 路板，係包括：核心板，係具有第一表面及相對應之第二 表面，且具有至少_貫穿該第一表面及該 ，開口；第一介電層，係形成於該核心板之第：表面玄： =介電層具有相對應該核心、板開口之介電層開Ί :該一介電層未接置該第二表面之表面 二有粗化面及非粗化面，並以該粗化面>1合 電層上’使該金屬層之粗化面顯露於該核心板 介電層開口：：： 覆設於該核心板開口及 黏著層上。""化面上，以及半導體晶片’係接置於該 依上述之嵌埋半導體元件之電 緣拓或且古括妨 攸β核心板係為絕 緣板戈具有線路之線路板；該金屬層係為鋼箱；該半導 110851 7 201001662 體晶片具有相對之作用而 -極墊，且該非作用面以心^面’於該作用面具有電 .㈣口 ^層接置於該核心㈣口及介電 依上述之結構，復包括於今、# 體晶片之作用面形成有辦声::構二乐一表面及半導 一咏入兩 風百θ層結構，該增層結構係包括至少 弟一；丨电層、設於該第二介電層上之 ^ 一 第二介電層中之導電盲孔，該導雨亡y ^及。又於竣 層與半導體晶片之電極墊，又二;：：：電性連接該線路 "M ; s層…構之最外層線路 ^結叙料層覆設有防辉 二 層亚具有複數開孔，以對應露出各該電性接觸 依上所述，該第：介電層並填人該半導體W與核心 板開口之間的間隙、以及該半導曰 的間隙中。 與介電層開口之間 本^明復提供-種截埋半導體元件之電路板製法，係 供-核心板，該核心板係具有第_表面及相對應 之第二表面，且具有至少一貫穿該第—表面及該第二表面 j心板開口’於該第二表面形成有第一介電層，且該第 -，丨電層具有介電層開口，以對應該核心板開口；於該第 ^層未接置該第二表面之表面上壓合_金屬層，該金 屬曰具有粗化面及非粗化面，並以該粗化面壓合於該第一 ^電層上’使該金屬層之粗化面顯露於該核心板開口及介 電層開口中；於該核心板開口及介電層開口中之粗化面 上形成有黏著層；以及於該黏著層上結合半導體晶片。 110851 8 201001662 依上述之嵌埋半導體开 為絕緣板或具有線路之線路板；m’該核心板係 半導體晶片具有相對之作用霉層知為鋼箔；該 有电極墊，且以非作用面接置於該黏著層上。- 依上述之製法，復包括於該核心板之第一表 體晶片之作用面形成有择屏ζ士雄 半導 m 該增層結構係包括至少 於該第二介電層中之導 电線路層、及形成 線路層與半導體晶片…“目孔並電性連接該 綠敗心二塾’又於該增層結構之最外声 形成有複數電性接觸墊，且於該增層結構之最外； ^有防㈣’於該防烊層中形成有複 出各該電性接觸墊。 ^對應路 依上所34，該第二介電層並填人該半導體 板開口之間的間隙、以及 的間隙中。 卞守販日日乃/、彡丨電層開口之間 按卜if明鼓埋半導體元件之電路板及其製法，係於具有 第人=口之核心板的第二表面形成具有介電層開口之 二=及金屬層，其中，該金屬層係以粗化面厂堅合於 二人J電層上’再將該半導體晶片之非作用面以黏著層 口於該粗化面上’俾藉由該粗化面以提高該半導體曰 /、金屬層之間的結合性，以避免該半導體晶 增層結構產生偏銘的叫B 设'、、只幵/成 Μ· 偏&的問題，進而使該增層結構之線路層中 、Β盲孔能準確電性連接該半導體晶片之電極塾， 免產生電性連接不良的情況，而能提高電性連接的可靠 110851 9 201001662 度。 【實施方式】 以下係藉由特定的具體實例說明本發明 只71又Λ施方 式’熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 = 請參閱第2Α至2F圖，係為本發明之嵌埋半導體元 之電路板及其製法實施例之剖面示意圖。 如第2Α圖所示，首先，提供一具有相對應之第—矛 面2〇a及第二表面20b之核心板2〇，該核心板2〇係為絕 緣板或具有線路之線路板，並具有至少一貫穿該第—夺心 2〇a及第二表面2〇b之核心板開口 2〇〇。 "如第2B圖所示’於該核心板2〇之第二表面2卟形成 有第-介電層21，且該第-介電層21具有相對應該核心 板開口 200之介電層開口 21〇。The opening U of the carrier board 12 forms the dielectric layer 15 and fills the semiconductor 7; the gap between the body day 13 and the carrier board is still caused by the gap The semiconductor wafer 13 of the opening 110851 6 201001662 120 = is offset; thus, the offset occurs in the semiconductor wafer, causing the conductive blind via 161 to be connected, (iv) the alignment deviation of the pole 131, and even Because the deviation is too large, it is impossible to electrically connect the "Hai House Pole 131", which affects the reliability of the electrical connection. How to propose a circuit board with embedded semiconductor components to avoid the problem that the semiconductor components contained in the opening of the core plate are offset during the embedded circuit board process, which is an urgent problem to be overcome in the industry. . SUMMARY OF THE INVENTION In view of the above-mentioned various deficiencies of the prior art, the main object of the present invention is to provide a circuit board embedded with a semiconductor element and a method of manufacturing the same, which can effectively fix a semiconductor wafer in an opening of a core board to avoid bias. shift. In order to achieve the above, the present invention provides an embedded semiconductor element road board, comprising: a core board having a first surface and a corresponding second surface, and having at least the first surface and the opening; The first dielectric layer is formed on the surface of the core board: the surface of the core layer: the dielectric layer has a dielectric layer opening corresponding to the core and the opening of the board: the surface of the second surface is not connected to the dielectric layer Second, there is a roughened surface and a non-roughened surface, and the roughened surface of the metallized layer is exposed on the roughened surface >1, and the roughened surface of the metal layer is exposed to the opening of the core layer of the core layer::: Plate opening and adhesive layer. ""Flat surface, and the semiconductor wafer 'connected to the electric edge of the above-mentioned buried semiconductor component or the ancient circuit block β core plate is an insulating board with a circuit board; the metal The layer is a steel box; the semiconductor wafer 110851 7 201001662 has a relative function and a pole pad, and the non-active surface has a power on the active surface. (4) a layer is placed on the core (four) port According to the above structure, the complex surface included in the working surface of the present invention is formed with a sound: a structure of a two-tone surface and a semi-conducting structure, and the structure of the layered structure includes at least a younger brother. a conductive layer, a conductive blind hole disposed in the second dielectric layer on the second dielectric layer, wherein the rain is y ^ and . And in the electrode layer of the germanium layer and the semiconductor wafer, and two;::: electrically connected to the line "M; s layer ... the outermost layer of the structure ^ knot layer is covered with anti-fade two layers of sub-multiple open The first dielectric layer fills the gap between the semiconductor W and the core plate opening and the gap between the semiconductor leads, as described above. Between the dielectric layer opening and the opening of the dielectric layer, the method for manufacturing a circuit board for burying a semiconductor component is a core-core board having a first surface and a corresponding second surface, and having at least one through The first surface and the second surface j-core opening ' are formed with a first dielectric layer on the second surface, and the first-electrode layer has a dielectric layer opening to correspond to the core plate opening; The second layer is not connected to the surface of the second surface, and the metal layer has a roughened surface and a non-roughened surface, and the roughened surface is pressed onto the first electrical layer to make a roughened surface of the metal layer is exposed in the opening of the core plate and the opening of the dielectric layer; an adhesive layer is formed on the roughened surface of the opening of the core plate and the opening of the dielectric layer; and the semiconductor wafer is bonded to the adhesive layer . 110851 8 201001662 According to the above embedded semiconductor as an insulating board or a circuit board having a line; m' the core board is a semiconductor wafer having a relative function as a steel foil; the electrode pad is provided with an inactive surface Placed on the adhesive layer. According to the above method, the active surface of the first body wafer included in the core board is formed with a selective screen gentleman semi-conducting m. The build-up structure includes at least a conductive line in the second dielectric layer. The layer, and the formation of the circuit layer and the semiconductor wafer, the "eye hole and the electrical connection of the green core" and the outermost sound of the layered structure are formed with a plurality of electrical contact pads, and the most Externally having an electrical contact pad formed in the anti-mite layer. ^ corresponding to the 34, the second dielectric layer filling the gap between the openings of the semiconductor board, and In the gap between the 卞 贩 乃 乃 乃 彡丨 彡丨 彡丨 彡丨 彡丨 彡丨 彡丨 彡丨 彡丨 彡丨 彡丨 彡丨 彡丨 彡丨 if if if if if if if if if if if if if if if if if if if if if if if if if if a second dielectric layer opening = and a metal layer, wherein the metal layer is adhered to the two-person J electric layer by a roughening surface factory, and the non-active surface of the semiconductor wafer is adhered to the roughened surface Upper '俾 by the roughened surface to improve the bonding between the semiconductor germanium/metal layer, The problem that the semiconductor crystal-enhanced layer structure is erroneously called B set ', 幵 Μ Μ Μ Μ 偏 偏 amp amp amp amp amp amp amp amp , , , , , , 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该The electrode 塾 of the wafer can avoid the occurrence of electrical connection failure, and can improve the reliability of the electrical connection 110851 9 201001662 degrees. [Embodiment] The following is a specific example to illustrate the invention. Other advantages and effects of the present invention can be easily understood by those skilled in the art. = Refer to Figures 2 to 2F, which are cross-sections of the embedded semiconductor device of the present invention and a method for fabricating the same As shown in Fig. 2, firstly, a core board 2 having a corresponding first spear surface 2a and a second surface 20b is provided, and the core board 2 is an insulating board or a circuit board having a line. And having at least one core plate opening 2 贯穿 extending through the first center 2 〇 a and the second surface 2 〇 b. " as shown in Fig. 2B 'on the second surface of the core plate 2 卟 2 卟Forming a first dielectric layer 21, and the first The dielectric layer 21 has a dielectric layer opening 21A corresponding to the core plate opening 200.
如第2C圖所示’於該第一介電層21未接置該第二表 面20b之表面上壓合一金屬層22,且該金屬層。具^粗 化面22a及非粗化面22b’並以該粗化面22a壓合於該第 -介電層21上，使該金屬層22之粗化面❿顯露於：核 心板開口 200及介電層開口 21〇中；其中，該金屬層u 係為銅箔（Copper foil)。 弟2D圖所不，於該核心板開口 2〇〇及介電層開口 210中之金屬| 22白勺粗化面22a上以黏著層μ結合 導體晶片24’該半導體晶片24具有一作用面24&及與其 目對應之非作用面24b，於該作用面他具有複數電極塾 110851 10 201001662 24卜 —如第2E圓所示，於該核心板2〇之第一表面 千導體晶片24之作用面叫形成有增層結構2 ^ 結構25係包括至少—第二介電層251、形成於該 電層251上之線路層252、及形成於該第二介 之導電盲孔253,該導電盲孔253並電性連接該線路= 中 與半導體晶片24之電極墊241，又於該增層結構μ曰之田 外層線路層252形成有電性接觸墊254，且於該 = 25之最外層覆設有防焊層W該防焊層26並形成 開孔260’以對應露出各該電性接觸墊254; ”二二 層251並填入該半導體晶片24與核心板開口 導體晶片24與介電層開口 21〇之間的間隙中 導體晶片24时於該核心板開σ 2⑽及介電層. 中。 本發明復提供-種嵌埋半導體元件之電路板，俜包 括.核心板20，係具有第一表面2〇a及相對應之 面20b’且具有至少一貫穿該第—表面2〇&及該 ^面 ;〇b:核心板開口 200;第一介電層2卜係形成於該核心 板20之弟二表面20b ’該第一介電，以有相對應該核 口 200之介電層開口 210;金屬層22，係壓合於該 第一，|電層21未接置該第二表面之表面上，該金屬 層=具有粗化面22a及非粗化面饥，並以該粗化面^ “於該第一介電層21上，使該金屬層22之粗化面22a 顯露於該核心板開口 200及介電層開口 2ι〇中黏著層 110851 11 201001662 23,係覆設於該核心板開口 200及介電層開口 2ι〇中之粗 .化面22&上；以及半導體晶片24，係接置於該黏著層23 上。 依上述欲埋半導體元件之電路板，該核心板2〇係為 絕緣板或具有線路之線路板；該金屬層22係為 半導體晶片24具有相對之作用面％及非作用面灿， 於該作用面24a具有電極㈣且以非作用自灿接置 於該粗化面22a上。 『、又依上述之結構，復包括黏著層23，係形成於該 導體晶片24之非作用面24b與粗化面22a之間。人 再依上述之結構，復包括於該核心板之第 2〇a及半導體晶片24之作用面如形成有增層結構… 該增層結構25係包括至少—第二介電層251、設於 二介電層251上之線路層252、及設於該第二介電 中之導電盲孔253，該導電盲別、，+ 曰 (之最外層線路層252具有電性接該增層結構25 ^ ΟΡ π电往接觸墊254，且於該增層社 f 25之最外層覆設有防焊層⑼，該防焊層26並 =孔260,以對應露出各該電性接觸墊脱第有= 電層25!並填入該半導體晶片24與核 ^ 的間隙、該半導體晶片24愈介+200之間 中。 力以與，丨電層開口 210之間的間隙 矣示上所述，本發明嵌 _ 、本，也认曰+ 队埋+ ¥體凡件之電路板及其製 彳.....肖心板開口之核心板的第二表面形成具有介 110851 12 201001662 電層開口之第一介電層及金屬 —化面壓合於該第一介 ：中3-屬層係以粗 ^电層上再將該半導體晶片之非作用 '囬以铂者層結合於該粗化面上， 半導體晶片與金屬層之間的結合性L。粗古面以提高該 於後續形成增層結構彦生偏移/乂避免°亥半導體晶片 之線路層中的導電盲減進而使該增層結構 uT罐電性連接該半導 电極墊，以避免產生電性連接 曰 連接的可靠度。 A的十月況’而能提高電性 上述實施例僅例示性說明本發明之 非用於限制本發明。任何孰習 ’、 /、1效，而 背本發明之精神及㈣下、、，：:員^ 變。因此，本發明之權利保護範圍了例進行修，與改 範圍所列。 ]保4乾固’應如後述之申請專利 【圖式簡單說明】 弟1A至1D®係為習知核心電路板 圖；以及 在又。丨〗面不意 第2A至2E圖係為本發明嵌埋半導體 其製法之剖面示意圖。 之电路板及 【主要元件符號說明】 11 第一承載板 12 第二承載板 120 開口 12a ' 20a 第一表面 12b、20b 第二表面 110851 13 201001662 13、24 半導體晶片 13a 、 24a 作用面 13b 、 24b 非作用面 131 、 241 電極墊 14、23 黏著層 15 介電層 16 、 252 線路層 161 > 253 導電盲孔 20 核心板 200 核心板開口 21 第一介電層 210 介電層開口 22 金屬層 22a 粗化面 22b 非粗化面 25 增層結構 251 第二介電層 254 電性接觸墊 26 防焊層 260 開孔 e 偏移差As shown in Fig. 2C, a metal layer 22 is bonded to the surface of the first dielectric layer 21 where the second surface 20b is not attached, and the metal layer is bonded. The roughened surface 22a and the non-roughened surface 22b' are pressed onto the first dielectric layer 21 by the roughened surface 22a, so that the roughened surface of the metal layer 22 is exposed to: the core plate opening 200 and The dielectric layer opening 21 is formed; wherein the metal layer u is a copper foil. 2D, the semiconductor wafer 24 has an active surface 24&urance on the metal plate opening 2〇〇 and the metal layer 22 in the dielectric layer opening 210 on the roughened surface 22a with the adhesive layer μ bonded to the conductor wafer 24'. And the non-acting surface 24b corresponding to the object, and having a plurality of electrodes 塾110851 10 201001662 24b on the active surface - as shown by the 2E circle, the active surface of the first surface of the core plate 2 The structure is formed by a build-up structure. The structure 25 includes at least a second dielectric layer 251, a circuit layer 252 formed on the electrical layer 251, and a conductive via 253 formed in the second via. 253 is electrically connected to the electrode pad 241 of the middle and the semiconductor wafer 24, and an electrical contact pad 254 is formed on the outer layer 252 of the build-up structure, and is disposed on the outermost layer of the = 25 a solder resist layer W and the opening 260' are formed to correspondingly expose the respective electrical contact pads 254; "two layers 251 and fill the semiconductor wafer 24 and the core board open conductor wafer 24 and the dielectric layer The conductor wafer 24 in the gap between the openings 21〇 is opened at the core plate by σ 2 (10) and The present invention provides a circuit board embedding a semiconductor component, comprising: a core plate 20 having a first surface 2a and a corresponding surface 20b' and having at least one through the first surface 2〇& and the surface; 〇b: core plate opening 200; the first dielectric layer 2 is formed on the second surface 20b of the core plate 20' the first dielectric to have a corresponding core port 200 The dielectric layer opening 210; the metal layer 22 is pressed against the first, the electrical layer 21 is not attached to the surface of the second surface, the metal layer = has a roughened surface 22a and a non-roughened surface hunger, And the roughened surface is formed on the first dielectric layer 21, and the roughened surface 22a of the metal layer 22 is exposed in the core plate opening 200 and the dielectric layer opening 2 ι 黏 in the adhesive layer 110851 11 201001662 23, The semiconductor wafer 24 is attached to the adhesive layer 23 and is disposed on the core plate opening 200 and the dielectric layer opening 2 ι. According to the circuit board for burying the semiconductor component, the core board 2 is an insulating board or a circuit board having a line; the metal layer 22 is such that the semiconductor wafer 24 has a relative active surface and a non-active surface. The face 24a has an electrode (4) and is placed on the roughened surface 22a in a non-acting manner. Further, according to the above configuration, the adhesive layer 23 is formed between the non-active surface 24b of the conductor wafer 24 and the roughened surface 22a. According to the above structure, the second surface of the core board and the active surface of the semiconductor wafer 24 are formed with a build-up structure. The build-up structure 25 includes at least a second dielectric layer 251. a wiring layer 252 on the second dielectric layer 251, and a conductive blind via 253 disposed in the second dielectric, the conductive blind, + 曰 (the outermost wiring layer 252 has electrical connection with the buildup structure 25 ΟΡ π is electrically connected to the contact pad 254, and the outermost layer of the build-up layer f 25 is covered with a solder resist layer (9), and the solder resist layer 26 is replaced by a hole 260 to correspondingly expose each of the electrical contact pads. = electric layer 25! and filled in the gap between the semiconductor wafer 24 and the core, and the semiconductor wafer 24 is between +200. The force is shown in the gap between the gate and the gate layer 210. Invented embedded _, this, also 曰 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ The first dielectric layer and the metallization surface are pressed into the first dielectric layer, and the 3-member layer is used to bond the semiconductor wafer to the non-active layer. The layer is bonded to the roughened surface, and the bond between the semiconductor wafer and the metal layer is L. The rough surface is increased in the circuit layer of the subsequently formed layered structure. The conductive blind reduction further electrically connects the build-up structure uT can to the semi-conductive electrode pad to avoid the reliability of the electrical connection connection. The A month condition of A can improve the electrical conductivity. The above embodiment is merely illustrative. It is to be understood that the present invention is not intended to limit the invention. Any of the simplifications of ', /, 1 effect, and the spirit of the present invention, and (4) the following, and the following: Repair, and change the scope listed.] Bao 4 dry solid ' should be patented as described later [simple description of the schema] Brother 1A to 1D® is a well-known core circuit board diagram; and in the 丨 面 不 不 第 2A 2E is a schematic cross-sectional view of a method for fabricating an embedded semiconductor according to the present invention. Circuit board and [large component symbol description] 11 first carrier 12 second carrier 120 opening 12a ' 20a first surface 12b, 20b second surface 110851 13 201001662 13,24 Semiconductor Wafer 13a, 24a active surface 13b, 24b non-active surface 131, 241 electrode pad 14, 23 adhesive layer 15 dielectric layer 16, 252 circuit layer 161 > 253 conductive blind hole 20 core plate 200 core plate opening 21 first dielectric Layer 210 dielectric layer opening 22 metal layer 22a roughened surface 22b non-roughened surface 25 build-up structure 251 second dielectric layer 254 electrical contact pad 26 solder resist layer 260 opening e offset difference