1269462 九、發明說明： 【發明所屬之技術領域】 本發明係有關於光電晶片之封裝技術，特別係有關於 一種光電晶片之多晶片增層封裝構造及其製造方法。 【先前技術】 光電晶片係應用於視訊電子產品，達到影像感測、影 像顯示、照明、光儲存、光輸出或光輸入等各種功能。由 於以往的光電晶片之封裝尺寸較大，因此會佔據視訊電子 產品之組裝空間，且其電性傳遞路徑亦相當長，容易有串 音效應（cross_talk effect)。 請參閱第1圖，一種習知影像感測器之光電晶片封裝 構造10 0係為卓晶片封裝型態，主要包含有一基板11 〇、 一光電晶片120、複數個銲線13〇以及一透光片140。該 基板11 0係具有一上表面111以及一下表面丨丨2，其包含 有電性導通該上表面111與該下表面n2之線路結構（圖未 繪出）’通常該基板11 〇係為多層印刷電路板。在該基板 110之該上表面111結合有一環壁113，以使該基板u〇 與環壁113構成一容晶穴114。該光電晶片12〇係為影像 感測晶片，其係以黏貼方式設置於該基板11〇之該上表面 111而位在該容晶穴Π4。在該光電晶片丨2〇之主動面係 开> 成有一感測區121以及複數個銲墊122。該些銲線130 係以打線形成於該容晶穴丨14内，其係電性連接該光電晶 片120之該些銲墊122與該基板11〇。該透光片140係設 置於該環牆113上，以氣閉密封該光電晶片120與該些銲 Γ269462 線130。在上述之光電晶片封裝構造！ 〇〇中，該光電晶片 12 0係藉由該些銲線13 0、該基板丨丨〇以電性傳導至一外 部電路板之數位信號處理器晶片（圖未繪出），其傳導路徑 較長而無法快速地進行影像處理且容易引發串音效應 (cross-talk effect) 〇 本國專利證書號數第M246808號「影像感測器之增層 t構」揭露，一影像感測器封裝構造係包含有一線路增層 結構，一影像感測晶片係容置於一載板之一晶穴内且其感 測區朝上，該線路增層結構係形成於該載板且在該影像感 測晶片上，由於該線路增層結構係形成於該影像感測晶片 之主動面與該載板之上，在增層封裝製程中容易污染至該 影像感測晶片之感測區，並且該線路增層結構必須具有一 窗口，該窗口係不可遮蓋至該感測區，因此該線路增層結 構内之導電線路配置受到限制，而無法密集化。此外，該 線路增層結構需預留該窗口導致製造成本增加。 【發明内容】 本發明之主要目的係在於提供一種光電晶片之多晶 片增層封裝構造及其製造方法，在一金屬載體之上方係依 續疊置有一積體電路晶片、一增層封裝結構以及一光電晶 片等，該增層封裝結構之複數個介電層係嵌埋該積體電路 晶片與該光電晶片，以該增層封裝結構之複數個線路層並 配合一透光導電基板以及複數個導電元件，使得嵌埋與該 些介電層中之該積體電路晶片與該光電晶片電性互連，其 係可以縮短晶片間電性傳導路徑，以加快光電作動速率。 Γ269462 此外，該增層封裝結構不會影響該光電晶片之一光電作動 區，並且該些線路層可以密集化，本發明係能薄化光電產 品並能增進被嵌埋積體電路晶片與光電晶片之間電性互 連與在封。藉以提昇組裝性、互連可靠度Gnterc〇nnecti〇n reliability)與電性效能、增加後續封裝密度以及降低串音 效應（cross-talk effect)。 本發明之次一目的係在於提供一種光電晶片之多晶 片增層封裝構造及其製造方法，該增層封裝結構之一介電 層係具有複數個導通孔，其係貫通至該金屬載體，以利該 增層封裝結構之該些線路層與該金屬載體之電性互連，其 可被應用於電源提供或是電源接地。較佳地，該金屬載體 係經圖案化而具有複數個連接墊，以供對外導接。 本發明之再一目的係在於提供一種光電晶片之多晶 片增層封裝構造及其製造方法，其中該金屬載體係經圖案 化而具有複數個連接墊以及一散熱片部，該散熱片部係可 供被嵌埋於該些介電層中之積體電路晶片貼附，以增進被 嵌埋積體電路晶片之散熱性。 依據本發明，一種光電晶片之多晶片增層封裝構造主 要包含一金屬載體、一積體電路晶片、一光電晶片及一增 層封裝結構之一第一介電層、一第二介電層、一第一線路 層、複數個導電元件以及一透光導電基板。該積體電路晶 片係設於該金屬載體上並具有複數個第一電極。該第一介 電層係形成於該金屬載體上，並覆蓋該積體電路晶片而顯 露該些第一電極。該第一線路層係形成於該第一介電層 1269462 上，並且電性連接至該些第一電極。該光電晶片係設於該 第一介電層之上方，並具有複數個第二電極以及一光電作 動區。該第一介電層係形成於該第一介電層之上方，以居 • 部覆蓋該光電晶片而顯露該些第二電極與該光電作動 區。该些導電元件係電性連接至該第一線路層並顯露於該 第二介電層之外。該透光導電基板係設置於該第二介電層 與該光電晶片之上，並以該透光導電基板之一導電線路層 • 電性連接該些導電元件與該些第二電極。藉以達到以增層 方式嵌埋之積體電路晶片與光電晶片電性互連。 【實施方式】 請參閱第2圖，一種光電晶片之多晶片增層封裝構造 2〇〇主要包含一金屬載體21〇_、一積體電路晶片22〇、一包 含至少二介電層與至少一線路層之增層封裝結構23〇、_ 光電晶片240、以及一透光導電基板25〇。在本實施例中， 該金屬載體2 1 0係為一銅箔並經圖案化，在圖案化之前， φ 該增層封裝結構230係形成於該金屬載體21〇上，該增層 封裝結構230係至少包含一第一介電層231、一第一線路 層232、一第二介電層233、複數個位於該第二介電層 導電元件234、一第三介電層235、一第二線路層236、 第四介電層237、以及-第三線路層238，其係以增層 方式形成於該金屬載體21〇上。其中，該第一介電層231、 該介電層233、該第三介電層235與該第四介電層237 等電層之材質係可為如PI & PET等電絕緣性物質。而 第線路層232、該第二線路層236、該第三線路層238 1269462 與該二導電7L件234之材質係可為銅或金等導電金屬 該積體電路晶片220係具有„主動面221以及一背 222並具有複數個形成於該主動δ 22i之第-電極如。 該積體電路晶片22〇係以一黏著層211黏設該背面$1269462 IX. Description of the Invention: [Technical Field] The present invention relates to a package technology for an optoelectronic wafer, and more particularly to a multi-wafer build-up package structure for an optoelectronic wafer and a method of fabricating the same. [Prior Art] Optoelectronic chips are used in video electronics to achieve various functions such as image sensing, image display, illumination, light storage, light output or light input. Due to the large package size of the conventional optoelectronic chip, it will occupy the assembly space of the video electronic product, and the electrical transmission path is also quite long, and it is easy to have a cross_talk effect. Referring to FIG. 1 , a photovoltaic chip package structure of a conventional image sensor is a wafer package type, and mainly includes a substrate 11 , an optoelectronic chip 120 , a plurality of bonding wires 13 , and a light transmission layer . Slice 140. The substrate 110 has an upper surface 111 and a lower surface 丨丨2, which includes a line structure (not shown) electrically conducting the upper surface 111 and the lower surface n2. Generally, the substrate 11 is multi-layered. A printed circuit board. A ring wall 113 is coupled to the upper surface 111 of the substrate 110 such that the substrate u and the ring wall 113 form a cavity 114. The photo-electric wafer 12 is an image sensing wafer which is disposed on the upper surface 111 of the substrate 11 in an adhesive manner to be positioned in the cavity 3. A sensing area 121 and a plurality of pads 122 are formed on the active surface of the photovoltaic chip. The bonding wires 130 are formed by wire bonding in the cavity 17 and electrically connected to the pads 122 of the photovoltaic chip 120 and the substrate 11 . The light-transmissive sheet 140 is disposed on the ring wall 113 to hermetically seal the photovoltaic wafer 120 and the wire 269462 lines 130. In the above optoelectronic chip package construction! In the middle, the optoelectronic chip 120 is electrically connected to the digital signal processor chip (not shown) of the external circuit board by the bonding wires 130, and the conduction path is compared. Long and unable to perform image processing quickly and easily lead to cross-talk effect 〇 National Patent Certificate No. M246808 "Additional Layer of Image Sensors", an image sensor package structure Included is a line build-up structure, an image sensing chip is housed in a cell of a carrier plate with a sensing area facing upward, and the line build-up structure is formed on the carrier and on the image sensing wafer Because the line build-up structure is formed on the active surface of the image sensing chip and the carrier, the sensing region of the image sensing chip is easily contaminated in the build-up packaging process, and the line build-up structure There must be a window that is not obscurable to the sensing area, so the conductive line configuration within the line build-up structure is limited and cannot be densified. In addition, the line build-up structure needs to reserve this window to cause an increase in manufacturing costs. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-wafer build-up package structure of an optoelectronic chip and a manufacturing method thereof, wherein an integrated circuit chip, a build-up package structure, and a build-up structure are stacked on top of a metal carrier. An optoelectronic chip or the like, the plurality of dielectric layers of the build-up package structure embed the integrated circuit chip and the optoelectronic chip, and the plurality of circuit layers of the build-up package structure are combined with a transparent conductive substrate and a plurality of The conductive component electrically interconnects the integrated circuit and the photovoltaic wafer in the dielectric layer, which can shorten the electrical conduction path between the wafers to accelerate the photoelectric operation rate. Γ 269462 In addition, the build-up package structure does not affect one of the optoelectronic chips, and the circuit layers can be dense. The present invention can thin the optoelectronic product and enhance the embedded circuit chip and the optoelectronic chip. Electrical interconnections are in between. In order to improve assembly, interconnect reliability and electrical performance, increase subsequent packaging density and reduce the cross-talk effect. A second object of the present invention is to provide a multi-wafer build-up package structure of a photovoltaic wafer and a method of fabricating the same, the dielectric layer of the build-up package having a plurality of via holes penetrating through the metal carrier to The circuit layers of the build-up package structure are electrically interconnected with the metal carrier, which can be applied to power supply or power supply ground. Preferably, the metal carrier is patterned to have a plurality of connection pads for external conduction. A further object of the present invention is to provide a multi-wafer build-up package structure for an optoelectronic chip and a method of fabricating the same, wherein the metal carrier is patterned to have a plurality of connection pads and a heat sink portion, and the heat sink portion can be The integrated circuit wafer embedded in the dielectric layers is attached to enhance heat dissipation of the embedded integrated circuit chip. According to the present invention, a multi-wafer build-up package structure of an optoelectronic chip mainly comprises a metal carrier, an integrated circuit chip, an optoelectronic chip and a first dielectric layer of a build-up package structure, a second dielectric layer, A first circuit layer, a plurality of conductive elements, and a light-transmissive conductive substrate. The integrated circuit wafer is mounted on the metal carrier and has a plurality of first electrodes. The first dielectric layer is formed on the metal carrier and covers the integrated circuit wafer to expose the first electrodes. The first circuit layer is formed on the first dielectric layer 1269462 and electrically connected to the first electrodes. The optoelectronic chip is disposed above the first dielectric layer and has a plurality of second electrodes and a photoelectric active region. The first dielectric layer is formed over the first dielectric layer to cover the optoelectronic wafer to expose the second electrodes and the opto-active region. The conductive elements are electrically connected to the first circuit layer and exposed outside the second dielectric layer. The transparent conductive substrate is disposed on the second dielectric layer and the optoelectronic wafer, and electrically connected to the conductive elements and the second electrodes. Thereby, the integrated circuit chip embedded in the build-up manner is electrically connected to the photovoltaic chip. [Embodiment] Referring to FIG. 2, a multi-wafer build-up package structure 2 of an optoelectronic chip mainly includes a metal carrier 21〇, an integrated circuit wafer 22, and at least two dielectric layers and at least one The build-up package structure of the circuit layer 23, the optoelectronic wafer 240, and a light-transmissive conductive substrate 25A. In this embodiment, the metal carrier 210 is a copper foil and is patterned. Before the patterning, the build-up package 230 is formed on the metal carrier 21, and the build-up package 230 is formed. The system includes at least a first dielectric layer 231, a first circuit layer 232, a second dielectric layer 233, a plurality of second dielectric layer conductive elements 234, a third dielectric layer 235, and a second The wiring layer 236, the fourth dielectric layer 237, and the - third wiring layer 238 are formed on the metal carrier 21A in a build-up manner. The material of the first dielectric layer 231, the dielectric layer 233, the third dielectric layer 235, and the fourth dielectric layer 237 may be an electrically insulating material such as PI & PET. The material of the second circuit layer 232, the second circuit layer 236, the third circuit layer 238 1269462 and the second conductive 7L 234 may be a conductive metal such as copper or gold. The integrated circuit wafer 220 has an active surface 221 And a back 222 having a plurality of first electrodes formed on the active δ 22i. The integrated circuit wafer 22 is adhered to the back surface by an adhesive layer 211.
該金屬載體加上。而該些第一電極223係可為凸塊或是 銲墊等。在本實施例中，該增層封裝結構23()之該第一介 電層23i係形成於該金屬載體21〇上，以覆蓋該積體電： 晶片220並顯露出該些第一電極223。該第一線路層如 係形成於該第-介電層231上，並且電性連接至該些第— 電極223該第—介電層23 1係高於該積體電路晶片 之該主動面221而覆蓋至該主動面221，以達到電性絕緣 之功效。在本實施例中，該第一線路層232係具有複數個 延伸至該積體電路晶片22〇上方之延伸線路232八，以增 加線路密集度。此外，該第一介電層23 1係具有複數個導 通孔23 1A，其係貫通至該金屬載體21〇，在該些導通孔 23 1A中係可形成有如電鍍層、金屬栓、導電樹脂等導電 物質232B，以電性連接該第一線路層232與該金屬載體 210，其可被應用於提供電源或是作為電源接地。 如第2圖所示，該光電晶片240係設於該第一介電層 23 1上方，其係可以一黏著層241將該光電晶片24〇黏設 於該第一介電層231上方。該光電晶片240係具有一主動 面242以及一背面243，在該主動面242上係形成有複數 個第二電極245以及一形成於該主動面242之光電作動區 244。較佳地，該光電晶片240係以位置垂直向的方式對 10 1269462 準於該積體電路晶片220，以縮小該光電晶片之多晶片增 層封裝構造200之表面覆蓋面積（f0〇tprint area)。 該第二介電層233係形成於該第一介電層231之上 方’並且局部覆蓋該光電晶片240而顯露該些第二電極245 與該光電作動區244，以達到局部嵌埋該光電晶片240之 功效。在本實施例中，該第二介電層233係覆蓋該光電晶 片240在該主動面242與該背面243之間之複數個側面。 齡此外’例如鍍通孔、金屬栓或金屬墊等之該些導電元件234 係電性連接至該第一線路層232並顯露於該第二介電層 2 3 3之外。 該透光導電基板250係設置於該第二介電層233與該 光電晶片240之上，其係具有一導電線路層251，以電性 連接該些導電元件234與該些第二電極245。在本實施例 中，該透光導電基板250係為一具有線路圖案之玻璃基 板’而該導電線路層251之材質係可為氧化錫銦（Indium | Tin Oxide，ITO)。較佳地，在該第二介電層233與該透光 導電基板250之間形成有一異方性導電層26〇，可為膜片 型態或粘膠型態並具有等粒徑之導電粒子，而該些第二電 極245係為凸塊’該些第二電極245與該些導電元件234 均突出於該第二介電層233，故能以熱壓合方式使該些第 電極245與該些導電元件234經由達到該異方性導電層 260縱向電性連接至該導電線路層251。 此外，在本實施例中，該增層封裝構造之該第一介電 層231與該第二介電層233間另形成有該第三介電層235 1269462 與該第四介電層237。該第三介電層235係形成於該第一 介電層23i與該第一線路層232上。該第二線路層2%係 形成於該第三介電層235上並經由該第三介電層235之開 孔而電性連接至該第一線路層232。同樣地，該第四介電 層237係形成於該第三介電層235與該第二線路層 上。該第二線路層23 8係形成於該第四介電層237上並經 由該第四介電層237之開孔而電性連接至該第二線路層 φ 236。如此，可以逐層往上形成介電層與線路層直到所需 的線路層數，該些導電元件234係能經由該第三線路層238 與該第二線路層236電性連接至該第一線路層232。而在 本實施例中，僅是以兩層介電層與兩層線路層例舉說明 之。 較佳i也’該積體電路晶片220係為數位訊號處理器晶 片（Digital Signal Processor，DSP)，而該光電晶片 240 係可 為 CMOS (Complementary Metal Oxide Semiconductor，互 • 補金屬氧化半導體）影像感測器晶片。藉由該增層封裝結構 230之該些線路層電性連接該光電晶片與該積體電路晶 片，以使該積體電路晶片220係能快速處理由該光電晶片 240接收的影像資訊。 因此，藉以上述形成於一金屬載體210上之增層封裝 結構2 3 0以及該透光導電基板2 5 0 ’能嵌埋該積體電路晶 片220與該光電晶片240並達到多晶片之間電路互連之功 效’使得由該光電晶片2 4 0接收之影像訊號能在極短電性 傳導路控下以該積體電路晶片2 2 0快速處理，故能降低串 12 1269462 音效應（cross-talk effect)。另，該增層封裝結構230之線 路層可以密集化設計’以薄化光電產品並能增進被嵌埋積 體電路晶片220與光電晶片240之電性互連與密封度。藉 以提昇組裝性、互連可靠度（interconnection reliability)與 電性效能、增加後續封裝密度，達到多晶片内部電性互連 之光電封裝。 此外，該圖案化金屬載體210係可圖案化而形成一散 . 熱片部212以及複數個連接墊213,並且該第一介電層231 具有一顯露表面。該散熱片部212係供該積體電路晶片22〇 之貼附，以增進對該積體電路晶片22〇之散熱效能與保護 性。該些連接墊213係經由該些導通孔231a内導電物質 232B電性連接至該第一線路層232,以供對外表面接合。 該光電晶片之多晶片增層封裝構造2〇〇可另包含有一鲜罩 層270，其係形成於該第一介電層231之該顯露表面，以 阻隔表面接合時銲料之不當橋接短路，且該銲罩層27〇至 > 少顯露該散熱片部212與該些連接墊213,該散熱片部212 與該些連接墊213具有一顯露表面。一如鎳_金材質之電鍍 層214可形成於該散熱片部212與該些連接墊213之該顯 露表面，以防止該散熱片部212與該些連接墊2丨3氧化。 關於該光電晶片之多晶片增層封裝構造2〇〇之製造方 法請參照第3A至3K圖。首先，請參閱第3人圖，提供該 金屬載體210,其中該金屬載體21〇係可為一完整片狀之 銅猪。將該積體電路晶片220貼附於該金屬載體21〇上。 之後，請參閱第3B圖，利用數位喷墨印刷（dighai比咖 13 1269462 或是鋼版印刷方式形成該第—介電# 屬載體210。其中以| 日231碲諄金 丹T以數位喷墨印刷方式 叫為較佳，可使MΉ該第一介電層 能控制該第-介=11達到各式圓案變化並 -介電層231::: 同區域的厚度差，例如該第 電層231在該積體電路晶片22〇 M 又该主動面221上的 旱又了較溥，而在該金屬載體2 於適當位置顯露該”一電極22二 厚 nQ,, 一笫電極223。此外可於同一步驟中 同％形成該些導通孔231a ~只賴鉻这些第一電極223，或 口在形成該第一介電層23 1之後，另以g \ 射鑽孔步驟形成該虺導通〜蝕” 、s X 一导逋孔231A，该些導通孔231A係貫 通至該金屬載體21〇〇 —^閱第3C® ’利用沉積或電鑛等技術將該 一線路層232形成於該第一介電層23ι上，該第一線路 ^ 232之-部分的線路係可連接至該些第—電極⑵，而 該第-線路層232之另-部分的線路係可經由該些導通孔 23^内之導電物質細連接至該金屬载體2…此外， 部分的延伸線路232A係可形成於該第一介電層231上並 位於該積體電路晶片22〇之上方。 …之後，請參閱第3D 0，將該第三介電層⑼形成於 忒第-介電層231與該第一缚路層232上，而露出該第一 友路層232之内連搂端。並請參閱第3E圖，將該第二線 路層J36係形成於該第三介電層235上並經由該第三介電 層235之開孔而電性連接至該第一線路層。之後，同 樣地，如第3F圖所示，將該第四介電層237係形成於該 14 1269462 第二”電層235與該第二線路層236上，再將該第三線路 層238係形成於該第四介電層237上並電性連接至該第二 線路層236。 之後’請參閱第3 G圖，運用黏晶技術將該光電晶片 240設於該第四介電層23 7上或是該第三線路層238上， 即該該光電晶片240係設於該第一介電層23 1之上方，此 時’該光電晶片240之複數個該些第二電極245與該光電 > 作動區244係為朝上。 之後’請參閱第3H圓，將該第二介電層233,形成於 該第三線路層23 8與該第四介電層237上，並局部覆蓋該 光電晶片240而顯露該些第二電極245與該光電作動區 244。 該第二介電層233大致與該光電晶片240為等高或 疋稍南於該光電晶片24p之主動面242，使該光電晶片240 為散埋型態。此外，並藉由在該第二介電層233内該些導 電元件234電性連接該第三線路層238，並且該些導電元 ► 件234係部分顯露於該第二介電層233之外。 之後’請參閱第31圖，利用熱壓合方式將該透光導電 基板250設置於該第二介電層233與該光電晶片24〇之 上’如第3J圖所示，該透光導電基板25〇之導電線路層 251係能電性連接該些導電元件234與該些第二電極 245。 本實施例在熱壓合步驟中，在該透光導電基板25〇 與該第二介電層233之間預形成有一異方性導電層260, 以達到在較低的熱壓合溫度下達到縱向導電路徑之形 成’故該光電晶片240可藉由該透光導電基板250、該異 15 1269462 方性導電層260、該些導電元件234、該第三線路層 該第二線路層236、該第一線路層232，能内部電曰性連接 至該積體電路晶片220。 較佳地，可以進一步圖案化該金屬載體21〇。請參閱 第3K圖，在該金屬載體21〇覆蓋一蝕刻遮罩31〇。在本 實施例中，㈣刻遮罩31G係為光阻材料，須經曝光顯影 方可形成圖案。經過一蝕刻步驟之後，以圖案化該金屬載 體210而形成該些連接墊213與該散熱片部212，並且使 侍该第一介電層23 1具有一顯露表面（如第2圖所示卜該 散熱片部212係供該積體電路晶片22()之貼附，而該些^ 接墊213係電性連接至該第一線路層232,進而電性連接 至該積體電路晶片220，以供對外表面接合β如第2圖所 示，該銲罩層270係可形成於該第一介電層231之該顯露 表面’並顯露該金屬載體21〇之該散熱片冑212與該些連 接墊213,該散熱片部212與該些連接墊213具有一顯露 表面。之後再形成一電鍍層214於該散熱片部212與該些 連接墊213之該顯露表面，以製成該光電晶片之多晶片增 層封裝構造200。 9 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 第1圖··習知影像感測器之光電晶片封裝構造之截 16 1269462 面不意圖。 第2 圖：依據本發明之一具體實施例，一種光電晶 片之多晶片增層封裝構造之截面示意圖。 第3A至3K圖：依據本發明之第一具體實施例，該光電晶 片之多晶片增層封裝構造於製程中之截 面示意圖。 【主要元件符號說明】 100 光電晶片封裝構造 110 基板 111 上表面 112 下表面 113 環牆 114 容晶穴 120 光電晶片 121 感測區 122 銲墊 130 銲線 140 透光片 200 光電晶片之多晶片增層封裝構造 210 金屬載體 211 黏著層 212 散熱片部 213 連接墊 214 電鍍層 220 積體電路晶片 221 主動面 222 背面 223 第一電極 23 0 增層封裝結構 231 第一介電層 23 1A 導通孔 232 第一線路層 232A 延伸線路 232B 導電物質 233 第二介電層 234 導電元件 235 第三介電層 236 第一線路層 237 第四介電層 238 第三線路層 240 光電晶片 241 黏著層’ 242 主動面 17 1269462 243 背面 244 光電作動區 245 第二電極 250 透光導電基板 251 導電線路層 260 異方性導電層 270 銲罩層 310 蝕’刻遮罩The metal carrier is added. The first electrodes 223 may be bumps or pads or the like. In this embodiment, the first dielectric layer 23i of the build-up package structure 23 is formed on the metal carrier 21 to cover the integrated body: the wafer 220 and the first electrodes 223 are exposed. . The first circuit layer is formed on the first dielectric layer 231 and electrically connected to the first electrode 223. The first dielectric layer 23 1 is higher than the active surface 221 of the integrated circuit chip. The active surface 221 is covered to achieve electrical insulation. In this embodiment, the first circuit layer 232 has a plurality of extension lines 232 extending above the integrated circuit wafer 22 to increase line density. In addition, the first dielectric layer 23 1 has a plurality of via holes 23 1A penetrating through the metal carrier 21 , and a plating layer, a metal plug, a conductive resin, etc. may be formed in the via holes 23 1A . The conductive material 232B is electrically connected to the first circuit layer 232 and the metal carrier 210, and can be applied to provide power or ground as a power source. As shown in FIG. 2, the optoelectronic wafer 240 is disposed above the first dielectric layer 23 1 , and the photo-electric wafer 24 is adhered to the first dielectric layer 231 by an adhesive layer 241 . The optoelectronic wafer 240 has an active surface 242 and a back surface 243. The active surface 242 is formed with a plurality of second electrodes 245 and a photoelectrically active region 244 formed on the active surface 242. Preferably, the optoelectronic chip 240 is aligned with the integrated circuit wafer 220 in a vertically oriented manner to reduce the surface coverage area (f0〇tprint area) of the multi-wafer build-up package structure 200 of the photovoltaic wafer. . The second dielectric layer 233 is formed over the first dielectric layer 231 and partially covers the optoelectronic wafer 240 to expose the second electrode 245 and the optoelectronic active region 244 to partially embed the optoelectronic wafer. 240 effect. In this embodiment, the second dielectric layer 233 covers a plurality of sides of the photo-electric wafer 240 between the active surface 242 and the back surface 243. The conductive elements 234, such as plated through holes, metal plugs or metal pads, are electrically connected to the first circuit layer 232 and exposed outside the second dielectric layer 233. The light-transmissive conductive substrate 250 is disposed on the second dielectric layer 233 and the photovoltaic wafer 240, and has a conductive circuit layer 251 electrically connected to the conductive elements 234 and the second electrodes 245. In the present embodiment, the light-transmitting conductive substrate 250 is a glass substrate having a line pattern, and the conductive circuit layer 251 is made of indium tin oxide (ITO). Preferably, an anisotropic conductive layer 26 is formed between the second dielectric layer 233 and the transparent conductive substrate 250, and may be a diaphragm type or a viscose type and has conductive particles of equal particle diameter. The second electrodes 245 are bumps. The second electrodes 245 and the conductive elements 234 protrude from the second dielectric layer 233, so that the first electrodes 245 can be thermally pressed. The conductive elements 234 are electrically connected to the conductive circuit layer 251 in a longitudinal direction via the anisotropic conductive layer 260. In addition, in the embodiment, the third dielectric layer 235 1269462 and the fourth dielectric layer 237 are formed between the first dielectric layer 231 and the second dielectric layer 233 of the build-up package structure. The third dielectric layer 235 is formed on the first dielectric layer 23i and the first wiring layer 232. The second circuit layer 2 is formed on the third dielectric layer 235 and electrically connected to the first circuit layer 232 via the opening of the third dielectric layer 235. Similarly, the fourth dielectric layer 237 is formed on the third dielectric layer 235 and the second wiring layer. The second circuit layer 238 is formed on the fourth dielectric layer 237 and electrically connected to the second circuit layer φ 236 via the opening of the fourth dielectric layer 237. In this manner, the dielectric layer and the wiring layer can be formed layer by layer up to the required number of circuit layers, and the conductive elements 234 can be electrically connected to the first circuit layer 236 via the third circuit layer 238 to the first Circuit layer 232. In the present embodiment, only two dielectric layers and two circuit layers are exemplified. Preferably, the integrated circuit chip 220 is a digital signal processor (DSP), and the photovoltaic chip 240 is a CMOS (Complementary Metal Oxide Semiconductor) image sense. Tester chip. The optoelectronic wafer and the integrated circuit wafer are electrically connected by the circuit layers of the build-up package structure 230, so that the integrated circuit wafer 220 can quickly process image information received by the optoelectronic wafer 240. Therefore, the build-up package structure 230 formed on the metal carrier 210 and the transparent conductive substrate 250' can embed the integrated circuit wafer 220 and the optoelectronic wafer 240 and reach the circuit between the multi-chips. The effect of the interconnection is such that the image signal received by the optoelectronic wafer 240 can be quickly processed by the integrated circuit chip 250 in a very short electrical conduction path, so that the string 12 1269462 sound effect can be reduced (cross- Talk effect). In addition, the wiring layer of the build-up package structure 230 can be densely designed to thin the optoelectronic product and improve the electrical interconnection and sealing degree between the embedded integrated circuit wafer 220 and the optoelectronic wafer 240. In order to improve assembly, interconnect reliability and electrical performance, and increase the subsequent packaging density, the photoelectric package of the internal interconnection of multiple wafers can be realized. In addition, the patterned metal carrier 210 can be patterned to form a heat sink portion 212 and a plurality of connection pads 213, and the first dielectric layer 231 has a exposed surface. The heat sink portion 212 is attached to the integrated circuit wafer 22 to improve the heat dissipation performance and protection of the integrated circuit wafer 22. The connection pads 213 are electrically connected to the first circuit layer 232 via the conductive substances 232B in the via holes 231a for bonding to the external surface. The multi-wafer build-up package structure 2 of the optoelectronic chip may further comprise a fresh cap layer 270 formed on the exposed surface of the first dielectric layer 231 to block improper soldering short-circuit of the solder when the surface is bonded, and The solder mask layer 27 〇 to > less exposes the heat sink portion 212 and the connection pads 213, and the heat sink portion 212 and the connection pads 213 have a exposed surface. An electroplated layer 214, such as a nickel-gold material, may be formed on the exposed surface of the fin portion 212 and the connection pads 213 to prevent oxidation of the fin portion 212 and the connection pads 2丨3. For the manufacturing method of the multi-wafer build-up package structure 2 of the photovoltaic wafer, please refer to Figs. 3A to 3K. First, referring to the figure of the third person, the metal carrier 210 is provided, wherein the metal carrier 21 can be a complete sheet of copper pig. The integrated circuit wafer 220 is attached to the metal carrier 21A. After that, please refer to FIG. 3B, using digital inkjet printing (dighai than coffee 13 1269462 or steel plate printing method to form the first-dielectric # genus carrier 210. Among them, 231 碲谆 碲谆 Jindan T in digital inkjet The printing method is preferably preferred, so that the first dielectric layer can control the first dielectric layer to reach a variety of round-state variations and the dielectric layer 231::: the difference in thickness of the same region, for example, the electrical layer 231, in the integrated circuit wafer 22〇M, the active surface 221 is further dry, and the metal carrier 2 exposes the “one electrode 22 and the second thickness nQ” at a suitable position. In the same step, the via holes 231a are formed in the same step, and only the first electrodes 223 are chrome-plated, or after the first dielectric layer 23 1 is formed, the germanium conduction is formed by a g laser drilling step. s X a guide hole 231A, the through holes 231A are penetrated to the metal carrier 21, and the third layer C2 is formed on the first layer by a technique such as deposition or electric ore. On the electrical layer 23, the line of the portion of the first line ^ 232 can be connected to the first electrode (2), and the first line The other portion of the circuit layer 232 may be thinly connected to the metal carrier 2 via the conductive material in the via holes 23... Further, a portion of the extension line 232A may be formed on the first dielectric layer 231. And being located above the integrated circuit wafer 22〇. After that, referring to FIG. 3D0, the third dielectric layer (9) is formed on the first dielectric layer 231 and the first binding layer 232 to be exposed. The first contact layer 232 is connected to the top end. Referring to FIG. 3E, the second circuit layer J36 is formed on the third dielectric layer 235 and is opened through the third dielectric layer 235. And electrically connected to the first circuit layer. Thereafter, as shown in FIG. 3F, the fourth dielectric layer 237 is formed on the 14 1269462 second "electric layer 235" and the second circuit layer 236. The third circuit layer 238 is formed on the fourth dielectric layer 237 and electrically connected to the second circuit layer 236. Then, please refer to FIG. 3G, using the die bonding technology to mount the photovoltaic chip. The photodiode 240 is disposed on the fourth dielectric layer 23 7 or the third circuit layer 238, that is, the optoelectronic chip 240 is disposed on the first dielectric layer 23 1 Above, at this time, the plurality of the second electrodes 245 and the photoelectric > actuation region 244 of the photovoltaic wafer 240 are upwards. Thereafter, please refer to the 3H circle, and the second dielectric layer 233 is formed on The second circuit layer 238 and the fourth dielectric layer 237 partially cover the optoelectronic wafer 240 to expose the second electrode 245 and the optoelectronic active region 244. The second dielectric layer 233 is substantially opposite to the optoelectronic device The wafer 240 is of the same height or 疋 slightly south than the active surface 242 of the photovoltaic wafer 24p, so that the photovoltaic wafer 240 is in a buried state. In addition, the third circuit layer 238 is electrically connected to the conductive elements 234 in the second dielectric layer 233, and the conductive elements 234 are partially exposed outside the second dielectric layer 233. . After that, please refer to FIG. 31, the transparent conductive substrate 250 is disposed on the second dielectric layer 233 and the photovoltaic wafer 24 by thermal compression bonding, as shown in FIG. 3J, the transparent conductive substrate The 25 导电 conductive layer 251 is electrically connected to the conductive elements 234 and the second electrodes 245. In the thermal compression bonding step, an anisotropic conductive layer 260 is pre-formed between the transparent conductive substrate 25A and the second dielectric layer 233 to achieve a lower thermal compression temperature. The formation of the longitudinal conductive path is such that the optoelectronic wafer 240 can pass through the transparent conductive substrate 250, the different 15 1269462 square conductive layer 260, the conductive elements 234, the third circuit layer, the second circuit layer 236, The first circuit layer 232 can be internally electrically connected to the integrated circuit wafer 220. Preferably, the metal carrier 21〇 can be further patterned. Referring to Figure 3K, the metal carrier 21 is covered with an etch mask 31. In the present embodiment, the (iv) mask 31G is a photoresist material which must be exposed to light to form a pattern. After an etching step, the metal carrier 210 is patterned to form the connection pads 213 and the heat sink portion 212, and the first dielectric layer 23 1 is provided with a exposed surface (as shown in FIG. 2). The heat sink portion 212 is attached to the integrated circuit wafer 22, and the pads 213 are electrically connected to the first circuit layer 232, and are electrically connected to the integrated circuit wafer 220. For the external surface bonding β, as shown in FIG. 2, the solder mask layer 270 can be formed on the exposed surface of the first dielectric layer 231 and expose the heat sink 212 and the metal carrier 21 The contact pad 213, the heat sink portion 212 and the connection pads 213 have a exposed surface, and then a plating layer 214 is formed on the exposed portion of the heat sink portion 212 and the connection pads 213 to form the photovoltaic wafer. Multi-wafer build-up package construction 200. 9 The scope of the invention is defined by the scope of the appended claims, and any changes made by those skilled in the art without departing from the spirit and scope of the invention And modifications are within the scope of protection of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a photovoltaic chip package structure of a conventional image sensor. FIG. 2 is a multi-wafer buildup layer of an optoelectronic wafer according to an embodiment of the present invention. FIG. 3A to FIG. 3K are diagrams showing a cross-sectional view of the multi-wafer build-up package structure of the photovoltaic wafer in the process according to the first embodiment of the present invention. [Major component symbol description] 100 Photovoltaic chip package structure 110 substrate 111 upper surface 112 lower surface 113 ring wall 114 cavity 120 optoelectronic chip 121 sensing area 122 pad 130 bonding wire 140 transparent sheet 200 multi-wafer build-up package structure of photovoltaic wafer 210 metal carrier 211 adhesive layer 212 heat dissipation Sheet portion 213 connection pad 214 plating layer 220 integrated circuit wafer 221 active surface 222 back surface 223 first electrode 23 0 build-up package structure 231 first dielectric layer 23 1A via hole 232 first circuit layer 232A extension line 232B conductive material 233 Second dielectric layer 234 conductive element 235 third dielectric layer 236 first circuit layer 237 fourth Electrical layer 238 Third circuit layer 240 Photovoltaic wafer 241 Adhesive layer '242 Active surface 17 1269462 243 Back surface 244 Photoelectric actuation area 245 Second electrode 250 Light-transmissive conductive substrate 251 Conductive circuit layer 260 Anisotropic conductive layer 270 Solder mask layer 310 Corrosion 'Engraved mask
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