201001656 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置，特別係有關於一 種多晶片並排於導線架上之半導體封裝構造。 【先前技術】 在傳統的半導體封裝構造中，導線架（1 e a d f r a m e )係 可作為晶片載體與電性轉接媒介，並以銲線作為内部電 性連接元件，而封膠體係用以密封晶片與銲線。以往的 多晶片半導體封裝構造内部晶片的設置方式可區分並 排（side by side)與晶片在晶片上的堆疊（stack)兩大類。 其中，並排方式是晶片個別黏貼在同一導線架上，適用 於受限的封裝厚度之條件下。然而，當晶片的厚度不同 時，在封膠體内厚度較厚的晶片會顯得擁擠，故會縮短 封膠體之頂面與較厚晶片之間的距離，使得封膠體在較 厚晶片之上下模封間隙的比值變大，進而導致填充封膠 體之上下層模流速度不一致，在模封時容易形成封膠氣 泡。此外，由於封膠體之頂面與此晶片之間的距離被縮 短，容易造成銲線外露於封膠體之外的問題，進而降低 多晶片並排於導線架上之半導體封裝構造之良率。此 外，封膠體在晶片上下部位的體積差異亦會造成半導體 封裝構造彎曲變形量過大的問題。 【發明内容】 有鑒於此，本發明之主要目的係在於提供一種多晶 片並排於導線架上之半導體封裝構造，利用導線架具有 5 201001656 不同沉置（downset)變化的黏晶區，以供並排設置不同厚 度之晶片，並改善模封時模流不平衡、銲線外露與半導 體封裝構造彎曲變形量過大之問題。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明所揭示之一種多晶片並排於導 線架上之半導體封裝構造，主要包含一導線架之複數個 引腳與一晶片承座、一第一晶片、一第二晶片以及一封 膠體。該晶片承座（die pad)係包含一第一黏晶區以及一 第二黏晶區，其中該第一黏晶區與該第二黏晶區係為水 平狀。該第一晶片係設置於該晶片承座之該第一黏晶區 上。該第二晶片係設置於該晶片承座之§亥弟·一黏晶區 上。該封膠體係密封該些引腳之内腳部、該晶片承座、 該第一晶片以及該第二晶片。其中，該第二晶片之厚度 係大於該第一晶片之厚度，並且該第二黏晶區相對於該 第一黏晶區更為沉置以使該第二黏晶區鄰近該封膠體 之一底面。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述多晶片並排於導線架上之半導體封裝構造 中，該第二黏晶區相對於該第一黏晶區之沉置深度可約 為該第二晶片與該第一晶片之厚度差值之二分之一。 在前述多晶片並排於導線架上之半導體封裝構造 中，該第二黏晶區係可為一次晶片承座（s u b - d i e p a d )。 在前述多晶片並排於導線架上之半導體封裝構造 6 201001656 中，該第一黏晶區係可相對於該些引腳之内腳部更為沉 置，但該第一黏晶區之沉置深度係小於該第二黏晶區之 沉置深度。 在前述多晶片並排於導線架上之半導體封裝構造 中，可另包含複數個第一銲線，電性連接該第一晶片至 該些引腳之内腳部。 在前述多晶片並排於導線架上之半導體封裝構造 中，可另包含複數個第二銲線，電性連接該第二晶片至 ί 4 該些引腳之内腳部。 本發明還揭示另一種多晶片並排於導線架上之半導 體封裝構造，主要包含：一導線架之複數個引腳、一第 一晶片、一第二晶片以及一封膠體。每一引腳係具有一 内腳部以及一外腳部，其中該内腳部係包含一第一水平 引腳部、一傾斜引腳部以及一第二水平引腳部，該傾斜 引腳部係連接該第一水平引腳部與該第二水平引腳 -- 部。該第一晶片係設置於該些内腳部之該些第一水平引 腳部上。該第二晶片係設置於該些内腳部之該些第二水 平引腳部上。該封膠體係密封該些内腳部、該第一晶片 以及該第二晶片，但顯露該些外腳部。其中，該第二晶 片之厚度係大於該第一晶片之厚度，並且該些第二水平 引腳部相對於該些第一水平引腳部更為沉置以使該些 第二水平引腳部鄰近該封膠體之一底面。 由以上技術方案可以看出，本發明之多晶片並排於 導線架上之半導體封裝構造及其製造方法，有以下優點 7 201001656 與功效： 一、 利用第二黏晶區相對於第一黏晶區更為沉置之設 計，能並排設置不同厚度之第一晶片與第二晶片， 而不會有模流不均勻而形成封膠氣泡以及因封膠 體在晶片上下部位的體積差異造成半導體封裝構 造彎曲變形之問題。 二、 利用黏晶區之多沉置配置，可降低較厚晶片的頂部 高度，因此可增加封膠體在較厚晶片上的厚度，藉 ' 此避免連接較厚晶片之銲線外露。 三、 利用多沉置黏晶區或引腳之連接方式，加強第二次 沉置（即第二黏晶區或第二水平引腳部）的支撐力， 以避免模流傾斜。 【實施方式】 依據本發明之第一具體實施例，一種多晶片並排於 導線架上之半導體封裝構造舉例說明於第1圖之在移 除某些元件後的上視圖與第2圖之沿著晶片承座及其連 接繫條（tie bar)剖切的截面示意圖。此外，第3圖為剖 切第一晶片的截面示意圖，第4圖為剖切第二晶片的截 面示意圖。該多晶片並排於導線架上之半導體封裝構造 1 00主要包含一導線架11 〇之複數個引腳11 1與一晶片 承座1 1 2、一第一晶片1 20、一第二晶片1 3 0以及一封 膠體140。其中，具有不同厚度之該第一晶片120與該 第二晶片130係以並排方式設置於該晶片承座112上。 請參閱第1圖所示’該些引腳111係分別排列在該 8 201001656 晶片承座1 1 2之側邊’並與該晶片承座1 1 2具有相同金 屬材質。並請參閱第3圖所示，該些引腳U丨係可具有 複數個内腳部1 1 5 ’位於該封膠體140内，以作為該第 曰曰片1 2 0與§亥第一晶片1 3 〇的内部電性連接。該此引 腳11 1係可具有複數個外腳部1 i 6，其係分別由該封膠 體1 40兩相應之側邊延伸而出，以供對外接合至—外部 印刷電路板（圖中未繪出）。該些外腳部丨丨6係可彎折成 海區I腳（gull lead)，或可彎折成其他形狀，如I形或】 形。 該aa片承座Π 2係包含一第一黏晶區丨丨3以及一第 黏bb區1 1 4，其中該第一黏晶區丨丨3與該第二黏晶區 系為水平狀但形成在不同沉置（d〇wnset)平面。請灸 閱第1及2圖所示，該晶片承座丨i 2更包含有複數個繫 條1 1 8與1 i 9，其係分別連接該晶片承座丨丨2之角隅。 忒些繫條1 1 8與】丨9與該晶片承座丨丨2係可為一體成 形’並具有適當的厚度以足以支撐該晶片承座112。 該第一晶片1 20係設置於該晶片承座11 2之該第一 黏晶區1 13上。在本實施例中，請參閱第3圖所示，該 第 a曰片1 2 0係具有一第一主動面1 2 1以及複數個形成 於該第—主動面121上之第一銲墊122。而該些第一銲 塾1 2 2係排列於該第一晶片丨2 〇之側邊，而部份之該些 引腳1 Π之該些内腳部1 1 5係往該些第一銲墊丨22延 伸。該多晶片並排於導線架上之半導體封裝構造丨〇〇係 可另包含有一第一黏晶膠1 23，其係形成於該第一晶片 9 201001656 1 20與該第一黏晶區1 1 3之間，以使該第一晶片1 20設 置於該晶片承座1 12上。請參閱第3圖所示，該多晶片 並排於導線架上之半導體封裝構造 1 00中可另包含複 數個第一銲線1 5 0，電性連接該第一晶片1 20之該些第 一銲墊1 2 2至該些引腳1 1 1之内腳部1 1 5。 該第二晶片1 3 0係設置於該晶片承座1 1 2之該第二 黏晶區1 14上。在本實施例中，請參閱第4圖所示，該 第二晶片1 3 0係具有一第二主動面1 3 1以及複數個形成 於該第二主動面131上之第二銲墊132。該些第二銲墊 1 3 2係排列於該第二晶片1 3 0之側邊，而部份之該些引 腳1 1 1之該些内腳部1 1 5係往該些第二銲墊1 3 2延伸。 該多晶片並排於導線架上之半導體封裝構造 1 00係可 另包含有一第二黏晶膠 13 3，其係形成於該第二晶片 1 3 0與該第二黏晶區1 1 4之間，以使該第二晶片1 3 0設 置於該晶片承座1 12上。請參閱第4圖所示，該多晶片 i； 並排於導線架上之半導體封裝構造100中可另包含複 數個第二銲線1 60，電性連接該第二晶片1 3 0之該些第 二銲墊1 3 2至該些引腳1 1 1之内腳部1 1 5。 該封膠體1 40係密封該些引腳1 11之内腳部1 1 5、該 晶片承座1 1 2、該第一晶片1 2 0以及該第二晶片1 3 0， 用以避免該第一晶片120、該第二晶片130受到外界污 染物侵入污染。通常該封膠體1 4 0係以壓模方式形成。 其中，該第二晶片130之厚度係大於該第一晶片120 之厚度，並且該第二黏晶區1 1 4相對於該第一黏晶區 10 201001656 1 1 3更為沉置以使該第二黏晶區1 1 4鄰近該封膠體1 40 之一底面1 4 1。請參閱第2圖所示，該第一黏晶區1 1 3 與該第二黏晶區1 1 4之間係形成有一沉置彎折1 1 7，以 使該第二黏晶區1 1 4相對於該第一黏晶區1 1 3更為沉 置。換言之，該第一黏晶區1 1 3至該封膠體1 40之該底 面1 4 1的距離係大於該第二黏晶區1 1 4至該封膠體1 40 之該底面1 4 1的距離。在本實施例中，該沉置彎折i 1 7 係為傾斜的狹長板狀。請參閱第2圖所示，由於該第二 黏晶區1 1 4更為沉置，該第二晶片1 3 0之該第二主動面 131只會略高於該第一晶片120之該第一主動面121， 以使該第一晶片1 20係大致位於該第二晶片1 3 0之一水 平中心線。 在本實施例中，請參閱第2圖所示，該第二黏晶區 1 1 4相對於該第一黏晶區1 1 3之沉置深度可約為該第二 晶片130與該第一晶片120之厚度差值之二分之一。更 ( 具體而言，請參閱第3圖所示，該第一黏晶區1 13係可 相對於該些引腳1 1 1之内腳部1 1 5更為沉置，但如第2 圖所示，該第一黏晶區11 3之沉置深度係小於該第二黏 晶區1 1 4之沉置深度。 進一步具體說明一種具體可行之不同沉置深度的形 成方法，如第1及2圖所示，該些繫條1 1 8係鄰近該第 一黏晶區11 3之外側邊角隅，並形成有兩（多）段沉置折 痕1 1 8 A，以使該第一黏晶區1 1 3為沉置配置；該些繫 條1 1 9係鄰近該第二黏晶區1 1 4之外側邊角隅，並形成 11 201001656 有兩（多）段沉置折痕11 9 A，以使該第二黏晶區1 置配置。其中，該些沉置折痕1 1 9 A係相對於該 痕1 1 8 A更鄰近該封膠體1 4 0之該底面1 4 1，以 第二黏晶區1 1 4相對於該第一黏晶區1 1 3更鄰近 14 1° 因此，藉由該第一黏晶區1 1 3與該第二黏晶 分別沉置在不同水平面之設計，可供並排設置不 之該第一晶片1 20與該第二晶片1 3 0，以減少由 晶片130至該頂面142與由該第二晶片130至 1 4 1之厚度差，使得該封膠體1 40在該第二晶片 厚晶片）之上下層模流速度概為相等，以改善模 流不均勻之問題，進一步避免形成封膠氣泡之缺 且，該封膠體1 40在該第二晶片1 3 0與該第一晶 之上下體積差異可以縮小，甚至相等，故在該 140的固化過程也就不會造成該半導體封裝構造 曲變形的問題。此外，由於該第二黏晶區11 4為 沉置之設計，可降低該第二晶片1 3 0的頂部高度 能增加由該第二晶片1 3 0至該封膠體1 40之該頂 之厚度，以提供更高的打線空間，藉此避免該些 線1 60外露於該封膠體1 40外，使得該多晶片並 線架上之半導體封裝構造100的良率更為提高。 第5圖係有關於本發明之第二具體實施例。 例之基本架構係大致與該第一具體實施例相同， 能的主要元件係以相同圖號表示之，例如包含該 ί4為沉 沉置折 達成該 該底面 區114 同厚度 該第二 該底面 130(較 封時模 陷。並 片120 封膠體 1*0 0 彎 第二次 ，因此 面142 第二銲 排於導 該實施 相同功 導線架 12 201001656 1 1 0之該些引腳1 1 1與該晶片承座 1 1 2、該第一晶片 12〇、該第二晶片130以及該封膠體140，不再資述。 該晶片承座1 1 2係包含該第一黏晶區1 1 3以及該第二黏 晶區1 1 4，其中該第一黏晶區1 1 3與該第二黏晶區1 1 4 係為水平狀但具有不同沉置深度，以供設置不同厚度之 晶片。在本實施例中，該第二黏晶區1 1 4係可為一次晶 片承座，也就是在已沉置的晶片承座1 1 2中再增設的小 型沉置晶片承座（如第5圖所示）。在該次晶片承座之邊 緣形成為複數個槽孔1 1 2 Α。該第二黏晶區1 1 4係具有 複數個内繫條1 1 4 A，其係連接該第二黏晶區1 1 4之角 隅至該晶片承座1 1 2，該些内繫條1 1 4 A係可沉置彎折 以使該第二黏晶區1 1 4相對於該第一黏晶區1 1 3更為沉 置。請再參閱第5圖所示，該些繫條1 1 8係連接該晶片 承座1 1 2之角隅。該些繫條1 1 8中形成兩（多）段沉置折 痕1 1 8 A，以使該第一黏晶區1 1 3為第一沉置，並利用 次晶片承座的方式’使得該苐二黏晶區1 1 4為更下沉的 第二沉置，並能加強第二次沉置（即第二黏晶區1 1 4)的 支撐力，以避免模流傾斜。 依據本發明之第三具體實施例中，另一種多晶片並 排於導線架上之半導體封裝構造舉例說明於第 6圖之 上視圖與第7圖之截面示意圖。此外，第8圖為剖切第 一晶片的截面示意圖，第9圖為剖切第二晶片的截面示 意圖。在本實施例中，該多晶片並排於導線架上之半導 體封裝構造 200係適用於晶片在引腳上（COL, Chip 13 201001656 -On- Lead)之封裝型態。其中，在此所指「晶 上」係指晶片的背面（即相對於晶片主動面之—在引腳 附於導線架的引腳，以達到在封裝過程中晶片之表面)貼 該多晶片並排於導線架上之半導體封裝構造固疋。 包含一導線架210之複數個引腳2U、— 〇主要 -第二晶…及一封勝體24〇。每—弟引：晶片咖、 七 引腳21 1係目 有—内腳部215以及一外腳部216，其中「 你具 r 為弓丨腳被封設在封膠體内的部位；「 内腳部」係 延伸在封膠體之外的部位。盆中，，广」係指引腳 甲该内腳部2 1 S及a 一:-水平引腳部⑴、-傾斜”腳部217以及含 =平引腳部214’該傾斜引腳部217係 k 引腳部213與該些第二水平弓丨 該弟一水平 係取自於同一導線架210,其;7214°該些引腳川 金屬材料，並具有適當厚产，遠、係可為鐵、鋼或其他BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor package structure in which a plurality of wafers are arranged side by side on a lead frame. [Prior Art] In a conventional semiconductor package structure, a lead frame (1 eadframe) can be used as a wafer carrier and an electrical transfer medium, and a bonding wire is used as an internal electrical connection component, and a sealing system is used to seal the wafer and Welding wire. In the conventional multi-wafer semiconductor package structure, the arrangement of the internal wafers can be divided into two categories: side by side and stack of wafers on the wafer. Among them, the side-by-side mode is that the wafers are individually adhered to the same lead frame and are suitable for a limited package thickness. However, when the thickness of the wafer is different, the thicker wafer in the sealant body will appear crowded, so the distance between the top surface of the sealant and the thicker wafer will be shortened, so that the sealant is molded over the thicker wafer. The ratio of the gap becomes large, which in turn leads to inconsistent mold flow velocity above the filling sealant, and it is easy to form sealant bubbles during molding. In addition, since the distance between the top surface of the encapsulant and the wafer is shortened, the problem that the bonding wire is exposed outside the encapsulant is liable to occur, thereby reducing the yield of the semiconductor package structure in which the multi-wafer is placed on the lead frame. In addition, the difference in the volume of the sealant between the upper and lower portions of the wafer also causes a problem that the amount of bending deformation of the semiconductor package structure is excessive. SUMMARY OF THE INVENTION In view of the above, the main object of the present invention is to provide a semiconductor package structure in which a plurality of wafers are arranged side by side on a lead frame, and the die holder has a die-forming area with 5 201001656 different downset changes for side by side. The wafers of different thicknesses are set, and the problem of unbalanced mold flow, exposed wire bonding, and excessive bending deformation of the semiconductor package structure is improved. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. A semiconductor package structure in which a plurality of wafers are arranged side by side on a lead frame according to the present invention mainly comprises a plurality of leads of a lead frame and a wafer holder, a first wafer, a second wafer, and a colloid. The die pad includes a first die bond region and a second die bond region, wherein the first die bond region and the second die bond region are horizontal. The first wafer is disposed on the first die attach region of the wafer holder. The second wafer is disposed on the sigma-polycrystalline region of the wafer holder. The encapsulation system seals the inner leg of the pins, the wafer holder, the first wafer, and the second wafer. Wherein the thickness of the second wafer is greater than the thickness of the first wafer, and the second die attaching region is further disposed relative to the first die attach region such that the second die attach region is adjacent to the sealant. Bottom surface. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the semiconductor package structure in which the plurality of wafers are arranged side by side on the lead frame, the depth of the second die attach region relative to the first die attach region may be greater than the thickness difference between the second die and the first die. Half. In the semiconductor package structure in which the plurality of wafers are side by side on the lead frame, the second die bonding region may be a primary wafer holder (s u b - d i e p a d ). In the semiconductor package structure 6 201001656 in which the plurality of wafers are juxtaposed on the lead frame, the first die bonding region can be more disposed relative to the inner leg portions of the pins, but the first die bonding region is disposed. The depth system is smaller than the depth of the second die attach region. In the semiconductor package structure in which the plurality of wafers are arranged side by side on the lead frame, a plurality of first bonding wires may be further included to electrically connect the first chip to the inner leg portions of the pins. In the semiconductor package structure in which the plurality of wafers are arranged side by side on the lead frame, a plurality of second bonding wires may be further included to electrically connect the second chip to the inner leg of the pins. The present invention also discloses another semiconductor package structure in which a plurality of wafers are arranged side by side on a lead frame, and mainly comprises: a plurality of leads of a lead frame, a first wafer, a second wafer, and a gel. Each of the pins has an inner leg portion and an outer leg portion, wherein the inner leg portion includes a first horizontal pin portion, an inclined pin portion, and a second horizontal pin portion, and the inclined pin portion The first horizontal pin portion and the second horizontal pin portion are connected. The first wafer is disposed on the first horizontal leg portions of the inner leg portions. The second wafer is disposed on the second horizontal lead portions of the inner leg portions. The encapsulation system seals the inner leg portion, the first wafer, and the second wafer, but exposes the outer leg portions. Wherein the thickness of the second wafer is greater than the thickness of the first wafer, and the second horizontal lead portions are further recessed relative to the first horizontal lead portions to make the second horizontal lead portions Adjacent to a bottom surface of the sealant. It can be seen from the above technical solution that the semiconductor package structure and the manufacturing method thereof for the multi-wafer side by side on the lead frame have the following advantages: 7 201001656 and efficacy: 1. Using the second die bonding region relative to the first die bonding region The more recessed design enables the first wafer and the second wafer of different thickness to be arranged side by side without uneven mold flow to form the sealing bubble and the semiconductor package structure is bent due to the difference in volume between the upper and lower parts of the wafer. The problem of deformation. Second, the use of the multi-pitched configuration of the die-bonding region can reduce the top height of the thicker wafer, thereby increasing the thickness of the encapsulant on the thicker wafer, thereby avoiding the exposure of the bonding wires connecting the thicker wafers. 3. The support force of the second sinking (ie, the second die-bonding region or the second horizontal pin portion) is strengthened by using a plurality of deposited crystal regions or pin connections to avoid mold flow tilt. [Embodiment] According to a first embodiment of the present invention, a semiconductor package structure in which a plurality of wafers are arranged side by side on a lead frame is illustrated in the first view of FIG. 1 after removing certain components and along the second figure. A cross-sectional view of the wafer holder and its tie bar. Further, Fig. 3 is a schematic cross-sectional view showing the first wafer, and Fig. 4 is a cross-sectional view showing the second wafer. The semiconductor package structure 100 of the multi-chip side by side on the lead frame mainly comprises a plurality of leads 11 1 of a lead frame 11 and a wafer holder 1 1 2, a first wafer 1 20, and a second wafer 1 3 0 and a colloid 140. The first wafer 120 and the second wafer 130 having different thicknesses are disposed side by side on the wafer holder 112. Referring to Fig. 1, the pins 111 are respectively arranged on the side of the 8 201001656 wafer holder 1 1 2 and have the same metal material as the wafer holder 1 1 2 . As shown in FIG. 3, the pins U can have a plurality of inner legs 1 1 5 ' located in the encapsulant 140 as the first wafer 1 2 0 and the first wafer 1 3 〇 internal electrical connection. The pin 11 1 can have a plurality of outer leg portions 1 i 6 extending from the respective side edges of the encapsulant 140 for external bonding to the external printed circuit board (not shown) Draw). The outer leg portions 6 can be bent into a gull lead or can be bent into other shapes, such as an I shape or a shape. The aa piece bearing Π 2 system comprises a first viscous zone 丨丨3 and a first viscous bb zone 141, wherein the first viscous zone 丨丨3 and the second viscous zone are horizontal but Formed in different sinking (d〇wnset) planes. As shown in Figures 1 and 2, the wafer holder 丨i 2 further includes a plurality of ties 1 18 and 1 i 9 which are respectively connected to the corners of the wafer holder 丨丨 2 . The tie bars 1 18 and 丨 9 and the wafer holder 2 can be integrally formed and have a suitable thickness to support the wafer holder 112. The first wafer 120 is disposed on the first die attach region 1 13 of the wafer holder 11 2 . In this embodiment, as shown in FIG. 3 , the first a die 120 has a first active surface 1 2 1 and a plurality of first pads 122 formed on the first active surface 121 . . The first solder fillets 1 2 2 are arranged on the side of the first wafer 丨 2 ,, and some of the inner legs 1 1 5 of the pins 1 系 are connected to the first solders The mattress 22 extends. The semiconductor package structure of the multi-wafer side by side on the lead frame may further comprise a first adhesive paste 1 23 formed on the first wafer 9 201001656 1 20 and the first die bonding region 1 1 3 Between the first wafers 120 is disposed on the wafer holders 1 12 . As shown in FIG. 3, the plurality of first package wires 150 may be further included in the semiconductor package structure 100 of the multi-chip side-by-side of the lead frame, and the first ones of the first wafers 120 are electrically connected. Pad 1 2 2 to the foot 1 1 5 of the pins 1 1 1 . The second wafer 130 is disposed on the second die attach region 1 14 of the wafer holder 112. In this embodiment, as shown in FIG. 4, the second wafer 1300 has a second active surface 133 and a plurality of second pads 132 formed on the second active surface 131. The second pads 1 3 2 are arranged on the side of the second wafer 130, and some of the inner legs 1 1 5 of the pins 1 1 1 are connected to the second pads. Pad 1 3 2 extends. The semiconductor package structure 100 of the multi-chip side by side on the lead frame may further comprise a second adhesive layer 13 3 formed between the second wafer 130 and the second die bonding region 1 1 4 The second wafer 130 is disposed on the wafer holder 1 12 . Referring to FIG. 4, the multi-chip i; the semiconductor package structure 100 arranged side by side on the lead frame may further include a plurality of second bonding wires 160, electrically connecting the second wafers 130 Two pads 1 3 2 to the legs 1 1 5 of the pins 1 1 1 . The encapsulant 110 seals the leg portion 1 1 5 of the pins 1 11 , the wafer holder 1 1 2, the first wafer 1 2 0 and the second wafer 1 3 0 to avoid the first A wafer 120 and the second wafer 130 are contaminated by external contaminants. Usually, the encapsulant 140 is formed by compression molding. The thickness of the second wafer 130 is greater than the thickness of the first wafer 120, and the second die-bonding region 112 is more placed relative to the first die-bonding region 10 201001656 1 1 3 to make the first The two-bonded crystal region 1 1 4 is adjacent to a bottom surface 1 4 1 of the sealant 1 40. Referring to FIG. 2, between the first die-bonding region 1 1 3 and the second die-bonding region 1 14 4, a sinking bend 1 17 is formed to make the second die-bonding region 1 1 4 is more placed relative to the first die-bonding region 1 1 3 . In other words, the distance from the first die attach region 1 1 3 to the bottom face 141 of the sealant 1400 is greater than the distance from the second die attach region 1 14 to the bottom face 148 of the sealant 140 . In the present embodiment, the sinking bend i 1 7 is an elongated elongated plate shape. Referring to FIG. 2, since the second die-bonding region 112 is more placed, the second active surface 131 of the second wafer 130 is only slightly higher than the first wafer 120. An active surface 121 is disposed such that the first wafer 120 is substantially at a horizontal centerline of the second wafer 110. In this embodiment, as shown in FIG. 2, the depth of the second die attach region 141 relative to the first die attach region 141 may be about the second die 130 and the first One-half of the difference in thickness of the wafer 120. More specifically, please refer to FIG. 3, the first die region 1 13 can be more placed relative to the inner leg 1 1 5 of the pins 1 1 1 , but as shown in FIG. 2 The depth of the first die-bonding region 11 3 is smaller than the depth of the second die-bonding region 112. Further, a specific method for forming different depths of the sinking depth, such as the first and 2, the tie bars 1 18 are adjacent to the outer corner corners of the first die-bonding region 11 3 and are formed with two (multiple) segments of the creases 1 18 A to make the first A die-bonding zone 1 1 3 is a sinking configuration; the tie bars 1 1 9 are adjacent to the outer edge corners of the second die-bonding zone 1 1 4 and form 11 201001656 with two (multiple) sections of the sinking fold Marking 11 9 A to arrange the second die-bonding region 1 , wherein the deposited creases 1 1 9 A are closer to the bottom surface 1 of the sealant 1 4 0 relative to the mark 1 18 A 4, the second viscous region 1 1 4 is closer to 14 1° than the first viscous region 1 1 3 , and therefore, the first viscous region 1 1 3 and the second viscous crystal are respectively deposited Designed in different horizontal planes, the first crystal can be set side by side. The film 1 20 and the second wafer 130 are used to reduce the difference in thickness between the wafer 130 to the top surface 142 and the second wafer 130 to 14 1 such that the encapsulant 140 is on the second wafer thick wafer. The upper and lower mold flow velocities are equal to improve the problem of mold flow non-uniformity, further avoiding the formation of sealant bubbles, and the sealant 140 is above the second wafer 1300 and the first crystal. The difference in volume can be reduced or even equal, so that the curing process of the 140 does not cause a problem of distortion of the structure of the semiconductor package. In addition, since the second die-bonding region 11 is a sinking design, the top height of the second wafer 130 can be increased to increase the thickness of the top of the second wafer 130 to the sealant 140. In order to provide a higher wire-bonding space, the wires 1 60 are prevented from being exposed outside the sealing body 140, so that the yield of the semiconductor package structure 100 on the multi-chip splicing frame is further improved. Figure 5 is a second embodiment of the invention. The basic structure of the example is substantially the same as that of the first embodiment, and the main components of the energy are represented by the same figure, for example, including the ί4 for the sinking to achieve the bottom surface area 114 and the thickness of the second bottom surface 130 ( When the seal is sealed, the die 120 seals the 1*0 0 bend for the second time, so the face 142 is soldered to the pins 1 1 1 of the same work lead frame 12 201001656 1 1 0 The wafer holder 1 1 2, the first wafer 12, the second wafer 130, and the encapsulant 140 are not described. The wafer holder 112 includes the first die region 1 1 3 and the a second die-bonding region 1 1 4, wherein the first die-bonding region 1 1 3 and the second die-bonding region 1 1 4 are horizontal but have different depths of deposition for providing different thicknesses of the wafer. In an embodiment, the second die attach region 1 14 can be a primary wafer holder, that is, a small sink wafer holder that is further added to the deposited wafer holder 112 (as shown in FIG. 5). a plurality of slots 1 1 2 Α are formed at the edge of the wafer carrier. The second die bond region 1 1 4 has a plurality of a strip 1 1 4 A, which is connected to the corner of the second die-bonding region 1 1 4 to the wafer holder 1 1 2, and the inner tie strips 1 1 4 A can be placed and bent to make the second The die-bonding region 1 14 is more placed relative to the first die-bonding region 1 1 3 . Please refer to FIG. 5 again, the tie bars 1 18 are connected to the corner of the wafer holder 1 1 2 Two (multiple) segments of the creases 1 18 A are formed in the strips 1 18 to make the first die region 1 1 3 be the first sink and use the sub-wafer socket' The bismuth crystal region 11 14 is made to be a sinking second sink, and the supporting force of the second sinking (ie, the second viscous region 1 14) can be strengthened to avoid the mold flow tilt. In a third embodiment of the present invention, another semiconductor package structure in which a plurality of multi-wafers are arranged side by side on a lead frame is illustrated in a cross-sectional view of the upper view and the seventh view of Fig. 6. In addition, Fig. 8 is a cutaway first A schematic cross-sectional view of the wafer, and a cross-sectional view of the second wafer cut away from Fig. 9. In the present embodiment, the semiconductor package structure 200 in which the multi-chip is placed side by side on the lead frame is suitable for the wafer on the lead (COL, Chip 13 201001656 - On-Lead package type. Here, "on-chip" refers to the back side of the wafer (ie, relative to the active side of the wafer - attached to the lead of the lead frame at the pin). The surface of the wafer during the packaging process is fixed to the semiconductor package structure of the multi-chip and arranged on the lead frame. A plurality of pins 2U including a lead frame 210, - 〇 main - second crystal ... and a winning body 24 — 每 每 每 每 每 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片The inner leg portion extends beyond the sealant. In the basin, the wide" refers to the pin A. The inner leg 2 1 S and a one: - the horizontal pin portion (1), the - inclined "foot portion 217" and the = flat pin portion 214' the inclined pin portion 217 The k-pin portion 213 and the second horizontal bows are taken from the same lead frame 210, and the 7214° pin-shaped metal material has a suitable thick product, and the far-reaching system can be iron. , steel or other
4到足以承載嗜筮B 220與該第二晶片230的結構载μ第-晶片 在* & 里度。請參閱第811郎·- 在本實施例中，該第—水平引卿 圖所不， 腳之外腳部216。如第6圖所示…’、可連接相對引 封膠體240之兩相對側邊往该些引腳211係由該 並弯折往該第二晶片23。之方；伸至該第-…2。， ^ Ν雙伸。 該第一晶片220係設置於該此 一水平引腳部213上。請參閱第：内腳215之該些第 220係具有-第-主動面221及、，所不’該第-晶片 該也第俨執2 ? ? 货數個第一銲墊2 2 2。 〜“塾222係可排列於讀第一 邊。該第一晶片220係利用_ 221之側 弟〜黏晶膠223之黏貼而 14 201001656 設置於該些第一水平引腳部2 1 3。 該第二晶片2 3 0係設置於該些内腳部2 1 5之 二水平引腳部214上。請參閱第9圖所示，該第 230係具有一第二主動面231及複數個第二銲墊 該些第二銲墊232係排列於該第二主動面23 1 邊。該第二晶片2 3 0係利用一第二黏晶膠2 3 3之 設置於該些第二水平引腳部2 1 4。 更具體而言，請參閱第7圖所示，該内腳部 可更包含一接指2 1 8，係連接該第二水平引腳部 可與該第一水平引腳部2 1 3大致為共平面配置， 短銲線長度。請參閱第8圖所示，該多晶片並排 架上之半導體封裝構造200可另包含複數個第 250，電性連接該第一晶片220之該些第一銲墊 該些引腳2 1 1之該些第一水平引腳部2 1 3。請參 圖所示，該多晶片並排於導線架上之半導體封 200可另包含複數個第二銲線260，電性連接該 片230之該些第二銲墊232至該些引腳211之接 該封膠體240係密封該些内腳部21 5、該第 220以及該第二晶片230，但顯露該些外腳部2 1 其中，該第二晶片2 3 0之厚度係大於該第一晶 之厚度，並且該些第二水平引腳部2 1 4相對於該 水平引腳部2 1 3更為沉置以使該些第二水平引胸 鄰近該封膠體240之一底面241。請參閱第7圖 該第二水平引腳部2 1 4相對於該些第一水平引胸 該些第 二晶片 232 ° 之一側 黏貼而 215係 214並 用以縮 於導線 一鲜線 222至 閱第9 裝構造 弟二晶 ^ 218° 一晶片 6 ° 片220 些第一 部2 14 所示， 部2 1 3 15 201001656 之沉置深度可約為該第二晶片230與該第一晶片220之 厚度差值之二分之一。 因此，藉由該第一水平引腳部2 1 3與該第二水平引 腳部2 1 4，可供並排設置不同厚度之該第一晶片220與 該第二晶片2 3 0，並改善模封時模流不均勻之問題。此 外，由於該第二水平引腳部2 1 4為沉置配置，故可避免 該些第二銲線260外露於該封膠體240外。此外，該些 第二水平引腳部2 1 4可經由與該第一水平引腳部2 1 3共 平面之接指2 1 8往外連接至一固定物（圖中未繪出），例 如導線架之繫條、擾流板或膠帶，得到在封裝過程的支 樓力，以避免模流傾斜。 依據本發明之第四具體實施例，另一種多晶片並排 於導線架上之半導體封裝構造舉例說明於第1 0圖之截 面示意圖。一種多晶片並排於導線架上之半導體封裝構 造3 0 0之基本架構係大致與第三具體實施例相同，相同 功能的主要元件係以相同圖號表示之，不再贅述。該多 晶片並排於導線架上之半導體封裝構造3 00主要包含 該些引腳211、該第一晶片220、該第二晶片23 0以及 該封膠體2 4 0。每一引腳2 1 1係具有該内腳部2 1 5以及 該外腳部2 1 6，其中該内腳部2 1 5係包含該第一水平引 腳部2 1 3、該第二水平引腳部2 1 4以及該連接該第一水 平引腳部 2 1 3與該第二水平引腳部 2 1 4之傾斜引腳部 2 1 7。該外腳部2 1 6係相連至對應的該内腳部2 1 5接近 該第一水平引腳部2 1 3之部位。在本實施例中，每一引 16 201001656 f 腳2 1 1 該第二 係分別 水平引 不’該 動元件 焊接至 該些内 但顯露 之厚度 平引腳 以使該 面241 町另具有一第二外 水平引㈣2141第―晶片…與該二 設置於該些第-水平引腳部213上與該此 腳部214上。在本實施例中’請參閱第^ 第一曰曰片230係可為被動元件’例如 。可利用鲜料370將該第二晶片230之兩端 該些第一水平弓丨聊部214。該封膠體24〇 腳部215、該第—晶片220以及該/ 該些外腳吾"16與319。其中，讀第 係大於該第-晶片22。之厚度’教且該些曰第 部214相對於該些第一水平引腳部213更為 些第二水平引腳部214鄰近該封膠體24〇 卿部319,其係相連至姆 係 晶片 之 以上所述，僅是本發明的較佳實施例而已並 本發明作任何形式上的限制，本發明技術方案範圍 v 所附申請專利範圍為準。任何熟悉本專業的技術人 利用上述揭示的技術内容作出些許更動或修飾為 變化的等效實施例，但凡是未脫離本發明技術方案 容，依據本發明的技術實質對以上實施例所作的任 單修改、等同變化與修飾，均仍屬於本發明技術方 範圍内。 【圖式簡單說明】 第1圖：為依據本發明第—具體實施例的—種多晶 排於導線架上之半導體封裝構造在移除 應的 23 0 第二 圖所 型被 電極 密封 230， 230 二水 沉置 一底 非對 當依 員可 等同 的内 何簡 案的 片並 某些 17 201001656 元件後的上視圖。 第2圖：為依據本發明第一具體實施例的多晶片並排 導線架上之半導體封裝構造沿著晶片承座 其連接繫條刮切的截面示意圖。 第3圖：為依據本發明第一具體實施例的多晶片並排 導線架上之半導體封裝構造剖切第一晶片 截面示意圖。 第4圖：為依據本發明第一具體實施例的多晶片並排 導線架上之半導體封裝構造剖切第二晶片 截面示意圖。 第5圖：為依據本發明第二具體實施例的多晶片並排 導線架上之半導體封裝構造之導線架的上 圖。 第6圖：為依據本發明第三具體實施例的另一種多晶 並排於導線架上之半導體封裝構造在移除 些元件後的上視圖。 第7圖：為依據本發明第三具體實施例的多晶片並排 導線架上之半導體封裝構造沿著引腳剖切 截面示意圖。 第8圖：為依據本發明第三具體實施例的多晶片並排 導線架上之半導體封裝構造剖切第一晶片 截面示意圖。 第9圖：為依據本發明第三具體實施例的多晶片並排 導線架上之半導體封裝構造剖切第二晶片 於 及 於 的 於 的 於 視 片 某 於 的 於 的 於 的 18 201001656 截面示意圖。 第1 〇圖：為依據本發明第四具體實施例的另一種多晶4 is sufficient to carry the structure of the eosin B B and the second wafer 230 to carry the μ-th wafer in * & Please refer to the 811th lang. - In this embodiment, the first horizontal level is not the foot 216. As shown in Fig. 6, the opposite sides of the opposing encapsulant 240 can be connected to the pins 211 and bent to the second wafer 23. The party; stretched to the first -...2. , ^ Ν double stretch. The first wafer 220 is disposed on the horizontal lead portion 213. Please refer to the section: the 220th of the inner leg 215 has a -first active surface 221 and, if not the first wafer, the first wafer is also the second soldering pad 2 2 2 . ~ "塾 222 series can be arranged on the first side of the reading. The first wafer 220 is attached to the first horizontal lead portion 2 1 3 by the bonding of the _221 side to the adhesive 223 and 14 201001656. The second wafer 203 is disposed on the two horizontal pin portions 214 of the inner leg portions 2 1 5 . As shown in FIG. 9 , the 230th frame has a second active surface 231 and a plurality of second portions. The second pads 232 are arranged on the second active surface 23 1 . The second wafer 203 is disposed on the second horizontal portions by using a second adhesive 2 3 3 . 2 1 4. More specifically, as shown in FIG. 7 , the inner leg portion further includes a finger 2 1 8 , and the second horizontal pin portion is connected to the first horizontal pin portion 2 The semiconductor package structure 200 on the multi-wafer side-by-side shelf may further include a plurality of 250th portions electrically connected to the first wafer 220, as shown in FIG. The first solder pads of the pins 2 1 1 are the first horizontal lead portions 2 1 3 . As shown in the figure, the semiconductor package 200 of the multi-chip side by side on the lead frame may be additionally a plurality of second bonding wires 260, electrically connecting the second bonding pads 232 of the film 230 to the pins 211 and sealing the sealing bodies 240 to seal the inner leg portions 215, the 220th and the a second wafer 230, but the outer leg portions 2 1 are exposed, wherein the thickness of the second wafer 210 is greater than the thickness of the first crystal, and the second horizontal pin portions 2 14 are relative to the level The lead portion 2 1 3 is further disposed such that the second horizontal chests are adjacent to a bottom surface 241 of the sealant 240. Please refer to FIG. 7 for the second horizontal lead portion 2 1 4 relative to the first Horizontal chest, the second wafer 232 ° side of the second paste and 215 series 214 and used to shrink the wire a fresh line 222 to read the 9th structure of the two crystals 218 ° a wafer 6 ° piece 220 some first part 2 14, the depth of the sinking of the portion 2 1 3 15 201001656 may be about one-half the difference between the thicknesses of the second wafer 230 and the first wafer 220. Therefore, by the first horizontal lead portion 2 1 3 and the second horizontal lead portion 2 1 4, the first wafer 220 and the second wafer 2 3 0 of different thicknesses can be arranged side by side, and the molding is improved. In addition, since the second horizontal lead portion 2 14 is in a sinking configuration, the second bonding wires 260 can be prevented from being exposed outside the sealing body 240. In addition, the second horizontal leads are The leg portion 2 14 can be externally connected to a fixture (not shown) via a finger 2 1 8 coplanar with the first horizontal pin portion 2 1 3, such as a tie bar of a lead frame, a spoiler Or tape to get the support force in the packaging process to avoid mold flow tilt. According to a fourth embodiment of the present invention, another semiconductor package structure in which a plurality of wafers are arranged side by side on a lead frame is illustrated in a cross-sectional view of Fig. 10. A basic structure of a semiconductor package structure in which a plurality of wafers are arranged side by side on a lead frame is substantially the same as that of the third embodiment. The main components of the same function are denoted by the same reference numerals and will not be described again. The semiconductor package structure 300 of the multi-chip side by side on the lead frame mainly comprises the pins 211, the first wafer 220, the second wafer 230, and the encapsulant 240. Each of the pins 2 1 1 has the inner leg portion 2 1 5 and the outer leg portion 2 1 6 , wherein the inner leg portion 2 1 5 includes the first horizontal pin portion 2 1 3 , the second level The lead portion 2 1 4 and the inclined lead portion 2 17 of the first horizontal lead portion 2 1 3 and the second horizontal lead portion 2 1 4 are connected. The outer leg portion 2 16 is connected to a portion of the corresponding inner leg portion 2 1 5 that is adjacent to the first horizontal pin portion 2 1 3 . In this embodiment, each of the leads 16 201001656 f the foot 2 1 1 the second line is horizontally not respectively soldered to the inner but exposed thickness flat pins so that the face 241 has another The second outer horizontal guide (four) 2141 first "wafer" and the second are disposed on the first-horizontal lead portion 213 and the leg portion 214. In the present embodiment, please refer to the first die 230 as a passive component'. The first horizontal bow portion 214 of the second wafer 230 can be used by the fresh material 370. The encapsulant 24 is a leg portion 215, the first wafer 220, and the outer legs & 16 and 319. The read system is larger than the first wafer 22. The thickness of the first portion 214 relative to the first horizontal lead portions 213 is further adjacent to the encapsulant 24 〇 319, which is connected to the slab The above is only the preferred embodiment of the present invention and the present invention is not limited to any form, and the scope of the technical solution of the present invention is subject to the scope of the appended patent application. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but without departing from the technical scope of the present invention, the order of the above embodiments is based on the technical essence of the present invention. Modifications, equivalent changes and modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a semiconductor package structure in which a polycrystalline silicon is arranged on a lead frame according to a first embodiment of the present invention, and an electrode seal 230 of the type shown in FIG. 230 Two water sinking a bottom is not the same as the one that can be equivalent to the inner and short case and some 17 201001656 components after the upper view. Fig. 2 is a cross-sectional view showing the semiconductor package structure on the multi-wafer side-by-side lead frame in accordance with the first embodiment of the present invention, which is scraped along the connecting strip of the wafer holder. Figure 3 is a cross-sectional view showing the first wafer in a semiconductor package structure on a multi-wafer side-by-side lead frame in accordance with a first embodiment of the present invention. Figure 4 is a cross-sectional view showing a second wafer cut away for a semiconductor package structure on a multi-wafer side-by-side lead frame in accordance with a first embodiment of the present invention. Fig. 5 is a top view of a lead frame of a semiconductor package structure on a multi-wafer side-by-side lead frame in accordance with a second embodiment of the present invention. Fig. 6 is a top plan view showing a semiconductor package structure in which a plurality of polycrystals are arranged side by side on a lead frame in accordance with a third embodiment of the present invention. Figure 7 is a cross-sectional view, taken along the line, of a semiconductor package structure on a multi-wafer side-by-side lead frame in accordance with a third embodiment of the present invention. Figure 8 is a cross-sectional view showing a first wafer cut away for a semiconductor package structure on a multi-wafer side-by-side lead frame in accordance with a third embodiment of the present invention. Figure 9 is a cross-sectional view showing a semiconductor wafer package structure on a multi-wafer side-by-side lead frame in accordance with a third embodiment of the present invention, and a view of the second wafer, and a view of the video film of 18 201001656. Figure 1 is another polycrystalline according to a fourth embodiment of the present invention
片 並排於導線架上之半導 •體封裝構造的截 意 :圖。 [主 -要元件符號說明】 100 多晶片 並排 於導線架上之半導體 封裝構造 110 導線架 111引腳 112 晶片承座 112A槽孔 113 第一黏 晶區 114 第二 黏晶區 114A 内繫條 115 内腳部 116 外腳部 117沉置 彎折 118 繫條 Π8Α沉置折痕 119 繫條 119A沉置折痕 120 第一晶 片 121 第一 主動面 122 第一銲墊 123 第一黏 晶膠 130 第一晶 片 131 第二 主動面 132 第二銲墊 133 第二黏 晶膠 140 封膠體 i41底面 150 第一銲 142 頂面 線 160 第二 銲線 200 多晶片 並排 於導線架上之车道 210 導線架 < +導體 211引腳 封裝構造 213 第一水 平引 腳部 214 第二水平引 腳部 216 外腳部 2 1 7傾斜 引腳部 215 218 内腳部 接指 19 201001656 220 第 一 晶 片 221 第一主動面 222 第- -銲墊 230 第 二 晶 片 23 1 第二主動面 232 第： 二銲墊 240 封 膠 體 241 底面 250 第 一 銲 線 260 第二銲線 300 多 晶 片 並排於導線; 架上之半導體封裝構造 3 19 第 _ 外 腳部 370 銲料A semi-conducting body-side package structure that is placed side by side on the lead frame: Figure. [Main-Required Symbol Description] 100 multi-chip semiconductor package structure side by side on the lead frame 110 lead frame 111 pin 112 wafer holder 112A slot 113 first die bond region 114 second die bond region 114A inner tie bar 115 Inner leg 116 outer leg portion 117 sinking and bending 118 tie Π 8 Α sinking crease 119 tie 119A sinking crease 120 first wafer 121 first active surface 122 first solder pad 123 first adhesive glue 130 A wafer 131, a second active surface 132, a second solder pad 133, a second adhesive layer 140, a sealant i41, a bottom surface 150, a first solder 142, a top surface line 160, a second bonding wire 200, a plurality of wafers, and a lane 210 on the lead frame. + conductor 211-pin package structure 213 first horizontal pin portion 214 second horizontal pin portion 216 outer leg portion 2 1 7 oblique pin portion 215 218 inner leg finger 19 201001656 220 first wafer 221 first active Face 222 - solder pad 230 second wafer 23 1 second active surface 232: second solder pad 240 sealant 241 bottom surface 250 first bond wire 260 Two wafer bonding wires 300 parallel to the wire; semiconductor package 319 configured in a holder on the outer leg portion 370 of the solder _
2020