200837922 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種多晶片封裝構造，特別 於一種文善利用基板黏晶區之多晶片封裝構造。 【先前技術】 多晶片封裝構造是越來越受到重視的半導體 品，這是因為可以增加一封裝體内積體電路的密 中以晶片在晶片上（Chip-〇n-Chip)的堆疊方式不 •封裝表面接合面積，更優於晶片並胡 (side-by-side)。若是直接將所有需要的積體電路 單一晶片内，會有不良率提高的問題，且晶片的 變大’導致封裝體之表面接合面積擴大。 請參閱第1圖所示，一種習知的多晶片封裝賴 主要包含一基板110、複數個表面黏著型被 120、一第一晶片130、一第二晶片14〇、複數 馨 151與152以及一封膠體160。該第二晶片14〇 上係大於該第一晶片1 3 0，並設置於該基板〗j 〇 面111。該第二晶片140係具有一主動面141、 之背面142以及複數個形成於該主動面141之第 1 4 3。利用複數個銲線1 5 2電性連接該第二晶片 銲塾143至該基板110。該些表面黏著型被動元 又可稱之為晶片型被動元件，例如電容、電感、 積層陶瓷電容（MLCC)，其係設置於該基板U〇 面111在黏晶區之外的其餘部位。在有限的基 係有關 封裝產 度，其 會增加 E方式 整合於 尺寸會 卜造100 動元件 個銲線 在尺寸 之一表 一相對 二銲墊 140之 件 120, 電阻或 之該表 -板面積 200837922 内，並同時預留有第二晶片140與該些表面黏著型被動 元件120的設置面積’故第一晶片140之尺寸受到限 制’目前而言無法擴大到晶片尺寸封裝（Chip200837922 IX. Description of the Invention: [Technical Field] The present invention relates to a multi-chip package structure, and more particularly to a multi-chip package structure using a substrate die-bonding region. [Prior Art] Multi-chip package structure is a semiconductor product that is receiving more and more attention because it can increase the denseness of a package circuit in a package to chip-on-chip stacking. The surface area of the package is better than the side-by-side. If all of the required integrated circuits are directly placed in a single wafer, there is a problem that the defective rate is increased, and the wafer becomes larger, resulting in an increase in the surface joint area of the package. Referring to FIG. 1 , a conventional multi-chip package mainly includes a substrate 110 , a plurality of surface mount patterns 120 , a first wafer 130 , a second wafer 14 , a plurality of 151 and 152 , and a Sealant 160. The second wafer 14 is larger than the first wafer 130 and disposed on the substrate 111. The second wafer 140 has an active surface 141, a back surface 142, and a plurality of first ones formed on the active surface 141. The second wafer pad 143 is electrically connected to the substrate 110 by a plurality of bonding wires 152. The surface-adhesive passive elements may also be referred to as wafer-type passive components, such as capacitors, inductors, and multilayer ceramic capacitors (MLCC), which are disposed on the rest of the substrate U-plane 111 outside the die-bonding region. In a limited base system related to package yield, it will increase the E-mode integration in the size of the assembly. 100 moving parts of a wire in one of the dimensions of the table 1 relative to the two pads 140 of the piece 120, the resistance or the table-board area In 200837922, at the same time, the second wafer 140 and the surface area of the surface-adhesive passive components 120 are reserved. Therefore, the size of the first wafer 140 is limited. Currently, it is not possible to expand to the chip size package (Chip).
SizeSize
Package ’簡稱CSP)等級。當更小尺寸的第一晶片 貼設在該第二晶片1 4 0之主動面1 4 1之邊緣，但會影響 其它晶片堆疊與权流平衡。此外，第一晶片之鲜塾 131可利用複數個銲線151電性連接至該基板n〇。通 常該多晶片封裝構造100係為一種數位保全記憶卡 (Micro SD card) ’該第一晶片13〇係可為一控制器晶 片，該第二晶片1 40係可為一快閃記憶體晶片。該封膠 體160係形成於該基板11〇之該表面m，並密封該第 一晶片130、該第二晶片14〇、該些銲線&與152。 當記憶體或積體電路的密度擴大，該第二晶片14〇之尺 寸亦會變大，相對使得可設置該些表面黏著型被動元件 120的面積縮小。 【發明内容】 本發明之主要目的得、在於提供一種妥善利用基板黏Package ‘referred to as CSP) level. When the smaller size of the first wafer is attached to the edge of the active surface 141 of the second wafer 140, it affects other wafer stack and weight balance. In addition, the fresh slab 131 of the first wafer can be electrically connected to the substrate n 利用 by using a plurality of bonding wires 151. Typically, the multi-chip package structure 100 is a micro SD card. The first wafer 13 can be a controller wafer, and the second wafer 140 can be a flash memory chip. The encapsulant 160 is formed on the surface m of the substrate 11 and seals the first wafer 130, the second wafer 14 , the bonding wires & When the density of the memory or integrated circuit is increased, the size of the second wafer 14 is also increased, so that the area of the surface-adhesive passive element 120 can be reduced. SUMMARY OF THE INVENTION The main object of the present invention is to provide a proper use of substrate adhesion.
利影響。 1的尺寸可進一步擴大 的設置面積，並減少較 :流平衡所能產生的不Benefits. The size of 1 can be further enlarged to set the area and reduce the ratio of:
於被隱藏較小晶 目的係在於提供一種妥善利用基板黏 良構造，可以避免上方堆疊較大晶片對 片以及對於下方承載之表面黏著型被 7 200837922 動元件的電性短路。 發月的目的及解決其技術問題是採用以下技術方 實現的。依據本發明，一種妥善利用基板黏晶區之 夕曰曰片封裝構造主要包含一基板、複數個表面黏著型被 動兀件、_第_晶片以及一第二晶片。該基板之一表面The purpose of hiding the smaller crystals is to provide a proper use of the substrate adhesion structure to avoid stacking larger wafer pairs above and electrically shorting the underlying surface mount type. The purpose of the moon and the resolution of its technical problems are achieved by the following techniques. According to the present invention, a matte package structure for properly utilizing a die attach region of a substrate mainly comprises a substrate, a plurality of surface mount type passive members, a _th wafer, and a second wafer. One surface of the substrate
上並電性連接至該基板’且該第二晶片之覆蓋面積係對 應於該黏晶區。另揭示該多晶片封裝構造之應用及其使 係界疋有一黏晶區。該些表面黏著型被動元件係設置於 該黏^之角隅或邊緣並電性連接至該基板。該第一晶 片係設置於該黏晶區之―相對中央位置並電性連接至 該基板。該第二晶片係設置於該些表面黏著型被動元件 用之基板 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的多晶片封裝構造中，該些表面黏著型被動 元件係可具有一間隔維持高度’以避免該第二晶片壓觸 該第一晶片。 ’可另包含複數個第一 電性連接該第一晶片與 馬係不超過該間隔維持 在前述的多晶片封裝構造中 銲線，其係位於該黏晶區内，以 該基板，並且該些第一銲線之弧 高度。 在前述的多晶片封裝構造中， 可另包含複數個第二 銲線，其係電性連接該第二晶片與該基板。 在前述的多晶片封裝構造中， 曰 ^ 晶片係可設有 200837922 複數個凸塊，以覆晶接合至該基板，其中該第一晶片之 背面係不超過該間隔維持高度。 在前述的多晶片封裝構造中，該第二晶片之背面係 可被覆有一絕緣層’其係貼觸於該些表面黏著型被動元 件之表面電極上’以避免該些表面黏著型被動元件之短 路。 在前述的多晶片封裝構造中，該黏晶區係可不小於 該基板之表面面積百分之七十，以構成晶片尺寸封裝。 Φ 在前述的多晶片封裝構造中，該基板於該表面係可 設有複數個第一内接墊、複數個第二内接墊與複數個表 面黏者塾’以供該第一晶片、該第二晶片與該些表面黏 著型被動元件之電性連接，其中該些第一内接墊與該些 表面黏著墊係位於該黏晶區内，並且該些表面黏著塾相 對較鄰近於該黏晶區之邊緣或角隅。 在前述的多晶片封裝構造中，該多晶片封裝構造係 ⑩ 可為一種數位保全記憶卡（Micro SD card)，其中該第一 曰曰片係為一控制晶片、該第二晶片係為一快閃記憶體 晶片。 在前述的多晶片封裝構造中，可另包含有至少一第 三晶片’其係疊設於該第二晶片上，該第三晶片係為一 快閃記憶體晶片且尺寸實質相同於該第二晶片。 在前述的多晶片封裝構造中，可另包含有至少一第 三晶片，其係疊設於該第二晶片上。 在前述的多晶片封裝構造中，可另包含有一封膠 9 200837922 體，其係密封該第二晶片。 在前述的多晶片封襞構造中，可另包含有_魏晶物 質，其係黏接該第二晶片並密封該第一晶片與該些表面 黏著型被動元件。 【實施方式】 依據本發明之第一具體實施例，揭示一種妥善利用 基板黏晶區之多晶片封裝構造。第2圖係為該多晶片封 裝構造之截面示意圖。第3圖係為該多晶片封裝構造透 視封膠體之基板表面示意圖。第4圖係為該多晶片封裝 構造多晶片封裝構造之另一截面不意圖。第5圖係為該 多晶片封裝構造之基板表面示意圖。 請參閱第2圖所示，一種妥善利用基板黏晶區之多 晶片封裝構造200主要包含一基板2〗〇、複數個表面黏 著型被動元件220、一第一晶片230以及一第二晶片 2 4 0。該基板2 1 0係可為一印刷電路板、一陶兗電路板 或一電路薄膜，其係具有一上表面211與一下表面 212。請參閱第3圖並配合第5圖所示，該基板21〇之 上表面2 11係界定有一黏晶區2丨3，其尺寸大小對應於 該第二晶片240。此外，該上表面211係可設有複數個 第一内接墊214、複數個第二内接墊215與複數個表面 黏著墊216，以分別可供該第一晶片23〇、該第二晶片 240與該些表面黏著型被動元件22〇之電性連接，其中 該些第一内接墊214與該些表面黏著墊216係位於該黏 晶區213内，該些第二内接墊215係位於該黏晶區213之 10 200837922 外，並且該些表面黏著墊2 1 6相對於該些第一内接塾 2 1 4較鄰近於該黏晶區2 1 3之邊緣或角隅。在本實施例 中，該黏晶區213係可不小於該基板210之該上表面 211面積百分之七十，即該第二晶片24〇之主動面尺寸 可接近該基板210之上表面2 u，以構成晶片尺寸封 裝。請參閱第4圖所示，該基板210更可包含有複數個 外接墊217，其係形成於該基板210之下表面212。 該些表面黏著型被動元件220係設置於該黏晶區 213之角隅或邊緣並電性連接至該基板21〇之該些表面 黏著墊2 1 6。該些表面黏著型被動元件2 2 0或可稱為晶 片型被動元件，其外形係為條塊狀小顆粒，如〇2〇 1或 04 02等被動元件規格，可利用表面黏著（SMT)技術焊設 於該基板210之該些表面黏著塾216。較佳地，該些表 面黏著型被動元件220係可具有一間隔維持高度hi， 以避免該第二晶片240壓觸該第一晶片230。如第2及 3圖所示，不受局限地，部分之表面黏著型被動元件2 2 〇 係可設置於該黏晶區2 1 3之外。 請參閱第2、3及4圖所示，該第一晶片23 〇之尺寸 係小於該第二晶片240。該第一晶片230係設置於該黏 晶區213之一相對中央位置並電性連接至該基板21〇 q 在本實施例中，該第一晶片2 3 0係具有複數個第一銲墊 23 1，在晶片設置之後，該些第一銲墊23〗係為朝上。 複數個第一銲線2 5 1係形成於該黏晶區2 1 3内，以電性 連接該些第一銲墊231與該基板210之該些第一内接墊 11 200837922 214。請參閱第4圖所示，較佳地，該些第一鍀 之弧高H2以及該第一晶片23〇皆不超過該間隔 度H1，以使該第一晶片mo隱藏在該第二晶片 該基板2 1 0之間且不會有電性短路的問題。 該第二晶片240係具有一主動面241及一相 面242 ’其中該主動面241係形成有複數個第 243。請參閱第2及4圖，該第二晶片240係設 些表面黏著型被動元件220上並利用複數個第 252電性連接該些第二銲墊243與該基板21〇之 二内接墊215 (如第3圖所示），並且如上述這般 二晶片240之覆蓋面積係對應於該黏晶區21 3 地，該第二晶片240之背面242係可被覆有一 2 44 ’其係貼觸於該些表面黏著型被動元件22〇 電極上’以避免作為晶片間隔控制的該些表面黏 動元件220在表面電極與表面電極之間產生電括 具體而言，該多晶片封裝構造200可另包含 膠體260，其係形成於該基板21〇之該上表面2 密封該第一晶片230、該第二晶片240、該些表 型被動元件220、該些第一銲線251與該些第 252。在本實施例中，該多晶片封裝構造200係 種數位保全記憶卡（Micro SD card)，其中該第 230係為一控制器晶片、該第二晶片240係為一 憶體晶片。 因此，在上述的多晶片封裝構造200中，較 線25 1 維持高 240與 對之背 二銲墊 置於該 二銲線 該些第 ，該第 。較佳 絕緣層 之表面 著型被 .短路。 有一封 1 1，以 面黏著 一鲜線 可為一 一晶片 快閃記 大的第 12 200837922 二晶片 240的尺寸可進一步擴大且不會減少表面 型被動元件220的設置面積，特別是第二晶片240 動面241面積可達到接近該基板210之上表面211 構成晶片尺寸封裝。此外，並能減少較小被隱藏的 晶片230對於晶片堆疊與模流平衡所能產生的不 響。本發明之另一顯著功效為，不需要隨著表面黏 被動元件220的設置數量增加而被迫縮小第二晶片 的尺寸，相反地，表面黏著型被動元件220的設置 增加更可以增加第二晶片240的打線支撐，以提高 良率。 在本發明之第二具體實施例，揭示另一種妥善 基板黏晶區之多晶片封裝構造。請參閱第6圖所示 多晶片封裝構造3 00主要包含一基板310、複數個 黏著型被動元件320、一第一晶片330以及一第二 3 4 〇。該基板3 1 〇之一上表面3 1 1係界定有一黏晶 對應於該第二晶片340。該基板310更具有複數個 墊3 1 3，其係形成於該基板3 1 〇之一下表面3丨2。 該些表面黏著型被動元件3 2 0係設置於該黏晶 角隅或邊緣並以錫膏電性連接至該基板31〇。該第 片3 3 0係設置於該黏晶區之一相對中央位置並電 接至該基板3 1 0。在本實施例中，該第一晶片3 3 〇 為一覆晶晶片’其係設有複數個凸塊331，以覆晶 至該基板310’其中該第一晶片33〇之背面332係 過該間隔維持高度H3。因此，該些表面黏著型被 黏著 之主 ，以 第一 利影 著型 240 數量 製程 利用 ，該 表面 晶片 區， 外接 區之 一晶 性迷 係可 接合 不超 動元 13 200837922 件3 20係能提供一間隔維持高度H3，以避免該第二晶 片340壓觸該第一晶片330。 該第二晶片340係設置於該些表面黏著型被動元件 320上並電性連接至該基板3 1〇，且該第二晶片34〇之 覆蓋面積係對應於該黏晶區。該第二晶片3 4 〇係具有一 主動面341 ’該主動面341係設有複數個銲墊343。利 用複數個#線351電性連接該第二晶片3 4〇之銲塾343 至該基板3 10。 較佳地，該第二晶片340之背面342係可被覆有一 絕緣層344,以避免該些表面黏著型被動元件32〇之短 路。在本實施例中，該多晶片封裝構造3〇〇可另包含有 一黏晶物質370，其係黏接該第二晶片34〇並密封該第 一晶片330與該些表面黏著型被動元件32〇。 該多晶片封裝構造300可另包含有_封膠體36〇 , 其係密封該第二晶片340。當該封膠體36〇形成之後， 可製成^片狀。具體而言，該多晶片封裝構造3 0 0係 可為一種數位保全記憶卡（MicroSDcard)，其中該第一 晶片330係為一控制器晶片、該第二晶片34〇係為一快 閃記憶體晶片。 該多晶片封裝構造300可另包含有至少一第三晶片 380，其係疊設於該第二晶片340上，該第三晶片以〇 係為一快閃記憶體晶片且尺寸實質相同於該第二晶片 34〇。該第三晶片380係疊設於該第二晶片34〇上，並 使該第三晶片380之複數個銲墊381係位於其朝上之主 14 200837922 a 動面，可藉由複數個銲線352電性連接該些銲墊381至 該基板310。該第二晶片340與該第三晶片38〇之間係 設有一間隔片390，以提供該第三晶片38〇在正向堆疊 時之打線間隔，並可避免該第三晶片38〇壓觸至相對下 方之該些銲線3 5 1。 因此，該多晶片封裝構造300係可將一較小尺寸之 2 一晶片33〇與該些表面黏著型被動元件32〇隱藏在同 、一層之黏晶間隙，不會影響較大尺寸之第二晶片340與 暑第m80的縱向堆疊而導致堆疊厚度增加。此外， b萵要縮小較大尺寸之第二晶片3 4 〇而能設置更多數 里的表面黏著型被動元件32〇，具有實用性。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實施 路如上’然而並非用以限定本發明，任何熟悉本專 ! 業的技術人員，在不脫離本發明技術方案範圍内，冬可 j 矛丨J na « 田 丨馨 述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 ^ ’依據本發明的技術實質對以上實施例所作的任何簡 : 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖··一種習知多晶片封裝構造之截面示意圖。 第2圖：依據本發明之第一具體實施例，一種妥善利用 基板黏晶區之多晶片封裝構造之截面示意圖。 15 200837922 第3圖：依據本發明之第一具體實施例，該多晶片封裝 構造透視封膠體之基板表面示意圖。 第4圖：依據本發明之第一具體實施例，該多晶片封裝 構造多晶片封裝構造之另一截面示意圖。 第5圖：依據本發明之第一具體實施例，該多晶片封裝 構造之基板表面示意圖。 第6圖：依據本發明之第二具體實施例，另一種妥善利 用基板黏晶區之多晶片封裝構造之截面示意 ⑩ 圖。 【主要元件符號說明】 100多晶片封裝構造And electrically connected to the substrate ' and the coverage area of the second wafer corresponds to the die bonding region. Another application of the multi-wafer package construction is disclosed and the bonding layer has a die-bonding region. The surface-adhesive passive components are disposed at the corners or edges of the adhesive and electrically connected to the substrate. The first wafer is disposed at a "opposing center" position of the die bonding region and electrically connected to the substrate. The second wafer is disposed on the substrate for the surface-adhesive passive component. The object of the present invention and solving the technical problem thereof can be further achieved by the following technical measures. In the aforementioned multi-chip package construction, the surface-adhesive passive components may have a spacing maintaining height ' to prevent the second wafer from pressing against the first wafer. 'A further comprising a plurality of first electrical connections connecting the first wafer and the horse system to the soldering line in the multi-chip package structure not exceeding the interval, the system is located in the die bonding region, and the substrate The arc height of the first weld line. In the foregoing multi-chip package structure, a plurality of second bonding wires may be further included, which electrically connect the second wafer and the substrate. In the foregoing multi-chip package construction, the 晶片 ^ wafer system may be provided with 200837922 plurality of bumps to be flip-chip bonded to the substrate, wherein the back side of the first wafer does not exceed the interval maintaining height. In the foregoing multi-chip package structure, the back surface of the second wafer may be covered with an insulating layer that is attached to the surface electrodes of the surface-adhesive passive components to avoid short-circuiting the surface-adhesive passive components. . In the above multi-wafer package construction, the die bond region may be no less than seventy percent of the surface area of the substrate to constitute a wafer size package. Φ In the above multi-chip package structure, the substrate may be provided with a plurality of first inner pads, a plurality of second inner pads and a plurality of surface adhesives for the first wafer, The second wafer is electrically connected to the surface-adhesive passive components, wherein the first inner pads and the surface adhesive pads are located in the die-bonding region, and the surface adhesive pads are relatively adjacent to the adhesive layer The edge or corner of the crystal zone. In the above multi-chip package structure, the multi-chip package structure 10 can be a micro SD card, wherein the first chip is a control chip, and the second chip is fast. Flash memory chip. In the foregoing multi-chip package structure, at least one third wafer is additionally disposed on the second wafer, the third wafer is a flash memory chip and the size is substantially the same as the second Wafer. In the foregoing multi-chip package construction, at least one third wafer may be further included on the second wafer. In the foregoing multi-chip package construction, an adhesive 9 200837922 may be additionally included, which seals the second wafer. In the foregoing multi-wafer sealing structure, a wei-wei substance may be further included, which bonds the second wafer and seals the first wafer and the surface-adhesive passive elements. [Embodiment] According to a first embodiment of the present invention, a multi-chip package structure for properly utilizing a die attach region of a substrate is disclosed. Figure 2 is a schematic cross-sectional view of the multi-wafer package construction. Figure 3 is a schematic view of the surface of the substrate of the multi-chip package structure through the encapsulant. Figure 4 is another cross-sectional view of the multi-chip package construction multi-chip package construction. Figure 5 is a schematic view of the surface of the substrate of the multi-chip package structure. Referring to FIG. 2, a multi-chip package structure 200 for properly utilizing a die attach region of a substrate mainly includes a substrate 2, a plurality of surface-adhesive passive components 220, a first wafer 230, and a second wafer 24. 0. The substrate 210 can be a printed circuit board, a ceramic circuit board or a circuit film having an upper surface 211 and a lower surface 212. Referring to FIG. 3 and in conjunction with FIG. 5, the upper surface 2 11 of the substrate 21 defines a die-bonding region 2丨3 having a size corresponding to the second wafer 240. In addition, the upper surface 211 can be provided with a plurality of first inner pads 214, a plurality of second inner pads 215 and a plurality of surface adhesive pads 216 for respectively receiving the first wafer 23 and the second wafer. The second inner pad 214 and the surface adhesive pad 216 are located in the die bonding area 213, and the second inner pad 215 is electrically connected to the surface bonding type passive component 22 The surface adhesive pad 2 16 is located adjacent to the edge or corner of the die bond region 2 1 3 relative to the first inscribed ports 2 1 4 . In this embodiment, the die attach region 213 is not less than 70% of the area of the upper surface 211 of the substrate 210, that is, the active surface size of the second wafer 24 is close to the upper surface of the substrate 210. To form a wafer size package. Referring to FIG. 4, the substrate 210 further includes a plurality of external pads 217 formed on the lower surface 212 of the substrate 210. The surface-adhesive passive components 220 are disposed at the corners or edges of the die-bonding region 213 and are electrically connected to the surface-adhesive pads 2 16 of the substrate 21 . The surface-adhesive passive component 220 may be referred to as a wafer-type passive component, and its shape is a small block-shaped particle, such as a passive component specification such as 〇2〇1 or 04 02, which can utilize surface adhesion (SMT) technology. The surface of the substrate 210 is soldered to the surface of the substrate 210. Preferably, the surface-adhesive passive components 220 can have a spacing maintaining height hi to prevent the second wafer 240 from pressing against the first wafer 230. As shown in Figures 2 and 3, a portion of the surface-adhesive passive component 2 2 can be disposed outside of the die-bonding region 2 1 3 without limitation. Referring to Figures 2, 3 and 4, the first wafer 23 is smaller in size than the second wafer 240. The first wafer 230 is disposed at a central position of the die bond region 213 and electrically connected to the substrate 21 〇q. In this embodiment, the first die 305 has a plurality of first pads 23 1. After the wafer is disposed, the first pads 23 are facing upward. A plurality of first bonding wires 251 are formed in the die bonding region 2 1 3 to electrically connect the first pads 231 and the first interconnect pads 11 200837922 214 of the substrate 210 . Referring to FIG. 4, preferably, the first arc height H2 and the first wafer 23〇 do not exceed the interval H1, so that the first wafer mo is hidden on the second wafer. There is no problem of electrical short between the substrates 2 10 . The second wafer 240 has an active surface 241 and a phase 242', wherein the active surface 241 is formed with a plurality of 243th portions. Referring to FIGS. 2 and 4, the second wafer 240 is mounted on the surface-adhesive passive component 220 and electrically connected to the second bonding pads 243 and the second bonding pads 215 of the substrate 21 by using a plurality of 252th electrodes. (As shown in FIG. 3), and as described above, the coverage area of the two wafers 240 corresponds to the die bonding region 21 3 , and the back surface 242 of the second wafer 240 can be covered with a 2 44 ' On the surface-adhesive passive elements 22 〇 electrodes to avoid the surface-adhesive elements 220 as wafer spacing control between the surface electrodes and the surface electrodes, specifically, the multi-chip package structure 200 can be additionally a colloid 260 is formed on the upper surface 2 of the substrate 21 to seal the first wafer 230, the second wafer 240, the phenotype passive components 220, the first bonding wires 251, and the second 252 . In the present embodiment, the multi-chip package structure 200 is a micro SD card, wherein the 230th is a controller chip, and the second wafer 240 is a memory chip. Therefore, in the multi-wafer package structure 200 described above, the line 25 1 is maintained at a height of 240 and the back of the second pad is placed in the second bond line. Preferably, the surface of the insulating layer is shaped to be short-circuited. There is a 1,1 surface to stick a fresh line, which can be a flash of a wafer. The 12th wafer of the second wafer 240 can be further enlarged without reducing the installation area of the surface type passive component 220, especially the second wafer 240. The movable surface 241 has an area close to the upper surface 211 of the substrate 210 to constitute a wafer size package. In addition, it can reduce the impact of the smaller hidden wafer 230 on wafer stack and mold flow balance. Another significant effect of the present invention is that it is not required to reduce the size of the second wafer as the number of surface-adhesive passive elements 220 is increased. Conversely, the increase in the setting of the surface-adhesive passive element 220 can increase the second wafer. 240 line support to improve yield. In a second embodiment of the present invention, another multi-chip package construction of a proper substrate die-bonding region is disclosed. Referring to FIG. 6, the multi-chip package structure 300 mainly includes a substrate 310, a plurality of adhesive passive elements 320, a first wafer 330, and a second 34. One of the upper surfaces 31 1 of the substrate 3 1 界定 defines a die bond corresponding to the second wafer 340 . The substrate 310 further has a plurality of pads 3 1 3 formed on a lower surface 3 丨 2 of the substrate 3 1 . The surface-adhesive passive components 320 are disposed at the corners or edges of the die bond and are electrically connected to the substrate 31 by solder paste. The first piece 300 is disposed at a center of the one of the die bonding regions and is electrically connected to the substrate 310. In this embodiment, the first wafer 3 〇 is a flip chip, and a plurality of bumps 331 are formed to be crystallized to the substrate 310 ′ where the back surface 332 of the first wafer 33 系 is The interval is maintained at height H3. Therefore, the surface-adhesive type is adhered to, and the first type of wafer is used in the number 240 process. The surface wafer area, one of the external areas, can be bonded to the non-moving element 13 200837922 piece 3 20 system energy An interval maintaining height H3 is provided to prevent the second wafer 340 from pressing against the first wafer 330. The second wafer 340 is disposed on the surface-adhesive passive component 320 and electrically connected to the substrate 310, and the coverage area of the second wafer 34 corresponds to the die-bonding region. The second wafer 34 has an active surface 341'. The active surface 341 is provided with a plurality of pads 343. A plurality of wires 351 are electrically connected to the second wafer 34 343 to the substrate 3 10 . Preferably, the back surface 342 of the second wafer 340 can be covered with an insulating layer 344 to avoid short circuits of the surface-adhesive passive components 32. In this embodiment, the multi-chip package structure 3 can further include a die attach material 370 that bonds the second die 34 and seals the first die 330 and the surface-adhesive passive components 32. . The multi-chip package structure 300 can further include a sealant 36 〇 that seals the second wafer 340. After the sealant 36 is formed, it can be formed into a sheet shape. Specifically, the multi-chip package structure 300 can be a digital memory card (MicroSDcard), wherein the first chip 330 is a controller chip, and the second chip 34 is a flash memory. Wafer. The multi-chip package structure 300 may further include at least one third wafer 380 stacked on the second wafer 340. The third wafer is a flash memory chip and has substantially the same size as the first wafer. Two wafers 34 〇. The third wafer 380 is stacked on the second wafer 34, and the plurality of pads 381 of the third wafer 380 are located on the upper surface of the main 14 200837922 a, which can be separated by a plurality of bonding wires. 352 electrically connects the pads 381 to the substrate 310. A spacer 390 is disposed between the second wafer 340 and the third wafer 38〇 to provide a wire spacing of the third wafer 38 when stacked in the forward direction, and the third wafer 38 can be prevented from being touched. The wire bonds 3 51 are opposite to the lower ones. Therefore, the multi-chip package structure 300 can hide a small-sized 2-pad 33 〇 and the surface-adhesive passive components 32 〇 in the same layer, and does not affect the second of the larger size. The longitudinal stacking of the wafer 340 with the summer m80 results in an increase in the thickness of the stack. In addition, it is practicable to reduce the size of the second wafer 34 of a larger size and to provide a larger number of surface-adhesive passive elements 32 。. The above is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way. Although the invention has been described as preferred, it is not intended to limit the invention. The skilled person can make some modifications or modifications to the equivalent embodiment of the technical content disclosed by the technical content disclosed in the field of the invention without departing from the technical solution of the present invention, but without departing from the technical solution of the present invention. Any simplifications of the above embodiments in accordance with the technical spirit of the present invention: single modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional multi-chip package structure. Fig. 2 is a schematic cross-sectional view showing a multi-chip package structure for properly utilizing a die attach region of a substrate in accordance with a first embodiment of the present invention. 15 200837922 FIG. 3 is a schematic view showing the surface of a substrate of a see-through encapsulant in accordance with a first embodiment of the present invention. Figure 4 is another cross-sectional view of the multi-chip package construction multi-chip package construction in accordance with a first embodiment of the present invention. Figure 5 is a schematic view showing the surface of a substrate of the multi-chip package structure in accordance with a first embodiment of the present invention. Fig. 6 is a cross-sectional view showing another embodiment of a multi-chip package structure in which a substrate die-bonding region is suitably used in accordance with a second embodiment of the present invention. [Main component symbol description] 100 multi-chip package structure
110 基板 111表面 120 表面黏著型被動元件 130 第一晶片 131銲墊 140 第二晶片 141主動面 142 背面 143 銲墊 151 詳線 152銲線 160 封膠體 200 多晶片封裝構造 210 基板 211上表面 212 下表面 213 黏晶區 214第一内接墊 215 第二内 216 表面黏著墊 217外接墊 220 表面黏著型被動元件 230 第一晶片 231第一銲墊 240 第二晶片 241主動面 242 背面 16 200837922 243第二銲墊 244絕緣層 251第一銲線 252第二銲線 260封膠體 300多晶片封裝構造 3 10基板 3 11上表面 312下表面 313外接墊 、320表面黏著型被動元件 330第一晶片 331凸塊 φ 340第二晶片 341主動面 343銲墊 344絕緣層 332背面 342背面 351銲線 352銲線 360封膠體 370黏晶物質 381銲墊 390間隔片 H1 間隔維持高度H2 弧高 Η 3 間隔維持高度 380第三晶片 17110 substrate 111 surface 120 surface-adhesive passive component 130 first wafer 131 solder pad 140 second wafer 141 active surface 142 back surface 143 solder pad 151 detailed line 152 bonding wire 160 encapsulant 200 multi-chip package structure 210 substrate 211 upper surface 212 Surface 213 die bond region 214 first inner pad 215 second inner surface 216 surface adhesive pad 217 outer pad 220 surface adhesive passive component 230 first wafer 231 first pad 240 second wafer 241 active surface 242 back surface 16 200837922 243 Two pads 244 insulating layer 251 first bonding wire 252 second bonding wire 260 sealing body 300 multi-chip package structure 3 10 substrate 3 11 upper surface 312 lower surface 313 lap pad, 320 surface-adhesive passive component 330 first wafer 331 convex Block φ 340 second wafer 341 active surface 343 solder pad 344 insulating layer 332 back surface 342 back surface 351 bonding line 352 bonding line 360 sealing body 370 adhesive material 381 solder pad 390 spacer H1 interval maintaining height H2 arc height Η 3 interval maintaining height 380 third chip 17