201009928 九、發明說明： 【發明所屬之技術領域】 本發明疋關於一種形成開口的方法，尤指一種形成鎮*·^ 結構之開口的方法。 【先前技術】 隨著半導體工業的進展，為了符合該等高密度積體電$ ^ 之開發與設計，各式元件之尺寸皆降至次微米以下。該等 積體電路之性能表現，除了取決於其内部元件的可靠& 外，亦受制於用以傳遞各元件間電子訊號之金屬内連線。 因此，隨著目前持續縮小積體電路尺寸之趨勢，積體電$ 製程已朝向多重金屬内連線方向發展。而為了解決在乡$ (multi-layer)中製作金屬内連線之困難，鑲嵌製程 (damascene process)係受到廣泛研究與發展；另外，由於 銅（Cu)具有比鋁(A1)和絕大多數金屬更低的電阻係數和優 異的電子遷移（electromigration)抗拒性，且低介電常數 (low-k)材料可幫助降低金屬導線之間的電阻·電容延遲效 應（resistance-capacitance，R_C delay effect)，因 itb鋼導線與 低介電常數(l〇w-k)絕緣層已被大量的用於製作單鑲喪結構 (single damascene structure)與雙鑲嵌結構（dual damascene structure)。而且銅製程亦被認為是解決未來深次微米（deep sub-half micron)積體電路金屬連線問題的新技術。 201009928 值得注意的是’習知在利用硬遮罩來形成鑲嵌結構的開 σ後都是在硬遮罩還覆蓋在介電層上的情況下來直接沈積 阻Ρ早層。因此所形成的阻障層除了會覆蓋在開口的底部及 ^電層的側壁表面外，還會同時覆蓋部分的硬遮罩表面。 '、、、&著線寬降低，硬遮罩的阻隔會大幅降低阻障層濺鍍時 的入射角（incident angle)，使阻障層無法在介電層的側壁表 面形成連續的輪廊（continuous profile)。由於不連續的阻障 Ο 層會使後續電鍍的銅金屬層產生缺口（void)並製作出不良 的鑲嵌結構，因此如何改善習知的鑲嵌製程即為現今一重 要課題。 【發明内容】 因此本發明主要是揭露一種形成鑲嵌結構開口的方 法’以解決習知製程中容易使銅金屬層產生缺口的情形。 餐 根據本發明之較佳實施例，本發明形成開口之方法主要 包含有下列步驟。首先提供一半導體基底，且該半導體基 底中包含至少一金屬内連線層。然後形成一堆疊薄膜於半 導體基底上’且堆疊薄膜包含有至少一介電層以及一硬遮 罩。接著利用硬遮罩形成一開口於堆疊薄膜中且不暴露出 遠金屬内連線層。隨後去除硬遮罩，並形成一阻障層於半 導體基底上並覆蓋部分介電層及部分金屬内連線層表面。 201009928 本發明之另一實施例所揭露形成開口的方法包含有下 列步驟。首先提供一半導體基底，且該半導體基底中包含 至少一金屬内連線層。然後形成一堆疊薄膜於半導體基底 上，且堆疊薄膜包含有至少一介電層以及一硬遮罩。接著 利用硬遮罩形成一開口於介電層中且不暴露出金屬内連線 層。隨後去除硬遮罩，並沈積一阻障層於半導體基底上並 覆蓋部分介電層及部分金屬内連線層表面。然後填入一金 @ 屬層於開口中，並進行一化學機械研磨製程，去除部分金 屬層及阻障層並使金屬層表面與介電層表面齊平。 【實施方式】 請參照第1圖至第5圖，第1圖至第5圖本發明第一實 施例製作一單鑲嵌結構之示意圖。如第1圖所示，首先提 供一半導體基底12，例如一矽基底或一絕緣層上覆矽 (silicon-on-insulator, SOI)基底。半導體基底12中包含至少 ❹一金屬内連線層14，且金屬内連線層14則是選自由銅、 鋁、鈦、氮化鈦、钽、氮化钽以及鎢等金屬所構成的群組。 然後形成一堆疊薄膜16於半導體基底12上。其中，堆 疊薄膜16包含複數個介電層18、20、22以及一由金屬所 構成的硬遮罩24。介電層18、20、22分別可為一低介電 常數介電層、超低介電常數介電層或普通介電層，例如多 孔性低介電常數介電材料、碳掺雜氧化物（carbon-doped 8 201009928 oxide，CDO)、有機石夕玻璃（〇SGs)、含氟二氧化石夕(fsGs)、 超低介電常數(111的1〇\¥-]<:;1^<2.5)、氮氧化石夕卻〇1^、氮 化石夕或TEOS(四乙基氧石夕烧）等材料層，且形成介電層18、 20、22的方法包含有化學氣相沈積製程(CvD)、旋轉鍍膜 (spin-coating)製程、電漿加強化學氣相沉積製程 (plasma-enhanced chemical vapor deposition ; PECVD)以及 兩密度電漿化學氣相沉積(high density plasma chemical ❹ vapor deposition ; HDPCVD)等製程方法。 在本實施例中，介電層18是由碳氮化矽（SiCN)所組成 的NBLOK或由氮化矽所構成、介電層2〇是由多孔性低介 電常數材料(porous low-k dielectric)或由 Dow chemical 公 司所提供的SiLK所構成、介電層22是由l氧化石夕所構成， 而硬遮罩24則選自於由欽、氮化鈦、组、氮化组、銘或銅 銘合金所構成的群組。需注意的是，本實施例雖然採用金 屬所構成的硬遮罩24，但不侷限於這種配置方式，本發明 又可視製程需求來選擇其他非金屬材料來做為硬遮罩24， 例如旋塗式玻璃（spin-on glass，SOG)、氧化物(oxides)非晶 碳(amorphous carbon)、多晶矽(polysiiicon)或非晶矽 (amorphous silicon)等材料，此皆屬本發明所涵蓋的範圍。 接者覆蓋一由氣氧化石夕（silicon oxynitride，SiON)所構成 .的絕緣層26在硬遮罩24表面，並對絕緣層26與硬遮罩 201009928 24進行一圖案轉移製程，例如先形成一圖案化光阻層42 在絕緣層26上，然後再進行製程，㈣絕緣 與硬遮罩24中形成一開口 28。氮氧化石夕層％在此製程中 具有底抗反射層（Bottom ARC)的作用。 如第2圖所示，接著利用灰化(ashing)、去杳 製程去除圖案化錄層42與絕緣層26，並繼續進/_ ❹ ❺ 圖案轉移製程。例如利用圖案化硬遮罩24來 丁另 99 '-fe 丁"電層 20、 仃一餘刻製程，將圖案化硬遮罩24中的開 份轉移至介電層2〇、22中，以於介電層2()、2 了 對應的部份開σ 3〇。值得住意的是，此步驟 相二 的部份開口 3。於堆疊薄膜16中，開口 3。可能會=201009928 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of forming an opening, and more particularly to a method of forming an opening of a town structure. [Prior Art] With the advancement of the semiconductor industry, in order to meet the development and design of these high-density integrated devices, the size of various components has been reduced to sub-micron. The performance of these integrated circuits, in addition to the reliability of their internal components, is also limited by the metal interconnects used to transmit the electronic signals between the components. Therefore, with the current trend of shrinking the size of integrated circuits, the integrated power process has moved toward multiple metal interconnects. In order to solve the difficulty of making metal interconnects in the multi-layer, the damascene process has been extensively researched and developed; in addition, since copper (Cu) has more than aluminum (A1) and most Metals have lower resistivity and superior electronmigration resistance, and low dielectric constant (low-k) materials help reduce resistance-capacitance (R_C delay effect) between metal wires. Because itb steel wire and low dielectric constant (l〇wk) insulation layer has been used in a large number of single damascene structure and dual damascene structure (dual damascene structure). Moreover, the copper process is also considered to be a new technology to solve the problem of metal wiring in deep sub-half micron integrated circuits in the future. 201009928 It is worth noting that the conventional method uses a hard mask to form the opening σ of the damascene structure, and directly deposits the early layer of the barrier layer while the hard mask is also covered on the dielectric layer. Therefore, the formed barrier layer covers a portion of the hard mask surface at the same time except that it covers the bottom of the opening and the sidewall surface of the electrical layer. ',,, & The line width is reduced, and the barrier of the hard mask greatly reduces the incident angle of the barrier layer during sputtering, so that the barrier layer cannot form a continuous corridor on the sidewall surface of the dielectric layer. (continuous profile). Since the discontinuous barrier layer causes voids in the subsequently plated copper metal layer and creates a poor mosaic structure, how to improve the conventional damascene process is an important issue today. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a method of forming an opening of a damascene structure to address a situation in which a copper metal layer is easily chipped in a conventional process. Meal According to a preferred embodiment of the present invention, the method of forming an opening of the present invention mainly comprises the following steps. First, a semiconductor substrate is provided, and the semiconductor substrate includes at least one metal interconnect layer. A stacked film is then formed on the semiconductor substrate and the stacked film comprises at least one dielectric layer and a hard mask. A hard mask is then used to form an opening in the stacked film without exposing the far metal interconnect layer. The hard mask is then removed and a barrier layer is formed over the semiconductor substrate and covers portions of the dielectric layer and portions of the metal interconnect layer surface. 201009928 Another embodiment of the invention discloses a method of forming an opening comprising the following steps. First, a semiconductor substrate is provided, and the semiconductor substrate includes at least one metal interconnect layer. A stacked film is then formed over the semiconductor substrate, and the stacked film includes at least one dielectric layer and a hard mask. A hard mask is then used to form an opening in the dielectric layer without exposing the metal interconnect layer. The hard mask is then removed and a barrier layer is deposited over the semiconductor substrate and covers portions of the dielectric layer and portions of the metal interconnect layer surface. Then, a gold layer is filled in the opening, and a chemical mechanical polishing process is performed to remove part of the metal layer and the barrier layer and make the surface of the metal layer flush with the surface of the dielectric layer. [Embodiment] Referring to Figures 1 to 5, Figs. 1 to 5 are schematic views showing a single damascene structure according to a first embodiment of the present invention. As shown in Fig. 1, a semiconductor substrate 12 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 12 includes at least one metal interconnect layer 14, and the metal interconnect layer 14 is selected from the group consisting of metals such as copper, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and tungsten. . A stacked film 16 is then formed on the semiconductor substrate 12. The stacked film 16 includes a plurality of dielectric layers 18, 20, 22 and a hard mask 24 made of metal. The dielectric layers 18, 20, 22 may each be a low-k dielectric layer, an ultra-low dielectric constant dielectric layer or a common dielectric layer, such as a porous low-k dielectric material, a carbon-doped oxide. (carbon-doped 8 201009928 oxide, CDO), organic stone glass (〇SGs), fluorine-containing dioxide (fsGs), ultra-low dielectric constant (111 〇\¥-]<:;1^ <2.5), a layer of material such as nitrous oxide oxide, cerium nitride or TEOS (tetraethyl oxysulfide), and the method of forming the dielectric layers 18, 20, 22 comprises chemical vapor deposition Process (CvD), spin-coating process, plasma-enhanced chemical vapor deposition (PECVD), and high density plasma chemical vapor deposition (high density plasma chemical vapor deposition). Process methods such as HDPCVD). In the present embodiment, the dielectric layer 18 is made of NBLOK composed of tantalum carbonitride (SiCN) or composed of tantalum nitride, and the dielectric layer 2 is made of a porous low dielectric constant material (porous low-k). Dielectric) or SiLK provided by Dow Chemical Company, dielectric layer 22 is composed of oxidized stone, while hard mask 24 is selected from chin, titanium nitride, group, nitride group, Ming Or a group of copper alloys. It should be noted that although the hard mask 24 made of metal is used in this embodiment, it is not limited to this configuration. The present invention can select other non-metal materials as the hard mask 24 according to the process requirements, such as spinning. Materials such as spin-on glass (SOG), oxides, amorphous carbon, polysiiicon, or amorphous silicon are within the scope of the present invention. The insulator covers an insulating layer 26 composed of silicon oxynitride (SiON) on the surface of the hard mask 24, and performs a pattern transfer process on the insulating layer 26 and the hard mask 201009928 24, for example, forming a first The patterned photoresist layer 42 is on the insulating layer 26 and then processed, and (iv) an opening 28 is formed in the insulating and hard mask 24. The oxynitride layer has a bottom anti-reflective layer (Bottom ARC) function in this process. As shown in Fig. 2, the patterned recording layer 42 and the insulating layer 26 are then removed by an ashing, de-icing process, and the pattern transfer process is continued. For example, the patterned hard mask 24 is used to transfer the opening of the patterned hard mask 24 to the dielectric layers 2, 22, by using another 99'-feding " electrical layer 20; For the dielectric layer 2 (), 2 corresponding parts open σ 3 〇. It is worthwhile to note that part of this step is the same as opening 3. In the stacked film 16, the opening 3 is formed. May =
餘刻而延伸進人介電層18，但並不會暴露出半導體H 中的金屬内連線層14。又’根據此步驟所使用的㈣氣體， 〇的侧壁可此會形成一層聚合物層，因此可選擇性地 利用一氧電漿步驟來剝除此聚合物層。 #如第3圖所示，先進行一選擇性飯刻製程，例如利用氣 氣(CIO來進行一電漿蝕刻製程，以去除部分的圖案化硬遮 罩24。在本實施例中，被蝕刻的圖案化硬遮罩24側壁會 口蝕刻氣體的侵蝕而退縮並形成一略微斜角（tapered)的圖 案然後再以ChxFy系的蝕刻化學品而進行另一蝕刻製程 來去除。p分的介電層18，以暴露出金屬内連線層Μ，其中 201009928 χ、y為整數。值得注意的是，在去除部分介電層18的過 程中，介電層22的側壁也會被部分移除，而形成一如圖案 化遮罩層24 —般的斜角狀側壁。 如第4圖所示，依序以濺鍍的方式沈積一阻障層32以 及一晶種層34在圖案化遮罩層24、介電層18、20、22及 金屬内連線層14的裸露表面。阻障層32可由鈦、氮化鈦、 ©钽、氮化钽等單層或複合材料層所構成，除了可避免後續 所填入的銅金屬擴散至介電層18、20、22之外，又可提升 後續覆蓋於單鑲嵌結構上的金屬層與單鑲嵌結構之間的附 著力。晶種層34除了是提供電流一導電路徑之外，另一重 要目的是為先行提供銅的成核層，以利後續之電鍍銅可在 其上成核與成長。然後進行一電鍍製程，以於晶種層34表 面形成一由銅所構成的金屬層3 6，並使金屬層3 6填滿開 口 30。 ❹ 如第5圖所示，進行一或多道化學機械研磨製程，去除 部分金屬層36、晶種層34、阻障層32、圖案化遮罩層24 以及介電層22，使殘留於開口 30中的金屬層36大致上切 齊於介電層20表面。至此即完成本發明第一實施例之單鑲 嵌結構40。 請參照第6圖至第10圖，第6圖至第10圖為本發明第 11 201009928 一實施例製作一單鑲後結構之示意圖。如第6圖所示，首 先提供一半導體基底62，例如一矽基底或一絕緣層上覆矽 (silicon-〇n-insulator，s〇I)基底。半導體基底62中包含至少 一金屬内連線層64，且金屬内連線層64則是選自由銅、 鈦、氮化鈦、钽、氮化钽以及鎢等金屬導體所構成的群組。 然後形成一堆疊薄膜66於半導體基底62上。其中，堆 ❹疊薄膜66包含複數個介電層68、70、72、一由金屬所構 成的硬遮罩74以及一設置於介電層72與硬遮罩74之間的 氮氧化矽（SiON)層（圖未示），且此氤氧化矽層可在後續圖案 化硬遮罩74的時候作為一蝕刻停止層（etchst〇piayer)。介 電層68、70、72分別可為一低介電常數介電層、超低介電 常數介電層或普通介電層，例如多孔性低介電常數介電材 料、奴摻雜氧化物（carb〇n_d〇ped oxide ; CDO)、有機石夕玻 璃（0SGs)、含氟二氧化矽(FSGs)、超低介電常數(Uitra - 1 l〇w-k ; k<2.5)、氮化矽或TEOS(Gg乙基氧矽烷）等材料層’ 且形成介電層68、70、72的方法包含有化學氣相沈積製程 (CVD)、旋轉鍍膜(sPin-coating)製程、電漿加強化學氣相沉 積製权（plasma-enhanced chemical vapor deposition ; PECVD) 以及兩在、度電衆化學氣相沉積（high density plasma chemical vapor deposition ; HDPCVD)等製程方法。 在本實施例中’介電層68是由碳氮化矽（SiCN)所組成 12 201009928 的NBLOK或由氮化矽所構成、介電層70是由多孔性低介 電常數材料(porous low-k dielectric)或由 Dow chemical 公 司所提供的SiLK所構成、介電層72是由四乙基氧矽烷 (tetraethylorthosilicate, TEOS)所構成，而硬遮罩 74 則選自 於由鈦、氮化鈦、鈕、氮化鉅、鋁或銅鋁合金所構成的群 組。需注意的是，本實施例雖然採用金屬所構成的硬遮罩 74 ’但不侷限於這種配置方式，本發明又可視製程需求來 ❹選擇其他非金屬材料來做為硬遮罩74，例如旋塗式玻璃 (spin-οπ glass, SOG)、氧化物（oxides)非晶碳（amorphous carbon)、多晶矽(p〇lysiiiCOI1)或非晶矽（am〇rph〇us silic〇n) 等材料，此皆屬本發明所涵蓋的範圍。 接著再覆蓋一由氮氧化石夕(silicon oxynitride, SiON)所構 成的絕緣層76在硬遮罩74表面，並對絕緣層76與硬遮罩 _ 74進行一圖案轉移製程，例如先形成一圖案化光阻層92 在絕緣層76上，然後再進行一蝕刻製程，以於絕緣層％ 與硬遮罩74中形成一開口 78。應注意，氮氧化石夕層％在 此製程中具有底抗反射層（B〇tt〇mARC)的作用。 如第7圖所不’接著利用灰化(ashing)、去殘清(descum) 製程去除圖案化光阻層92與絕緣層76，並繼續進行另一 圖案轉移製程。例如利用圖案化硬遮罩74來對介電層7〇、 • 72進行-餘刻製程’將圖案化硬遮罩74中的開〇圖案部 13 201009928 份轉移至介電層70、72中， 對應的部份開口 80。值得住音的:’電層70、72中形成相 的部份開口 80於堆疊薄膜 ^此步驟會形成相對應 _而延伸進入介電層68卞並中不可能會因為减 中的金屬内連線層64。-不會暴露出半導體基底62 ❹ 74,然後8再圖進所矛另’先進行一㈣製程來去除圖案化硬遮罩 露出金=:胸來去除部分的介電層-以暴 屬内連線層64’或是直接在 :::::分的介電層68並暴露二 利用圖宰化的_。另需注意的是，本實施例* 圖^硬遮罩74於介電層7G、72中形成部份開口 8〇 之後去除圖案化硬遮罩？4等步驟可以在同一真空系 統中的不同反應室所完成。 接著如第9圖所示’依序以賴的方式沈積-阻障層82 以及一晶種層84在介電層68、70、72及金屬内連線層64 的裸路表© °阻障層82可由欽、氮化欽、组、氮化组等單 層或複合材料層所構成’除了可避免後續所填入的銅金屬 擴放至介電層68、70、72之外，又可提升後續覆蓋於單鎮 嵌結構上的金屬層與單鑲嵌結構之間的附著力。晶種層84 =了是提供電流一導電路徑之外，另一重要目的是為先行 提供鋼的成核層’以利後續之電鍍銅可在其上成核與成 201009928 長。然後進行一電鍍製程，以於晶種層84表面形成一由銅 所構成的金屬層86，並使金屬層86填滿開口 80。 如第10圖所示，進行一或多道化學機械研磨製程，去 除部分金屬層86、晶種層84、阻障層82以及介電層72， 使殘留於開口 80中的金屬層86大致上切齊於介電層70表 面。至此即完成本發明第二實施例之單鑲嵌結構90。 ❹ 請參照第11圖至第16圖，第11圖至第16圖本發明第 三實施例製作一雙鑲嵌結構之示意圖。如第11圖所示，首 先k供一半導體基底102 ’例如一碎基底或一絕緣層上覆 矽（silicon-on-insulator，SOI)基底。半導體基底102中包含 至少一金屬内連線層104，且金屬内連線層104是選自由 銅、鈦、氮化鈦、钽、氮化组以及鎢等金屬導體所構成的 群組。 . 然後形成一堆疊薄膜106於半導體基底102上。其中’ 堆疊薄膜106包含複數個介電層108、110、112以及一由 金屬所構成的硬遮罩U4，其中介電層1〇8、110、112的材 質類似於第一實施例之介電層68、70、72的材質’而硬遮 罩114的材料則類似於第一實施例之硬遮罩74的材質。在 本實施例中，介電層1〇8是由碳氮化矽（SiCN)所組成的 NBLOK、介電層11〇是由多孔性低介電常數材料(P〇rous 15 201009928 low-k dielectric)或由 Dow chemical 公司所提供的 SiLK 戶斤 構成、介電層112是由四乙基氧矽烷(tetraethyi〇rth〇siHcate， TEOS)所構成，而硬遮罩114則包含有鈦、氮化鈦、钽、 氮化组、鋁或銅鋁合金所構成的群組。如同本發明第一實 施例，本實施例雖然採用金屬所構成的硬遮罩114，但不 偈限於這種配置方式，本發明又可視製程需求來選擇其他 非金屬材料來做為硬遮罩114，例如旋塗式玻璃（spin_on ❹ glass，SOG)、氧化物（oxides)、多晶矽（p〇iySiiicon)或非晶碳 (amorphous carbon)等材料，此皆屬本發明所涵蓋的範圍。 接著覆蓋一由氮氧化矽(silicon oxynitride，SiON)所構成 的絕緣層116在硬遮罩114表面，並對絕緣層116與硬遮 罩114進行一圖案轉移製程’例如先形成一圖案化光阻層 142在絕緣層116上’然後再進行一钱刻製程，以於絕緣 層116與硬遮罩114中形成一定義溝渠的開口 118。應注 ® 意，氮氧化矽層Π6在此製程中具有底抗反射層（Bottom ARC)的作用。 如第12圖所示，在利用.灰化(ashing)、去殘潰（descum) 製程去除圖案化光阻層142之後，形成另一圖案化光阻層 120在絕緣層116及介電層112表面。然後利用圖案化光阻 層120進行一蝕刻製程，去除部分的介電層no、in，以 於介電層110、112中形成一部份接觸洞（partial via)122。 16 201009928 如同先前之實施例，本蝕刻製程會於介電層110、112中形 成相對於圖案化光阻層120的部份接觸洞122但不會暴露 出半導體基底102中的金屬内連線層104。 如第13圖所示，先利用灰化(ashing)、去殘潰（descum) 製程去除圖案化光阻層120及絕緣層116，然後利用圖案 化硬遮罩114進行另一蝕刻製程，以於介電層110、112中 ^ 形成對應圖案化硬遮罩114開口的溝渠124。應注意的是， 溝渠124可能會因為過度餘刻而延伸進入介電層108，但 並不會暴露出半導體基底102中的金屬内連線層104。 接著如第14圖所示，先進行一蝕刻製程來移除圖案化 硬遮罩114，然後再進行另一蝕刻製程來去除溝渠124中 殘餘的介電層108以暴露出金屬内連線層104,或是直接 在去除圖案化硬遮罩114的同時去除溝渠124中殘餘的介 參 電層108並暴露出金屬内連線層104，此皆屬本發明所涵 蓋的範圍。另外需注意的是，本實施例從形成圖案化光阻 層120到形成溝渠124等步驟均可以在同一真空系統中的 不同反應室所完成。 然後如第15圖所示，依序形成一阻障層126以及一晶 種層128在介電層108、110、112及金屬内連線層104表 面。如同先前實施例所述，阻障層126是由鈦、氮化鈦、 17 201009928 組、氮化组等單一材料層所構成，除了可避免後續所填入 的銅金屬擴散至介電層108、110、112之外，又可提升後 續覆蓋於單鑲嵌結構上的金屬層與單鑲嵌結構之間的附著 力。隨後進行一電鍍製程，以於晶種層128表面形成一由 銅所構成的金屬層130，並使金屬層130填滿溝渠124以 及接觸洞122。 ©如第16圖所示，進行一或多道化學機械研磨製程，去 除介電層110表面的部分金屬層130、晶種層128、阻障層 126以及介電層112,使殘留於溝渠124中的金屬層130大 致上切齊於介電層110表面。至此即完成本發明第三實施 例之雙鑲嵌結構140。另需注意的是，本實施例是以第二 實施例中完全去除圖案化硬遮罩的方式來結合雙鑲嵌製 程。但不侷限於這個作法，本發明又可融合第一實施例中 僅部分去除圖案化硬遮罩的方式來完成雙鑲嵌製程，此均 ® 屬本發明所涵蓋的範圍。 請參照第17圖至第19圖，第17圖至第19圖本發明第 四實施例製作一雙鑲嵌結構之示意圖。如第Π圖所示，本 發明可先進行第12圖至第13圖的製程並以氮氧化矽來形 成介電層112，然後再於圖案化硬遮罩114、介電層110及 112中形成對應的接觸洞122與溝渠124。 18 201009928 接著進行一選擇性蝕刻製程，例如利用氣氣(ci2)來進行 一電漿蝕刻製程，以去除部分的圖案化硬遮罩114。在本 實施例中，被蝕刻的圖案化硬遮罩114側壁會因蝕刻氣體 的侵钱而退縮並形成一略微斜角（tapered)的圖案。 如第18圖所示，再以ChxFy系的触刻化學品進行另一 蝕刻製程來去除部分的介電層108，以暴露出金屬内連線 ^ 層104,其中x、y為整數。值得注意的是，在去除部分介 電層丨08的過程中，介電層112的側壁也會被部分移除， 而形成一如圖案化遮罩層114 一般的斜角狀侧壁。 如第19圖所示，依序形成一阻障層126以及一晶種層 128在圖案化硬遮罩114、介電層108、110、112及金屬内 連線層104表面。同先前所述之實施例，阻障層126可由 鈦、氮化鈦、钽、氮化钽等單一材料層所構成。隨後進行 ❿一電鍍製程，以於晶種層128表面形成一由銅所構成的金 屬層130，並使金屬層130填滿溝渠124以及接觸洞122。 最後可進行一或多道化學機械研磨製程，去除介電層110 表面的部分金屬層130、晶種層128、阻障層126以及介電 層112，使殘留於溝渠124中的金屬層130大致上切齊於 介電層110表面.。 綜上所述，本發明主要是在介電層中尚未完全蝕刻出所 19 201009928 需之鑲嵌圖案以及沈積阻障層前先完全去除或部分去除用 來形成鑲嵌結構開口的硬遮罩，然後再進行後續所需的濺 鍍與電鍍製程。由於去除此硬遮罩的步驟可大幅提昇阻障 層濺鍍時的入射角，因此在濺鍍阻障層的時候可在介電層 側壁表面形成具有連續輪廓的阻障層，並使後續覆蓋在阻 障層上的銅金屬層不會因阻障層的不連續而產生缺口。 ^ 以上所述僅為本發明之較佳實施例，凡依本發明申請 ❿ 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 【圖式簡單說明】 第1圖至第5圖本發明第一實施例製作一單鑲嵌結構之示 意圖。 第6圖至第10圖本發明第二實施例製作一單鑲嵌結構之示 © 意圖。 第11圖至第16圖本發明第三實施例製作一雙鑲嵌結構之 示意圖。 第17圖至第19圖本發明第四實施例製作一雙鑲嵌結構之 示意圖。 【主要元件符號說明】 12 半導體基底 14 金屬内連線層 20 201009928It extends all the way into the dielectric layer 18, but does not expose the metal interconnect layer 14 in the semiconductor H. Further, according to the (iv) gas used in this step, the sidewall of the crucible may form a polymer layer, so that the polymer layer may be selectively stripped by an oxygen plasma step. # As shown in Fig. 3, a selective rice etching process is first performed, for example, using a gas plasma (CIO to perform a plasma etching process to remove a portion of the patterned hard mask 24. In this embodiment, it is etched. The patterned hard mask 24 sidewalls are retracted by the etching of the etching gas and form a slightly tapered pattern and then removed by another etching process using ChxFy-based etching chemicals. Layer 18 to expose a metal interconnect layer layer, wherein 201009928 χ, y are integers. It is noted that the sidewall of dielectric layer 22 is also partially removed during removal of portion of dielectric layer 18. A beveled sidewall is formed as in the patterned mask layer 24. As shown in FIG. 4, a barrier layer 32 and a seed layer 34 are sequentially deposited in a patterned mask layer by sputtering. 24. The exposed surfaces of the dielectric layers 18, 20, 22 and the metal interconnect layer 14. The barrier layer 32 may be composed of a single layer or a composite layer of titanium, titanium nitride, germanium or tantalum nitride, in addition to Avoiding the subsequent filling of the copper metal to the outside of the dielectric layers 18, 20, 22, and lifting Covering the adhesion between the metal layer on the single damascene structure and the single damascene structure. In addition to providing a current-conducting path, the seed layer 34 is another important purpose to provide a copper nucleation layer in advance for subsequent The electroplated copper can be nucleated and grown thereon. Then, an electroplating process is performed to form a metal layer 3 made of copper on the surface of the seed layer 34, and fill the opening 30 with the metal layer 36. As shown in FIG. 5, one or more chemical mechanical polishing processes are performed to remove portions of the metal layer 36, the seed layer 34, the barrier layer 32, the patterned mask layer 24, and the dielectric layer 22 to remain in the opening 30. The metal layer 36 is substantially tangential to the surface of the dielectric layer 20. Thus, the single damascene structure 40 of the first embodiment of the present invention is completed. Referring to FIGS. 6 to 10, FIGS. 6 to 10 are the present invention. 11th 201009928 An embodiment is a schematic diagram of a single inlaid structure. As shown in FIG. 6, a semiconductor substrate 62 is first provided, such as a germanium substrate or an insulating layer (silicon-〇n-insulator, s〇 I) a substrate. The semiconductor substrate 62 comprises at least one metal The wire layer 64, and the metal interconnect layer 64 is selected from the group consisting of metal conductors such as copper, titanium, titanium nitride, tantalum, tantalum nitride, and tungsten. Then, a stacked film 66 is formed on the semiconductor substrate 62. The stacking film 66 includes a plurality of dielectric layers 68, 70, 72, a hard mask 74 made of metal, and a bismuth oxynitride disposed between the dielectric layer 72 and the hard mask 74 ( a SiON) layer (not shown), and the tantalum oxide layer can serve as an etch stop layer for subsequent patterning of the hard mask 74. The dielectric layers 68, 70, 72 can each be a low Dielectric constant dielectric layer, ultra-low dielectric constant dielectric layer or common dielectric layer, such as porous low-k dielectric material, carb〇n_d〇ped oxide (CDO), organic stone Glass (0SGs), fluorine-containing cerium oxide (FSGs), ultra-low dielectric constant (Uitra - 1 l〇wk; k < 2.5), tantalum nitride or TEOS (Gg ethyl oxane) Methods of forming dielectric layers 68, 70, 72 include chemical vapor deposition (CVD), spin coating (spin-coating) processes, plasma enhancement Plasma-enhanced chemical vapor deposition (PECVD) and two methods of high-density plasma chemical vapor deposition (HDPCVD). In the present embodiment, the dielectric layer 68 is made of tantalum carbonitride (SiCN) 12 201009928 NBLOK or made of tantalum nitride, and the dielectric layer 70 is made of porous low dielectric constant material (porous low- k dielectric) or SiLK provided by Dow Chemical Co., the dielectric layer 72 is composed of tetraethylorthosilicate (TEOS), and the hard mask 74 is selected from titanium, titanium nitride, A group of buttons, nitrided giant, aluminum or copper-aluminum alloy. It should be noted that although the present embodiment uses a hard mask 74' made of metal, but is not limited to this configuration, the present invention can select other non-metal materials as the hard mask 74 depending on the process requirements, for example, Spin-us glass (SOG), oxides amorphous carbon, polycrystalline germanium (p〇lysiiiCOI1) or amorphous germanium (am〇rph〇us silic〇n), etc. All are within the scope of the invention. Then, an insulating layer 76 made of silicon oxynitride (SiON) is overlaid on the surface of the hard mask 74, and a pattern transfer process is performed on the insulating layer 76 and the hard mask _74, for example, a pattern is formed first. The photoresist layer 92 is on the insulating layer 76, and then an etching process is performed to form an opening 78 in the insulating layer % and the hard mask 74. It should be noted that the oxynitride layer has a bottom anti-reflection layer (B〇tt〇mARC) in this process. The patterning photoresist layer 92 and the insulating layer 76 are removed by an ashing and descum process, as in Fig. 7, and another pattern transfer process is continued. For example, by using the patterned hard mask 74 to perform dielectric processing on the dielectric layers 7〇, 72, the opening pattern portion 13 201009928 in the patterned hard mask 74 is transferred to the dielectric layers 70, 72, Corresponding partial opening 80. It is worthy of the sound: 'The partial opening 80 of the phase formed in the electrical layers 70, 72 is formed on the stacked film. This step will form a corresponding _ and extend into the dielectric layer 68 卞 and it is impossible to reduce the metal interconnect layer. 64. - Do not expose the semiconductor substrate 62 ❹ 74, then 8 then enter the spear and then 'first perform a (4) process to remove the patterned hard mask to expose the gold =: chest to remove part of the dielectric layer - to violently connect The line layer 64' is either directly at the dielectric layer 68 of ::::: and exposing the _ by the use of the graph. It should be noted that, in this embodiment, the hard mask 74 is formed in the dielectric layers 7G, 72 to form a partial opening 8 〇 after removing the patterned hard mask. Steps 4 can be done in different reaction chambers in the same vacuum system. Then, as shown in FIG. 9, the deposition of the barrier layer 82 and the seed layer 84 on the dielectric layers 68, 70, 72 and the metal interconnect layer 64 are shown in FIG. The layer 82 may be composed of a single layer or a composite material layer such as a Qin, a nitrided group, a group, a nitrided group, etc., in addition to avoiding the subsequent filling of the copper metal into the dielectric layers 68, 70, 72, and The adhesion between the metal layer and the single damascene structure covering the single-town embedded structure is subsequently improved. The seed layer 84 = provides a current-conducting path, and another important purpose is to provide a nucleation layer of steel first, so that the subsequent electroplated copper can be nucleated and formed on 201009928. An electroplating process is then performed to form a metal layer 86 of copper on the surface of the seed layer 84 and to fill the opening 80 with the metal layer 86. As shown in FIG. 10, one or more chemical mechanical polishing processes are performed to remove portions of the metal layer 86, the seed layer 84, the barrier layer 82, and the dielectric layer 72, so that the metal layer 86 remaining in the opening 80 is substantially It is aligned with the surface of the dielectric layer 70. Thus, the single damascene structure 90 of the second embodiment of the present invention is completed. ❹ Referring to Figures 11 to 16, Figures 11 through 16 show a schematic view of a dual damascene structure in accordance with a third embodiment of the present invention. As shown in Fig. 11, first, a semiconductor substrate 102' is used, for example, a broken substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 102 includes at least one metal interconnect layer 104, and the metal interconnect layer 104 is selected from the group consisting of copper, titanium, titanium nitride, tantalum, nitride groups, and metal conductors such as tungsten. A stacked film 106 is then formed over the semiconductor substrate 102. Wherein the stacked film 106 comprises a plurality of dielectric layers 108, 110, 112 and a hard mask U4 made of metal, wherein the dielectric layers 1 〇 8, 110, 112 are made of a dielectric similar to that of the first embodiment. The material of the layers 68, 70, 72' and the material of the hard mask 114 are similar to those of the hard mask 74 of the first embodiment. In the present embodiment, the dielectric layer 1〇8 is made of tantalum carbonitride (SiCN), and the dielectric layer 11 is made of a porous low dielectric constant material (P〇rous 15 201009928 low-k dielectric). Or the SiLK package provided by Dow Chemical Company, the dielectric layer 112 is composed of tetraethyi〇rth〇siHcate (TEOS), and the hard mask 114 contains titanium and titanium nitride. Group of 钽, 钽, nitrided, aluminum or copper-aluminum alloys. As in the first embodiment of the present invention, although the hard mask 114 made of metal is used in the embodiment, it is not limited to this configuration. The present invention can select other non-metal materials as the hard mask 114 according to the process requirements. For example, spin-on ❹ glass (SOG), oxides, polysilicon (p〇iySiiicon) or amorphous carbon, etc., are all within the scope of the present invention. Then, an insulating layer 116 made of silicon oxynitride (SiON) is covered on the surface of the hard mask 114, and a pattern transfer process is performed on the insulating layer 116 and the hard mask 114. For example, a patterned photoresist is formed first. The layer 142 is then 'on the insulating layer 116' and then subjected to a process to form an opening 118 defining the trench in the insulating layer 116 and the hard mask 114. It should be noted that the yttria layer 6 has a bottom anti-reflective layer (Bottom ARC) in this process. As shown in FIG. 12, after the patterned photoresist layer 142 is removed by an ashing and descum process, another patterned photoresist layer 120 is formed on the insulating layer 116 and the dielectric layer 112. surface. An etching process is then performed using the patterned photoresist layer 120 to remove portions of the dielectric layers no, in to form a partial via 122 in the dielectric layers 110, 112. 16 201009928 As in the previous embodiment, the etching process forms a portion of the contact holes 122 in the dielectric layers 110, 112 relative to the patterned photoresist layer 120 but does not expose the metal interconnect layers in the semiconductor substrate 102. 104. As shown in FIG. 13, the patterned photoresist layer 120 and the insulating layer 116 are removed by an ashing and descum process, and then another etching process is performed using the patterned hard mask 114. The trenches 124 corresponding to the openings of the patterned hard mask 114 are formed in the dielectric layers 110, 112. It should be noted that the trench 124 may extend into the dielectric layer 108 due to excessive remnants, but does not expose the metal interconnect layer 104 in the semiconductor substrate 102. Next, as shown in FIG. 14, an etching process is performed to remove the patterned hard mask 114, and then another etching process is performed to remove the residual dielectric layer 108 in the trench 124 to expose the metal interconnect layer 104. The removal of the residual dielectric layer 108 in the trench 124 and the exposing of the metal interconnect layer 104 directly while removing the patterned hard mask 114 are within the scope of the present invention. It should also be noted that the steps from forming the patterned photoresist layer 120 to forming the trench 124 in this embodiment can be performed in different reaction chambers in the same vacuum system. Then, as shown in Fig. 15, a barrier layer 126 and a seed layer 128 are sequentially formed on the surfaces of the dielectric layers 108, 110, 112 and the metal interconnect layer 104. As described in the previous embodiment, the barrier layer 126 is composed of a single material layer such as titanium, titanium nitride, 17 201009928, nitrided group, etc., except that the subsequently filled copper metal is prevented from diffusing to the dielectric layer 108, In addition to 110, 112, the adhesion between the metal layer covering the single damascene structure and the single damascene structure can be improved. An electroplating process is then performed to form a metal layer 130 of copper on the surface of the seed layer 128, and the metal layer 130 fills the trench 124 and the contact hole 122. As shown in FIG. 16, one or more chemical mechanical polishing processes are performed to remove a portion of the metal layer 130, the seed layer 128, the barrier layer 126, and the dielectric layer 112 on the surface of the dielectric layer 110 so as to remain in the trench 124. The metal layer 130 is substantially tangential to the surface of the dielectric layer 110. Thus, the dual damascene structure 140 of the third embodiment of the present invention is completed. It should also be noted that this embodiment incorporates the dual damascene process in such a manner that the patterned hard mask is completely removed in the second embodiment. However, the present invention is not limited to this practice, and the present invention can be combined with the method of partially removing the patterned hard mask in the first embodiment to complete the dual damascene process, which are all covered by the present invention. Referring to Figures 17 to 19, Figs. 17 to 19 show a schematic view of a double damascene structure according to a fourth embodiment of the present invention. As shown in the figure, the present invention can firstly perform the processes of FIGS. 12 to 13 and form the dielectric layer 112 with hafnium oxynitride, and then pattern the hard mask 114, the dielectric layers 110 and 112. Corresponding contact holes 122 and trenches 124 are formed. 18 201009928 Next, a selective etching process is performed, for example, using a gas (ci2) to perform a plasma etching process to remove portions of the patterned hard mask 114. In this embodiment, the sidewall of the etched patterned hard mask 114 is retracted by the intrusion of the etching gas and forms a slightly tapered pattern. As shown in Fig. 18, another etching process is performed with the ChxFy-based etchant to remove a portion of the dielectric layer 108 to expose the metal interconnect layer 104, where x and y are integers. It should be noted that during the removal of a portion of the dielectric layer 丨08, the sidewalls of the dielectric layer 112 are also partially removed to form a beveled sidewall such as the patterned mask layer 114. As shown in Fig. 19, a barrier layer 126 and a seed layer 128 are sequentially formed on the surface of the patterned hard mask 114, the dielectric layers 108, 110, 112, and the metal interconnect layer 104. As with the previously described embodiments, the barrier layer 126 may be comprised of a single layer of material such as titanium, titanium nitride, tantalum, or tantalum nitride. Subsequently, a first electroplating process is performed to form a metal layer 130 of copper on the surface of the seed layer 128, and the metal layer 130 fills the trench 124 and the contact hole 122. Finally, one or more chemical mechanical polishing processes may be performed to remove portions of the metal layer 130, the seed layer 128, the barrier layer 126, and the dielectric layer 112 on the surface of the dielectric layer 110, so that the metal layer 130 remaining in the trench 124 is substantially The upper surface is tangent to the surface of the dielectric layer 110. In summary, the present invention is mainly to completely remove or partially remove the hard mask used to form the opening of the mosaic structure before completely etching the mosaic pattern required by the 19 201009928 in the dielectric layer and before depositing the barrier layer. The subsequent sputtering and plating processes required. Since the step of removing the hard mask can greatly increase the incident angle when the barrier layer is sputtered, a barrier layer having a continuous contour can be formed on the sidewall surface of the dielectric layer when the barrier layer is sputtered, and the subsequent coverage is performed. The copper metal layer on the barrier layer does not become a gap due to the discontinuity of the barrier layer. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the application of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 5 show the intention of fabricating a single damascene structure in the first embodiment of the present invention. 6 to 10 show a single damascene structure of the second embodiment of the present invention. 11 to 16 are views showing a double damascene structure of a third embodiment of the present invention. 17 to 19 are views showing a fourth embodiment of the present invention for fabricating a dual damascene structure. [Main component symbol description] 12 Semiconductor substrate 14 Metal interconnection layer 20 201009928
16 堆疊薄膜 18 介電層 20 介電層 22 介電層 24 硬遮罩 26 絕緣層 28 開口 30 開口 32 阻障層 34 晶種層 36 金屬層 38 介電層 40 單鑲嵌結構 42 圖案化光阻層 62 半導體基底 64 金屬内連線層 66 堆疊薄膜 68 介電層 70 介電層 72 介電層 74 硬遮罩 76 絕緣層 78 開口 80 開口 82 阻障層 84 晶種層 86 金屬層 90 單鑲嵌結構 92 圖案化光阻層 102 半導體基底 104 金屬内連線層 106 堆疊薄膜 108 介電層 110 介電層 112 介電層 114 硬遮罩 116 絕緣層 118 開口 120 圖案化光阻層 122 接觸洞 124 溝渠 126 阻障層 128 晶種層 130 金屬層 21 201009928 圖案化光阻層 140 雙鑲嵌結構 14216 stacked film 18 dielectric layer 20 dielectric layer 22 dielectric layer 24 hard mask 26 insulating layer 28 opening 30 opening 32 barrier layer 34 seed layer 36 metal layer 38 dielectric layer 40 single damascene structure 42 patterned photoresist Layer 62 semiconductor substrate 64 metal interconnect layer 66 stacked film 68 dielectric layer 70 dielectric layer 72 dielectric layer 74 hard mask 76 insulating layer 78 opening 80 opening 82 barrier layer 84 seed layer 86 metal layer 90 single damascene Structure 92 patterned photoresist layer 102 semiconductor substrate 104 metal interconnect layer 106 stacked film 108 dielectric layer 110 dielectric layer 112 dielectric layer 114 hard mask 116 insulating layer 118 opening 120 patterned photoresist layer 122 contact hole 124 Ditch 126 barrier layer 128 seed layer 130 metal layer 21 201009928 patterned photoresist layer 140 dual damascene structure 142
22twenty two