201007902 九、發明說明： 【發明所屬之技術領域】 ，且㈣+係，t種主動式半導體元件的晶片技術領域 二㈣i係& =種能省略焊線或焊球(凸塊)等半導體元 域程’且月匕與印刷電路基板【⑽】和封裝基板 (59)(轉接板)直接形成電氣連接之半導體晶片結構。 【發明之先前技術】 ❹201007902 IX. Description of the invention: [Technical field of invention], and (4) + system, wafer technology of t kinds of active semiconductor elements 2 (4) i series & = can omit semiconductor elements such as bonding wires or solder balls (bumps) The semiconductor wafer structure in which the domain and the printed circuit board [(10)] and the package substrate (59) (array plate) are directly electrically connected. [Prior Art of the Invention] ❹
雷六按f動式半導體元件(電晶體或1C)泛指除了電感、 ’―般來說主動式半導體元件泛指除了電 二：二、電阻外’如二極體、積體電路、電晶體 等）、大功率半導體元件、受光元件、 t 鎵元件等多數㈣體元件，而线式半導體 兀件(電晶體或IC)的製作法係經由下列步驟製造出來的： •先從邦械鍺(Ga)等元素製作出半導縣板之製程。 •前段製程：在半導體基板上形成半導體晶片之製程。 •後段製程：將半導體晶片封裝成1C之製程。 、上述製程中，前段製歡晶片係如第二®所示，該主 動式半導體晶片係先從元素週期表中的㈣族元素(石夕⑶) 、鍺(Ga))以及第π族、第v族的化合物(坤化鎵⑴仏）、 磷化鎵(GaP))等元素製作出半導體基板（3)。 在半導體基板表面反覆進行黃光微影、蝕刻及雜質 擴散製程，藉由熱擴散法⑽ermai diffusi〇n meth〇d卜離 子注入法（1〇n-mjecti〇n method)或磊晶成長法（氣相成長 法）(epitaxial growth method)形成不同磊晶成長層（31) 5 201007902 卜）’並將鋁、銅、鈦、鉻 片表面形成電極（51)( ^ ’進而形成各種不同的半 及絕緣層（32)(如氧化膜層等） 、白金、金或合金等蒸鍍在晶片 如閘極、汲極及源極等）及配線， 導體晶片（5)。 、Ray six press f-type semiconductor components (transistor or 1C) refers to the exception of inductors, '------------------------------------------------------------------------------------------- ()), high-power semiconductor components, light-receiving components, t-gallium components and other (four) body components, and the production method of linear semiconductor components (transistors or ICs) is manufactured through the following steps: Ga) and other elements make the process of the semi-conductor plate. • Front-end process: A process for forming a semiconductor wafer on a semiconductor substrate. • Back-end process: The process of packaging a semiconductor chip into a 1C process. In the above process, the front segment of the wafer is as shown in the second ®, and the active semiconductor wafer is firstly derived from the group (4) elements (Shi Xi (3)), 锗 (Ga), and the π, A semiconductor substrate (3) is produced from an element such as a compound of the v group (gallium gallium (1) ruthenium) or gallium phosphide (GaP). Yellow lithography, etching and impurity diffusion processes are repeatedly performed on the surface of the semiconductor substrate by thermal diffusion method (10) ermai diffusi〇n meth〇d ion implantation method (1〇n-mjecti〇n method) or epitaxial growth method (vapor phase growth) (epitaxial growth method) forming different epitaxial growth layers (31) 5 201007902 卜)' and forming aluminum, copper, titanium, chrome sheets on the surface of the electrode (51) (^' to form a variety of different semi-insulating layers ( 32) (such as oxide film layer, etc.), platinum, gold or alloy, etc., deposited on wafers such as gates, drains, and sources, and wiring, conductor wafers (5). ,
習式第二種製程為球閘陣列封裝【Ball Grid Array ; 抓A】’其躲晶片⑸上形成有複數與外部進行電 礼連，的電極（51)，而其封裝方式係先行將晶片（5 )固疋至一導線板（50)上，再以打線技術於晶片（5 )電極（51)與導線板（5〇)之積體電路（58)接點間 串接連接線（54) ’且以封膠技術進行封裝，使晶片（ 5)、與連接線（54)包覆於構裝體（55)内，製成主動 式半導體元件（20)，並利用植球技術於導線板（5〇) 外側表面預先設置固接用的焊球（凸塊）（8〇 )，至於固 )固定至-具複數接腳（52)的導線架（53)上，再以 打線技術於晶片（5)電極（51)與接腳（52)間串接 連接線（54) ’且以封膠技術進行封裝，使晶片⑴ J連接線（54)包覆於構裝體（55)内，製成主動式半 體元件（10)，至於固定方式，則係透過前述導線架 (53)的接腳（52)固設於基板（9〇)的對應印刷電路 201007902 ^方式則係利用别述導線板（π)的焊球（凸塊）（so i焊固於電路基板（9G)對應的印刷電路（9D上，而 完成其固定之製程； 少習式第三種製程為覆晶封骏【Flip ChiP;FC】，其 係於aB片（5)上形成有複數與外部進行電氣連接的電 極（51)，接著透過半導體製程於晶片（5)之電極（ 51)上，利用植球技術形成焊球（凸塊）【如錫球 或金球】’再將晶片⑸以焊球（凸塊）（8〇)固定於一 ❹封裝基板（59)(轉接板）之積體電路（58)上，再以注 膠技術進打封裝，使晶片（5)與焊球（凸塊）（8〇)包覆 於構裝體（55)内，製成主動式半導體元件（30)。該 封裝基板（轉接板）（59)再利用植球技術預先設置固接 用的焊球（凸塊）（80)，至於該覆晶封裝【Flip Chip ; FC】的固定方式，則係利用前述封裝基板（轉接板）（59 )的焊球（凸塊）（80)焊固於電路基板（90)對應的印 刷電路（91)上’而完成其固定之製程。 ❹ 至於晶圓級封裝【Wafer Level Chip Scale Package ;WLCSP】，其係於晶片（5)上形成有複數與外部進 行電氣連接的電極（51)，而其封裝方式係先行利用半 導體製程於晶片（5)之電極（51)上形成焊球（凸塊）（ 80)【如錫球或金球】。至於晶圓級封裝【Wafer Level Chip Scale Package ; WLCSP】的固定方式，則係利用前 述晶片（5)的焊球（凸塊）（80)直接連固於電路基板（ 90)對應的印刷電路（91)上，而完成其固定之製程。 由於前述各習式的主動式半導體元件製程中，由於晶 201007902 片（5)本身因電極（51)的面積小，都必須經由多道的後 * 段製程(如固晶、焊線、植球或膠裝等），才能製成主動式半 導體元件（10) (2〇) (30) ’由於製程繁瑣，必然會 使良率降低且製造成本增加。又晶圓級封裝製程之晶片 (5)在實際使用上，雖然無需如前三種封裝方式（如固晶 、焊線、或膠裝等），但還是因為其電極（51)的面積小， 因此仍需經由植球技術，才能將預先形成焊球(凸塊）（8〇) 的晶片（5)，藉由焊球（凸塊）（80)間接或直接與電路基 〇 板（90)的印刷電路（91)連結、導通、固定，且該晶片 (5)在形成焊球（凸塊）（80)的封裝製程中，不僅增加製 程的流程與時間，亦容易發生焊球(凸塊）球徑或高度 不足或位置偏移等問題，造成產品不良率的提高，大幅ς 高了製作成本。 故上述各習式的主動式半導體元件後段製程中 φ 特殊專用的設備【如焊線機、植球機及塑脂包裝 :成等1增加且價格昂責及製程繁項™率降低及ί 舆製=此釺事相關產業之研發 f程時，所面臨的問題深入探討，並積極尋求解決 經過長期努力之研究與發展，終於成:一1道， 體晶片結構’藉以克服前述主動式半導體I件需使=導 電路(==製程’才能固設於封裝基板(轉接板)ΐ 電路基板【㈣】的印刷電路上的_ 钱板)或 201007902 【發明内容】The second process of the formula is a ball grid array package [Ball Grid Array; grab A] 'the hidden chip (5) is formed with a plurality of electrodes (51) connected to the outside, and the package method is to advance the wafer ( 5) Fixing to a wire plate (50), and then connecting the wire (54) between the contacts of the integrated circuit (58) of the wafer (5) electrode (51) and the wire plate (5〇) by wire bonding technology. The package is encapsulated, and the wafer (5) and the connecting wire (54) are wrapped in the package body (55) to form an active semiconductor component (20), and the ball-fed technique is used for the wire guide plate ( 5〇) The outer surface is pre-set with solder balls (bumps) (8〇) for fixing, and fixed to the lead frame (53) with multiple pins (52), and then wire-bonded to the wafer ( 5) The connecting wire (54) is connected in series between the electrode (51) and the pin (52) and encapsulated by a sealing technique, so that the wafer (1) J connecting wire (54) is wrapped in the structure body (55), and is made. The active half body component (10), as for the fixing mode, is fixed to the corresponding printed circuit 20100790 of the substrate (9〇) through the pin (52) of the lead frame (53). 2 ^ mode is to use the soldering ball (bump) of the wire plate (π) (so i soldered to the printed circuit (9D) corresponding to the printed circuit (9D) to complete its fixed process; less The three processes are Flip ChiP (FC), which is formed on the aB sheet (5) with a plurality of electrodes (51) electrically connected to the outside, and then through the semiconductor process on the electrodes of the wafer (5) ( 51), using the ball placement technology to form solder balls (bumps) [such as solder balls or gold balls] 'replace the wafer (5) with solder balls (bumps) (8 〇) on a package substrate (59) The integrated circuit (58) of the board is further packaged by a glue injection technique, and the wafer (5) and the solder ball (bump) (8 〇) are wrapped in the package body (55) to be made. An active semiconductor component (30). The package substrate (array plate) (59) is further provided with solder balls (bumps) (80) for fixing using a ball bonding technique, and the flip chip package [Flip Chip; FC] The fixing method is to solder the solder ball (bump) (80) of the package substrate (array) (59) to the corresponding printed circuit of the circuit board (90). (91) On the 'completed its fixed process. ❹ As for the wafer level package [Wafer Level Chip Scale Package; WLCSP], it is formed on the wafer (5) with a plurality of electrodes (51) electrically connected to the outside, The package method is to first form a solder ball (bump) (80) such as a solder ball or a gold ball on the electrode (51) of the wafer (5) by using a semiconductor process. As for the wafer level package [Wafer Level Chip Scale Package] The fixing method of the WLCSP is performed by directly bonding the solder ball (bump) (80) of the wafer (5) to the corresponding printed circuit (91) of the circuit substrate (90) to complete the fixing process. Due to the above-mentioned conventional active semiconductor device manufacturing process, since the crystal 201007902 piece (5) itself has a small area of the electrode (51), it must pass through multiple post-stage processes (such as solid crystal, wire bonding, and ball placement). Or a plastic device (10) (2) (30) 'Because of the cumbersome process, the yield will be reduced and the manufacturing cost will increase. The wafer-level packaging process wafer (5) is actually used, although it does not need the first three packaging methods (such as solid crystal, wire bonding, or glue mounting), but because the electrode (51) has a small area, It is still necessary to pass the ball placement technique to pre-form the solder ball (bump) (8 〇) wafer (5) by solder balls (bumps) (80) indirectly or directly with the circuit substrate raft (90). The printed circuit (91) is connected, turned on, and fixed, and the wafer (5) not only increases the process and time of the process, but also easily causes solder balls (bumps) in the process of forming the solder balls (bumps) (80). Problems such as insufficient ball diameter or height or positional shifts have led to an increase in product defect rate, which has greatly increased production costs. Therefore, in the above-mentioned various types of active semiconductor components in the back-end process, φ special special equipment [such as wire bonding machine, ball planting machine and plastic packaging: the increase of 1 and the price and the process TM rate reduction and ί 舆System = The development of this industry related to the industry, the problems faced in-depth discussion, and actively seek to solve the long-term efforts of research and development, and finally become: one, the body wafer structure 'to overcome the aforementioned active semiconductor I The device needs to make the = conduction circuit (== process 'can be fixed on the package substrate (array board) 电路 the circuit board [(4)] on the printed circuit _ money board) or 201007902 [invention content]
，获以靖& 月主要目的在於提供一種半導體晶片結構 、拿I:、主動式半導體^件無需經由封裝製程即可直接 ^ 、固&於封裝基板（轉接板）或電路基板 [PCB 】上’而細雜製_職降低㈣成本之目的。The main purpose of obtaining the Jing & month is to provide a semiconductor wafer structure, take I:, active semiconductor components without the need to go through the packaging process to directly ^, solid & on the package substrate (arbitrage board) or circuit substrate [PCB 】 On 'and fine miscellaneous _ job lower (four) cost purpose.
又，本發明另一目 藉以提鬲主動式半導體 運作的穩定性。 的在於提供一種半導體晶片結構， 元件的散熱效果，提升半導體元件 為此’本發明主要係透過下列的技術手段，來具體實 現該半導體晶片結構可直接與電路基板【pCB】 的印刷電 路連結、導通與固定之目的與效能： 、 該主動式半導體晶片係先從元素週期表中的第IV族元 素（矽（Si)、鍺(Ga))以及第π族、第V族的化合物（砷化鎵 (GaAs)、磷化鎵(GaP))等元素製作出半導體基板。Further, another object of the present invention is to improve the stability of active semiconductor operation. The invention provides a semiconductor wafer structure, a heat dissipation effect of components, and a semiconductor device for improving the same. The present invention mainly realizes that the semiconductor wafer structure can be directly connected and electrically connected to a printed circuit of a circuit substrate [pCB] through the following technical means. And the purpose and effectiveness of the fixation: The active semiconductor wafer is firstly from the Group IV elements of the periodic table (矽(Si), 锗(Ga)) and the πth, Vth group of compounds (gallium arsenide) A semiconductor substrate is produced by elements such as (GaAs) or gallium phosphide (GaP).
在半導體基板表面反覆進行黃光微影、蝕刻及雜質 擴散製私’藉由熱擴散法(thermai diffusion method)、離 子注入法（ion-injection method)或磊晶成長法（氣相成長 法)(epitaxial growth method)形成一磊晶成長層及絕緣層 (如氧化膜層專）’並將銘、銅、欽、絡、白金、金或合 金等蒸鍍在晶片表面形成電極（如閘極、汲極及源極等） 及配線，形成所需之半導體晶片。 再者晶片於絕緣層（如氧化膜層等）、電極及晶片侧 邊壁面彼覆有一防護層，其中防護層係由不導電、防水 、且熱傳導性佳的材料所製成，且晶片透過如蠢晶成長 9 201007902 面Jr等半導體製程於防護層頂面形成有複數大 .穿P大罐思墊、，各導電墊的面積大於電極，並分別透過一 ΐ&ι：! 4的連接部與對應之電極形成電氣連接，進而 / 〔肖4層及大面積導電墊之半導體晶片結構。 ㈣透過前述技術手段的展現，利用本發明之晶片 件時，嫩罐、焊球(凸 ❹ 而疋藉由大面積的導電墊與轉接板（封裝 二板)，電路基板【PCB】的印刷電路直接連結、導通與固Yellow lithography, etching, and impurity diffusion are repeated on the surface of the semiconductor substrate. 'Thermal diffusion method, ion-injection method, or epitaxial growth method (epitaxial growth) Method) forming an epitaxial growth layer and an insulating layer (such as an oxide film layer) and evaporating the surface of the wafer, such as a gate, a bungee, and the like, on the surface of the wafer, such as copper, zirconia, ruthenium, platinum, gold, or alloy. Source, etc.) and wiring to form the desired semiconductor wafer. Furthermore, the wafer is covered with a protective layer on the insulating layer (such as an oxide film layer), the electrode and the side wall of the wafer, wherein the protective layer is made of a material that is non-conductive, waterproof, and thermally conductive, and the wafer is transparent. Stupid crystal growth 9 201007902 The semiconductor process such as Jr is formed on the top surface of the protective layer with a large number. The P-shaped cans are worn, and the area of each conductive pad is larger than the electrodes, and the connection portions of the ΐ & ι:! The corresponding electrodes form an electrical connection, and/or a semiconductor wafer structure of a 4-layer and a large-area conductive pad. (4) Through the above-mentioned technical means, when using the wafer device of the present invention, the cans and the solder balls (the bumps are printed by the large-area conductive pads and the adapter plates (package two plates), and the circuit substrate [PCB]) Direct connection, conduction and solidification of the circuit
Hi到输製程時間與降㈣作成本之目的，且能提高 、的散熱效率’提升其運作的穩定性，以減少故障的 ’而能增加產品的附加價值，且提升產品的競爭力 經濟效益。 、 、為使其進一步了解本發明的構成、特徵及其他目的， 知:乃舉本發明之若干較佳實施例’並配合圖式詳細說明 q，同時讓熟悉該項技術領域者能夠具體實施，惟以下 ❿ίίΓ僅在於說明本發明之較佳實施例，並非用以限制 明二之範15，故凡有以本發明之精神為基礎，而為本發 1Γ形式之修飾或變更’皆仍應屬於本發明意圖保護之 【實施方式】 本發明係一種主動式半導體晶片結構【如第三、四 五圖所不】’斜導體晶片⑷係先從元素週期表中 ㈣元素(石夕(Si)、鍺(Ga))以及第職、第ν 、= 化鎵（GaAs)、魏鎵（GaP))以素製作出半導體== 201007902 Ο 在半導體基板（7)表面反覆進行黃光微影、蝕刻及 雜質擴散製程，藉由熱擴散法(thermai diffusion method) 、離子注入法（ion-injection method)或磊晶成長法（氣相 成長法）(epitaxial growth method)形成一磊晶成長層（7〇 )及絕緣層（如氧化膜層等）（71)，並將鋁、銅、鈦、 鉻、白金、金或合金等蒸鍍在晶片表面形成電極（72) 【如閘極電極（ 720)、汲極電極（721)或源極（722 )】及配線’形成所需之半導體晶片（6)。 又於絕緣層（如氧化膜層等）（71)、電極（72)頂 面覆設有一較厚的防護層（77)，該防護層（77)並具有 可覆設於晶片（6)側邊壁面的侧面防護層（78)，其中防 護層（77)與侧面護層（78)係由不導電、防水、且舞 佳的材料所製成’能產生抗澄氣、抗氧化及防i 旦/缀^保4作用，以保護晶片（6)不受電弧與渥性 ΐ瑣㈣^速散發熱氣，無須像—般的晶片必須藉由 不良率。2= 護晶片，既增加製造成本又會提高 半導體！)透過如磊晶成長、蝕刻或蒸鍍等 = (77)頂面形成有複數大面 ==(7:)、(751)、(752)】，該導電墊 電塾(二穑：、銅，、錫、合金等材料，且各導 防護層（77)的、查於電極（72)，並分別透過一貫穿 叫Λ對部（76)【如_、㈤、（ (似】電極（72)【如⑽）、（72。、 成電氣連接’進而形成具有防護層（77)及 11 201007902 大面積導電墊（72)之半導體晶片（6)結構。 由於各放大導電塾（75)具有較大面積、且該面積及 相f間距離，可依晶片⑷面積大小及電性橋接容許值 内設計，【如第六及七圖所示】，並可延伸至 側邊壁面。 门之 藉此，無需使用焊線、焊球（凸塊）等技術製程， 直接與封褒基板（59)(轉接板)之積體電路（59)或電路 基板【PCB】（90)的印刷電路（91)連結、導通 牛=形成製作成本低、且具高散熱性的主動式半導體元 而本發明於主動式半導體元件製造過程中 時，則【如第八及九圖】所揭示者，由於該半導體曰曰了 )之絕緣層（如氧化膜層等）（71)及電極（曰^ 設有一的防護層㈤，且晶片⑷側邊壁面更進开覆 成有側面防έ蔓層（78)，而利用該防護層（ 乂 / 護層㈤具防水、不導電與高散熱性的== 等）⑻不受外部環境因素所損壞，且由層 6)具有大面積的放大導電墊（乃） 、曰曰片（ [Surface Mounted Technology , SM^ 式藉由導輯質㈤）直接輕、導通與 $ = (州轉接板)或電路基板⑽】（9〇)的印:^ 90上’[如第-圖所不】相較於習式者採焊球(凸塊）間接（ 201007902 固設的方式而言，本發明不带 程，形成主動式半導體元件谭線等製 間，同時降低製作絲式半導體元件成本；^讀程時 、j者本發明半導體晶片結構（6)係利用防護層（77 體藉（4〇)亦可利用注膠的技術【如第九圖所示】，^ 主I:/:構裝體(56)内，做更完善的防護，且 ❹由日μ 女而疋件（4〇)時所產生的高熱，可直接藉 59:=其:Γ放大導電墊(75)傳導至封裝基板（ 59)或電路基板【PCB】㈤）上散熱，大幅提高半導體 元㈣散熱效果，故能增進其運作的穩定性，且減少應用 電氣设備的故障率，並可延長其使用壽命。 ’·不上所述本發明可確實產生前述之優點及實用價值 L且本發明確實為-新騎步關作，在相_技術領域 I未見相同或近似的產品公開使用，故本發明已符合發明 ❹專利的要件，乃依法提出申請，祈請早曰賜准本案發明專 利。 【圖式簡單說明】 第-圖：係本發明與f式之半導體元件製程比較及示意圖 〇 第=圖m之半導體晶片的結構剖面示意圖。 第三圖：係本發明之轉體晶片前段製程之結構剖面示意 圖。 第四圖：係本發明之半導體晶片結構的剖面示意圖。 13 201007902 第五圖 第六圖 第七圖 第八圖 第九圖 結構的俯視平面示意圖。 另一結構的俯視平面示意 係本發明之半導體晶片 係本發明之半導體晶片 圖。 2發明之半導體晶片另—結構的剖面示意圖。 '、本f明之半導體晶片結構連接於封裝基板的剖 面示意圖。 係本發明之半導體晶#結構連接於電路基板的剖 面示意圖。 【主要元件符號說明】 (3) 半導體基板 (6) 半導體晶片 (1〇) 主動式半導體元件 (30) 主動式半導體元件 (32) 絕緣層 (50) 導線板 (52) 接腳 (54) 連接線 (56) 構裝體 (58) 積體電路 (60) 導電材料 (71) 絕緣層 (720) 閘極電極 (722) 源極電極 (750) 放大導電墊 (5) 半導體晶片 (7) 半導體基板 (20) 主動式半導體元件 (31) 蟲晶成長層 (40) 主動式半導體元件 (51) 電極 (53) 導線板 (55) 構裝體 (57) 構裝體 (59) 封裝基板 (70) 蟲晶成長層 ,(72) 電極 (721) 沒極電極 (75) 放大導電墊 (751) 放大導電墊 14 201007902 (752) 放大導電墊 (76) 連接部 (760) 連接部 (761) 連接部 (762) 連接部 (77) 防護層 (78) 侧面防護層 (80) 焊球(凸塊) (90) 電路基板 (91) 印刷電路 〇 15Hi to the process time and down (four) for the purpose of cost, and can improve the heat dissipation efficiency 'to improve the stability of its operation, to reduce the failure' can increase the added value of the product, and enhance the competitiveness of the product economic benefits. In order to further understand the structure, features and other objects of the present invention, it is to be understood that the preferred embodiments of the invention are described in detail in conjunction with the drawings, The following is a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Therefore, any modification or alteration of the present invention based on the spirit of the present invention should still belong to [Invention] The present invention is an active semiconductor wafer structure [as shown in the third, fourth and fifth figures] 'the oblique conductor wafer (4) is first from the element of the periodic table (four) elements (Shi Xi (Si),锗(Ga)) and the first, the ν, = gallium (GaAs), and the gallium (GaP) are made of a semiconductor. == 201007902 黄 Yellow lithography, etching, and impurity diffusion are repeated on the surface of the semiconductor substrate (7). The process comprises forming an epitaxial growth layer (7〇) and insulation by a thermai diffusion method, an ion-injection method, or an epitaxial growth method (epitaxial growth method). Floor Such as an oxide film layer, etc. (71), and aluminum, copper, titanium, chromium, platinum, gold or alloy, etc. are evaporated on the surface of the wafer to form an electrode (72) [such as a gate electrode (720), a gate electrode (721) Or source (722) and wiring 'to form the desired semiconductor wafer (6). Further, on the insulating layer (such as an oxide film layer, etc.) (71), the top surface of the electrode (72) is covered with a thick protective layer (77), and the protective layer (77) has a coating layer (6) The side wall protective layer (78), wherein the protective layer (77) and the side covering layer (78) are made of non-conductive, waterproof, and well-behaved materials, which can produce anti-gas, anti-oxidation and anti-i The effect of the guarantee/protection 4 is to protect the wafer (6) from arcing and smudging (4), and to dissipate the heating gas, and the wafer does not have to be defective. 2= Protect the wafer, which increases the manufacturing cost and increases the semiconductor! Through such as epitaxial growth, etching or evaporation, etc. = (77) The top surface is formed with a plurality of large faces == (7:), (751), (752), and the conductive pad is electrically enthalpy (two: copper) , tin, alloy and other materials, and each of the protective layer (77) is inspected on the electrode (72), and respectively passed through a pair of spurs (76) [such as _, (5), (like) electrode (72 [[10], (72., electrical connection) to form a semiconductor wafer (6) structure with a protective layer (77) and 11 201007902 large-area conductive pads (72). Since each of the enlarged conductive turns (75) has The large area and the distance between the area and the phase f can be designed according to the area of the wafer (4) and the allowable value of the electrical bridge, as shown in Figures 6 and 7, and can be extended to the side wall. No need to use welding wire, solder ball (bump) and other technical processes, directly with the printed circuit (59) of the substrate (59) (array) or the printed circuit of the circuit board [PCB] (90) (91 Linking, conducting cattle = forming an active semiconductor element with low manufacturing cost and high heat dissipation, and the present invention is in the process of manufacturing an active semiconductor device Then, as disclosed in the eighth and ninth figures, the insulating layer (such as an oxide film layer) (71) and the electrode (the protective layer (5) provided by the semiconductor layer) and the side of the wafer (4) The wall is further covered with a side tamper-proof layer (78), and the protective layer (乂/protective layer (five) is waterproof, non-conductive and highly heat-dissipating ==, etc.) (8) is not damaged by external environmental factors, And by layer 6) having a large area of enlarged conductive pads (or), cymbals ([Surface Mounted Technology, SM^ by guided matter (5)) direct light, conduction with $ = (state adapter board) or circuit Substrate (10)] (9〇) printing: ^90 on '[as in the first figure] compared to the in-use welding ball (bump) indirect (201007902 fixed way, the present invention does not lead Forming an active semiconductor device such as a tan wire and the like, and at the same time reducing the cost of fabricating the wire-type semiconductor device; when reading, the semiconductor wafer structure (6) of the present invention utilizes a protective layer (77 body borrowing (4〇)) Using the glue injection technology [as shown in the ninth figure], ^ main I: /: assembly body (56), to do more perfect protection, and the day The high heat generated by the female (4〇) can be directly transferred by the 59:=: Γ amplified conductive pad (75) to the package substrate (59) or the circuit substrate [PCB] (5)), greatly improving the semiconductor The energy dissipation effect of the element (4) can improve the stability of its operation, reduce the failure rate of the applied electrical equipment, and prolong its service life. '·The above invention can indeed produce the aforementioned advantages and practical value L and The invention is indeed a new riding step, and the same or similar product is not disclosed in the technical field of the invention. Therefore, the invention has met the requirements of the invention, and is an application according to law, and pray for the case. Patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a structure of a semiconductor wafer of the present invention and a f-type semiconductor device. Fig. 3 is a schematic cross-sectional view showing the structure of the front stage of the swivel wafer of the present invention. Fourth Figure: is a schematic cross-sectional view of a semiconductor wafer structure of the present invention. 13 201007902 The fifth figure The sixth picture The seventh picture The eighth picture The ninth figure The schematic plan view of the structure. A plan view of another structure is a semiconductor wafer of the present invention which is a semiconductor wafer of the present invention. 2 is a cross-sectional view of another structure of the semiconductor wafer of the invention. A schematic cross-sectional view of the semiconductor wafer structure of the present invention connected to the package substrate. A schematic cross-sectional view showing the structure of the semiconductor crystal structure of the present invention connected to a circuit substrate. [Main component symbol description] (3) Semiconductor substrate (6) Semiconductor wafer (1〇) Active semiconductor device (30) Active semiconductor device (32) Insulation layer (50) Conductor plate (52) Pin (54) Connection Line (56) Structure (58) Integrated Circuit (60) Conductive Material (71) Insulation (720) Gate Electrode (722) Source Electrode (750) Amplified Conductive Pad (5) Semiconductor Wafer (7) Semiconductor Substrate (20) Active semiconductor device (31) Insular growth layer (40) Active semiconductor device (51) Electrode (53) Conductor plate (55) Structure (57) Structure (59) Package substrate (70 ) Insect crystal growth layer, (72) Electrode (721) Nothing electrode (75) Amplified conductive pad (751) Amplified conductive pad 14 201007902 (752) Amplified conductive pad (76) Connection (760) Connection (761) Connection Part (762) Connection (77) Protective layer (78) Side protection layer (80) Solder ball (bump) (90) Circuit board (91) Printed circuit〇15