201005927 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種多階式快閃記憶體結構及其製備方 法’特別係關於一種藉由一凸部隔離複數個儲存結構之多 階式快閃記憶體結構及其製備方法，其可避免快閃記憶體 之尺寸縮小時，該些儲存結構發生融合問題。 【先前技術】 快閃記憶體由於具有有低功率消耗、存取迅速及存入 之資料在斷電後也不會消失等優點，已經廣泛應用在筆記 型電腦、電子記事薄、行動電話、數位相機、數位錄音筆 及MP3播放器等電子產品之資料儲存上。典型的快閃記憶 體具有矽-氧化矽_氮化矽-氧化矽-矽（SONOS)結構，其具有 較薄的記憶單元且製作容易等優點，因而已廣泛應用於快 閃記憶體之中。 圖21例示一習知之快閃記憶胞1〇〇，揭示於u s. 6,011，725。該記憶胞包含在一半導體基板11〇内之擴散源極 120A/汲極120B、設置於該半導體基板11〇上之閘絕緣層13〇 以及設置於該閘絕緣層130上之閘極150。該閘絕緣層13〇 具有一 ΟΝΟ結構，包含一氮化矽層14〇，其係夾置於二氧化 夕層132及—氧化石夕層】34之間。二位元之資料係以捕陷電 何之型式儲存於記憶胞100，其中電荷係捕陷於該氮化矽層 140之電荷捕陷區14〇人或14〇Β。根據各電荷捕陷區ι4〇α或 140Β之捕陷電荷的狀態，各電荷捕陷區14〇八或14叩可分別 對應於儲存值為〇或1。 5 201005927 該§2*憶胞1 0 0之優點在於使用單一記憶胞即可非揮發 性地儲存二位元資料，即提昇儲存密度（相較於習知一位元 /一儲存電晶體）。然而，縮小該記憶胞1 00之尺寸卻面臨了 許多困難。特而言之’該記憶胞1〇〇之操作需要將電荷分別 注入該氮化碎層140之電何捕陷區140Α或140Β。隨著該氮 化矽層140之寬度縮小，該電荷捕陷區14〇八與14〇Β之間的 距離將變成太短，其可能造成該電荷捕陷區14〇八與14〇]8發 生融合問題。 • 【發明内容】 本發明提供一種多階式快閃記憶體結構及其製備方法 ，其藉由一凸部隔離複數個儲存結構以避免快閃記憶體之 尺寸縮小時’該些儲存結構發生融合問題。 本發明之多階式快閃記憶體結構之一實施例，包含具 有一凸部之一半導體基板'被該凸部隔離之複數個儲存結 構、覆蓋該些儲存結構與該半導體基板之凸部的一介電層 φ 、没置於該介電層上之一閘極結構以及設置於該半導體基 板之凸部側邊的複數個擴散區。各儲存結構包含一電荷捕 陷部以及一絕緣結構，其隔離該電荷捕陷部與該半導體基 板。 隨著快閃記憶體之尺寸縮小，習知快閃記憶體之電荷 捕區之間距將變成太短，其可能造成該電荷捕陷區發生 ㉞合問題。㈣地’本發明之儲存結構係被該閘極結構之 下區塊或上區塊予以隔離，因此即使快閃記憶體之尺寸縮 小，本發明仍可避免儲存結構發生融合問題。 201005927 本發明之多階式快閃記憶體結構之製備方法之—實施 例，包含形成一凸部於一半導體基板中、形成複數個健存 結構於該凸部之側邊、形成一介電層於該些儲存結構與該 半導體基板之凸部上、形成一閘極結構於該介電層上以及 形成複數個擴散區於該半導體基板之凸部的侧邊。各儲存 結構包含一電荷捕陷部以及一絕緣結構，其隔離該電荷捕 陷部與該半導體基板。 馨 上文已相當廣泛地概述本發明之技術特徵及優點，俾 使下文之本發明詳細描述得以獲得較佳瞭解。構成本發明 之申請專利範圍標的之其它技術特徵及優點將描述於下文 〇 【實施方式】 圖1至圖10例示本發明之多階式快閃記憶體結構10之 製備方法之一實施例。首先，進行一微影製程以形成一光 阻層20於一抗反射層18上，該抗反射層18係形成於一半導 • 體基板12上。該半導體基板12可為一P型矽基板，且具有一 淺溝隔離結構14及設置於該淺溝隔離結構14間之一 p型井 1 6。忒光阻層20具有複數個開口 20’，其局部曝露該半導體 基板12之P型井16。之後，使用該光阻層2〇為蝕刻遮罩，進 行一乾蝕刻製程以局部去除在該開口2〇，下方之抗反射層18 及P型井16，俾便形成複數個凹部22於該半導體基板12之一 上部以及一凸部24於該些凹部22之間，再將該抗反射層18 及該光阻層20去除，如圖2所示。 參考圖3 ’進行一熱氧化製程以形成一絕緣結構26於該 7 201005927 半導體基板12表面及該些凹部22之内壁，再進行一沈積製 程以形成一電荷捕陷層28於該絕緣結構26上並填入該些凹 部22。該絕緣結構26可包含氧化矽以作為閘極氧化物，該 電荷捕陷層28可包含氮化矽或多晶矽。之後，進行一平2 化製程（例如，化學機械研磨製程）以局部去除該凸部％上之 電荷捕陷層28，如圖4所示。 ，考圖5進行一乳化製程以形成一介電層3〇，其覆蓋 該半導體基板12之凸部μ及該些凹部22内之電荷捕陷層28 ，其中該氧化製程可為臨場蒸氣產生技術(in shu generation，ISSG)，而該介電層30可為厚度均均之一氮氧 化矽層。此外，該氧化製程可為一熱氧化製程以形成一介 電層30’於該半導體基板12之凸部24上，其中該介電層”, 係一氧化矽層，其在該凸部24上之厚度大於在該電荷捕陷 層28上之厚度’如圖6所示。 參考圖7，在圖5之介電層30上進行沈積製程以形成一 閘極堆疊36於圖5之介電層30上，該閘極堆疊36包含一多晶 矽層32(摻雜N型摻質）以及一矽化金屬層34(例如，矽化鎢 層）’再利用沈積製程形成一氮化矽層3 8於該閘極堆疊36上 。特而言之’若該沈積製程係在圖6之介電層3〇,上進行，則 該閉極堆疊36係形成該介電層3〇|及該電荷捕陷層28上。之 後’利用微影製程形成一光阻層4〇(具有複數個開口 4〇,)於 該氮化矽層38上’再利用該光阻層4〇為蝕刻遮罩進行一乾 餘刻製程以局部去除該光阻層40之開口 40,下方之氮化矽層 38 ’俾便形成一硬遮罩42於該閘極堆疊36上，如圖8所示。 8 201005927 參考圖9，將該光阻層40去除以曝露該硬遮罩42，其具 有複數個開口 42’。特而言之，該硬遮罩42局部覆蓋在該些 凹邓22内之電荷捕陷層28，而該些開口 42,則位於在該些凹 部22内之電荷捕陷層28之局部區域的正上方。之後，進行 一非等向性蝕刻製程（例如，乾蝕刻製程）以局部去除在該硬 遮罩42之開口 42,下方之閘極堆疊36、介電層3〇及電荷捕陷 層28，俾便形成一閘極結構44於該介電層3〇上以及複數個 儲存結構48。進行一摻雜製程以形成複數個擴散區5〇於該 半導體基板12之凸部24的侧邊，俾便完成該快閃記憶體結 構10’如圖10所示。 該乾钱刻製程亦局部去除該開口 42'下方之電荷捕陷層 28及絕緣結構26以形成該些儲存結構48，其係被該凸部24 予以隔離。該些儲存結構48係呈扇形且包含該電荷捕陷部 46及該絕緣結構26，其隔離該電荷捕陷部46與該半導體基 板12。特而言之’該些擴散區5〇係形成於半導體基板12中 ，且低於該電荷捕陷部46。 此外，該些擴散區50之上端係低於該淺溝隔離結構14 之上端’且該電荷捕陷部46之上端對齊該淺溝隔離結構i4 之上端。再者，該電荷捕陷部46係形成於該半導體基板12 中，且該介電層30覆蓋該些儲存結構48。該多階式快閃記 憶體結構1 0可藉由通道熱電子注入（channel hot electron injection，CHEI)機制進行編程（pr〇gramming)操作，藉由帶 間隧穿（band-to-band tunneling，BTBT)強化熱電洞注入 (hot hole enhanced injection，HHEI)機制進行抹除（erase)操 9 201005927 作，並藉由反向讀取（reversed read)機制讀取資料。 隨著快閃記憶體之尺寸縮小’習知快閃記憶體1 〇〇之電 荷捕陷區140A及140B之間距將變成太短，其可能造成該電 荷捕陷區140A及140B發生融合問題。相對地，本發明之快 閃記憶體結構10的儲存結構48係被該半導體基板12之凸部 24予以隔離，因此即使該快閃記憶體結構1〇之尺寸縮小， 仍可避免該些儲存結構48發生融合問題。 圖11至圖20例示本發明之多階式快閃記憶體結構的之 製備方法之一實施例。首先，進行一微影製程以形成一光 阻層70於一抗反射層68上，該抗反射層68係形成於一半導 體基板12上。該半導體基板12可為一 ？型矽基板，且具有一 淺溝隔離結構64以及設置於該淺溝隔離結構64間之一 p型 井66。該光阻層7G具有複數個開σ7(),，其局部曝露該半導 體基板62之P型井66。之後，使用該光阻層川為㈣遮罩， 進行-錢刻製程以局部去除在該光阻層7()之開口7〇，下方 的抗反射層68及Ρ型井66，俾便形成複數個凹和於該 體基板62之-上部以及一凸部74於該些凹部η之間，再將 該抗反射層68及該光阻層7G去除，如圊12所示。 今半導一―熱乳化製程以形成—絕緣結構76於 該R體基板62之表面及該些凹部72之㈣，再進行一沈 =製程以形成—電荷捕陷層78於該絕緣結構％上並填入， :=^：=6可包含氧…作為閘極氧_ 部去除該凸部74上—之m化學機械研磨製程）以局 上之電何捕陷層78,俾便形成複數個扇形 201005927 之電荷捕陷部78,於該凸部74侧邊之凹部72内，如圖μ所示 5平-化製程形成複數個儲存結構98，其係被該凸部74 予以隔離。各儲存結構98包含該電荷捕陷部78,及該絕緣結 構76,其隔離該電荷捕陷部78，與該半導體基板a。 多考圊I5進行一氧化製程以形成一介電層8〇於該些 健存結構98及該半導體基板62之凸部74上，其中該氧化製 程可為臨場蒸氣產生技術（in situ steam generati〇n，issg) φ ，而該介電層80可為厚度均均之一氮氧化矽層。此外，該 氧化製程可為一熱氧化製程以形成一介電層8〇，於該些儲存 結構98及該半導體基板62之凸部74上，其中該介電層肋，係 一氧化矽層，其在該凸部74上之厚度大於在該電荷捕陷部 78上之厚度’如圖16所示。 參考圖17，在圖15之介電層8〇上進行沈積製程以形成 一閘極堆疊86於圖5之介電層80上，該閘極堆疊86包含一多 晶矽層82(摻雜N型摻質）以及一矽化金屬層84(例如，矽化 φ 鎢層），再利用沈積製程形成一氮化矽層88於該閘極堆疊86 上。之後’利用微影製程形成一光阻層9〇(具有複數個開口 90')於該氮化石夕層88上，再利用該光阻層90為蝕刻遮罩進行 一乾钮刻製程以局部去除該光阻層90之開口 90’下方的氮化 石夕層88，俾便形成一硬遮罩92於該閘極堆疊86上，如圖18 所示。 參考圖19，將該光阻層90去除以曝露該硬遮罩92，其 具有複數個開口 92,。特而言之，該些開口 92,並未位於則位 於在該電荷捕陷部78'之正上方，而係位於該電荷捕陷部78, 201005927 之側邊。進行一非等向性蝕刻製程（例如，乾蝕刻製程）以局 部去除位該硬遮罩92之開口 92,下方之閘極椎疊86，俾便形 成一閘極結構94於該介電層8〇上。之後，進行一摻雜製程 以形成複數個擴散區96於該電荷捕陷部78,側邊之半導體基 板62中，俾便完成該快閃記憶體結構60，如圖20所示。201005927 IX. Description of the Invention: [Technical Field] The present invention relates to a multi-step flash memory structure and a method for fabricating the same, particularly relating to a multi-step fast method for isolating a plurality of storage structures by a convex portion The flash memory structure and the preparation method thereof can avoid the fusion problem of the storage structures when the size of the flash memory is reduced. [Prior Art] Flash memory has been widely used in notebook computers, electronic notebooks, mobile phones, and digital computers because of its advantages of low power consumption, fast access, and the fact that stored data does not disappear after power is turned off. Data storage for electronic products such as cameras, digital recorders and MP3 players. A typical flash memory has a structure of a germanium-yttria-yttria-yttria-ytterbium oxide (SONOS) structure, which has a thin memory cell and is easy to fabricate, and thus has been widely used in flash memory. Figure 21 illustrates a conventional flash memory cell, disclosed in u s. 6,011,725. The memory cell includes a diffusion source 120A/drain 120B in a semiconductor substrate 11b, a gate insulating layer 13B disposed on the semiconductor substrate 11A, and a gate 150 disposed on the gate insulating layer 130. The gate insulating layer 13A has a germanium structure comprising a tantalum nitride layer 14 crucible sandwiched between the dioxide layer 132 and the oxidized layer 34. The two-bit data is stored in the memory cell 100 in the form of trapping electricity, in which the charge trapped in the charge trapping region of the tantalum nitride layer 140 is 14 or 14 〇Β. Depending on the state of the trapping charge of each charge trapping zone ι4 〇 α or 140 ,, each of the charge trapping regions 14 或 or 14 叩 may correspond to a storage value of 〇 or 1, respectively. 5 201005927 The advantage of §2*Recalling Cell 100 is that non-volatile storage of binary data can be achieved by using a single memory cell, ie increasing the storage density (compared to the conventional one-dimensional/one-storage transistor). However, reducing the size of the memory cell 100 has faced many difficulties. In particular, the operation of the memory cell requires that a charge be injected into the electric trapping region 140 or 140 分别 of the nitriding layer 140, respectively. As the width of the tantalum nitride layer 140 is reduced, the distance between the charge trapping regions 14 and 14 将 will become too short, which may cause the charge trapping region to occur at 14 与 8 and 14 〇 8 Convergence issues. The present invention provides a multi-step flash memory structure and a method for fabricating the same, which isolates a plurality of storage structures by a convex portion to prevent the size of the flash memory from being reduced when the size of the flash memory is reduced. problem. An embodiment of the multi-step flash memory structure of the present invention comprises a plurality of storage structures having a semiconductor substrate of a convex portion separated by the convex portion, covering the storage structures and the convex portions of the semiconductor substrate a dielectric layer φ, a gate structure not disposed on the dielectric layer, and a plurality of diffusion regions disposed on sides of the convex portion of the semiconductor substrate. Each of the storage structures includes a charge trap and an insulating structure that isolates the charge trap from the semiconductor substrate. As the size of the flash memory shrinks, the distance between the charge traps of the conventional flash memory will become too short, which may cause the charge trap region to have a problem. (4) The storage structure of the present invention is isolated by the lower block or the upper block of the gate structure, so that even if the size of the flash memory is reduced, the present invention can avoid the problem of fusion of the storage structure. 201005927 A method for fabricating a multi-step flash memory structure according to the present invention includes an embodiment of forming a convex portion in a semiconductor substrate to form a plurality of memory structures on a side of the convex portion to form a dielectric layer Forming a gate structure on the dielectric layer and forming a plurality of diffusion regions on the side of the convex portion of the semiconductor substrate on the storage structures and the convex portions of the semiconductor substrate. Each of the storage structures includes a charge trap and an insulating structure that isolates the charge trap from the semiconductor substrate. The technical features and advantages of the present invention are summarized in the foregoing, and the detailed description of the present invention will be better understood. Other technical features and advantages of the subject matter of the present invention will be described hereinafter. [Embodiment] Figs. 1 to 10 illustrate an embodiment of a method of manufacturing the multi-step flash memory structure 10 of the present invention. First, a lithography process is performed to form a photoresist layer 20 on an anti-reflection layer 18 which is formed on the semiconductor substrate 12. The semiconductor substrate 12 can be a P-type germanium substrate and has a shallow trench isolation structure 14 and a p-type well 16 disposed between the shallow trench isolation structures 14. The photoresist layer 20 has a plurality of openings 20' that partially expose the P-well 16 of the semiconductor substrate 12. Thereafter, the photoresist layer 2 is used as an etch mask, and a dry etching process is performed to partially remove the anti-reflection layer 18 and the P-type well 16 under the opening 2, and a plurality of recesses 22 are formed on the semiconductor substrate. An upper portion of the 12 and a convex portion 24 are disposed between the recesses 22, and the anti-reflective layer 18 and the photoresist layer 20 are removed, as shown in FIG. Referring to FIG. 3, a thermal oxidation process is performed to form an insulating structure 26 on the surface of the semiconductor substrate 12 and the inner walls of the recesses 22, and a deposition process is performed to form a charge trapping layer 28 on the insulating structure 26. The recesses 22 are filled in. The insulating structure 26 may comprise ruthenium oxide as a gate oxide, and the charge trap layer 28 may comprise tantalum nitride or polysilicon. Thereafter, a planarization process (e.g., a chemical mechanical polishing process) is performed to partially remove the charge trapping layer 28 on the convex portion, as shown in FIG. 5, an emulsification process is performed to form a dielectric layer 3, which covers the convex portion μ of the semiconductor substrate 12 and the charge trapping layer 28 in the recesses 22, wherein the oxidation process can be a field vapor generation technology. (in shu generation, ISSG), and the dielectric layer 30 may be a layer of arsenic oxynitride having a uniform thickness. In addition, the oxidizing process may be a thermal oxidation process to form a dielectric layer 30' on the convex portion 24 of the semiconductor substrate 12, wherein the dielectric layer" is a ruthenium oxide layer on the convex portion 24. The thickness is greater than the thickness on the charge trap layer 28 as shown in Figure 6. Referring to Figure 7, a deposition process is performed on the dielectric layer 30 of Figure 5 to form a gate stack 36 in the dielectric layer of Figure 5. At 30, the gate stack 36 includes a polysilicon layer 32 (doped with an N-type dopant) and a deuterated metal layer 34 (eg, a tungsten-deposited tungsten layer) 're-use a deposition process to form a tantalum nitride layer 38 to the gate. On the pole stack 36. In particular, if the deposition process is performed on the dielectric layer 3A of FIG. 6, the closed-pole stack 36 forms the dielectric layer 3〇| and the charge trapping layer 28 Then, a photoresist layer 4 〇 (having a plurality of openings 4 〇) is formed on the tantalum nitride layer 38 by the lithography process, and the photoresist layer 4 is reused to perform an etching process for the etch mask. To partially remove the opening 40 of the photoresist layer 40, the lower layer of tantalum nitride 38' forms a hard mask 42 on the gate stack 36, as shown in FIG. 8 201005927 Referring to FIG. 9, the photoresist layer 40 is removed to expose the hard mask 42 having a plurality of openings 42'. In particular, the hard mask 42 partially covers the recesses 22 The charge trapping layer 28, and the openings 42 are located directly above the partial region of the charge trapping layer 28 in the recesses 22. Thereafter, an anisotropic etching process (for example, a dry etching process) is performed. To partially remove the opening 42 of the hard mask 42 , the lower gate stack 36 , the dielectric layer 3 , and the charge trapping layer 28 , a gate structure 44 is formed on the dielectric layer 3 以及 and plural The memory structure 48. A doping process is performed to form a plurality of diffusion regions 5 on the side of the convex portion 24 of the semiconductor substrate 12, and the flash memory structure 10' is completed as shown in FIG. The charge engraving process also partially removes the charge trap layer 28 and the insulating structure 26 under the opening 42' to form the memory structures 48, which are isolated by the protrusions 24. The memory structures 48 are fan-shaped and include the a charge trap 46 and the insulating structure 26, which isolate the charge trap 46 from the The semiconductor substrate 12, in particular, the diffusion regions 5 are formed in the semiconductor substrate 12 and lower than the charge trap 46. In addition, the upper ends of the diffusion regions 50 are lower than the shallow trench isolation structure. The upper end of the charge trap 46 is aligned with the upper end of the shallow trench isolation structure i4. Further, the charge trap 46 is formed in the semiconductor substrate 12, and the dielectric layer 30 covers the The storage structure 48. The multi-step flash memory structure 10 can be programmed by a channel hot electron injection (CHEI) mechanism by band-to-band tunneling (band-to -band tunneling, BTBT) Enhanced hot hole enhanced injection (HHEI) mechanism for erase operation 9 201005927, and reads data by reverse read mechanism. As the size of the flash memory is reduced, the distance between the charge trapping regions 140A and 140B of the conventional flash memory 1 will become too short, which may cause fusion problems in the charge trapping regions 140A and 140B. In contrast, the memory structure 48 of the flash memory structure 10 of the present invention is isolated by the convex portion 24 of the semiconductor substrate 12, so that even if the size of the flash memory structure 1 is reduced, the storage structures can be avoided. 48 There is a fusion problem. 11 to 20 illustrate an embodiment of a method of fabricating the multi-step flash memory structure of the present invention. First, a lithography process is performed to form a photoresist layer 70 on an anti-reflection layer 68 which is formed on one of the semiconductor substrates 12. The semiconductor substrate 12 can be one? The ruthenium substrate has a shallow trench isolation structure 64 and a p-type well 66 disposed between the shallow trench isolation structures 64. The photoresist layer 7G has a plurality of openings σ7() which partially expose the P-well 66 of the semiconductor substrate 62. Thereafter, the photoresist layer is used as a (four) mask, and the etching process is performed to partially remove the opening 7 在 in the photoresist layer 7 (), the anti-reflection layer 68 and the Ρ-shaped well 66 below, and the 俾 形成 形成The concave portion and the upper portion of the body substrate 62 and a convex portion 74 are between the recesses η, and the anti-reflective layer 68 and the photoresist layer 7G are removed, as shown by 圊12. The present invention introduces a thermal emulsification process to form an insulating structure 76 on the surface of the R body substrate 62 and (4) of the recesses 72, and then perform a sinking process to form a charge trapping layer 78 on the insulating structure. And filled in, :=^:=6 may contain oxygen... as the gate oxygen _ part removes the convex portion 74 - m chemical mechanical polishing process) to the local electrical and trap layer 78, the sputum forms a plurality of The charge trapping portion 78 of the fan shape 201005927 is formed in the concave portion 72 on the side of the convex portion 74, and a plurality of storage structures 98 are formed by the flattening process shown in Fig. 5, and are separated by the convex portion 74. Each of the storage structures 98 includes the charge trap portion 78, and the insulating structure 76, which isolates the charge trap portion 78 from the semiconductor substrate a. The oxidation process of the I5 is performed to form a dielectric layer 8 on the salient structures 98 and the convex portions 74 of the semiconductor substrate 62, wherein the oxidation process can be a spot steam generation technology (in situ steam generati〇) n, issg) φ , and the dielectric layer 80 may be a layer of arsenic oxynitride having a uniform thickness. In addition, the oxidizing process may be a thermal oxidation process to form a dielectric layer 8 〇 on the storage structures 98 and the convex portions 74 of the semiconductor substrate 62, wherein the dielectric layer ribs are a ruthenium oxide layer. Its thickness on the convex portion 74 is larger than the thickness on the charge trap portion 78 as shown in FIG. Referring to FIG. 17, a deposition process is performed on the dielectric layer 8A of FIG. 15 to form a gate stack 86 on the dielectric layer 80 of FIG. 5. The gate stack 86 includes a polysilicon layer 82 (doped N-type doping). And a germanium metal layer 84 (eg, a germanium φ tungsten layer), and a deposition process is used to form a tantalum nitride layer 88 on the gate stack 86. Then, a photoresist layer 9 (having a plurality of openings 90') is formed on the nitride layer 88 by a lithography process, and the photoresist layer 90 is used to perform a dry button etching process for the etching mask to partially remove the photoresist layer 90. The nitride layer 88 below the opening 90' of the photoresist layer 90 forms a hard mask 92 on the gate stack 86, as shown in FIG. Referring to Figure 19, the photoresist layer 90 is removed to expose the hard mask 92 having a plurality of openings 92. In particular, the openings 92 are not located directly above the charge trap 78' and are located on the side of the charge traps 78, 201005927. An anisotropic etching process (eg, a dry etching process) is performed to partially remove the opening 92 of the hard mask 92, and the lower gate stack 86, and a gate structure 94 is formed on the dielectric layer 8 〇上. Thereafter, a doping process is performed to form a plurality of diffusion regions 96 in the charge trap portion 78, the side semiconductor substrate 62, and the flash memory structure 60 is completed, as shown in FIG.
該電荷捕陷部46之上端對齊該淺溝隔離結構64之上端 ，且該些擴散區96之上端亦對齊該淺溝隔離結構64之上端 。該該多階式快閃記憶體結構6〇可藉由通道熱電子注入 (channel hot electron injecti〇n，CHEI)機制進行編程 (programming)操作，藉由帶間隧穿（band_t〇 band tunne][ing ’ BTBT)強化熱電洞注入㈣ h〇le enhanced ίη_ί〇η， HHEI)機制進行抹除（erase)操作，並藉由反向讀取 read)機制讀取資料。The upper end of the charge trap 46 is aligned with the upper end of the shallow trench isolation structure 64, and the upper ends of the diffusion regions 96 are also aligned with the upper end of the shallow trench isolation structure 64. The multi-step flash memory structure 6 can be programmed by a channel hot electron injecting (CHEI) mechanism, with band-t〇band tunne[ Ing 'BTBT) enhanced thermoelectric hole injection (4) h〇le enhanced ίη_ί〇η, HHEI) mechanism to erase (erase) operation, and read data by reverse read read mechanism.
隨著快閃記憶體之尺寸縮小，習知快閃記憶體1〇〇之電 荷捕陷區190八及19叩之間距將變成太短’其可能造成該電 荷捕陷區190A及190B發生融合問題。相對地，本發明之快 閃記憶體結構60的儲存結構98係被該半導體基板62之凸部 74予以隔離，因此即使該快閃記憶體結構9〇之尺寸縮小， 仍可避免該些儲存結構98發生融合問題。 本發明之技術内容及技術特點已揭示如上，然而本發 明所屬技術領域中具有通常知識者應瞭解，在不背離後附 申請專利範圍所界定之本發明精神和_内，本發明之教 示及揭示可作種種之替換及修飾。例如，上文揭示之許多 製程可以不同之方法實施或以其它製程予以取代，或者採 12 201005927 用上述二種方式之組合。 此外，本案之權利範圍並不偈限於上文揭示之特定實 施例的製程、機台、製造、物質之成份、裝置、方法或步 驟。本發明所屬技術領域中具有通常知識者應瞭解，基於 本發明教示及揭示製程、機台、製造、物質之成份、裝置 、方法或步驟，無論現在已存在或日後開發者，其與本案 實施例揭示者係以實質相同的方式執行實f相同的功能了 而達到實質相同的結果，亦可使用於本發明。因此，以下 之申請專職圍係用以涵蓋用以此類製程、機台、製造、 物質之成份、裝置、方法或步驟。 【圖式簡要說明】 藉由參照前述說明及下列圖戎 ^ w _ 圖式本發明之技術特徵及 優點付以獲得完全瞭解。 圖1至圖10例示本發明之多階4 法之一實施例； 夕階式快閃記憶體之製備方 ❹ 圖11及圖20例示本發明之多階 式快閃記憶體之製備古 法之一實施例；以及 表備方 圖21例示一習知之快閃記憶胞。 【主要元件符號說明】 10 多階式快閃記憶體 12 14 淺溝隔離結構 16 18 抗反射層 20 20' 開口 22 24 凸部 26 半導體基板 p型井 光P且層 凹部 絕緣結構 13 201005927As the size of the flash memory shrinks, the distance between the 190 and 19 电荷 of the charge trapping region of the conventional flash memory will become too short', which may cause fusion problems in the charge trapping regions 190A and 190B. . In contrast, the memory structure 98 of the flash memory structure 60 of the present invention is isolated by the convex portion 74 of the semiconductor substrate 62, so that even if the size of the flash memory structure 9 is reduced, the storage structures can be avoided. 98 fusion problem occurred. The technical contents and technical features of the present invention have been disclosed as above, but those skilled in the art to which the present invention pertains should understand that the teachings and disclosures of the present invention are not to be construed as departing from the spirit and scope of the invention as defined by the appended claims. Can be used for various substitutions and modifications. For example, many of the processes disclosed above may be implemented in different ways or in other processes, or in combination with the above two approaches. Moreover, the scope of the present invention is not limited to the process, machine, manufacture, compositions, means, methods or steps of the particular embodiments disclosed. Those of ordinary skill in the art to which the present invention pertains will appreciate that the present invention and the embodiments of the present invention, based on the teachings and disclosures of the process, the machine, the manufacture, the composition, the device, the method, or the steps of the present invention, whether present or future developers The revealer performs substantially the same function in substantially the same manner and achieves substantially the same result, and can also be used in the present invention. Therefore, the following application full-time enclosures are intended to cover such processes, machines, manufacturing, components, devices, methods or steps. BRIEF DESCRIPTION OF THE DRAWINGS The technical features and advantages of the present invention are obtained by referring to the foregoing description and the following drawings. 1 to 10 illustrate one embodiment of the multi-step 4 method of the present invention; preparation method of the hop-order flash memory; FIG. 11 and FIG. 20 illustrate the preparation of the multi-step flash memory of the present invention. An embodiment; and a preparation table 21 illustrates a conventional flash memory cell. [Main component symbol description] 10 Multi-step flash memory 12 14 Shallow trench isolation structure 16 18 Anti-reflection layer 20 20' Opening 22 24 Projection 26 Semiconductor substrate p-type well Light P and layer recess Insulation structure 13 201005927
28 電荷捕陷層 30 介電層 32 多晶矽層 34 矽化金屬層 36 閘極堆疊 38 氮化矽層 40 光阻層 40' 開口 42 硬遮罩 44 閘極結構 46 電荷捕陷部 48 儲存結構 50 擴散區 60 多階式快閃記憶體 62 半導體基板 64 淺溝隔離結構 66 P型井 68 抗反射層 70 光阻層 70' 開口 72 凹部 74 凸部 76 絕緣結構 78 電荷捕陷層 78' 電荷捕陷部 80 介電層 82 多晶矽層 84 矽化金屬層 86 閘極堆疊 88 氮化矽層 90 光阻層 90， 開口 92 硬遮罩 94 閘極結構 96 擴散區 98 儲存結構 100 快閃記憶胞 110 半導體基板 120A源極 120B 源極 130 閘絕緣層 132 氧化矽層 134 氧化矽層 140 氮化矽層 140A電荷捕陷區 140B 電荷捕陷區 150 閘極 1428 Charge trapping layer 30 Dielectric layer 32 Polysilicon layer 34 Deuterated metal layer 36 Gate stack 38 Tantalum nitride layer 40 Photoresist layer 40' Opening 42 Hard mask 44 Gate structure 46 Charge trap 48 Storage structure 50 Diffusion Area 60 Multi-step flash memory 62 Semiconductor substrate 64 Shallow trench isolation structure 66 P-type well 68 Anti-reflection layer 70 Photoresist layer 70' Opening 72 Concave portion 74 Projection 76 Insulation structure 78 Charge trapping layer 78' Charge trapping Portion 80 Dielectric layer 82 Polysilicon layer 84 Deuterated metal layer 86 Gate stack 88 Tantalum nitride layer 90 Photoresist layer 90, opening 92 Hard mask 94 Gate structure 96 Diffusion region 98 Storage structure 100 Flash memory cell 110 Semiconductor substrate 120A source 120B source 130 gate insulating layer 132 hafnium oxide layer 134 hafnium oxide layer 140 tantalum nitride layer 140A charge trapping region 140B charge trapping region 150 gate 14