26537twf.doc/n 200933847 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝製程與封裝結構，且特別是 有關於一種覆晶式四方扁平無引腳型態封裝結構及其封裝 製程。 【先前技術】 在半導體產業中’積體電路(integrated circuits，1C)的 生產主要可分為三個階段：積體電路的設計(IC design)、 積體電路的製作（IC process)及積體電路的封裝（ic package)。其中，封裝的目的在於，防止晶片受到外界溫 度、濕氣的影響以及雜塵污染，並提供晶片與外部電路之 間電性連接的媒介。 在半導體封裝製程當中，包含有許多種封裝形態。目 前’以四方扁平無引腳(Quad Flat Non-Leaded，QFN)封裝 結構因具有較短之訊號傳遞路徑，且具有較快之訊號傳遞 速度等優點，因此一直是低腳位構裝型態的主流之一，適 用於高頻傳輸(例如射頻頻帶)之晶片封裝結構之中。 但是’現行的四方扁平無引腳封裝結構，大多是採用 打線接合(wire bonding)的方式，以使晶片電性連接至承載 器上，而承載器例如為一導線架(lead frame)或一封裝基板 (package substrate)。然而，此種封裝結構形態的缺點在於 製作成本較高與體積較大。此外’目前一般覆晶形式之 QFN封裝體，晶片焊墊都藉由凸塊而直接與引腳電性接 5 26537twf.doc/n 200933847 觸’因此該覆晶QFN封裝體之晶片尺寸的大小就必定得跟 該導線架引腳的尺寸大小相同，而無法使用小尺寸晶片來 降低封裝成本。然而’目前晶片尺寸已經朝向微小化，因 此在積體電路封裝技術中，如何利用小尺寸晶片形成QFn 封裝體以及如何使四方扁平無接腳封裝結構更為小型化， 實為一待解決之問題。 Ο ❹ 【發明内容】 ，鑑於此’本發明的目的就是在提供—種覆晶式四方 叮祖Γ =腳型㈣裝製程，能夠更為降低封裝體厚度，且 可提尚製程便利性。 腳型ί:二/的，提供一種覆晶式四方扁平無引 而可二I古’能夠藉由介電層與重配置線路層的設計 有不同焊墊排列型態之晶片，另外，更因為 微小尺寸之晶片形成QFN封裝體，因而得以降= 聊型ϊΐΐίΓιΓΓ提出m切方扁平無引 然後，在導線架:形==包導線架。 層==二在， 和這些?丨腳的上表面的條連接這些焊墊 重配置線路層、介電H防焊層，覆蓋 焊塾的表面。繼之，乂成且^焊層暴露出這些 焊θ上形成—黏著層。然後，提 6 200933847 26537twf.doc/n 供一晶片，晶片上具有多個凸塊，而且藉由黏著層使晶片 貼附於防焊層上，以使各凸塊分別與其中—個焊^電： 接。 依照本發明的實施例所述之覆晶式四方扁平無引聊 型態封裝製程，更包括形成一封裝膠體，以包覆晶'片'、防 焊層與介電層，以及填滿晶片與防焊層所包圍形成之空 間’且封裝膠體裸露出該些引腳的下表面。在一實施例中^ ❹ 還可進一步包括，在介電層中形成至少一貫通開口，而重 配置線路層的這些焊墊形成於貫通開口周圍，且在防焊層 中暴露出貫通開口。另外，在貫通開口中更包括填充有封 依照本發明的實施例所述之覆晶式四方扁平盔引腳 型態封裝製程，其中祕重配置線路層財法例如·是激艘 製程。 又 依照本發明的實施例所述之覆晶式四方扁平無引腳 型態封裝製程，其中介電層的材質例如是環氧樹脂。 依照本發明的實施例所述之覆晶式四方扁平盔引腳 型態封裝製程，其中黏著層的材質例如是環氧樹脂或 階特性之熱固性膠材。 、 依照本發明的實施例所述之覆晶式四方扁平盔引腳 ，態封裝製程，其中介電層的厚度小於或等於這些引腳的 高度。在一實施例中，封裝膠體包覆這些引腳之侧邊。 依照本發明的實施例所述之覆晶式四方扁平無引腳 型態封裴製程，其中形成防焊層的方法例如是塗佈製程。 200933847 26537twf.doc/n 依照本發明的實施例所述之覆晶式四方扁 ::製程’ Γ導線架更包含一框架，而這些⑽與 ”連接且沿框架巾心延伸而呈卩㈣㈣或呈單列排列。 ❹26537twf.doc/n 200933847 IX. Description of the Invention: [Technical Field] The present invention relates to a package process and package structure, and more particularly to a flip-chip quad flat no-lead package structure and Packaging process. [Prior Art] In the semiconductor industry, the production of integrated circuits (1C) can be mainly divided into three stages: IC design, IC process, and integrated circuits. Circuit package (ic package). Among them, the purpose of the package is to prevent the wafer from being affected by external temperature, moisture, and dust pollution, and to provide a medium for electrically connecting the wafer to an external circuit. In the semiconductor packaging process, there are many package types. At present, the Quad Flat Non-Leaded (QFN) package structure has always been a low-pin configuration because of its short signal transmission path and fast signal transmission speed. One of the mainstream, suitable for high-frequency transmission (such as RF band) in the chip package structure. However, the current quad flat no-lead package structure is mostly wired bonding to electrically connect the chip to the carrier, such as a lead frame or a package. a package substrate. However, such a package structure has the disadvantage of being relatively expensive to manufacture and bulky. In addition, in the current general flip-chip QFN package, the wafer pads are directly connected to the leads by bumps, so the size of the wafer of the flip-chip QFN package is It must be the same size as the lead frame pins, and it is not possible to use small size wafers to reduce packaging costs. However, 'the current wafer size has been miniaturized. Therefore, how to use a small-sized wafer to form a QFn package and how to make the quad flat unpinped package structure more compact in integrated circuit packaging technology is a problem to be solved. .发明 ❹ [Invention] In view of the above, the object of the present invention is to provide a flip-chip type tetragonal 叮 Γ Γ = foot type (four) mounting process, which can further reduce the thickness of the package and improve the process convenience. The foot type ί: two /, provides a flip-chip quad flat no-lead and can be used to design a wafer with different pad arrangement patterns through the dielectric layer and the reconfigured circuit layer, and more, because The tiny size of the wafer forms the QFN package, so it can be lowered = chat type ϊΐΐ Γ Γ ΓΓ ΓΓ m m m m m m m m m m m 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在Layer == two, and these strips on the upper surface of the foot are connected to these pads to reconfigure the circuit layer, dielectric H solder mask, and cover the surface of the solder bump. Subsequently, the solder layer exposes the solder layer θ to form an adhesive layer. Then, 6 200933847 26537twf.doc/n is provided with a wafer having a plurality of bumps thereon, and the wafer is attached to the solder resist layer by an adhesive layer, so that each bump is respectively soldered to the solder bump : Pick up. The flip-chip quad flat no-learning type packaging process according to the embodiment of the present invention further includes forming an encapsulant to encapsulate the crystal 'chip', the solder resist layer and the dielectric layer, and filling the wafer with The space formed by the solder mask is surrounded and the encapsulant exposes the lower surface of the pins. In one embodiment, the method further includes forming at least one through opening in the dielectric layer, and the pads of the reconfigured wiring layer are formed around the through opening, and the through opening is exposed in the solder resist layer. In addition, the through-opening further includes a flip-chip quadrilateral flat-panel pin type package process filled with a seal according to an embodiment of the present invention, wherein the secret-distribution line layer method is, for example, a process. Further, in the flip-chip quad flat no-lead package process according to the embodiment of the invention, the material of the dielectric layer is, for example, an epoxy resin. According to the embodiment of the present invention, the flip-chip quadrilateral flat helmet lead type packaging process, wherein the adhesive layer is made of, for example, an epoxy resin or a thermosetting adhesive of a meta-characteristic. According to an embodiment of the invention, a flip-chip quadrilateral flat helmet lead state, wherein the thickness of the dielectric layer is less than or equal to the height of the pins. In one embodiment, the encapsulant encapsulates the sides of the pins. A flip-chip quad flat no-lead type sealing process according to an embodiment of the present invention, wherein the method of forming the solder resist layer is, for example, a coating process. 200933847 26537twf.doc/n A flip-chip quad flat according to an embodiment of the invention: a process ' Γ lead frame further comprises a frame, and these (10) are connected to and extend along the frame center to represent (four) (four) or Single column arrangement.
基於上述目的，本發明另提出一種覆晶式四方扁平盈 引腳型態封裝結構，包括··-介電層、多個引腳、一重配 置線路層、一防焊層、一黏著層以及晶片。其中，多個 腳配置在介電射，且暴露出其上表面與下表面。重配置 線路層配置在介電層上，而重配置線路層包含多個焊墊以 及多條連接這些焊墊和這些引腳的上表面的導線。防焊層 ^蓋重配置線路層、介電層與這些引腳，且防焊層暴露^ 這些垾墊的表面。另外，黏著層配置在防焊層上。晶片上 具有多個凸塊，且藉由黏著層以貼附於防焊層上，而各凸 塊分别與其中一個焊墊電性連接。 依照本發明的實施例所述之覆晶式四方爲平無引腳 型態封裝結構，更包括一封裝膠體，以包覆晶片、‘防浑層 與介電層，以及配置於晶片與防焊層所包圍形成之空間: 且封骏膠體裸露出這些引腳的下表面。在—實施例中，介 電層中具有至少一貫通開口，且在防焊層中暴露出貫通^ 口。而且，在貫通開口内還可更包括配置有封裝膠體。 a依照本發明的實施例所述之覆晶式四方扁平無引腳 =態封裝結構，其中介電層的表面與這些引腳的上表面切 齊’且介電層的厚度小於或等於這些引腳的高度。在一實 施例中，封裝膠體包覆這些引腳之侧邊。 、 依照本發明的實施例所述之覆晶式四方扁平無引腳 8 200933847 26537twf.doc/n 型態封裝結構，其中介電層的材質例如是環氧樹脂。 2本發明的實施例所述之覆晶式四方扁平益 ^封裂結構，更包括-框架，而這些弓丨腳與框 沿框架中心延伸而呈陣列排列或呈單列排列。 依照本發明的實施例所述之覆晶式四 型態縣結構，其中黏著層的材質例如是環氧 階特性之熱固性膠材。 娜曰次具雙 Ο ❹ 本發明可藉由形成有介電層’而在其上方可形成重配 置線路層’因此可具備有與f知縣製程巾的基板之相同 作用，使晶片可電性連接重配置線路層與引腳。另一方面， 本發明之介中具有貫通開口，其可使縣膠體能夠均 勻分佈而填滿所有的空隙，以提高封裝膠體與晶片、介電 層具有更佳的結合力。而且，本發明是利用黏著層，例如， 具有雙階特性之熱固性膠材，以固定晶片，因此在封裝製 程上具有較大的便利性，因而可降低成本，並容易地^有 效地製造封裝體結構。此外，本發明是利用覆晶式封裝技 術來代替習知的打線接合技術，因此可進一步使封裝後的 體積較為縮小，即可降低封裝體厚度。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 實施方式】 圖1A至圖1F為依照本發明之一實施例所繪示的覆晶 9 26537twf.doc/n 200933847 式四方扁平無引腳(Quad Flat Non-Leaded，Qfn)型維封裝 製程的剖面示意圖。 & 首先，請參照圖1A，本實施例之封裝製程包括下列 步驟。首先，k供一導線架106 ’其具有多個引腳。在 本實施例中，導線架106還可包括有一框架1〇4。導線架 106上的這些引腳102可與框架104連接’且沿框架1〇4 中心延伸而呈陣列排列或者是單列排列（未繪示），其例如 ❹ 可以排列於框架⑽的兩側或者是環狀排列於框架104的 四邊。 導線架106的材質例如是鋼、銅合金、鎳鐵合金等金 屬材料。導線架106的形成方法例如是，先提供一金屬材 料層，然後對此金屬材料層進行圖案化製程、一次性地完 成微影、钱刻等步驟而形成所需的圖案。 几 Ο 然後，請參照圖1B ’在導線架1〇6上形成一介電芦 108。介電層⑽的材質例如是環氧樹脂或其他合適之介^ 材料。而且，如圖2所示，其繪示圖m之結構沿著線t 丁， 的剖面示意圖。此介電層則是會暴露出這些引腳搬 的上表面與下表面。介電層⑽的厚度為小於這些引腳1〇2 ’而介電層⑽的厚度亦可以是等於這些引腳1〇2 的冋度。另外，在-實施例中，於介電層1〇8巾可形 =貫通開口 no ’其可例如是位於這些引腳1〇2所圍繞 之^域内。為了便於說明，此實施例的貫通開口⑽僅纷 接著’請參照ffi ic ’在介電層108上形成—重配置 26537twf.doc/n 200933847 ❹ 線路層116,以改變晶片上對外電性連接的線路佈局。 配置線路層116包含多個焊墊112以及多條導線114]重 導線114為連接焊塾112與引腳1〇2的上表面]此重酉 線路層116的形成方法可例如是利用濺鍍製程。在本 例中，重配置線路層116的材質例如是銅或是其他合、高施 金屬材料。在一實施例中，重配置線路層116的這二 112可以是形成於貫通開口 110的周圍。此外，本發明 此亦不限制重配置線路層116上焊墊112與導線ιΐ4 列方式或分佈位置。 值得注意的是，本實施例之介電層1〇8及其上方 成的重配置線路層116’即可具備有與f知封裝製程中^ 基板之相同作用’使後續所_的晶片可藉由重配置線路 層116與導線架1〇6之引腳ι〇2電性連接。 之後，晴參照圖1〇，形成一防桿層(3〇1(1咖邮118, 以覆蓋住重配置線路層116、介電層⑽以及引腳1〇2，且 防焊層118暴露出重配置線路層116之焊㈣2的表面。 在-實施例中，於防焊層118中亦可暴露出貫通開口 11〇。 防焊層118的材質例如是以環氧樹脂，且其形成方法 是利用塗佈製程。 然後，請參照圖1E，在形成防焊層118之後，接著在 = 118上形成一黏著層120。黏著層12〇的材質例如 疋環氧树月a纟有雙階特性之熱固性膠材(B階膠材），或 是其他黏著材質。隨後，提供—晶片122(如圖3所示），发 上之焊墊123❺分布可例如是周圍分布型(peripheral Pad) 11 200933847 26537twf! doc/n 或t央刀布型(central pad)等。在本實施例令，則是以繪示 焊墊的分布為中央分布型來做說明。在晶片122之主動表 ^有多個凸塊124，且每—個凸塊124則是形成於晶 片122的焊墊123之上，這些凸塊材質例如是金、銅、錄、 ❻ Ο 鋁、錫、鉛或者為上述其一金屬所組合而成之合金。而且， ，再次參照’將晶片122翻覆’以使主動表面朝下，而 曰曰片122可藉由黏著層12〇而貼附於防焊層上，晶片 122上之各凸塊124則分別與重配置線路層:一 個焊墊122電性連接。 〃 說明的疋’在本實施例中’藉由形成於防焊層 t ^者層’例如’具有雙階特性之_性膠材，可使晶 焊層、重配置線路層、介電層與導線架的 ’更_方便於各製程簡之輸送過程，並容易 且有效崎“Π線㈣龍轉 重配置線路層116，而使本發明可以使用其他且有不同： 墊排列型態之晶片。 Z、他，、有不间知 古色rf"本實施例7^彻覆晶式封裝技術，代替習知四 ^扁平…、引腳型態封裳的打線接合，因此可進一步使封裝 後的體?較摘λ!、，即可降低縣體厚度。 接著，請參照圖1F與圖4 ,圖4為 沿著線㈣剖面示意圖。本實二之^ 形成有-封_ 126。難賴126 Z焊層，與介電層⑽，_更可^122 裸路出導線_之這些引腳_下表面，另外封裝膠 12 26537twf.doc/n 200933847 體120還可包覆這些引腳102之側邊。在一實 裝膠體126亦可流入介電層108與防焊層U8中二丄= 貫通開口 m，其可使封膠材料能夠均勻分佈而 的空隙，而使得封裝膠體126與晶片122、介電層1〇8且 Ϊ=ίί料封裝膠體126的材質為環氧樹;或其：Based on the above object, the present invention further provides a flip-chip quad flat pack structure, including a dielectric layer, a plurality of leads, a reconfigurable circuit layer, a solder resist layer, an adhesive layer, and a wafer. . Wherein, the plurality of legs are disposed in the dielectric and expose the upper surface and the lower surface. The reconfiguration circuit layer is disposed on the dielectric layer, and the reconfiguration circuit layer includes a plurality of pads and a plurality of wires connecting the pads and the upper surface of the pins. The solder resist layer ^ covers the wiring layer, the dielectric layer and these pins, and the solder resist layer exposes the surface of these pads. In addition, the adhesive layer is disposed on the solder resist layer. The wafer has a plurality of bumps thereon, and is adhered to the solder resist layer by an adhesive layer, and each bump is electrically connected to one of the pads. The flip-chip type quadruple according to the embodiment of the present invention is a flat leadless package structure, and further comprises an encapsulant for coating a wafer, a tamper-proof layer and a dielectric layer, and being disposed on the wafer and solder resist. The space surrounded by the layers: and the seal colloid exposes the lower surface of these pins. In an embodiment, the dielectric layer has at least one through opening and a through opening is exposed in the solder resist layer. Moreover, an encapsulant may be further disposed in the through opening. A flip-chip quad flat no-lead=state package structure according to an embodiment of the invention, wherein a surface of the dielectric layer is aligned with an upper surface of the leads and the thickness of the dielectric layer is less than or equal to the reference The height of the foot. In one embodiment, the encapsulant encapsulates the sides of the pins. The flip-chip quad flat no-lead 8 200933847 26537 twf.doc/n type package structure according to the embodiment of the invention, wherein the material of the dielectric layer is, for example, an epoxy resin. 2 The flip-chip tetragonal flat-fracture structure of the embodiment of the invention further comprises a frame, and the arch legs and the frame extend along the center of the frame to be arranged in an array or in a single column. A flip-chip type IV structure according to an embodiment of the present invention, wherein the material of the adhesive layer is, for example, a thermosetting adhesive of epoxy-like characteristics.曰 曰 曰 ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ Reconfigure the line layer and pins. On the other hand, the present invention has a through opening which allows the county colloid to be uniformly distributed to fill all the voids to improve the bonding strength of the encapsulant to the wafer and the dielectric layer. Moreover, the present invention utilizes an adhesive layer, for example, a thermosetting adhesive material having a double-order property to fix a wafer, thereby providing greater convenience in a packaging process, thereby reducing cost and easily and efficiently manufacturing the package. structure. In addition, the present invention utilizes flip-chip packaging technology instead of the conventional wire bonding technique, so that the packaged volume can be further reduced to reduce the thickness of the package. The above and other objects, features and advantages of the present invention will become more <RTIgt; 1A to 1F are cross-sectional views of a flip-chip 9 26537 twf.doc/n 200933847 quad flat Non-Leaded (Qfn) type dimensional packaging process according to an embodiment of the invention. schematic diagram. & First, referring to FIG. 1A, the packaging process of this embodiment includes the following steps. First, k is provided for a lead frame 106' which has a plurality of pins. In the present embodiment, the lead frame 106 may further include a frame 1〇4. The pins 102 on the leadframe 106 can be connected to the frame 104 and extend in the center of the frame 〇4 to be arranged in an array or in a single column arrangement (not shown), for example, ❹ can be arranged on either side of the frame (10) or The rings are arranged on four sides of the frame 104. The material of the lead frame 106 is, for example, a metal material such as steel, copper alloy or nickel-iron alloy. The lead frame 106 is formed by, for example, providing a metal material layer, then patterning the metal material layer, performing lithography, etching, and the like in a single step to form a desired pattern. A few Ο Then, a dielectric reed 108 is formed on the lead frame 1〇6 with reference to FIG. 1B'. The material of the dielectric layer (10) is, for example, an epoxy resin or other suitable material. Moreover, as shown in FIG. 2, a schematic cross-sectional view of the structure of the figure m along the line t is shown. This dielectric layer exposes the upper and lower surfaces of these pins. The thickness of the dielectric layer (10) is less than these pins 1〇2' and the thickness of the dielectric layer (10) may also be equal to the twist of these pins 1〇2. Further, in the embodiment, the dielectric layer 1 〇 8 can be shaped = the through opening no ' which can be, for example, located within the area surrounded by the pins 1 〇 2 . For convenience of explanation, the through opening (10) of this embodiment is formed only by referring to ffi ic on the dielectric layer 108 - reconfiguring the 26537 twf.doc/n 200933847 线路 circuit layer 116 to change the external electrical connection on the wafer. Line layout. The configuration circuit layer 116 includes a plurality of pads 112 and a plurality of wires 114. The heavy wires 114 are upper surfaces of the bonding pads 112 and the pins 1〇2. The method for forming the wiring layer 116 may be, for example, a sputtering process. . In this example, the material of the reconfiguration wiring layer 116 is, for example, copper or other composite or high-strength metal material. In an embodiment, the two 112 of the reconfiguration circuit layer 116 may be formed around the through opening 110. In addition, the present invention does not limit the manner in which the pads 112 and the wires ΐ4 are arranged or distributed on the rewiring circuit layer 116. It should be noted that the dielectric layer 1 〇 8 of the present embodiment and the reconfigured circuit layer 116 ′ formed thereon may have the same function as the substrate in the package process, so that the subsequent wafer can be borrowed. The reconfiguration circuit layer 116 is electrically connected to the pin ι 2 of the lead frame 1〇6. Thereafter, referring to FIG. 1A, an anti-bar layer (3〇1) is formed to cover the relocation wiring layer 116, the dielectric layer (10), and the lead 1〇2, and the solder resist layer 118 is exposed. The surface of the solder (4) 2 of the wiring layer 116 is reconfigured. In the embodiment, the through opening 11 is also exposed in the solder resist layer 118. The material of the solder resist layer 118 is, for example, epoxy resin, and the method of forming the same is Referring to FIG. 1E, after the solder resist layer 118 is formed, an adhesive layer 120 is formed on the surface 118. The material of the adhesive layer 12 is, for example, a double-layered property. Thermosetting adhesive (B-stage adhesive), or other adhesive material. Subsequently, a wafer 122 (shown in Figure 3) is provided, and the distribution of the pads 123❺ can be, for example, a peripheral pad 11 200933847 26537twf Doc/n or t central pad, etc. In the present embodiment, the distribution of the pads is described as a central distribution type. The active surface of the wafer 122 has a plurality of convexities. Block 124, and each bump 124 is formed on the pad 123 of the wafer 122, such as bump material, for example Gold, copper, recorded, ❻ 铝 aluminum, tin, lead or an alloy formed by combining one of the above metals. Moreover, referring again to 'turning the wafer 122' so that the active surface faces downward, and the cymbal 122 can The bumps 12 are attached to the solder resist layer, and the bumps 124 on the wafer 122 are electrically connected to the re-wiring circuit layer: a solder pad 122. 〃 The description 疋 'in this embodiment' By forming a solder resist layer, such as a _-type adhesive material having a double-order property, the crystal solder layer, the re-distribution circuit layer, the dielectric layer and the lead frame can be made more convenient for each process. The transport process is easy and effective, and the Π ( (4) 转 转 转 线路 线路 线路 116 116 116 116 116 116 116 116 116 四 四 四 四 四 四 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 116 In the present embodiment, the 7* chip-on-package packaging technology replaces the wire bonding of the conventional four-flat... pin type, so that the packaged body can be further removed by λ! Body thickness. Next, please refer to FIG. 1F and FIG. 4, and FIG. 4 is a schematic cross-sectional view along line (four). The second two ^ formed with - seal _ 126. Difficult to 126 Z solder layer, and dielectric layer (10), _ can be ^ 122 bare way out the wire _ these pins _ lower surface, another package adhesive 12 26537twf.doc / n 200933847 The body 120 can also cover the sides of the pins 102. A mounting gel 126 can also flow into the dielectric layer 108 and the solder mask U8 in the second pass = through opening m, which can make the sealing material uniform The gaps are distributed such that the encapsulant colloid 126 and the wafer 122, the dielectric layer 1 8 and the material of the encapsulant 126 are epoxy trees; or
接下來，以圖1F與圖4說明利用上述之封裝製程所 形成之本發明的覆晶式四方扁平無引腳型態封裝結構，其 中封裝結構之各構件的㈣及其形成方法已於上述中做^ 細說明，故於此不再贅述。 本實施例的封震結構包括介電層1〇8、多個引腳1〇2、 重配置線路層116、防焊層118、黏著層12〇以及晶片122。 其中，如圖1Α所示，引腳1〇2例如是與一框架1〇4連接 構成本實施例之導線架1〇6，且引腳1〇2為沿框架^⑽中 心延伸而呈陣列排列。 i承上述，引腳1〇2是配置於介電層1〇8中，且暴露出 其上，面與下表面。而且，如圖2所示，介電層108的表 面與這些引腳102的上表面切齊，且介電層觀的厚度小 於或等於引腳1G2的高度。在—實施例中，介電層⑽中 具有至少一貫通開口 110。 另外，重配置線路層116配置在介電層108上，此重 配置線路々116包含多個烊塾112以及多條導線114(如圖 1C所不）。防焊層覆蓋重配置線路層116、介電層108 引腳102，且防焊層118暴露出重配置線路層116之焊 墊Π2的表面。在一實施例中，在防焊層118中亦暴露出 13 26537twf.doc/n 200933847 貫通開π m。黏著層120配置在防焊層118上本發明 所使用之黏著層120例如是具有雙階特性之熱固性膠材， 得以使封裝過程更具便利性。晶片122具有多個凸塊124, 且藉由黏者層120以貼附於防焊層U8上，而各凸塊 分別與重配置線路層m的其中一個焊塾⑴電性連接。 ❹ ❹ 本實施·縣結構射包括配置有封裝雜 ’，、包覆晶片122、防焊層118與介電層⑽較佳的 ^可以填充於晶片122與防焊層118所包圍形成之空間 而且’封裝膠體m裸露出導線架1〇6之這些引 下表面，另外封裝膠體126還可包覆這些引腳ι〇2 ^則邊。在-實關中，縣膠體126亦可填滿介電層⑽ 與防焊層118中所形成的貫通開口 11〇。 综上所述，在本發明之封裝製程與封裝結構中， 層’其可與引聽合’且在其上可形成重配置線路， 而可適用於具有不同形式焊墊之晶片。另外，介電層及盆 =的重配置線路層，亦可取代習知封裝製程中的^板了 使曰曰片可藉由重配置線路層與引腳電性連接。而且， =的貫賴π可賊裝賴簡均自分佈轉滿所 j ’而提高封裝雜與“、介電層具有更佳的結合^， 本發明可以使収小尺寸晶片，_更可以降低 雖然本發明已以較佳實施例揭露如上，然其 限定本發明’任何熟習此技藝者，在不脫離本發明之 ^範圍内’當可作些許之更動與潤饰，因此本發明= 範圍當視後附之申請專利範圍所界定者為準。 …隻 26537twf.doc/n 200933847 【圖式簡單說明】 圖1A至圖IF為依照本發明之一實施例所繪示的覆晶 式四方扁平無引腳型態封裝製程的剖面示意圖。 圖2為繪示圖1B之結構沿著線Ι-Γ的剖面示意圖。 圖3為繪示本發明之一實施例的晶片的示意圖。 圖4為繪示圖1F之結構沿著線ΙΙ-ΙΓ的剖面示意圖。 【主要元件符號說明】 102 :引腳 104 :框架 106 :導線架 108 :介電層 110 :貫通開口 112、123 :焊墊 114 :導線 116 :重配置線路層 118 :防焊層 120 :黏著層 122 :晶片 124 :凸塊 126 :封裝膠體 128 :空間 15Next, a flip-chip quad flat no-lead package structure of the present invention formed by the above-described package process will be described with reference to FIG. 1F and FIG. 4, wherein (4) of each component of the package structure and a method for forming the same are described above. Do a detailed description, so I won't go into details here. The shock absorbing structure of this embodiment includes a dielectric layer 1 〇 8 , a plurality of leads 1 〇 2, a relocation wiring layer 116 , a solder resist layer 118 , an adhesive layer 12 〇 , and a wafer 122 . As shown in FIG. 1A, the pin 1〇2 is connected to a frame 1〇4 to form the lead frame 1〇6 of the embodiment, and the pins 1〇2 are arranged in an array along the center of the frame ^(10). . In the above, the pin 1〇2 is disposed in the dielectric layer 1〇8, and the upper surface and the lower surface are exposed. Moreover, as shown in Fig. 2, the surface of the dielectric layer 108 is aligned with the upper surface of the pins 102, and the thickness of the dielectric layer is less than or equal to the height of the pin 1G2. In an embodiment, the dielectric layer (10) has at least one through opening 110 therein. In addition, the reconfiguration line layer 116 is disposed on the dielectric layer 108. The reconfiguration line 116 includes a plurality of turns 112 and a plurality of wires 114 (not shown in FIG. 1C). The solder mask covers the reconfigured wiring layer 116, the dielectric layer 108 pin 102, and the solder resist layer 118 exposes the surface of the pad 2 of the reconfigured wiring layer 116. In an embodiment, 13 26537 twf.doc/n 200933847 is also exposed in the solder mask layer 118. The adhesive layer 120 is disposed on the solder resist layer 118. The adhesive layer 120 used in the present invention is, for example, a thermosetting adhesive having a double-order property, which makes the packaging process more convenient. The wafer 122 has a plurality of bumps 124, and is adhered to the solder resist layer U8 by the adhesive layer 120, and each bump is electrically connected to one of the soldering pads (1) of the reconfigurable wiring layer m. ❹ ❹ This embodiment·the county structure includes a package impurity, and the package wafer 122, the solder resist layer 118 and the dielectric layer (10) are preferably filled in a space surrounded by the wafer 122 and the solder resist layer 118. The encapsulating colloid m exposes the lower surface of the lead frame 1〇6, and the encapsulant 126 can also cover the pins ι〇2^. In the real-time, the county colloid 126 may also fill the dielectric layer (10) and the through opening 11〇 formed in the solder resist layer 118. In summary, in the package process and package structure of the present invention, the layer 'which can be combined with the listener' can form a reconfigurable line thereon, and can be applied to a wafer having different types of pads. In addition, the dielectric layer and the potted reconfigurable circuit layer can also replace the board in the conventional packaging process so that the chip can be electrically connected to the pin by reconfiguring the circuit layer. Moreover, the π 可 可 装 装 装 均 均 均 均 均 均 均 均 均 均 均 均 均 均 均 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高Although the present invention has been disclosed in the above preferred embodiments, the invention is intended to be limited to the details of the invention, and the invention may be modified and modified. The scope of the patent application is defined as follows. ...only 26537 twf.doc/n 200933847 [Simplified Schematic] FIG. 1A to FIG. 1A are flip-chip quad flat nos according to an embodiment of the present invention. 2 is a schematic cross-sectional view of the structure of FIG. 1B along the line Γ-Γ. FIG. 3 is a schematic view of a wafer according to an embodiment of the present invention. 1F is a schematic cross-sectional view of the structure along the line ΙΓ-ΙΓ. [Main component symbol description] 102: Pin 104: Frame 106: Lead frame 108: Dielectric layer 110: Through opening 112, 123: Pad 114: Conductor 116 : reconfiguration circuit layer 118: solder resist layer 120: adhesive 122: wafer 124: bump 126: encapsulant 128: Space 15