200926926 九、發明說明： 【發明所屬之技術領域】 ' 本發明涉及電路板製作技術，尤其涉及一種電路板導 • 孔之製作方法。 【先前技術】 隨著電子產品往小型化、高速化方向發展，電路板亦 從單面電路板、雙面電路板往多層電路板方向發展。多層 電路板係指具有多層導電線路之電路板，由於其具有較多 〇佈線面積、較高裝配密度而得到廣泛應用，請參見Takahashi， A.等人於 1992 年發表於 IEEE Trans, on Components, Packaging，and Manufacturing Technology 之文獻 High density multilayer printed circuit board for HITAC M-880。 多層電路板之各層導電線路之間藉由導孔實現電氣連 通。所述導孔係指孔壁具有一定厚度可導電鍍銅層之過 孔，所述過孔係指穿透各層導電線路間之樹脂層並連接各 層導電線路之通孔、盲孔或埋孔。孔壁鍍銅層之品質十分 ϋ 重要，其會影響各層導電線路間之連通效果，進而影響多 層電路板之工作性能。 多層電路板之導孔通常藉由如下方法製作。首先於覆 銅板（Copper Clad Laminate，CCL)之預定位置鑽孔以形 成過孔，該覆銅板係指包括銅箔與樹脂層之板狀基材。然 後進行化學鍍銅製程，於過孔之孔壁及覆銅板之銅箔表面 形成化學鍍銅層。由於化學鍍銅層之厚度僅為零點幾個微 米或幾個微米，為確保孔壁銅層之連續性與可靠性，化學 200926926 鍍銅後還需要進行電鍍薄銅製程，以於化學鍍銅層上形成 一層電鍍薄銅層。之後再藉由圖像轉移法以僅於孔壁之電 鍍薄銅層上形成電鍍厚銅層，而並不於覆銅板之銅箔表面 形成電鍍厚銅層。從而，不但避免浪費電鍍液，而且使得 孔壁銅層增加至需要厚度，具有較好導電性及可靠性。200926926 IX. INSTRUCTIONS: [Technical Field of the Invention] The present invention relates to a circuit board manufacturing technology, and more particularly to a method for manufacturing a circuit board guide hole. [Prior Art] With the development of electronic products in the direction of miniaturization and high speed, circuit boards have also evolved from single-sided circuit boards and double-sided circuit boards to multilayer circuit boards. Multi-layer circuit board refers to a circuit board with multiple layers of conductive lines. It is widely used due to its large wiring area and high assembly density. Please refer to Takahashi, A. et al., 1992, IEEE Trans, on Components. Packaging, and Manufacturing Technology, High density multilayer printed circuit board for HITAC M-880. Electrical communication is made between the conductive lines of each layer of the multilayer circuit board through the via holes. The via hole refers to a via hole having a certain thickness of a conductive copper plating layer, and the via hole refers to a through hole, a blind hole or a buried hole which penetrates the resin layer between the conductive lines of each layer and connects the conductive lines of the respective layers. The quality of the copper plating layer on the hole wall is very important, which affects the connection between the conductive lines of each layer, which in turn affects the performance of the multi-layer circuit board. The via holes of the multilayer circuit board are usually fabricated by the following method. First, a hole is drilled at a predetermined position of a Copper Clad Laminate (CCL), which is a plate-like substrate including a copper foil and a resin layer. Then, an electroless copper plating process is performed to form an electroless copper plating layer on the surface of the via hole and the copper foil of the copper clad laminate. Since the thickness of the electroless copper plating layer is only a few micrometers or a few micrometers, in order to ensure the continuity and reliability of the copper layer of the hole wall, the chemical 200926926 needs to be electroplated with a thin copper process for electroless copper plating. A layer of electroplated thin copper is formed on the layer. Thereafter, an electroplated thick copper layer is formed on the electroplated thin copper layer only on the hole walls by an image transfer method, and a thick copper plating layer is not formed on the surface of the copper clad copper foil. Thereby, not only the waste of the plating solution is avoided, but also the copper layer of the hole wall is increased to the required thickness, which has better conductivity and reliability.
❹ 惟，如上所述之導孔之製作方法具有如下缺點：第一， 導孔之製作需要較多製程，較為複雜；第二，於覆銅板之 銅箔表面形成化學鍍銅層與電鍍薄鋼層，由於電鍍薄銅層 之均勻性、可撓性較差，從而降低覆銅板之可撓性以及後 續製作之線路品質；第三，孔壁銅層包括化學鍍銅層、電 鍍薄銅層及電鍍厚銅層，各銅層之結構 將對孔壁_之導電性、穩定性造絲響/b，、有差異’ 有鑑於此，有必要提供一種電路板導孔之製作方法， 其製程簡單’對覆銅板可撓性以及線路品質影響較小，且 形成之孔壁銅層之導電性及穩定性均較好。 【發明内容】 以下將以實施例說明一種電路板導孔之製作方法。 -種電路板導孔之製作方法，包括以下步驟：提供具 有至少-過孔之覆銅基材；進行化學料製㈣於過孔之 孔壁形成-層化學_層；烘烤該覆鋼基材，以去除化與 鍍銅層中之水分；進行魏銅製程以於孔壁之化學鑛銅: 上形成-層電鑛銅層，從而，將該過孔 本技術方案之電路板導孔之製作方法具有點. 首先，化學㈣後直接進行魏厚銅製程，省略電鐘薄銅 200926926 製程，簡化電路板導孔之製作工藝；其次，僅於孔壁之化 學鍍銅層上形成電鍍銅層，避免於覆銅板表面形成電鍍銅 層，從而並不對覆銅板之可撓性及後續製作之線路品質造 • 成影響；再次，藉由烘烤覆銅板去除化學鍍銅層中之水分， 不但使得化學鍍銅層結構較為緻密，而且可避免化學鍍銅 層完全鈍化；最後，形成之孔壁銅層僅包括極薄之化學鑛 銅層與較厚之電鍍銅層，孔壁銅層之導電性能、穩定性能 較為良好。 ®【實施方式】 下面將結合附圖及實施例，對本技術方案提供之電路 板導孔之製作方法作進一步之詳細說明。 請參閱圖1，本技術方案實施方式提供之電路板導孔之 製作方法包括以下步驟： 第一步，提供具有至少一過孔101之覆銅基材10。 該覆銅基材10包括至少二表面銅層及至少一樹脂層， ^其可為雙面覆銅基板，還可為已完成内部線路製作、尚未 進行表面線路製作之多層基板。請參閱圖2，本實施例中， 覆銅基材10為雙面覆銅基板，其包括第一銅層11、第二銅 層12及位於第一銅層11與第二銅層12間之樹脂層13。該 第一銅層11、第二銅層12可為壓延銅箔或電解銅箔，優選 為具有較好可撓性之壓延銅箔。該樹脂層13可為硬性樹脂 層，如環氧樹脂、玻纖布等，亦可為柔性樹脂層，如聚酿 亞胺（Polyimide，PI )、聚乙烯對苯二曱酸乙二醇醋 (Polyethylene Terephtalate, PET)、聚四敦乙烯（Teflon)、聚 200926926 硫胺（Polyamide)、聚曱基丙浠酸甲6|(P〇ly-methyl-methacrylate，PMMA)、聚碳酸酯（Polycarbonate)或聚醯亞胺 -聚乙烯-對苯二甲醋共聚物（Polyamide polyethylene-• terephthalate copolymer)等。 另外，第一銅層11、第二銅層12與樹脂層13之間還 可具有黏膠層，以使得第一銅層11、第二銅層12與樹脂層 13之間具有較大之黏結力。 該覆銅基材10可具有一個或複數過孔101，該過孔101 〇係指至少貫穿一銅層與一樹脂層之通孔或盲孔。本實施例 中，覆銅基材10具有一過孔101，其為貫穿第一銅層11、 樹脂層13及第二銅層12之通孔，以該過孔101為例，說 明將過孔101製成導孔之方法。 第二步，進行化學鍍銅製程以於過孔101孔壁形成一 層化學鍍銅層20。 化學鐘銅又稱自催化鑛銅（Autocatalytic Plating)、無 ^電鍍銅（Electroless Copper Plating)等，係指於沒有外加電流 條件下，利用自催化氧化還原反應原理於基體表面形成具 有一定厚度及功能之金屬銅層之處理技術。 化學鍍銅製程通常包括清洗、粗化、預浸、活化、沈 銅等步驟。具體地，首先以鹼液清洗覆銅基材10,去除覆 銅基材10表面之油污、灰塵。其次，以雙氧水-硫酸體系粗 化覆銅基材10之第一銅層11表面、笫二銅層12表面以及 過孔101孔壁。再次，將覆銅基材10置於預浸液或敏化液 中，以預防覆銅基材1〇帶入雜質，並潤濕第一銅層11表 200926926 .面、第二銅層12表面以及過孔101孔壁。預浸後進行活化， 使貴金屬催化劑均勻吸附於第一銅層11表面、第二銅層12 ' 表面以及過孔101之孔壁，形成化學沈銅所需之活化中心。 最後即可將覆銅基材10放置於化學鍍銅液中，使得化學鍍 銅液中之金屬銅鹽與還原劑於具有催化活性之第一銅層11 表面、第二銅層12表面以及過孔101孔壁上進行自催化氧 化還原反應，並於第一銅層11表面、第二銅層12表面以 及過孔101孔壁上形成具有一定厚度之化學鍍銅層20，如 〇圖3所示。 通常來說，該化學鍍銅層20之厚度可為0.1〜3微米之 間。 第三步，烘烤該覆銅基材10，以去除化學鍍銅層20 中之水分。 將形成化學鍍銅層20之覆銅基材10置於100〜150攝 氏度之溫度環境下，烘烤1〜4個小時，以充分去除化學鍍 ^銅層20中之水分及氫氣，使得化學鍍銅層20結構緻密， 從而使得化學鍍銅層20較好結合於孔壁，並具有較好導電 性能。另，烘烤使得化學鍍銅層20僅於表面形成一極薄緻 密氧化銅層，進而阻止化學鍍銅層20進一步氧化，保證化 學鑛銅層之導電性。 第四步，進行電鍍銅製程以於孔壁之化學鍍銅層20上 形成一層電鍍銅層30，從而將該過孔101製成導孔102。 進行電鍍銅製程之前，通常需要進行去除不導電氧化 銅層、露出導電銅層之步驟，以能於化學鍍銅層20上進一 200926926 步形成電鍍銅層30。去除氧化銅層之方法優選為將覆銅基 材10放置於3〜6%之硫酸溶液中進行酸洗適當時間，不但 可將氧化銅層去除，而且不會對銅層造成過度咬钱。當然’ ' 除酸洗外，亦可將覆銅基材10放置於硫酸-雙氧水混合溶 液、硫酸-硫酸鈉混合溶液或其他溶液.中清洗適當時間。 為避免於第一銅層11、第二銅層12上形成電鍍銅層 30,造成電鍍液浪費，將覆銅基材10浸置於電鍍槽之前， 通常還需藉由圖像轉移法以遮蔽第一銅層11、第二銅層 ® 12，僅露出過孔101，從而僅於過孔101孔壁之化學鍍銅層 20上形成電鍍銅層30，而不於第一銅層11、第二銅層12 之化學鍍銅層20上形成電鍍銅層30。具體地，請參閱圖4, 首先於第一銅層11、第二銅層12上分別壓合第一乾膜14、 第二乾膜15。該第一乾膜14、第二乾膜15可為正型光阻， 亦可為負型光阻。本實施例中，僅以正型光阻為例，說明 其後之曝光、顯影等製程。其次，請參閱圖5，分別藉由第 ^ 一光罩16、第二光罩17對第一乾膜14、第二乾膜15進行 曝光。該第一光罩16、第二光罩17分別具有第一開口 161、 第二開口 171，該第一開口 161、第二開口 171均與過孔101 對應。曝光時，與第三開口 141對應之乾膜受到光線照射， 發生分解反應，而沒有受到光線照射之乾膜則不發生反 應。再次，以顯影液噴淋第一乾膜14、第二乾膜15，發生 分解反應之乾膜於顯影液中具有高溶解度，可被顯影液溶 解；而未發生分解反應之乾膜則於顯影液中具有低溶解 度，不可被顯影液溶解。因此，顯影後，與第一開口 161、 11 200926926 過孔101對應之第一乾膜14相應區域形成第三開口 141， 與第二開口 171、過孔101對應之第二乾膜15相應區域形 成第四開口 151，如圖6所示。 ' 然後，將覆銅基材10放置於電鍍槽中，以覆銅基材10 做陰極，以銅棒或銅板做陽極，以含有銅鹽之電解質溶液 作為電鍍液，接通直流電源即可於電鍍液中發生電解反 應，從而於覆銅基材10之導電表面沈積上電鍍銅層30， 即，於孔壁之化學鍍銅層20上形成一定厚度之電鍍銅層 ◎ 30,如圖7所示。電鍍銅層30之厚度可依具體電路板之設 計需求而定，一般可為5〜30微米。 請參閱圖8,於覆銅基材10上形成電鍍銅層30後，還 應當將第一乾膜14、第二乾膜15剝除，露出第一銅層11、 第二銅層12，以便於進行後續製程。 如上所述，於過孔101之孔壁上形成了化學鍍銅層20 與電鍍銅層30，即，將過孔101製成了具有導通第一銅層 • 11、第二銅層12能力之導孔102。 將覆銅基材10之過孔101製成導孔102之後，後續可 進行導電線路之製作、光學檢測、阻焊層塗覆等步驟，從 而將覆銅基材10製成雙面電路板。 本技術方案之電路板導孔之製作方法具有如下優點： 首先，化學鍍銅後直接進行電鍍厚銅製程，省略電鍍薄銅 之製程，從而簡化電路板導孔之製作工藝；其次，僅於孔 壁之化學鐘銅層上形成電鐘銅層，避免於覆銅板表面形成 電鍍銅層，從而並不對覆銅板之可撓性與後續製作之線路 12 200926926 之品質造成影響；再次，藉由烘烤覆銅板去除化學鍍銅層 中之水分，不但使得化學鍍銅層結構較為緻密，而且可避 "免化學鍍銅層完全鈍化；最後，形成之孔壁銅層僅包括極 • 薄之化學鍍銅層與較厚之電鍍銅層，孔壁銅層之導電性、 穩定性均較為良好。 綜上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案 ®技藝之人士援依本發明之精神所作之等效修飾或變化，皆 應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係本技術方案實施方式提供之電路板導孔之製作 方法之流程圖。 圖2係本技術方案實施方式提供之覆銅基材之示意圖。 圖3係本技術方案實施方式提供之覆銅基材上沈積化 $學鑛銅層之示意圖。 圖4係本技術方案實施方式提供之覆銅基材表面壓膜 後之不意圖。 圖5係本技術方案實施方式提供之覆銅基材表面壓 膜、曝光後之示意圖。 圖6係本技術方案實施方式提供之覆銅基材表面壓 膜、曝光、顯影後之示意圖。 圖7係本技術方案實施方式提供之覆銅基材之孔壁上 形成電鍍銅後之示意圖。 13 200926926 圖8係本技術方案實施方式提供之覆銅基材表面之乾 膜剝除後之示意圖。 【主要元件符號說明】 '覆銅基材 10 第一銅層 11 第二銅層 12 樹脂層 13 第一乾膜 14 ❹第二乾膜 15 第一光罩 16 第二光罩 17 化學鍍銅層 20 電鍍銅層 30 過孔 101 導孔 102 ©第三開口 141 第四開口 151 第一，開口 161 第二開口 171 14惟 However, the manufacturing method of the via hole as described above has the following disadvantages: First, the fabrication of the via hole requires more processes and is complicated; secondly, the electroless copper plating layer and the electroplated thin steel are formed on the surface of the copper foil of the copper clad laminate. Layer, due to the uniformity and flexibility of the electroplated thin copper layer, thereby reducing the flexibility of the copper clad laminate and the quality of the subsequently fabricated circuit; third, the hole wall copper layer includes an electroless copper plating layer, an electroplated thin copper layer, and electroplating Thick copper layer, the structure of each copper layer will make a sound / b, and there is a difference in the conductivity and stability of the hole wall. In view of this, it is necessary to provide a method for manufacturing a circuit board guide hole, which is simple in process. The copper clad plate has less influence on the flexibility and the line quality, and the formed copper layer of the hole wall has good conductivity and stability. SUMMARY OF THE INVENTION A method of fabricating a via hole of a circuit board will be described below by way of embodiments. - a method for fabricating a via hole of a circuit board, comprising the steps of: providing a copper-clad substrate having at least a via hole; performing a chemical material preparation (4) forming a hole-layer chemical layer on the via hole; baking the steel-clad base Material to remove moisture from the copper plating layer; perform a Wei copper process to form a chemical layer of copper on the pore wall: a layer of electro-mineral copper is formed thereon, thereby, the via hole of the circuit board of the present technical solution is The manufacturing method has a point. First, after the chemical (four), the Wei thick copper process is directly performed, the electric clock thin copper 200926926 process is omitted, and the manufacturing process of the circuit board guide hole is simplified; secondly, the electroplated copper layer is formed only on the electroless copper plating layer of the hole wall. To avoid the formation of an electroplated copper layer on the surface of the copper clad laminate, so as not to affect the flexibility of the copper clad laminate and the quality of the subsequently produced circuit; again, the moisture in the electroless copper plating layer is removed by baking the copper clad plate, not only The electroless copper plating layer is relatively dense and can avoid complete passivation of the electroless copper plating layer. Finally, the formed copper wall layer only includes a very thin chemical ore layer and a thick electroplated copper layer, and the conductivity of the copper layer of the hole wall ,stability Can be better. ® [Embodiment] The method for fabricating the via hole of the circuit board provided by the present technical solution will be further described in detail below with reference to the accompanying drawings and embodiments. Referring to FIG. 1, a method for fabricating a via hole of a circuit board provided by an embodiment of the present technical solution includes the following steps: In a first step, a copper clad substrate 10 having at least one via 101 is provided. The copper-clad substrate 10 includes at least two surface copper layers and at least one resin layer, which may be a double-sided copper-clad substrate, or a multi-layer substrate on which internal wiring has been completed and surface lines have not been fabricated. Referring to FIG. 2 , in the embodiment, the copper-clad substrate 10 is a double-sided copper-clad substrate, and includes a first copper layer 11 , a second copper layer 12 , and a first copper layer 11 and a second copper layer 12 . Resin layer 13. The first copper layer 11 and the second copper layer 12 may be a rolled copper foil or an electrolytic copper foil, preferably a rolled copper foil having good flexibility. The resin layer 13 may be a hard resin layer such as an epoxy resin, a fiberglass cloth, or the like, or a flexible resin layer such as Polyimide (PI) or polyethylene terephthalate (eg, polyethylene terephthalate). Polyethylene Terephtalate, PET), Teflon, Poly 200926926 Polyamide, P〇ly-methyl-methacrylate (PMMA), Polycarbonate (Polycarbonate) or Polyamide polyethylene-terephthalate copolymer (Polyamide polyethylene-• terephthalate copolymer). In addition, an adhesive layer may be further disposed between the first copper layer 11 and the second copper layer 12 and the resin layer 13 so that the first copper layer 11 and the second copper layer 12 and the resin layer 13 have a large bond. force. The copper clad substrate 10 may have one or a plurality of vias 101 which are through holes or blind vias extending through at least one of the copper layers and a resin layer. In this embodiment, the copper-clad substrate 10 has a via 101 which is a through hole penetrating through the first copper layer 11, the resin layer 13, and the second copper layer 12. The via 101 is taken as an example to illustrate the via hole. 101 method of making a guide hole. In the second step, an electroless copper plating process is performed to form a layer of electroless copper plating layer 20 on the walls of the via 101. Chemical clock copper, also known as Autocatalytic Plating, Electroless Copper Plating, etc., refers to the formation of a certain thickness and function on the surface of the substrate by the principle of autocatalytic redox reaction without applied current. The treatment technology of the metal copper layer. The electroless copper plating process usually includes steps of cleaning, roughening, prepreg, activation, and copper sinking. Specifically, the copper-clad substrate 10 is first washed with an alkali solution to remove oil stains and dust on the surface of the copper-clad substrate 10. Next, the surface of the first copper layer 11 of the copper clad substrate 10, the surface of the beryllium copper layer 12, and the via 101 walls are roughened by a hydrogen peroxide-sulfuric acid system. Again, the copper-clad substrate 10 is placed in a prepreg or sensitizing liquid to prevent the copper-clad substrate 1 from being contaminated with impurities, and wetting the first copper layer 11 to the surface of the second copper layer 12 And the through hole 101 hole wall. After the pre-dip is activated, the noble metal catalyst is uniformly adsorbed on the surface of the first copper layer 11, the surface of the second copper layer 12', and the pore walls of the via 101 to form an activation center required for chemical copper deposition. Finally, the copper-clad substrate 10 can be placed in the electroless copper plating solution, so that the metal copper salt and the reducing agent in the electroless copper plating solution are on the surface of the catalytically active first copper layer 11, the surface of the second copper layer 12, and An autocatalytic redox reaction is performed on the pores of the pores 101, and an electroless copper plating layer 20 having a certain thickness is formed on the surface of the first copper layer 11, the surface of the second copper layer 12, and the pore walls of the via 101, as shown in FIG. Show. Generally, the electroless copper plating layer 20 may have a thickness of between 0.1 and 3 μm. In the third step, the copper clad substrate 10 is baked to remove moisture in the electroless copper plating layer 20. The copper-clad substrate 10 forming the electroless copper plating layer 20 is placed in a temperature environment of 100 to 150 degrees Celsius, and baked for 1 to 4 hours to sufficiently remove moisture and hydrogen in the electroless copper plating layer 20, so that electroless plating is performed. The copper layer 20 is densely structured, so that the electroless copper plating layer 20 is better bonded to the pore walls and has better electrical conductivity. In addition, the baking causes the electroless copper plating layer 20 to form a very thin and dense copper oxide layer only on the surface, thereby preventing the electroless copper plating layer 20 from further oxidizing and ensuring the conductivity of the chemical ore copper layer. In the fourth step, an electroplating copper process is performed to form an electroplated copper layer 30 on the electroless copper plating layer 20 of the hole wall, thereby forming the via hole 101 into the via hole 102. Before performing the electroplating copper process, a step of removing the non-conductive copper oxide layer and exposing the conductive copper layer is generally required to form a copper plating layer 30 on the electroless copper plating layer 20 by a step of 200926926. The method of removing the copper oxide layer is preferably carried out by placing the copper-clad substrate 10 in a sulfuric acid solution of 3 to 6% for pickling for a suitable period of time, which not only removes the copper oxide layer, but also does not cause excessive biting of the copper layer. Of course, ''In addition to pickling, the copper-clad substrate 10 may be placed in a sulfuric acid-hydrogen peroxide mixed solution, a sulfuric acid-sodium sulfate mixed solution or other solution for a suitable period of time. In order to avoid the formation of the electroplated copper layer 30 on the first copper layer 11 and the second copper layer 12, the plating solution is wasted. Before the copper-clad substrate 10 is immersed in the plating bath, it is usually shielded by image transfer. The first copper layer 11 and the second copper layer 12 are only exposed to the via hole 101, so that the electroplated copper layer 30 is formed only on the electroless copper plating layer 20 of the via 101 wall, instead of the first copper layer 11, An electroplated copper layer 30 is formed on the electroless copper plating layer 20 of the two copper layers 12. Specifically, referring to FIG. 4, the first dry film 14 and the second dry film 15 are first pressed on the first copper layer 11 and the second copper layer 12, respectively. The first dry film 14 and the second dry film 15 may be positive photoresist or negative photoresist. In the present embodiment, only the positive photoresist is taken as an example to describe the subsequent exposure and development processes. Next, referring to Fig. 5, the first dry film 14 and the second dry film 15 are exposed by the first photomask 16 and the second photomask 17, respectively. The first mask 16 and the second mask 17 respectively have a first opening 161 and a second opening 171. The first opening 161 and the second opening 171 respectively correspond to the via 101. At the time of exposure, the dry film corresponding to the third opening 141 is irradiated with light to cause a decomposition reaction, and the dry film which is not irradiated with the light does not react. Further, the first dry film 14 and the second dry film 15 are sprayed with a developing solution, and the dry film which has undergone decomposition reaction has high solubility in the developing solution and can be dissolved by the developing solution; and the dry film which does not undergo decomposition reaction is developed. It has low solubility in the liquid and cannot be dissolved by the developer. Therefore, after the development, the corresponding region of the first dry film 14 corresponding to the first opening 161, 11 200926926 via 101 forms a third opening 141, and the corresponding region of the second dry film 15 corresponding to the second opening 171 and the via 101 is formed. The fourth opening 151 is as shown in FIG. Then, the copper-clad substrate 10 is placed in a plating bath, the copper-clad substrate 10 is used as a cathode, the copper rod or the copper plate is used as an anode, and the electrolyte solution containing a copper salt is used as a plating solution, and the DC power source can be turned on. An electrolytic reaction occurs in the plating solution to deposit an electroplated copper layer 30 on the conductive surface of the copper clad substrate 10, that is, a copper plating layer of a certain thickness is formed on the electroless copper plating layer 20 of the hole wall, as shown in FIG. Show. The thickness of the electroplated copper layer 30 can vary depending on the design requirements of the particular circuit board, and can typically be from 5 to 30 microns. Referring to FIG. 8 , after the electroplated copper layer 30 is formed on the copper clad substrate 10 , the first dry film 14 and the second dry film 15 should also be stripped to expose the first copper layer 11 and the second copper layer 12 so that For subsequent processes. As described above, the electroless copper plating layer 20 and the electroplated copper layer 30 are formed on the walls of the via holes 101, that is, the via holes 101 are formed to have the ability to conduct the first copper layer 11 and the second copper layer 12. Guide hole 102. After the via 101 of the copper-clad substrate 10 is formed as the via hole 102, subsequent steps of fabrication of the conductive trace, optical detection, and solder resist coating can be performed, thereby forming the copper clad substrate 10 into a double-sided circuit board. The manufacturing method of the circuit board guiding hole of the technical solution has the following advantages: First, the electroplating thick copper process is directly performed after electroless copper plating, the process of electroplating thin copper is omitted, thereby simplifying the manufacturing process of the circuit board guiding hole; secondly, only the hole The electric clock copper layer is formed on the copper layer of the chemical clock of the wall to avoid forming an electroplated copper layer on the surface of the copper clad board, thereby not affecting the flexibility of the copper clad board and the quality of the subsequently produced circuit 12 200926926; again, by baking The copper-clad plate removes the moisture in the electroless copper plating layer, which not only makes the electroless copper plating layer denser, but also avoids the "chemical-free copper plating layer completely passivated; finally, the formed hole-wall copper layer only includes the electro-plated electroless plating. The copper layer and the thick electroplated copper layer have good conductivity and stability of the copper layer of the hole wall. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by those skilled in the art of the present invention in the spirit of the present invention are intended to be included in the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing a method of fabricating a via hole of a circuit board provided by an embodiment of the present technical solution. 2 is a schematic view of a copper-clad substrate provided by an embodiment of the present technical solution. 3 is a schematic view showing a deposited copper layer on a copper-clad substrate provided by an embodiment of the present technical solution. 4 is a schematic view of the surface of the copper-clad substrate provided by the embodiment of the present technical solution. Fig. 5 is a schematic view showing the surface of a copper-clad substrate provided by an embodiment of the present invention and after exposure. Fig. 6 is a schematic view showing the surface of the copper-clad substrate provided by the embodiment of the present invention, after exposure and development. Fig. 7 is a schematic view showing the formation of electroplated copper on the wall of the copper-clad substrate provided by the embodiment of the present invention. 13 200926926 FIG. 8 is a schematic diagram of the dry film stripping of the surface of the copper-clad substrate provided by the embodiment of the present technical solution. [Description of main component symbols] 'Copper-clad substrate 10 First copper layer 11 Second copper layer 12 Resin layer 13 First dry film 14 ❹ Second dry film 15 First mask 16 Second mask 17 Electroless copper plating 20 electroplated copper layer 30 via 101 via hole 102 © third opening 141 fourth opening 151 first, opening 161 second opening 171 14