200924140 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板結構，尤指一種適用於覆 晶封裝結構中，且降低板彎勉情況產生之封裝基板結構。 5 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (Integration)以及微型化（Miniaturization)的封裝要求，提供 10 夕數主被動元件及線路連接之封裝基板，亦逐漸由單層板 演變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connection)擴大封裝基板上可利用的佈線面積 而配合高電子密度之積體電路（Integrated circuit)需求。 目前，半導體封裝結構大多是將半導體晶片黏貼於基 15 板頂面後進行打線接合（wire bonding)，或是將半導體晶片 以覆晶接合（Flip chip)方式與基板電性連接，爾後再於基板 之背面植以錫球，以電性連接至如印刷電路板之外部電子 裝置。 圖1為習知之封裝基板結構剖視圖。此封裝基板結構包 20括：一核心板11，其上、下表面具有一第一線路層12a;複數 個電鍍導通孔！2b’係電性導通核心板u之上、下表面之第 一線路層12a; —線路增層結構15，15，，係於該核心板11之 上、下表面上，且其表面具有複數電性連接墊152，152,； 一 防焊層16,係設於線路增層結構15，15，表面，且具有複數開 200924140 孔160，以顯露該些電性連接墊152,152';以及複數焊料凸 塊170與複數焊料球Hi，係分別形成於該些電性連接墊 152,152'上。其中，此封裝基板下方之焊料球171尺寸較大’ 以提供電性連接至一印刷電路板（圖未示），封裝基板上方之 5 焊料凸塊170尺寸較小，以提供電性連接至一晶片（圖未 示）。此外’線路增層結構15，15,係由介電層150，150'與第二 線路層151,151’依序增層所構成之結構。 然而，業界大多採用FR4，FR5或BT樹脂（Bismaleimide Triazme Resin)作為封裝基板之核心板η，介電層15〇之材 10 料大多為ABF樹脂（Ajinomoto build-up film)，因不同材料間 的熱膨脹係數差異（CTE difference)，當核心板11的厚度小 於0_4mm時’有嚴重的板彎翹情況，其加工性不良，且晶片 封裝後可靠度不佳，導致產品良率偏低。 因此，提供一種可降低板彎翹情況且提高生產良率之 15 封裝基板結構係本發明之重要目標。 【發明内容】 有鑑於此，本發明提供一種封裝基板結構，可以降低 封裝基板發生板彎翹情況’有利於加工，且晶片封裝後可 20靠度佳；同時，本發明之封裝基板結構導熱性佳，因此可 使封裝基板具有較佳之散熱效果；另外，本發明之封裝基 板結構質地輕而厚度薄，有利於輕薄化之封裝結構，且適 用於細間距線路之電性需求；最後，本發明之封裝基板結 構亦可兼具接地（ground)功能。 200924140 5 10 15BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate structure, and more particularly to a package substrate structure suitable for use in a flip chip package structure and reducing the occurrence of plate bending. 5 [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, the package substrate with 10 Hz active and passive components and line connection is gradually evolved from a single layer board to a multilayer board to enable In a limited space, the interlayer area available on the package substrate is expanded by an interlayer connection technology to meet the demand for a high electron density integrated circuit. At present, the semiconductor package structure is mainly obtained by bonding a semiconductor wafer to the top surface of the substrate 15 for wire bonding, or electrically connecting the semiconductor wafer to the substrate by flip chip bonding, and then to the substrate. The back is implanted with a solder ball to electrically connect to an external electronic device such as a printed circuit board. 1 is a cross-sectional view showing a structure of a conventional package substrate. The package substrate package 20 includes a core board 11 having a first circuit layer 12a on the upper and lower surfaces and a plurality of plated vias! 2b' is electrically connected to the first circuit layer 12a on the upper and lower surfaces of the core board u; the line build-up structure 15, 15 is attached to the upper surface and the lower surface of the core board 11, and has a plurality of surfaces on the surface a soldering pad 152, 152,; a solder mask 16, is provided on the surface of the line build-up structure 15, 15, and has a plurality of openings 200924140 holes 160 to expose the electrical connection pads 152, 152'; and a plurality of solder bumps The block 170 and the plurality of solder balls Hi are formed on the electrical connection pads 152, 152', respectively. Wherein, the solder ball 171 under the package substrate is larger in size to provide electrical connection to a printed circuit board (not shown), and the 5 solder bumps 170 above the package substrate are small in size to provide electrical connection to the Wafer (not shown). Further, the line buildup structures 15, 15 are formed by sequentially adding layers of the dielectric layers 150, 150' and the second circuit layers 151, 151'. However, the industry mostly uses FR4, FR5 or BT resin (Bismaleimide Triazme Resin) as the core plate η of the package substrate, and the dielectric layer 15 is mostly made of ABF resin (Ajinomoto build-up film), due to different materials. The difference in thermal expansion coefficient (CTE difference), when the thickness of the core plate 11 is less than 0_4 mm, there is a serious plate bending condition, the workability is poor, and the reliability after chip packaging is poor, resulting in low product yield. Therefore, it is an important object of the present invention to provide a package substrate structure which can reduce the bending of the board and improve the production yield. SUMMARY OF THE INVENTION In view of the above, the present invention provides a package substrate structure, which can reduce the bending condition of the package substrate, which is favorable for processing, and can be 20 after the wafer is packaged. Meanwhile, the thermal conductivity of the package substrate structure of the present invention Preferably, the package substrate has a better heat dissipation effect; in addition, the package substrate structure of the present invention is light in weight and thin in thickness, is advantageous for a thin and light package structure, and is suitable for electrical requirements of fine pitch lines; finally, the present invention The package substrate structure can also have a ground function. 200924140 5 10 15
本發明提供之封裝基板結構，包括：一具有一第一表 面與第—表面之鋁載板，其中’第一表面及第二表面分 別具有一氧化鋁層；一第一線路層，係配置於該鋁載板之 第表面與第一表面之氧化铭層上；以及一導電通孔，係 貫通.亥銘載板之第—表面與第二表面，以電性連接第一表 面與第二表面上之第一線路層。 述結構中，該導電通孔之結構不限定，只要能電性 連接銘載板第-表面與第二表面之第-線路層即可。一較 佳實施方式為，該導電通孔具有—貫通該㈣板之通孔， 乂及配置於通孔内壁表面上之電性導通層。其中，通孔 斤餘工間可填滿—樹脂；或者，該電性導通層係填滿 孑。 上述結構中，通孔㈣表面可作為—接地區，其係紹 ，並與配置其上之電性導通層電性連接。 ^結構中，該電性導通層可延伸至通孔周緣紹载板 严。1 士面與第二表面之部分表面’以成為-電性導通 土，4電性導通環之平面形狀可㈣環與開環其中 壁表^明之另—實施例中’上述結構復可包括於通孔内 電性導通：：性導通層間具有一氧化銘層，遂使銘表面與 导通層互不電性導通。 具有ίΓΓ，氧化銘層於該銘載板之至少-表面復可 之 肩口’以顯露部份之鋁表面，其係與配置其上 #第-線路層電性連接，以提供—接地區。 20 200924140 發明之封裝基板結構中，復包括—線路增層結 構，係配置於該銘載板之至少—表面，該線路增層結構之 良式不限定，可為任何適用於封裝基板結構之線路增層結 構’較佳為包括至少一介電層、至少一疊置於該介電層上 5之第二線路層及複數導電盲孔，其令部份導電盲孔係電性 連接該些第二線路層，及電性連接第二線路層與第一線路 層，且最外面之第二線路層具有複數電性連接塾。此外， 部份導電盲孔亦可電性連接第：線路層與導電通孔之一 端。 1〇 上述結構復包括一防焊層，係配置於該線路增層結構 表面，其中該防焊層具有複數開孔，以顯露該些電性連接 塾0 綜上所述，本發明之封裝基板結構係採用兼具陶究剛 性與金屬動性之金屬（!呂）/陶究（氧化旬複合材料載板，以降 低封裝基板發生板彎勉情況。由於氧化紹具備優良的絕緣 性與機械性（楊式模數為380 Gpa)，因此可避免封裝基板產 生板f麵，有利於薄型化之封装結構；同時，紹質輕且導 熱性佳，因此可使封裝基板具有較佳之散熱效果且符合封 裝輕型化之需求；最後，本發明之封裝基板結構以銘為核 2〇 心板主體，亦可兼具接地功能。 入 【實施方式】 本發明之實施例中該等圖式均為簡化之示意圖。惟該 等圖式僅顯示與本發明有關之元件，其所顯示支元件非為 200924140 實際實施時之態樣’其實際實施時之元件數目、形狀等比 例為一選擇性之設計，且其元件佈局型態可能更複雜。 實施例1The package substrate structure provided by the present invention comprises: an aluminum carrier having a first surface and a first surface, wherein the first surface and the second surface respectively have an aluminum oxide layer; and a first circuit layer is disposed on The first surface of the aluminum carrier and the first surface of the oxidized layer; and a conductive via extending through the first surface and the second surface of the haiming carrier to electrically connect the first surface and the second surface The first circuit layer on it. In the above structure, the structure of the conductive via is not limited as long as it can electrically connect the first-surface layer of the first surface and the second surface of the carrier. In a preferred embodiment, the conductive via has a through hole penetrating through the (four) plate, and an electrical conduction layer disposed on the inner wall surface of the through hole. Wherein, the through hole can be filled with resin - or the electrically conductive layer is filled with helium. In the above structure, the surface of the through hole (4) can be used as a connection region, and is electrically connected to the electrically conductive layer disposed thereon. In the structure, the electrical conduction layer can extend to the periphery of the through hole. 1 part of the surface of the second surface and the surface of the second surface to become - electrically conductive soil, the planar shape of the 4 electrical conduction ring can be (four) ring and open ring, wherein the wall surface is different from the other embodiment - the above structure can be included in Electrical conduction in the via:: An oxidized layer between the conductive layers, so that the surface of the surface and the conductive layer are electrically non-conductive. The etched layer is etched on at least the surface of the inscription plate to expose a portion of the aluminum surface, which is electrically connected to the upper surface of the layer to provide a connection region. 20 200924140 In the package substrate structure of the invention, the circuit-added structure is disposed at least on the surface of the inscription board, and the line build-up structure is not limited, and may be any line suitable for the package substrate structure. Preferably, the build-up structure includes at least one dielectric layer, at least one second circuit layer stacked on the dielectric layer 5, and a plurality of conductive blind vias, wherein the conductive vias are electrically connected to the plurality of conductive vias. The second circuit layer is electrically connected to the second circuit layer and the first circuit layer, and the outermost second circuit layer has a plurality of electrical connections. In addition, some of the conductive blind vias may be electrically connected to one of the circuit layer and the conductive via. The structure includes a solder resist layer disposed on a surface of the circuit build-up structure, wherein the solder resist layer has a plurality of openings to expose the electrical connections. The package substrate of the present invention is described above. The structure adopts a metal (! Lu)/ceramic (metal oxide) composite material carrier plate to reduce the bending of the package substrate. Because of the excellent insulation and mechanical properties of Oxidation (Yang type modulus is 380 Gpa), so that the package substrate can be prevented from generating the surface of the board, which is advantageous for the thinned package structure. At the same time, the light weight and the thermal conductivity are good, so that the package substrate has better heat dissipation effect and conforms to the package. In the final embodiment, the package substrate structure of the present invention is a core 2 core plate body, and may also have a grounding function. [Embodiment] In the embodiments of the present invention, the drawings are simplified schematic views. However, the drawings only show the components related to the present invention, and the displayed components are not in the actual implementation of 200924140. The actual number of components and the shape of the components are one. Optional The design and layout of the elements thereof may be more complex patterns for Example 1
圊2A為本實施例之封裝基板結構剖視圖。請參見圖 5 2A，本實施例之封裝基板結構包括：一具有一第一表面2U 與一第二表面21b之鋁載板21，其中，第一表面21a及第二 表面21 b刀別具有一氧化鋁層2 π ; —第一線路層22，係配 置於触載板21之第-表面21a與第二表面m之氧化銘層 211上；一導電通孔23，係貫通該鋁載板21之第一表面 1〇與第二I面加，以電性連接第一表面2U與第二表面⑽上 之第一線路層22·，一線路增層結構24，係配置於鋁載板21 之至少一表面，包括至少一介電層24卜至少一疊置於該介 電層241上之第二線路層242及複數導電盲孔243，其中部份 導電盲孔243係電性連接該些第二線路層242、第二線路層 15 242與導電通孔23之兩端、及電性連接第二線路層242與第 一線路層22,且最外面之第二線路層242具有複數電性連接 墊24a，以及一防焊層25，係配置於線路增層結構24表面， 其中防焊層25具有複數開孔25卜以顯露電性連接墊24a。 於本實施例之封裝基板結構中，此導電通孔23具有一 20貫通鋁載板21之通孔231，以及一配置於通孔231内壁表面 上之電性導通層232，且通孔23 1内所餘空間係填滿一樹脂 233。其中，通孔231内壁表面係作為一接地區212，其係鋁 表面，並與配置其上之電性導通層232電性連接。此外，電 性導通層232係延伸至通孔231周緣該鋁载板21之第一表面 200924140 21a與第二表面21b之部分表面，以成為一電性導通環23a， 且本實施例電性導通環23a之平面形狀為閉環，如圖2人所 示0 又如圖2A’所示係本實施例之另一態樣，其結構與圖 2A大致相同，惟不同處在於，該電性導通層232係填滿通孔 231。 實施例2 本實施例之封裝基板結構與實施例丨大致相同，惟不同 10處在於，請參見圖2B及2B’，本實施例之封裝基板結構於通 孔231内壁表面與電性導通層232間復具有一氧化鋁層 211，其係το全覆蓋通孔231内壁表面，遂使鋁表面與電性 導通層232互不電性導通。 15 實施例3 本實施例之封裝基板結構與實施例2之圖2B大致相 同’惟不同處在於，請參見圖2C，氧化㈣211於該紹載板 21之至少一表面具有至少—開口 213，以顯露部份之鋁表 面，其係與配置其上之部份第一線路層22電性連接，以提 20 供一接地區212 » 實施例4 本實施例之封裝基板結構與實施例丨之圖2a,大致相 同，惟不同處在於’請參見圖2D，本實施例之電性導通層 200924140 232不具有電性導通環且該電性導通層232兩端係低於第一 線路層22之表面。 又如圖2D，所示係本實施例之另一態樣，其結構與圖2D 大致相同’惟不同處在於，該電性導通層232僅有一端係藉 5 由導電盲孔243與第二線路層242電性連接》 實施例5 本實施例之封裝基板結構與實施例4大致相同，惟不同 處在於，請參見圖2Ε及2Ε’，該電性導通層232兩端係與第 10 一線路層22之表面齊平。 實施例6 本實施例之封裝基板結構與實施例丨大致相同，惟不同 處在於，請參見圖3及3’，本實施例電性導通環23a之平面形 15 狀為開環。 據此，本發明之封裝基板結樽可以降低封裝基板發生 板彎翹情況，有利於加工，且晶片封裝後可靠度佳；同時， 本發明之封裝基板結構導熱性佳，因此可使封裝基板具有 較佳之散熱效果；另外，本發明之封裝基板結構質地輕而 厚度薄，有利於輕薄化之封裝結構，且適用於細間距線路 之電性需求；最後，本發明之封裝基板結構亦可兼具接地 (ground)功能。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而錢限 25 於上述會施你丨。 11 200924140 【圖式簡單說明】 圖1係習知之封裝基板結構剖視圖。 5 圖2A至3,係本發明較佳實施例之封裝基板結構剖視圖。2A is a cross-sectional view showing the structure of the package substrate of the present embodiment. Referring to FIG. 5A, the package substrate structure of the embodiment includes: an aluminum carrier 21 having a first surface 2U and a second surface 21b, wherein the first surface 21a and the second surface 21b have a The aluminum oxide layer 2 π ; - the first circuit layer 22 is disposed on the first surface 21a of the contact carrier 21 and the oxidized layer 211 of the second surface m; a conductive via 23 extends through the aluminum carrier 21 The first surface 1 〇 and the second I surface are electrically connected to the first surface 2U and the first circuit layer 22 on the second surface (10), and a line build-up structure 24 is disposed on the aluminum carrier 21 The at least one surface includes at least one dielectric layer 24 at least one of the second circuit layer 242 and the plurality of conductive vias 243 disposed on the dielectric layer 241, wherein the conductive vias 243 are electrically connected to the first layer The two circuit layers 242, the second circuit layer 15 242 and the two ends of the conductive via 23, and the second circuit layer 242 and the first circuit layer 22 are electrically connected, and the outermost second circuit layer 242 has a plurality of electrical connections. The pad 24a and a solder resist layer 25 are disposed on the surface of the line build-up structure 24, wherein the solder resist layer 25 has a plurality of openings 25 To expose the electrical connection pads 24a. In the package substrate structure of the embodiment, the conductive via 23 has a through hole 231 extending through the aluminum carrier 21 and an electrical conduction layer 232 disposed on the inner wall surface of the via 231, and the through hole 23 1 The remaining space is filled with a resin 233. The inner wall surface of the through hole 231 serves as a contact region 212 which is an aluminum surface and is electrically connected to the electrical conduction layer 232 disposed thereon. In addition, the electrical conduction layer 232 extends to a portion of the surface of the first surface 200924140 21a and the second surface 21b of the aluminum carrier 21 at the periphery of the through hole 231 to form an electrical conduction ring 23a, and the embodiment is electrically conductive. The planar shape of the ring 23a is a closed loop, as shown in FIG. 2, and another embodiment of the present embodiment is shown in FIG. 2A', and its structure is substantially the same as that of FIG. 2A except that the electrical conductive layer is The 232 system fills the through hole 231. The structure of the package substrate of the present embodiment is substantially the same as that of the embodiment ,, except that the difference is 10, referring to FIG. 2B and FIG. 2B, the package substrate structure of the embodiment is on the inner wall surface of the through hole 231 and the electrical conduction layer 232. There is an aluminum oxide layer 211 which completely covers the inner wall surface of the through hole 231, so that the aluminum surface and the electrical conduction layer 232 are electrically non-conductive. 15 Embodiment 3 The structure of the package substrate of this embodiment is substantially the same as that of FIG. 2B of Embodiment 2. The only difference is that, in FIG. 2C, the oxidation (four) 211 has at least one opening 213 on at least one surface of the carrier 21 to A portion of the aluminum surface is exposed, and is electrically connected to a portion of the first circuit layer 22 disposed thereon to provide a connection region 212. Embodiment 4 The package substrate structure and the embodiment of the present embodiment are shown in FIG. 2a, substantially the same, but the difference is that, please refer to FIG. 2D. The electrical conduction layer 200924140 232 of the embodiment does not have an electrical conduction ring and the two ends of the electrical conduction layer 232 are lower than the surface of the first circuit layer 22. . 2D, another aspect of the embodiment is shown, the structure of which is substantially the same as that of FIG. 2D. The only difference is that only one end of the electrically conductive layer 232 is connected by the conductive via 243 and the second. The circuit board 242 is electrically connected. Embodiment 5 The structure of the package substrate of this embodiment is substantially the same as that of Embodiment 4, except that, referring to FIG. 2A and FIG. 2, the two ends of the electrical conduction layer 232 are connected to the first one. The surface of the circuit layer 22 is flush. Embodiment 6 The structure of the package substrate of this embodiment is substantially the same as that of the embodiment, except that, referring to FIGS. 3 and 3', the planar shape of the electrical conduction ring 23a of the present embodiment is an open loop. Accordingly, the package substrate of the present invention can reduce the bending condition of the package substrate, facilitate processing, and has good reliability after chip packaging; meanwhile, the package substrate structure of the present invention has good thermal conductivity, so that the package substrate can be The heat dissipation effect of the package substrate of the present invention is lighter and thinner, which is advantageous for the thin and light package structure, and is suitable for the electrical requirements of the fine pitch circuit. Finally, the package substrate structure of the present invention can also have both Ground function. The above-described embodiments are merely examples for convenience of description, and the scope of the claims of the present invention is subject to the scope of the patent application, and the money limit 25 is applied to the above. 11 200924140 [Simplified description of the drawings] Fig. 1 is a cross-sectional view showing a structure of a conventional package substrate. 5A to 3 are cross-sectional views showing the structure of a package substrate in accordance with a preferred embodiment of the present invention.
【主要元件符號說明】 11 核心板 12b 電鍍導通孔 152, 152，，24a 電性連接塾 151， 242 第二線路層 160, 251 開孔 171 焊料球 21a 第一表面 211， 211’ 氧化銘層 213 開口 23a 電性導通環 232 電性導通層 243 導電盲孔 12a, 22 第一線路層 15, 15’，24 線路增層結構 150, 241 介電層 16, 25 防焊層 170 焊料凸塊 21 鋁載板 21b 第二表面 212 接地區 23 導電通孔 231 通孔 233 樹脂 12[Main component symbol description] 11 core board 12b plating via 152, 152,, 24a electrical connection 塾151, 242 second wiring layer 160, 251 opening 171 solder ball 21a first surface 211, 211' oxidized layer 213 Opening 23a Electrical Conduction Ring 232 Electrical Conduction Layer 243 Conductive Blind Hole 12a, 22 First Circuit Layer 15, 15', 24 Line Additive Structure 150, 241 Dielectric Layer 16, 25 Solder Mask 170 Solder Bump 21 Aluminum Carrier 21b second surface 212 connection region 23 conductive via 231 via 233 resin 12