CN1560911B - Manufacturing method of circuit carrier plate - Google Patents

Abstract

A method for manufacturing a circuit carrier is suitable for manufacturing a circuit carrier such as a package carrier or a printed circuit board. Firstly, providing a support substrate made of a conductive material, wherein the support substrate is divided into a first structural layer and a second structural layer which is mutually overlapped with the first structural layer; patterning the first structure layer to form a first conductive pattern having a plurality of first conductive contacts arranged in an array; forming an insulating pattern in a space enclosed between the second structure layer and the first conductive pattern; forming a multilayer interconnection structure on the insulating pattern and the first conductive pattern, wherein the multilayer interconnection structure has a high-density internal circuit which is connected with the first conductive contact, and the internal circuit is provided with a plurality of bonding pads which are positioned on the surface of the multilayer interconnection structure far away from the first conductive pattern; and finally, removing at least partial second structural layer to form the circuit carrier plate without the traditional Plated Through Hole (PTH) and consisting of the high-density wiring pattern and the contact array of the conductive material.

Description

Method for manufacturing circuit board

technical field

The invention relates to a method for manufacturing a circuit carrier, in particular to a circuit carrier that uses a support substrate made of conductive material as an initial layer and uses the support substrate to manufacture a circuit carrier with many conductive contacts manufacturing method.

Background technique

Flip Chip Interconnect Technology (FC for short) is a packaging method that electrically connects a chip (die) to a carrier (carrier). Flip-chip interconnection technology (FC) mainly uses the area array method to arrange multiple die pads on the active surface of the chip and form bumps on the die pads ( bump), and then after flipping the chip, these bumps are used to respectively connect the chip pad of the chip to the bump pad on the carrying part (bump pad) electrically and structurally, so that the chip can be connected via these bumps. It is electrically connected to the carrying part, and electrically connected to the external electronic device through the internal circuit of the carrying part. It is worth noting that because flip chip interconnection technology (FC) can be applied to high pin count (High Pin Count) chip packages, and has many advantages such as reducing the chip packaging area and shortening the signal transmission path, making flip chip Interconnection technology has been widely used in the field of chip packaging. Common chip packaging structures using flip chip bonding technology include flip chip ball grid array (Flip Chip/BallGrid Array, FC/BGA) and flip chip pin grid array. (Flip Chip/Pin Grid Array, FC/PGA) and other forms of chip packaging structures.

Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional flip-chip ball grid array electronic package. The electronic package 100 includes a circuit carrier 110 , a plurality of bumps 120 , a chip 130 and a plurality of solder balls 140 . The circuit carrier 110 has a top surface 112 and a bottom surface 114 opposite thereto. The circuit carrier 110 also has a plurality of bump pads 116a and a plurality of ballpads 116b. In addition, the chip 130 has an active surface 132 and an opposite back surface 134, wherein the active surface 132 of the chip 130 generally refers to the side of the chip 130 having an active device (not shown). In addition, the chip 130 also has a plurality of chip pads 136, which are disposed on the active surface 132 of the chip 130, and are used as a medium for the signal output and input of the chip 130, and the positions of the bump pads 116a are respectively connected with these chip pads 136. corresponding to the position. In addition, the bumps 120 respectively electrically and structurally connect one of the chip pads 136 with the corresponding one of the bump pads 116a. Furthermore, the solder balls 140 are respectively disposed on the solder ball pads 116b for electrical and structural connection with external electronic devices.

Please also refer to FIG. 1, the existing electronic packaging method is to assemble the chip 130 on the surface of the circuit carrier 110 after completing the internal circuit of the circuit carrier 110 and the contacts 116a, 116b, and then apply the primer (underfill) 150 fills the space enclosed by the top surface 112 of the circuit carrier 110 and the active surface 132 of the chip 130 to protect the bump pad 116a, the chip pad 136 and the bump 120, and at the same time relieve the circuit carrier 110 and the chip 130. The mismatch phenomenon of thermal strain generated between the circuit carrier 110 and the chip 130 when heated. Therefore, the chip pad 136 of the chip 130 can be electrically and structurally connected to the bump pad 116a of the circuit carrier 110 through the bump 120, and then routed down to the circuit through the internal circuit of the circuit carrier 110. The solder ball pads 116b on the bottom surface 114 of the carrier board 110 are finally electrically and structurally connected to external electronic devices via the solder balls 140 on the solder ball pads 116b.

As far as the circuit carrier board manufacturing method of high-density circuit wiring is concerned, the prior art usually uses a build-up process to form a single circuit layer on both sides of a dielectric core layer (dielectric core), or Multiple circuit layers are formed sequentially, and two circuit layers located on both sides of the dielectric core layer are electrically connected by using Plated Through Hole (PTH). However, since the circuit carrier board using a thinner dielectric core layer is prone to warp due to heat, the dielectric core layer of the circuit carrier board must have sufficient thickness so as to provide a relatively sufficient structure. Strength, but this also results in the inability to further reduce the thickness of the dielectric core layer.

In addition, in order to make plated through holes (PTH) on the dielectric core layer, the prior art usually uses drilling to form micro-sized through holes on the dielectric core layer, and then electroplating a The metal layer is on the inner wall of the through hole, and is used for electrically connecting two circuit layers respectively located on two sides of the dielectric core layer. However, since the existing plated through hole (PTH) manufacturing process usually utilizes drilling to form fine-sized through holes, the overall manufacturing cost of the circuit carrier increases. In addition, since the existing plated through hole (PTH) manufacturing process has been unable to effectively reduce the outer diameter of the plated through hole (PTH), and the plated through hole (PTH) with a larger outer diameter will have a negative impact on the electrical properties Therefore, the existing plated through hole (PTH) has become the bottleneck of the current high layout density (high layout density) circuit carrier design.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for manufacturing a circuit carrier, which is used to manufacture a circuit carrier with high wiring density and can effectively reduce the production cost of the circuit carrier.

To this end, the method for manufacturing a circuit carrier provided by the present invention includes: providing a supporting substrate made of a conductive material, the supporting substrate is divided into a first structural layer and a second structural layer overlapping with the first structural layer ; Patterning the first structural layer to form a first conductive pattern with a plurality of first conductive contacts arranged in an array; forming an insulating pattern in the space enclosed between the second structural layer and the first conductive pattern; A multi-layer interconnection structure is formed on the insulating pattern and the first conductive pattern, the multi-layer interconnection structure has a high-density internal circuit, which is connected to the first conductive contact, and the internal circuit has a plurality of interconnections located in the multi-layer bonding pads of the surface of the structure away from the first conductive pattern; finally removing at least part of the second structure layer.

Since the manufacturing method of the circuit carrier of the present invention is to manufacture a multi-layer circuit board with high density on a support substrate with electrical conductivity, high hardness (high stiffness), low coefficient of thermal expansion (low CTE) and high thermal conductivity (high thermal conductivity), Intra-layer interconnection structure, then remove the local support substrate, directly use the remaining support substrate to form multiple conductive contacts on the bottom of the circuit carrier, and become a circuit carrier with high-density circuits but no dielectric core layer; in addition, The invention does not need to form plated through holes, electroplating lines and welding mask layers, so the production cost of the circuit carrier can be effectively reduced.

Description of drawings

In order to make the above and other objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below with reference to the accompanying drawings. In the attached picture:

1 is a schematic cross-sectional view of an existing flip-chip ball grid array electronic package;

2A to 2E are schematic cross-sectional views of the manufacturing steps of the circuit carrier in a preferred embodiment of the present invention in sequence;

3 is a schematic cross-sectional view of the combination of the circuit carrier and the chip shown in FIG. 2E;

4A to 4C sequentially schematically show the cross-section of the circuit carrier board according to the preferred embodiment of the present invention, wherein a metal layer is additionally formed on the surface of the bonding pad and the conductive contact;

5A and 5B are schematic cross-sectional views of a circuit carrier board according to a preferred embodiment of the present invention, wherein the conductive contacts are made to protrude downward.

Explanation of reference signs

100 electronic package body 110 circuit carrier

112 top surface 114 bottom surface

116a bump pad 116b solder ball pad

120 bumps 130 chips

132 active surface 134 rear

136 chip pad 140 solder ball

150 Primer 200 Circuit carrier

202 Supporting substrate 204 First structural layer

206 second structural layer 208 first conductive pattern

210 first conductive contact 212 insulation pattern

214 Multi-layer interconnect structure 214a Conductor layer

214b dielectric layer 214c conductive blind hole

216 Bonding Pad 218 Plating Seed Layer

220 mask pattern 222 first metal layer

224 second metal layer 226 mask pattern

228 mask layer 230 second conductive pattern

232 Second conductive contact 240 Buried passive components

302 chip 304 conductive bump

306 primer 308 support layer

310 heat sink

Detailed ways

Please refer to FIG. 2A to FIG. 2E , which schematically illustrate a circuit carrier manufacturing method according to a preferred embodiment of the present invention in sequence.

As shown in FIG. 2A, a support substrate 202 is provided, and the substrate itself has characteristics such as electrical conductivity, high hardness (high stiffness), low coefficient of thermal expansion (low CTE) and high thermal conductivity (high thermalconductivity). Therefore, the support substrate 202 Materials such as iron, cobalt, nickel, copper, aluminum, titanium, tungsten, zirconium, chromium and their alloys, etc., and the surface of the support substrate 202 must have a relatively high level of flatness (co-planarity), in order to facilitate In a subsequent process, a multi-layer interconnection structure of microcircuits (as shown in reference numeral 214 in FIG. 2D ) is fabricated on the surface of the support substrate 202 . In addition, in order to facilitate the description of this embodiment, the supporting substrate 202 can be divided into a first structural layer 204 and a second structural layer 206 overlapping with the first structural layer 204 .

As shown in FIG. 2B, for example, by means of photolithography (photolithography), etc., the first structural layer 204 of the support substrate 202 is patterned (see FIG. 2A) to form a first conductive pattern (conductive pattern) 208, wherein the first conductive pattern 208 can constitute a plurality of first conductive contacts 210 , and these conductive contacts can be arranged in an array, for example.

As shown in FIG. 2C, for example, an insulating material is filled between the second structural layer 206 and the first conductive pattern 208 by means of printing (print), thereby forming an insulating pattern (dielectric pattern) 212. In this embodiment, An insulating material can be filled into the space enclosed between the second structural layer 206 and the first conductive pattern 208 to form an insulating pattern 212, which is a negative pattern of the first conductive pattern 208 and is connected with the first conductive pattern 208. Interfitted with each other, where the insulating material can use materials with high glass transition temperature (Tg) and low thermal expansion coefficient (CTE), such as epoxy resin (epoxy resin), polyamide resin (PI resin), BT resin, benzene (and) cyclobutene (BenzoCycloButene, BCB), polysilicate (poly(silsequioxane)), parylene (parylene), polyaryl ether (poly(aryl ether)s), polynorbornene (poly (norbornene)), polyphenylquinoxaline (poly(phenylquinoxaline)s).

As shown in FIG. 2D , for example, a multilayer interconnection structure 214 is formed on the first conductive pattern 208 and the insulating pattern 212 by a build-up process. The multi-layer interconnection structure 214 includes a plurality of patterned wire layers 214a, at least one dielectric layer 214b and a plurality of conductive blind holes 214c, wherein these wire layers 214a are sequentially overlapped on the first conductive pattern 208 and the insulating pattern 212 Each dielectric layer 214b is disposed between two adjacent wire layers 214a, and these conductive blind holes 214c respectively penetrate through one of the dielectric layers 214b, electrically connecting at least two wire layers 214a, these The wiring layer 214a and these conductive blind holes 214c together constitute an internal circuit, and the wiring forms a plurality of bonding pads 216 on the surface of the multilayer interconnection structure 214, wherein these bonding pads 216 can be formed by the conductive layer 214a, or by conductive blind holes 214c, the bonding pad 216 in FIG. 2D is represented by the latter, that is, the conductive blind hole 214c is used as the bonding pad 216 . In addition, the material of the wiring layer 214a is, for example, copper, aluminum and their alloys, and the material of the dielectric layer 214b can be silicon nitride (silicon nitride) and silicon oxide (silicon oxide), etc., or have a high glass transition temperature (Tg ) and low thermal expansion coefficient (low CTE) materials, such as epoxy resin, polyamide resin (PI resin), BT resin, benzo (and) cyclobutene (BenzoCycloButene, BCB), polysilicate (poly(silsequioxane) )), parylene, poly(aryl ether)s, polynorbornene (poly(norbornene)), poly(phenylquinoxaline)s.

As shown in FIG. 2D , the second structure layer 206 is removed by, for example, polishing or etching, thereby exposing the first conductive contacts 210 , and the fabrication of the circuit carrier 200 is completed.

Please refer to FIG. 3 , which is a schematic cross-sectional view of the combination of the circuit carrier and the chip shown in FIG. 2E . In this embodiment, the chip 302 is connected to the bonding pad 216 of the circuit carrier 200 through a plurality of conductive bumps 304 through flip chip bonding, and the circuit carrier 200 and the chip 302 A primer 306 is filled between them to form a chip package. It should be noted that the chip 302 is not only electrically connected to the circuit carrier 200 by flip-chip bonding, but also electrically connected to the circuit carrier 200 by wire bonding, but the latter is not shown In the accompanying drawings of this embodiment. In addition, in order to improve the heat dissipation effect of the chip package and increase its structural strength, a support layer (stiffner) 308 can be additionally added on the circuit carrier 200 around the chip 302, and a heat spreader (heat spreader) 310 is attached to the chip 302 and support layer 308 .

In order to facilitate the assembly of IC chips or other electronic components on the circuit carrier 200 of this embodiment in the form of surface mount technology (SMT), or to facilitate the assembly of the circuit carrier 200 in the form of surface mount technology (SMT) On the first-level circuit carrier board (not shown), please refer to FIG. 4A to FIG. 4C and the following, wherein FIG. 4A to FIG. A metal layer profile is additionally formed on the surface of the conductive contact.

As shown in FIG. 4A , which follows FIG. 2D , in order to provide the subsequent electroplating of the first metal layer 222 , part of the second structural layer 206 (see FIG. 2D ) can be removed to form an electroplating seed layer 218 . It should be noted that the second structural layer 206 can also be completely removed here, and then, for example, by electroplating, a conductive layer is completely formed on the surface of the first conductive pattern 208 and the surface of the insulating pattern 212 as the electroplating seed layer 218 .

As shown in FIG. 4B, a mask pattern 402 is formed on the electroplating seed layer 218, which exposes the first conductive contacts 210, and electroplating forms a pattern on the surfaces of these first conductive contacts 210 through the electroplating seed layer 218 respectively. The first metal layer 222, wherein the first metal layer 222 is, for example, a solder layer or a Ni/Au layer. It is worth noting that, in this embodiment, while forming the first metal layer 222, the electrically connected internal circuits of the electroplating seed layer 218 and the multilayer interconnection structure 214 can also be formed on the surfaces of these bonding pads 216 respectively. The upper electroplating forms the second metal layer 224 , wherein the second metal layer 224 is, for example, a solder layer or a Ni-Au layer.

As shown in FIG. 4C , after the formation of the first metal layer 222 and the second metal layer 224 , the mask pattern 402 is removed to expose the electroplating seed layer 218 .

In order to allow the first conductive contact 210 in FIG. 2E to protrude downward, please refer to FIG. 5A and FIG. 5B , which are cross-sectional schematic views of a circuit carrier board according to a preferred embodiment of the present invention, wherein the conductive contact is made to protrude downward.

As shown in FIG. 5A, following FIG. 2D, a mask pattern 226 is formed on the side of the second structure layer 206 away from the multilayer interconnection structure 214, and the mask pattern 226 has a plurality of mask layers 228, wherein the The positions of the mask layer 228 respectively correspond to the positions of the first conductive contacts 210 .

As shown in FIG. 5B , for example, the portion of the second structure layer 206 not covered by the mask pattern 226 is removed by etching to form a second conductive pattern 230, which has a plurality of second conductive contacts 232, and these first conductive patterns 230 are formed. The two conductive contacts 232 are respectively connected to the corresponding first conductive contacts 210, so that the first conductive contacts 210 can structurally extend outward through the second conductive contacts 232, and the first conductive contacts 210 and the second The conductive contacts 232 can also respectively form similar ball-shaped conductive contacts, which are used as contacts for connecting the electronic carrier board of the next level. It is worth noting that, in order to form a surface protection layer at the bottom of these second conductive contacts 232, the previous mask layer 228 (ie, the remaining mask pattern 226) can be directly used as the surface protection layer, thus omitting the existing Multiple steps to create a surface protection layer.

In order to provide flexibility in circuit design, or to meet the needs of circuit design, as shown in Figure 2B, after forming the first conductive pattern 208, one or more embedded passive components (embedded passive component ) 240 , for example, is disposed in the space enclosed between the second structural layer 206 and the first conductive contact 210 in such a manner that its backside is adhered to the second structural layer 206 . Next, as shown in FIG. 2C, when an insulating pattern 212 is formed in the space enclosed between the second structural layer 206 and the first conductive pattern 208, the insulating pattern 212 will cover the buried passive component 240, but expose the buried passive component 240. The plurality of contacts of the passive component 240 are electrically connected to the internal circuit of the multilayer interconnection structure 214 in the step of FIG. 2D . Therefore, as shown in FIG. 3, the buried passive component 240 will exist within the chip package structure shown in the figure.

In summary, the manufacturing method of the circuit carrier of the present invention has the following advantages:

(1) The present invention uses a thinner and more rigid support substrate to replace the existing dielectric core layer, so it can effectively reduce the overall thickness of the circuit carrier board, and directly use the support substrate to make conductive contacts, so that it can be fabricated A circuit carrier without a dielectric core layer.

(2) The present invention uses a build-up process to form a multilayer interconnection structure on one surface of the support substrate, so a circuit carrier with higher density circuits and contacts can be obtained.

(3) Compared with the existing multilayer interconnection structure formed on both sides of the dielectric core layer, the present invention only forms a single multilayer interconnection structure on one surface of the supporting substrate, so the circuit winding can be effectively reduced. wire length, which improves electrical performance.

(4) Compared with the existing electroplating line (plating line) to form micro-pitch bumps, solder layers or metal surface protection layers (such as nickel-gold layers) on the bonding pads of the circuit carrier, the present invention can The conductive support substrate can be directly used as the electroplating seed layer, so the circuit density of the internal circuit of the circuit carrier can be increased.

(5) As shown in FIGS. 5A and 5B , the present invention can also directly use the mask layer 228 as the surface protection layer of the second conductive contact without additional steps for forming a surface protection layer.

(6) When the present invention extends the first conductive contact through the second conductive contact, the second conductive contact can be directly used to connect the circuit carrier to the circuit carrier of the next level, such as a printed circuit board, without the need to Conductive balls or conductive bumps are additionally fabricated on the surface of a conductive contact.

Although the present invention has been disclosed above with preferred embodiments, the description is not intended to limit the present invention, and any person skilled in the art can make various changes and modifications without departing from the concept and protection scope of the present invention. Therefore , the scope of protection of the present invention should be subject to the scope of protection required by the appended claims.

Claims (12)

1. A method for manufacturing a circuit carrier, comprising: providing a support substrate made of conductive material, the support substrate is divided into a first structural layer and a second structural layer overlapping with the first structural layer; patterning the first structural layer to form a first conductive pattern, the conductive pattern including a plurality of first conductive contacts; forming an insulating pattern in the space enclosed between the second structural layer and the first conductive pattern; A multilayer interconnection structure is formed on the insulating pattern and the first conductive pattern, the multilayer interconnection structure has an internal circuit connected to the first conductive contact, the internal circuit has a plurality of bonding pads, The bonding pads are located on a surface of the multilayer interconnect structure away from the first conductive pattern; and At least part of the second structural layer is removed. 2. The method for manufacturing a circuit carrier as claimed in claim 1, wherein the step of removing at least part of the second structural layer comprises completely removing the second structural layer. 3. The method for manufacturing a circuit carrier as claimed in claim 2, further comprising forming an electroplating seed layer on the insulating pattern and the first conductive pattern; then forming a mask on the second structural layer pattern; then respectively electroplating a first metal layer on each of the first conductive contacts via the electroplating seed layer; finally removing the mask pattern and exposing a part of the electroplating seed layer. 4. The method for manufacturing a circuit carrier as claimed in claim 3, wherein, when forming the first metal layer by electroplating, it further comprises electroplating on each of the bonding pads simultaneously through the electroplating seed layer and the internal circuit. a second metal layer. 5 . The method for manufacturing a circuit carrier as claimed in claim 1 , wherein the step of removing part of the second structure layer comprises thinning the second structure layer to form an electroplating seed layer. 6. The method for manufacturing a circuit carrier as claimed in claim 5, further comprising forming a mask pattern on the second structure layer, and then forming a pattern on each of the first conductive contacts via the electroplating seed layer A first metal layer is formed by electroplating respectively, and then the mask pattern is removed to expose a part of the electroplating seed layer. 7. The method for manufacturing a circuit carrier as claimed in claim 6, wherein, when forming the first metal layer by electroplating, simultaneously electroplating on each of the bonding pads via the electroplating seed layer and the internal circuit A second metal layer is formed. 8. The method for manufacturing a circuit carrier according to claim 1, wherein the step of removing at least part of the second structural layer includes patterning the second structural layer to form a second conductive pattern, the pattern There are a plurality of second conductive contacts, and these conductive contacts are respectively connected to the first conductive contacts. 9. The method for manufacturing a circuit carrier as claimed in claim 8, wherein the step of patterning the second structure layer comprises forming a mask pattern on the second structure layer, and using the mask pattern as Mask etching removes part of the second structure layer, and the mask pattern remaining on the second conductive contact forms a plurality of surface protection layers. 10 . The method for manufacturing a circuit carrier as claimed in claim 1 , further comprising electroplating and forming a second metal layer on each of the bonding pads through the second structural layer and the internal circuit. 11 . 11. The method for manufacturing a circuit carrier as claimed in claim 1, wherein, after forming the first conductive pattern, further comprising a space configuration enclosed between the second structural layer and the first conductive pattern at least one buried passive component; then when the insulating pattern is formed in the space enclosed between the second structure layer and the first conductive pattern, the insulating pattern covers the buried passive component but exposes multiple contacts of the buried passive component. 12. The method for manufacturing a circuit carrier as claimed in claim 1, wherein the first conductive contacts are arranged in an array.

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