200919009 /\υυ/υζυυδ ^5435twf.doc/p 九、發明說明： 【發明所屬之技術領域】 Μ ίί明是有關於—種外⑽結構、具有㈣外引¥ 件陣列基板與光電裝置及其製造方法， 二，—種具有三維空間的排列設計的外弓!腳結構4 造ί法外引腳結構的主動元件_基板與光電裝置及其製 【先前技術】 電腦示器;泛地應用在手機、電視、筆記型 电子產口口中，且為因應市場的需求，除 幕=的尺寸不斷增大外，螢幕的解析度也二： 用數量也必麟之增加。 H〜片的使 的配的晶片接合的技術上’晶片可藉由數種 璃美板上^0顯示器中’比如是以晶片黏合於玻 上Glass ’c〇G) ’或是以晶片黏合於軟板 上(Uup 〇n Film，c〇f) 〇 破黏合於玻璃基板上的配置方式來說， 玻喊板上配置有連接於“以及液 二又=也隨之提高。但為了進一步提高接點的配置密 ς ;=習知技術是將玻璃基板上的外弓丨腳之間距(pitch) 鈿小或疋縮小外引腳之接點的尺寸。 然而，當玻璃基板上的外引腳之間的間距小到一定程 200919009 Αυυ/υ/υυδ zji435twf.doc/p 度時，將因超出機台的能力極限而影響機台的對位精度， 進而降低製程的良率。另外，為了配合小尺寸接點的設計 必須將晶片上的凸塊尺寸縮小。當晶片上的凸塊的尺寸小 到一疋私度時，凸塊的剪力強度會降低，因此凸塊容易脫 落而使可靠度偏低’進而增加製作成本。 【發明内容】 本發明關於一種外引腳結構及其製造方法，可增加基 板上的外引腳密度且不需將基板上的接點之間的間距縮小 或是縮小接點的尺寸。 ' 本發明另關於—種主動元件陣列基板及造方 法，可主動元件陣列基板上的晶片的輪出訊號。 本查明還關於-種光電褒置及其製造方法 電裝置中顯示面板的螢幕解析度。 紅同尤200919009 /\υυ/υζυυδ ^5435twf.doc/p IX. Invention Description: [Technical field of invention] Μ ί ί 是 是 — 种 — — — 种 种 种 种 种 种 种 种 种 10 10 10 10 10 10 10 10 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列Method, two, - an outer bow with a three-dimensional arrangement of the outer design! foot structure 4 active elements of the external pin structure _ substrate and optoelectronic device and its system [prior art] computer display; pan-applied in mobile phones In the TV and notebook electronic products, in order to meet the needs of the market, in addition to the increasing size of the screen, the resolution of the screen is also two: the number of users will increase. The technology of the H~-chip is to be bonded to the wafer. The wafer can be bonded to the glass by a wafer on a plurality of varnishes, for example, by bonding a wafer to a glass 'glass 'G'. On the soft board (Uup 〇n Film, c〇f), the configuration of the smashing and bonding on the glass substrate is such that the glass board is connected to "and the liquid 2 is also increased. However, in order to further improve the connection The configuration of the point is ς; = the conventional technique is to reduce the pitch of the outer bow on the glass substrate to the size of the contact of the outer pin. However, when the outer pin on the glass substrate The spacing between the two is as small as 200919009 Αυυ / υ / υυ δ zji435twf.doc / p degrees, will affect the alignment accuracy of the machine due to exceeding the capacity limit of the machine, and thus reduce the yield of the process. In addition, in order to match the small The size of the contact design must reduce the size of the bump on the wafer. When the size of the bump on the wafer is small enough, the shear strength of the bump will be reduced, so the bump is easy to fall off and the reliability is low. 'In turn, the production cost is increased. [Invention] The present invention In an external pin structure and a manufacturing method thereof, the density of the outer pins on the substrate can be increased without reducing the pitch between the contacts on the substrate or reducing the size of the contacts. The device array substrate and the manufacturing method thereof can perform the wheel-out signal of the wafer on the active device array substrate. The present invention also relates to the screen resolution of the display panel in the electrical device of the photoelectric device and the manufacturing method thereof.
為具體描述本發明之内容，在 構，且外引腳結構是配置在 =射卜引腳L 個第-外引腳、多個第二=土：腳結構包括多 -外引腳是配置在基板上，且第-外引 平行的第-導線以及位於第— =括夕條實質上 第L是配置在基板上’且第二，。 導線以及位於第二導線末端的多個第=包括多條弟二 點與其中—第—導線部份重疊。圖宰化介=且各第二接 引腳以及第二外引腳之間，且化=層位於第-外 點。 茶化7丨电層暴露出第一接 為具體描述本發明之内容，在此提出—種先電裳置， 200919009 Αυυ/υζυυδ z^435twf.doc/p 而光電裝置包括至少一上述之外引腳結構。 為具體描述本發明之内容’在此提出—齡動元件陣 列基，，而主動元件陣列基板包括一基板、多個晝素單元、 多個第-外引腳、多個第二外引腳以及一圖案化介電層。 其中，基板具有一顯示區與位於顯示區外之一周邊線路 區’而晝素單兀則配置於顯示區内。第一外引腳配置於周 邊，路區内並與晝素單元電性相連，且第—外引腳包括多 、 條第一導線以及位於第一導線末端的多個第一接點。第二 外引腳配置於周邊線路區内並與晝素單元電性相連，且& 二外引聊包括多條第二導線以及位於第二導線末端的多個 第二接點，而各第二接點與其中一第一導線部份重疊。圖 案化介電層配置於第一外引腳以及第二外引腳之間，且圖 案化介電層暴露出第一接點。 在本發明之一實施例中，第一接點沿著一第一方向排 列，而第二接點沿著一第二方向排列，且第一方向與第二 方向實質上平行。 / 林發日狀-f施射，第二導線與第—導線部份重 疊。 外在本發明之一實施例中，各第二導線包括—第一段、 -第二段以及-第三段，第-段與第—導線重疊並連^第 接點，第二段連接於第一段與第三段之間，第三段與第 一導線彼此平行交錯排列。 〃 在本發明之一實施例中 同膜層製作。 ’第三段與第一外引腳是由相 200919009 ^5435twf.doc/p 在本發明之一實施例中，每一 接點間其中至少一者實質上呈：二;接點間及每-第二 為具體描述本發明之内容左 的製造方法，包括.於提出—種外引腳結構 U▲⑦括.於—基板上形成多 第一外引腳包括多條實質上平 而 仃扪弟—導線以及位於第一 V線末_多個弟—接點。在 = 層，且圖案化介電層覆蓋部卜„成—圖案化介電 且第二接點與第一導線部份重疊 :工案化"電層上形成多個第二外引腳，而第二外引 ί ΐΐ條線肢位於第二導線末端的多個第二接 為具體描述本發明之内容，在此提出一種主動元件陣 列基板的製造枝，而线元件陣板的製造方法包括 上述之外弓丨腳結構的製造方法。 為具體描述本發明之内容，在此提出一種光電裝置的 製造方法，而光電裝置的製造方法包括上述之外引腳結構 的製造方法。 本發明之外引腳結構可使第一外引腳以及第二外引 腳呈現三維空間的排列設計以改善習知技術中只在二維平 面上排列外引腳而使得外引腳的接點分布密度無法提升的 問題。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉實施例，並配合所附圖式，作詳細說明如 下。 、 【實施方式】 200919009 z5435twf.d〇c/p 圖1為本發明一實施例之一種外引腳結構的示意圖， 而圖2A為圖1中沿ι_ι’線段的剖面圖，圖2b為圖1中沿 Π-Π’線段的剖面圖。請同時參照圖1、圖2A與圖2B， 本發明之外引腳結構1〇〇配置在一基板200上。基板2〇〇 可為透明基板(如.玻璃基板、石英基板、或其它基板）、 可撓性基板(如：塑膠基板、薄化玻璃基板、聚酯類基板、 聚酮類基板、聚醚類基板、聚脂類基板、聚烯類基板、聚 快類基板、聚環氧稀類基板、聚環稀類基板、聚環燒類基 板、聚醯類基板、聚酚類基板、聚醛類基板、或其它聚^ 物類基板、或上述之組合）、不透明基板(如：矽片、陶瓷、 或其它基板）、印刷電路板、可撓式印刷電路板、同時呈有 印刷電刷板及可撓式印刷電路板、或是其他適合的電路板 或是基板。外引腳結構100包括多個第一外引腳11〇、多 個第二外引腳120以及一圖案化介電層13〇。第—外引二 110配置在基板200上，且第一外引腳110包括多條實質 上平行的第一導線112以及位於這些第一導線112束端的 多個第一接點114,其中第一導線112與第一接點114連 接。 第一外引腳也疋配置在基板200上。第二外引腳 120包括第二導線122以及位於第二導線122末端的 接點124，其中第二導線122與第二接點124連接，且亇 一個第一接點124皆與其中一條第—導線112部分重聶: 此外，於本實施例中，第二導線122與第一導線112 ^、 部份重疊。第一外引腳110與第二外引腳12〇其中至+、 200919009 ^435twf.doc/p 構鐵❹锡^構’其材質包含不透明材質(如： 辞等金眉、卜、十、人人 敛、敛、组、紹、 或上述之組合5透^^金屬祕f、上述金屬氮化物、 崎氧化物、紹鋅氧化二:’:m、銦辞氧化物、 錫鋅氧化物、氧化給、氧’ u鋅氧化物、銦 合）、或上述之組合。辞或其它材質、或上述之組 外引腳二==1130位於第一外^卿110與第二 實質上電性絕緣。i中^安外5^ 11〇與第二外引腳Ϊ20 多層結構，綱邮=(==1結構或 氧化石夕、氧化铪、氮化铪、氧化乳:：、乳化矽、氮 其它材質、或上述之組合）、有機:鋅或 化物、聚醇類、聚_、聚亞_、苯虱氧之石夕 聚酮類、聚醚類、聚烯類、光 :丁烯、錢類、 聚環，聚_類、聚_、聚= = =、 個開口 ！32以暴露出第木=電層⑽具有多 也可以是只覆蓋-部分的第 接點114及另—部份的第—導線112,而美露弟一 份的第一導線112並不會與徭蜱 々路出的另一部 接，亦即包含第-導線112、Ί ^電層結構產生電性連 導線122之第二外引腳12〇仍铁實丄10及包含第二 傳輸訊號傳輸於原來的外引腳上。、、—絕緣而能讓所 200919009 /\υυ/υζυυδ -iD435twf.doc/p 然而，本發明的外引腳結構100並不限於此，也就是 外引腳結構100可以是兩層以上的導體結構，例如：外引 腳結構100還具有第三外引腳（未繪示）、第四外引腳（未 繪示）並藉由第二圖案化介電層（未繪示）、第三圖案化 介電層（未繪示）以分隔並絕緣。 承上所述，本發明之外弓丨腳結構1〇〇具有第一外引腳 110以及第二外引腳120,並藉由圖案化介電層13〇分隔第 Γ; 一外引腳110與第二外引腳120，使第一外引腳110與第 —外引腳120實質上電性絕緣。因此，本發明可使外引腳 110、120進行三維空間的排列設計以改善習知只在二維平 面上排列外引腳110、120而使得外引腳u〇、丨2〇的密度 無法提升的問題。也因此，本發明可以在不縮小接點114、 U4之間的間距或是接點114、124的尺寸的情況下，有效 增加基板200上的外引腳11〇、12〇的數量。 ^換言之，由於本發明可有效提升外引腳110、120的 雄、度，因此在基板200的相同面積上本發明可較習知技術 配置更多的外引腳11〇、12〇。而在基板2〇〇上配置較多的 外引腳110、120可有助於增加外引腳11〇、12〇傳輸訊號 的總量。因此，當外引腳結構1〇〇應用在顯示裝置時，將 有助於提升螢幕的解析度。當然，本發明也可以是在基板 2〇〇上配置的外引腳11〇、12〇數目與習知技術的外引腳數 目相同’但是本發明的外引腳11〇、12〇較習知技術的外引 =所佔的基板200的面積小。因此，在相同的傳輸訊號總 1的情況下，本發明的外引腳11〇、12〇有助於縮小基板 11 200919009 -i435twf.doc/p 200的面積。或者是，本發明的外弓丨腳no、120可增加基 板200上其他元件（未繪示）配置的自由度。 然後，請繼續參照圖1、圖2A與圖2B，本實施例之 外引腳結構1〇〇的製造方法如下所述。在基板上形成 多個第一外引腳no，而第一外弓丨腳no包括實質上平行 的一第一導線112以及位於第〆導線112末端的一第一接 點114。然後，在基板200上形成〆圖案化介電層130，而 且圖案化介電層130覆蓋第一導線112並暴露出第一接點 114為範例，但不限於此。之後，在圖案化介電層130上 形成多個第二外引腳12〇，第二外引腳120包括一第二導 線122以及位於第二導線122末端的一第二接點124，而 且第二接點124與第一導線112部份重疊。 本實施例之外引腳結構1〇〇的製造方法可以應用在主 動元件陣列基板的製造方法中，或是應用在光電裝置的製 造方法中。當本實施例之外引腳結構100的製造方法應用 在主動凡件陣列基板的製造方法中時，第一外引腳110及 外引腳120可以與主動元件陣列基板中的導體線路同 /成，而圖案化介電層13〇則可以與主動元件陣列基板 中的介電層(如：絕緣膜層、㈣介電層、保護層、及平坦 層、j層、或其它膜層、或上述之組合)同時形成。換言 之貫施例之外引聊結構1GG㈣作方法可相容於主動 製程當中。再者，本實施例之外引腳結構刚的 =此'*係以沈積、曝光及糊方式來當做範例，但不 限於此，亦可以喷墨方式、網版印财式、沈積及雷射剝 12 200919009 / ^.5435twf.doc/p 除(laser ablation)方式、或其它方式、或上述之组合。 於本實施例中，第二導線122包括一第一段ma、一 第二段i22b以及-第三段122c。其中，第一段ma與部 份第-導線112㈣並直接連接第二接點124。第二段咖 連接於第-段122a與第三段122c之間。第三段似與第 一導線112彼此平行排列，且第三段12及與第二段12沘 部分重疊並藉由接觸窗134電性連接。第三段122c鱼第一 外引腳110可以是由相同膜層製作。於其他實施射，第 二段122c與第一外引腳11〇也可以是由不同膜層製作。換 句話說，外引腳結構具有由不同膜層所製作的第一外引腳 以及第二外引腳’但不以此為⑯，亦可由相同膜層來製作。 於本實施例中，第一接點114可以沿著一方向A排 列，而第二接點124可以沿著—第二方向B排列，且第一 方向A與第二方向B實質上平行。也就是說，第—接點 114與第二接點124的排列方式是同步變化的。以下將在 圖3〜圖6中介紹第一接點114與第二接點124的其他多 種排列方式。當然，以下說明僅為實施範例，本發明並不 以此為限。 另外’請參照圖3，本發明之外引腳結構3〇〇的每一 第一接點314間及每一第二接點324間實質上皆呈高低交 錯排列。此外，第一接點314與第二接點324的排列方式 是同步變化的。由習知技術可知，高低交錯排列的接點配 置方式有助於提高接點的分布密度，而本發明除了位於同 一層的第一接點314呈高低交錯排列之外，還有另一層導 13 200919009 η________ ^5435twf.doc/p 體層所組成的第二接點324也可呈高低交錯排列。因此， 本發明之外引腳結構300可具有更高的外引腳31〇、32〇 分布密度。 此外，如圖4所示’本發明之外引腳結構4〇〇可以是 至少二個第一接點412間及至少二個第二接點422間實質 上皆呈高低交錯排列。於本實施例中，是以每三個第一接 點412間及每三個第二接點422間實質上皆呈高低交錯排 列為範例，但不限於此，亦可四個、五個、六個、七個以 上等等，而且每一組之第一接點的數目，可選擇性地相同 於或不同於另一組之第二接點的數目。換言之，本實施例 中可以將數個排列於同一直線上的第一接點412視為一 組，而各組第一接點412互相高低交錯排列。同理，本實 施例中亦可將數個排列於同一直線上的第二接點422視為 一組’而各組第二接點422互相高低交錯排列。另外，成 組的這些第一接點412與第二接點422可以同步的或是不 同步的呈現高低交錯排列。 再者’如圖5所示’第一接點114排列的方向也可以 與第二接點124排列的方向不平行，也就是彼此不同步地 變化。第一接點114可以是沿著第一方向a排列，而第二 接點512間則是實質上呈高低交錯排列，而且此種排列方 式之弟一接點512的數目’可為一個、二個、三個、四個、 五個、六個以上等等，或者是如圖6所示，第二接點124 間可以是沿著第二方向B排列，而第一接點612則是實質 上呈高低交錯排列，而且此種排列方式之第一接點612的 14 200919009 AUU/U20U« 25435twf.d〇c/p 四個、五個、六個以上等 數目，可為一個、二個、三個、 等。 -步，本發明之外引腳結構3__主 動讀_基板的實施例。當然’町說冊為實施 本發明並不以此為限。 1圖工為::例之—種主動元件陣列基板的示 Ί 7，本發明之主動元件陣列基板包括To specifically describe the content of the present invention, the external pin structure is configured in the = 射 pin pin L first-outer pin, a plurality of second = soil: the foot structure includes a multi-outer pin is disposed in On the substrate, and the first-outer lead-parallel and the -th-thirteenth strip are substantially disposed on the substrate 'and second'. The wire and the plurality of the second portion at the end of the second wire include a plurality of two points and a portion of the first wire overlap. Figure 7 is between and between each of the second and second outer pins, and the layer is located at the first-outer point. The first layer of the tea-electric layer is exposed to specifically describe the content of the present invention, and is proposed here to be first placed, 200919009 Αυυ/υζυυδ z^435twf.doc/p and the photovoltaic device includes at least one of the above-mentioned external references. Foot structure. For the purpose of specifically describing the present invention, it is proposed herein that an active device array substrate includes a substrate, a plurality of pixel units, a plurality of first-outer pins, and a plurality of second outer leads, and A patterned dielectric layer. The substrate has a display area and a peripheral line area located outside the display area, and the pixel unit is disposed in the display area. The first outer pin is disposed on the periphery, and is electrically connected to the pixel unit, and the first outer pin includes a plurality of first wires and a plurality of first contacts at the ends of the first wires. The second outer pin is disposed in the peripheral circuit region and electrically connected to the halogen unit, and the second external chat includes a plurality of second wires and a plurality of second contacts at the end of the second wire, and each of the plurality of contacts The two contacts partially overlap with one of the first wires. The patterned dielectric layer is disposed between the first outer lead and the second outer lead, and the patterned dielectric layer exposes the first contact. In one embodiment of the invention, the first contacts are arranged along a first direction and the second contacts are aligned along a second direction, and the first direction is substantially parallel to the second direction. / Linfa-f-spray, the second wire and the first wire partially overlap. In an embodiment of the present invention, each of the second wires includes a first segment, a second segment, and a third segment, wherein the first segment overlaps with the first wire and connects to the first contact, and the second segment is connected to Between the first segment and the third segment, the third segment and the first wire are staggered in parallel with each other.同 In one embodiment of the invention, the same film layer is fabricated. 'The third segment and the first outer pin are from phase 200919009 ^5435twf.doc/p. In one embodiment of the invention, at least one of each of the contacts is substantially: two; between the contacts and each of - The second is a manufacturing method for specifically describing the content of the present invention, including: the proposed external pin structure U ▲ 7 includes a plurality of first outer leads formed on the substrate, including a plurality of substantially flat and younger brothers - Wires and at the end of the first V line - multiple brothers - contacts. In the = layer, and the patterned dielectric layer covering portion is formed into a dielectric layer and the second contact portion is partially overlapped with the first conductive line: a plurality of second outer leads are formed on the electrical layer. And a plurality of second connections of the second outer lead wire at the end of the second wire are specifically described in the present invention. Here, a manufacturing branch of the active device array substrate is proposed, and the manufacturing method of the wire component array includes The manufacturing method of the above-described outer structure of the bow and the foot. In order to specifically describe the contents of the present invention, a method of manufacturing an optoelectronic device is proposed, and a method of manufacturing the optoelectronic device includes the above-described method of manufacturing a pin structure. The pin structure allows the first outer pin and the second outer pin to be arranged in a three-dimensional space to improve the conventional method of arranging the outer pins only on the two-dimensional plane, so that the joint density of the outer pins cannot be increased. The above and other objects, features, and advantages of the present invention will become more apparent <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 09 z5435twf.d〇c/p FIG. 1 is a schematic diagram of an outer lead structure according to an embodiment of the present invention, and FIG. 2A is a cross-sectional view taken along line ι_ι′ in FIG. 1 , and FIG. 2 b is a cross-sectional view along FIG. A cross-sectional view of the line segment. Please refer to FIG. 1 , FIG. 2A and FIG. 2B simultaneously, and the pin structure 1 本 of the present invention is disposed on a substrate 200. The substrate 2 can be a transparent substrate (eg, a glass substrate, quartz). Substrate or other substrate), flexible substrate (eg, plastic substrate, thinned glass substrate, polyester substrate, polyketone substrate, polyether substrate, polyester substrate, polyolefin substrate, poly fast) a substrate, a polyepoxy substrate, a polycyclic substrate, a polycyclic substrate, a polyfluorene substrate, a polyphenol substrate, a polyaldehyde substrate, or another polymer substrate, or a combination thereof; An opaque substrate (eg, enamel, ceramic, or other substrate), a printed circuit board, a flexible printed circuit board, a printed printed circuit board and a flexible printed circuit board, or other suitable circuit board or The outer lead structure 100 includes a plurality of first outer leads 11 〇 and a plurality of second outer leads The foot 120 and a patterned dielectric layer 13 are disposed on the substrate 200, and the first outer lead 110 includes a plurality of substantially parallel first wires 112 and a bundle of the first wires 112 a plurality of first contacts 114 of the terminal, wherein the first wire 112 is connected to the first contact 114. The first outer pin is also disposed on the substrate 200. The second outer pin 120 includes a second wire 122 and is located at the second a contact 124 at the end of the wire 122, wherein the second wire 122 is connected to the second contact 124, and a first contact 124 is partially overlapped with one of the first wire 112: In addition, in this embodiment, The two wires 122 partially overlap with the first wire 112. The first outer pin 110 and the second outer pin 12 are 至 、 、 2009 2009 2009 2009 2009 2009 2009 2009 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其Material (such as: words such as: gold eyebrows, b, ten, everyone convergence, convergence, group, Shao, or a combination of the above 5 through ^ ^ metal secret f, the above metal nitride, samarium oxide, Shao zinc oxidation two: ' :m, indium oxide, tin zinc oxide, oxidation, oxygen 'u zinc oxide, indium), or the above combination. The word or other material, or the above-mentioned external pin 2 = =1130, is located at the first outer layer 110 and is substantially electrically insulated from the second. i in the outer 5 ^ 11 〇 and the second outer pin Ϊ 20 multi-layer structure, TU = (= = 1 structure or oxidized stone, yttrium oxide, tantalum nitride, oxidized milk::, emulsified 矽, nitrogen other materials Or a combination of the above), organic: zinc or a compound, a polyalcohol, a poly-, a poly-, a benzophenone, a polyether, a polyene, a light: butene, money, Poly ring, poly _ class, poly _, poly = = =, an opening! 32 to expose the second wood = electrical layer (10) has more or only cover the - part of the contact point 114 and the other part of the first wire 112, and the first wire 112 of the beautiful body does not The other connection of the circuit, that is, the second outer pin 12 including the first wire 112 and the electrical layer structure to generate the electrical connecting wire 122 is still iron 10 and includes the second transmission signal transmission On the original outer pin. Insulation can be made 200919009 /\υυ/υζυυδ -iD435twf.doc/p However, the outer lead structure 100 of the present invention is not limited thereto, that is, the outer lead structure 100 may be a conductor structure of two or more layers. For example, the outer lead structure 100 further has a third outer lead (not shown), a fourth outer lead (not shown), and a second patterned dielectric layer (not shown), a third pattern. A dielectric layer (not shown) is provided to separate and insulate. As described above, the outer leg structure 1 of the present invention has a first outer pin 110 and a second outer pin 120, and is separated by a patterned dielectric layer 13 Γ; an outer pin 110 And the second outer pin 120 electrically insulates the first outer pin 110 from the first outer pin 120. Therefore, the present invention allows the outer pins 110, 120 to be arranged in a three-dimensional space to improve the conventional arrangement of the outer pins 110, 120 only on a two-dimensional plane so that the density of the outer pins u〇, 丨2〇 cannot be improved. The problem. Therefore, the present invention can effectively increase the number of outer leads 11 〇, 12 基板 on the substrate 200 without reducing the pitch between the contacts 114, U4 or the size of the contacts 114, 124. In other words, since the present invention can effectively improve the maleness and degree of the outer leads 110, 120, the present invention can configure more outer leads 11 〇, 12 较 than the conventional technology on the same area of the substrate 200. The arrangement of a large number of external pins 110, 120 on the substrate 2〇〇 can help increase the total amount of transmission signals of the external pins 11〇, 12〇. Therefore, when the external pin structure 1〇〇 is applied to the display device, it will help to improve the resolution of the screen. Of course, the present invention may also be that the number of outer pins 11〇, 12〇 disposed on the substrate 2〇〇 is the same as the number of outer pins of the prior art, but the outer pins 11〇, 12〇 of the present invention are more conventionally known. The outer lead of the technology = the area of the substrate 200 occupied is small. Therefore, in the case of the same total transmission signal 1, the outer pins 11A, 12A of the present invention contribute to reducing the area of the substrate 11 200919009 - i435twf.doc / p 200. Alternatively, the outer bow feet no, 120 of the present invention may increase the freedom of configuration of other components (not shown) on the substrate 200. Then, referring to Fig. 1, Fig. 2A and Fig. 2B, the manufacturing method of the outer lead structure 1A of this embodiment is as follows. A plurality of first outer leads no are formed on the substrate, and the first outer bow foot no includes a first wire 112 substantially parallel and a first contact 114 at the end of the second wire 112. Then, a patterned dielectric layer 130 is formed on the substrate 200, and the patterned dielectric layer 130 covers the first conductive line 112 and exposes the first contact 114 as an example, but is not limited thereto. Thereafter, a plurality of second outer leads 12A are formed on the patterned dielectric layer 130, and the second outer leads 120 include a second wire 122 and a second contact 124 at the end of the second wire 122, and The two contacts 124 partially overlap the first wire 112. The manufacturing method of the lead structure 1A other than the present embodiment can be applied to the manufacturing method of the active element array substrate or to the manufacturing method of the photovoltaic device. When the manufacturing method of the lead structure 100 is applied to the manufacturing method of the active device array substrate, the first outer pin 110 and the outer pin 120 may be the same as the conductor lines in the active device array substrate. The patterned dielectric layer 13 can be connected to a dielectric layer in the active device array substrate (eg, an insulating film layer, a (four) dielectric layer, a protective layer, and a flat layer, a j layer, or another film layer, or The combination) is formed at the same time. In other words, the method of the chat structure 1GG(4) is compatible with the active process. Furthermore, the pin structure of the present embodiment is just as an example of deposition, exposure, and paste, but is not limited thereto, and may also be an inkjet method, a screen printing type, a deposition, and a laser. Stripping 12 200919009 / ^.5435twf.doc/p In addition to (laser ablation) mode, or other means, or a combination of the above. In this embodiment, the second wire 122 includes a first segment ma, a second segment i22b, and a third segment 122c. The first segment ma and the portion of the first wire 112 (four) are directly connected to the second contact 124. The second paragraph is connected between the first segment 122a and the third segment 122c. The third segment and the first wires 112 are arranged in parallel with each other, and the third segment 12 and the second segment 12 are partially overlapped and electrically connected by the contact window 134. The third segment 122c fish first outer pin 110 can be made of the same film layer. For other implementations, the second segment 122c and the first outer lead 11A may also be fabricated from different layers. In other words, the outer lead structure has the first outer lead and the second outer lead 'made by different layers, but not 16 as well, and can be made of the same film layer. In the present embodiment, the first contacts 114 may be arranged along a direction A, and the second contacts 124 may be arranged along the second direction B, and the first direction A and the second direction B are substantially parallel. That is to say, the arrangement of the first contact 114 and the second contact 124 is synchronously changed. Other various arrangements of the first contact 114 and the second contact 124 will be described below with reference to Figs. Of course, the following description is only an example of implementation, and the invention is not limited thereto. In addition, please refer to FIG. 3, and each of the first contacts 314 and each of the second contacts 324 of the pin structure 3〇〇 of the present invention are substantially arranged with high and low interlaces. In addition, the arrangement of the first contact 314 and the second contact 324 is synchronously changed. It can be known from the prior art that the high and low staggered contact arrangement helps to increase the distribution density of the contacts, and the present invention has another layer 13 in addition to the first and second contacts 314 located in the same layer. 200919009 η________ ^5435twf.doc/p The second contacts 324 formed by the bulk layers can also be staggered in height. Therefore, the outer lead structure 300 of the present invention can have a higher outer pin 31 〇, 32 〇 distribution density. In addition, as shown in FIG. 4, the pin structure 4' of the present invention may be substantially staggered in height between at least two first contacts 412 and at least two second contacts 422. In this embodiment, each of the three first contacts 412 and each of the three second contacts 422 are substantially staggered in height, but are not limited thereto, and may be four or five. Six, seven or more, etc., and the number of first contacts of each group may be selectively the same as or different from the number of second contacts of the other group. In other words, in the embodiment, a plurality of first contacts 412 arranged on the same line may be regarded as a group, and each group of first contacts 412 may be staggered with each other. Similarly, in this embodiment, a plurality of second contacts 422 arranged on the same line may be regarded as a group ' and each group of second contacts 422 may be staggered with each other. In addition, the first contact 412 and the second contact 422 of the group may be arranged in a high or low staggered manner in synchronization or non-synchronization. Further, the direction in which the first contacts 114 are arranged as shown in Fig. 5 may be non-parallel to the direction in which the second contacts 124 are arranged, i.e., change asynchronously with each other. The first contacts 114 may be arranged along the first direction a, and the second contacts 512 are substantially high and low staggered, and the number of the contacts 512 of the arrangement may be one or two. One, three, four, five, six or more, etc., or as shown in FIG. 6, the second contacts 124 may be arranged along the second direction B, and the first contact 612 is substantially The upper and lower levels are staggered, and the first joint 612 of the arrangement is 14 200919009 AUU/U20U « 25435twf.d〇c/p four, five, six or more, which can be one, two, Three, etc. - Step, an embodiment of the external pin structure 3__active read_substrate of the present invention. Of course, the invention is not limited to the implementation of the present invention. 1 The drawing is: an example of an active device array substrate. The active device array substrate of the present invention includes
-基板7H)、多個晝素單元72〇、多個第—外引腳31〇、多 個弟二外引腳320以及圖案化介電層13〇。基板71〇呈有 -顯示區7^與位於該顯示區712外之一周邊線路區 714 ’而晝素單兀72(M立於顯示區712 μ。第一外引腳31〇 配置於周邊線路區714内，且第—外引腳31()與晝素單元 720電性相連。第二外引腳32〇配置於周邊線路區714内， 而且第二外引腳320與晝素單元72〇電性相連。另外，圖 案化介電層130配置於第—外引腳31()以及第二外引腳 320之間，且圖案化介電層13〇暴露出第—接點3丨4。圖案 化介電層130暴露出第—接點314的方式可以是圖案化介 電層130具有位置對應於第一接點314的多個開口 132或 疋圖案化介電層130覆蓋部分的第一導線312而暴露出第 一接點314及另一部份的第一導線312。然而本發明之實 施例，以其中一個周邊線路區714内具有第一外引腳31〇 及第二外引腳320之交錯排列為範例，但不限於此，第一 外引腳310及第二外引腳32〇之排列方式，亦可選擇自上 述實施例之其中至少一種排列方式。而且，第一外引腳31〇 15 200919009 Λυυ/^υυο ^5435twf.d〇c/p 及第一外引腳320設置於幾個周邊線路區714内，可視其 设汁上需求及周邊線路區714之數目（如：i個、2個、3 個、4個以上料）而定。再者，本發縣外⑽結構· 設置於主動元件陣列基板700上以做為範例，但不限於 此。舉例來說，本發明亦可選擇將上述實施例之外引腳結 ，所述之其中至少一個排列方式設置於驅動電路(如：、 曰曰片）與外部元件連接之區域上、可撓性印刷電路板與外部 元件連接之區域上、印刷電路板與外部元件連接^區域 上或其匕與外部元件連接之區域上、或上述區域之任意 組合。其中，外部元件可以是導線、接觸墊、具有傳遞訊 號功能之電路、或其它元件、或上述之任意組合。 圖8為本發明一實施例之一種光電裝置的示意圖。請 參照圖8，於本實施例中，本發明之外引腳結構可以應用 在光電裝置800中，而光電裝置800包括一顯示面板81〇、 至少一電子元件820。顯示面板81〇及電子元件82〇至少 其中之一中配置有用於傳遞訊號之外引腳結構，其中外引 =結構可以是上述實施例所述之任何一種或是多種外引腳 、、、。構。當頭示面板810為液晶顯示面板時，顯示面板81〇 可以是穿透型顯示面板、半穿透型顯示面板、反射型顯示 面板、彩色濾光片於主動層上（c〇l〇r册er〇narray)之顯 示面板、主動層於彩色濾光片上（array 〇n c〇l〇r niter )之 顯不面板、垂直配向型（VA)顯示面板、水平切換型（ips) ’、、、頁示面板、多域垂直配向型（mva)顯示面板、扭曲向列 型（TN)顯示面板、超扭曲向列型（STN)顯示面板、圖 16 200919009 Λυυ / ^：5435twf.doc/p 木垂直配向型（PVA)顯不面板、超級圖案垂直配向型 (S-PVA)顯示面板、先進大視角型（ASV)顯示面板、 邊緣電場切換型（FFS)顯示面板、連續焰火狀排列型 (CPA)顯示面板、轴對稱排列微胞型（ASM)顯示面板、 光學補彳i’考曲排列型（OCB)顯示面板、超級水平切換型 (S_IPS)顯示面板、先進超級水平切換型（AS-IPS)顯示 面板、極端邊緣電場切換型（UFFS)顯示面板、高分子穩 定配向型顯示面板、雙視角型（dual_view)顯示面板、三 視角型（triple-view )顯示面板、三維顯示面板 (three-dimensional)或其它型面板，或上述之組合。另外， 顯示面板也可以是有機電激發光顯示面板（如：螢光有機 電激發光顯示面板、磷光有機電激發光顯示面板、或上述 之組合），且磷光及螢光之分子可為小分子、大分子、或a substrate 7H), a plurality of pixel units 72A, a plurality of first outer pins 31A, a plurality of second outer leads 320, and a patterned dielectric layer 13A. The substrate 71 is provided with a display area 7^ and a peripheral line area 714' located outside the display area 712, and the pixel unit 72 is located at the display area 712 μ. The first outer lead 31 is disposed on the peripheral line. In the region 714, the first outer pin 31 () is electrically connected to the pixel unit 720. The second outer pin 32 is disposed in the peripheral line region 714, and the second outer pin 320 and the pixel unit 72 are disposed. In addition, the patterned dielectric layer 130 is disposed between the first outer lead 31 () and the second outer lead 320, and the patterned dielectric layer 13 〇 exposes the first contact 3 丨 4. The manner in which the patterned dielectric layer 130 exposes the first contact 314 may be that the patterned dielectric layer 130 has a first opening 132 corresponding to the first contact 314 or a first portion of the patterned portion of the patterned dielectric layer 130. The wire 312 exposes the first contact 314 and the other portion of the first wire 312. However, in one embodiment of the invention, one of the peripheral line regions 714 has a first outer pin 31 and a second outer pin. The staggered arrangement of 320 is an example, but is not limited thereto, and the arrangement of the first outer lead 310 and the second outer lead 32 , may also be selected from At least one of the arrangements of the embodiments, and the first outer leads 31〇15 200919009/Λυυ5^5435twf.d〇c/p and the first outer pins 320 are disposed in the plurality of peripheral line regions 714, Depending on the demand on the juice and the number of surrounding circuit areas 714 (eg, i, 2, 3, 4 or more materials), the outside (10) structure of the county is disposed on the active device array substrate 700. For example, the present invention may also select a pin junction other than the above embodiments, and at least one of the arrangements is disposed on a driving circuit (eg, a chip). The area to which the external component is connected, the area where the flexible printed circuit board is connected to the external component, the area where the printed circuit board is connected to the external component or the area to which the external component is connected, or any combination of the above. The external component may be a wire, a contact pad, a circuit having a function of transmitting signals, or other components, or any combination thereof. Figure 8 is a schematic view of an optoelectronic device according to an embodiment of the present invention. In this embodiment, the external pin structure of the present invention can be applied to the optoelectronic device 800, and the optoelectronic device 800 includes a display panel 81A, at least one electronic component 820. The display panel 81A and the electronic component 82 are at least one of The pin structure is configured to be used for transmitting signals, and the outer lead structure may be any one or more of the external pins, and the structure described in the above embodiments. When the head display panel 810 is a liquid crystal display panel, the display is displayed. The panel 81 can be a transmissive display panel, a transflective display panel, a reflective display panel, a color filter on the active layer (c〇l〇r book er〇narray) display panel, active layer in color Display panel on the filter (array 〇nc〇l〇r niter), vertical alignment type (VA) display panel, horizontal switching type (ips) ', ,, page display panel, multi-domain vertical alignment type (mva) Display panel, twisted nematic (TN) display panel, super twisted nematic (STN) display panel, Fig. 16 200919009 Λυυ / ^:5435twf.doc/p wood vertical alignment type (PVA) display panel, super pattern vertical Orientation type (S-PVA) Display panel, advanced large viewing angle (ASV) display panel, edge electric field switching type (FFS) display panel, continuous flame-like arrangement (CPA) display panel, axisymmetric array microcell type (ASM) display panel, optical complement 'Current Arrangement (OCB) display panel, Super Horizontal Switching (S_IPS) display panel, Advanced Super Horizontal Switching (AS-IPS) display panel, Extreme Edge Electric Field Switching (UFFS) display panel, polymer stable alignment type A display panel, a dual view display panel, a triple-view display panel, a three-dimensional display or other type of panel, or a combination thereof. In addition, the display panel may also be an organic electroluminescence display panel (eg, a fluorescent organic electroluminescence display panel, a phosphorescent organic electroluminescence display panel, or a combination thereof), and the phosphorescent and fluorescent molecules may be small molecules. , macromolecule, or
上述之組合。再者’顯示面板也可以是無機電激發光顯示 面板’或者顯示面板也可以是混合式顯示面板 dispiay panel)，例如：液晶顯示面板同時具有液晶成份及 包激發光成77或是電激發光顯示面板同時具有有機電激 發光成分及無機電激發光成分。 -此外電子元件820可以是控制元件、操作元件、處 件輸入兀件、e憶元件、驅動元件、發光元件、保 護元件L件、偵測元件、或其它功能⑽、或前述 ;組合。光電裝置_的類型包括可攜式產品（如手機、 攝衫機、相機、筆記型電腦、遊戲機、手錶、音樂播放 為、電子信件收發器、地圖導織、數位相片、或類似之 17 200919009 ^5435twf.doc/p f品）1影音產品（如影音放映器或類似之產品）、螢幕、 電視、戶内/戶外看板或投影機内之面板。 查幕 第二二十:述二發明之外引腳結構具有第-外引腳以及 外引腳，使第案化介電層分隔第—外引腳與第二 外5丨腳使弟一外引腳盘第_外 此，本發明可對外^㈣二：，貝上電性絕緣。因 知口在-維承而r腳進准工間的排列設計以改善習 列外引腳而使得外引腳的密度無法提 尺寸下，有效增力二 ;:】外::f應用在顯示展置時，可提升螢幕的解析 “ΐ引:3元件_基板的製程中亦可一併製得本 方法簡易’但不限於此。舉例來說 亦可不與主動7〇件陣列基板的製程—起制栌 样作闕^上，2二義以限定 尽炙明，任何所屬領域中具有通常 心 明之精神和範圍内，當可作些許之f3 ’在不脫離本發 明之保護範圍當視後附之申請專利此本發 【圖式簡單說明】 _所界定者為準。 板上發明一實施例之一種外弓1卿結構配置於一基 圖2A為圖1中沿1-1，線段的剖面圖。 圖2B為圖丄中沿，線段的剖面圖。 圖3為本發明一實施例之另一種外引腳結構配置於一 18 200919009 Αυυ/υζυυδ z5435twf.doc/p 基板上的示意圖。 圖4為本發明一實施例之又一種外引腳結構配置於一 基板上的示意圖。 圖5為本發明一實施例之再一種外引腳結構配置於一 基板上的示意圖。 圖6為本發明一實施例之另一種外引腳結構配置於一 基板上的示意圖。 圖7為本發明一實施例之一種主動元件陣列基板的示 意圖。 圖8為本發明一實施例之一種光電裝置的示意圖。 【主要元件符號說明】 100、300、400 :外引腳結構 110、310 :第一外引腳 112、312 :第一導線 114、314、412、612 :第一接點 120、320 :第二外引腳 122、322 :第二導線 122a :第一段 122b :第二段 122c :第三段 124、324、422、512 :第二接點 130 :圖案化介電層 132 :開口 134 :接觸窗 19 200919009 / υζ,υυο ^5435twf.doc/p 200、710 :基板 700 :主動元件陣列基板 712 :顯示區 714 :周邊線路區 720 :晝素單元 800 :光電裝置 810 :顯示面板 820 :電子元件 A :第一方向 B:第二方向 20Combination of the above. Furthermore, the 'display panel may also be an inorganic electroluminescent display panel' or the display panel may be a hybrid display panel. For example, the liquid crystal display panel has both a liquid crystal component and a package excitation light 77 or an electroluminescence display. The panel has both an organic electroluminescence component and an inorganic electroluminescence component. Further, the electronic component 820 may be a control component, an operational component, a device input component, an e-revenue component, a driving component, a light-emitting component, a protective component L component, a detecting component, or other function (10), or a combination thereof. Types of optoelectronic devices include portable products (such as cell phones, camcorders, cameras, notebooks, game consoles, watches, music playback, e-mail transceivers, map guides, digital photos, or the like 17 200919009 ^5435twf.doc/pf products) 1 audio and video products (such as audio and video projectors or similar products), screens, televisions, indoor/outdoor billboards or panels in projectors. Inspect the second twenty: the second pin structure of the invention has a first-outer pin and an outer pin, so that the first dielectric layer separates the first-outer pin from the second-outer 5-pin. The pin disk is _ outside, the invention can be externally ^ (four) two:, the shell is electrically insulated. Because the knowing mouth is in the dimension and the r-foot is in the alignment of the work to improve the external pins of the train, so that the density of the outer pins can not be increased, effectively increase the force two;:] outside::f application in the display At the time of display, the analysis of the screen can be improved. “This method can be easily produced in the process of 3 components_substrate, but it is not limited to this. For example, it may not be related to the process of the active 7-piece array substrate.起 上 , 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 The patent application is based on a simple description of the drawing. The one of the outer bows of the first embodiment of the invention is arranged on a base. FIG. 2A is a section along line 1-1 of FIG. Figure 2B is a cross-sectional view of a line along the middle of the figure. Figure 3 is a schematic view of another outer lead structure disposed on a substrate of 18 200919009 Αυυ / υζυυ δ z5435twf.doc / p according to an embodiment of the present invention. According to another embodiment of the present invention, an external pin structure is disposed on a substrate. Fig. 5 is a schematic view showing another external pin structure disposed on a substrate according to an embodiment of the present invention. Fig. 6 is a schematic view showing another external pin structure disposed on a substrate according to an embodiment of the invention. A schematic diagram of an active device array substrate according to an embodiment of the present invention is shown in Figure 8. Figure 8 is a schematic diagram of an optoelectronic device according to an embodiment of the present invention. [Description of Main Components] 100, 300, 400: External Pin Structures 110, 310: First outer leads 112, 312: first wires 114, 314, 412, 612: first contacts 120, 320: second outer pins 122, 322: second wires 122a: first segment 122b: second segment 122c: third segment 124, 324, 422, 512: second contact 130: patterned dielectric layer 132: opening 134: contact window 19 200919009 / υζ, υυ ο ^ 5435 twf. doc / p 200, 710: substrate 700: Active device array substrate 712: display area 714: peripheral line area 720: pixel unit 800: photovoltaic device 810: display panel 820: electronic component A: first direction B: second direction 20