TW200917271A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device has a simple layout pattern of a sub hole region. The semiconductor memory device includes a segment input/output line, a first local input/output line and a second local input/output line corresponding to the segment input/output line, an input/output switch configured to selectively connect the segment input/output line and the first local input/output line in response to a first switch control signal, and a dummy input/output switch which is connected to a second local input/output line but is not connected to the segment input/output line.

Description

200917271 IX. Description of the Invention: [Technical Field] The subject matter of this standard relates to a semiconductor memory device, and more particularly to a transistor layout in a sub-hole regi〇n of a semiconductor memory device . The present invention claims priority to Korean Patent Application Nos. 1〇-2〇〇7-0089644 and 10_2008_0083862, filed on Sep. 4, 2007, and August 27, 2008, respectively. The entire text is incorporated herein by reference. [Prior Art] A semiconductor memory device such as a dynamic random access memory (DRAM) includes an interface region, a core region, and a hierarchical data bus for transferring data between the interface region and the core region. structure. The segment input/output lines and local input/output lines are placed in the core area, and the global input/output lines are placed from the interface area to the core area. The configuration of the data path and cell array varies depending on the size and performance of the semiconductor memory device. In a conventional cell array structure, data stored in a plurality of cells share a single-segment input/output line via respective bit line sense amplifiers (BLSAs). For a bit line sense amplifier array commonly used in a common bit line sense amplifier structure between an upper cell array and a lower cell array, there is a means for selectively connecting a bit line sense amplifier and an upper/lower portion位 line bit line connector. Therefore, the data in the two upper cell array blocks and the lower cell array block of the shared bit line sense amplifier can also be shared by the 134022.doc 200917271 shared segment input/output line. The segment input/output line is connected to the local input/output line via an input/output switch. This is to prevent the segment input/output lines from being affected by the extremely high capacitance of the local input/output lines. Therefore, all of the sector input/output lines are connected to the local input/output lines via the input/output switches. The input/output switch is placed in the sub-hole area of the semiconductor memory device. The sub-hole region refers to a bit line sense amplifier array horizontally disposed between the upper/lower cell arrays and a sub word line driver array vertically disposed between the left/right cell G arrays. Another area. The bit line sense amplifier driving circuit, the bit line control circuit and the sub word line control circuit, and the above input/output switch are disposed in the sub-hole region. FIG. 1A, FIG. 1B and FIG. 1C show a typical memory of the semiconductor memory device. Library architecture. Figures 1A, 1B and 1C are portions of a single view. That is, the top of Fig. 1B is coupled to the bottom of Fig. 1A and the bottom of Fig. 1B is coupled to the top of Fig. 1C to form a single view. I) Referring to Figures 1A, 1B and 1C, a plurality of cell arrays (MAT) and sub-word driver arrays are arranged in a matrix. Here, the bit line sense amplifier array is not shown for convenience. The section input/output line 810 <〇>/81〇8<〇> and SIO<2>/SIOB<2>& section input/output line SIO<l>/SI〇B<l> and SIO<;3>/SIOB<3> are arranged in the column direction above and below the cell array MAT, respectively. Local input/output lines LIOU<0>/LI〇BU<〇>, LI0U<1>/LI0BU<1>, LIOD<0>/LIOBD<0> and L1〇D<l>/LI〇BD<l> and local input/transmission 134022.doc 200917271 outgoing LIOU<2>/LIOBU<2>, LIOU<3>/LIOBU<3>, LIOD<2>/LIOBD<2>, and LIOD<3>/LIOBD<;3> are arranged in the row direction between the cell arrays MAT, respectively. Even considering only the sector input/output lines SIO<0>/SIOB<0>, SIO<2>/SIOB<2>, SIO<l>/SIOB<l>, and SIO<3>/SIOB<3> Field input/output line LIOU<0>/LIOBU<0>,LIOU<l>/LI0BU<1>'LIOD<0>/LIOBD<0>ALIOD<1>/LIOBD<1>-^ match, connection section The shape of the input/output line of the input/output line and the local input/output line (placed in the sub-hole area) is different depending on the memory bank area. In more detail, the intermediate memory bank includes a first input/output switch 51A for connecting the segment input and output lines SIO and SIOB with the upper local input/output lines LIOU and LIOBU, and for connecting the segment input. / Output line SIO and SIOB and one of the lower local input/output lines LIOD and LIOBD, the second input/output switch 51B. The upper memory bank area includes only the first input/output switch 51A for connecting the section input/output lines SIO and C / SIOB and the upper local area input/output lines LIOU and LIOBU. The lower memory bank area includes only a second input/output switch 51B for connecting the section input/output lines SIO and SIOB with the lower local input/output lines LIOD and LIOBD. For reference only, the pre-charging unit LIO PRECHARGE is placed in the upper memory bank area at the upper end of the local input/output line. 2A, 2B, and 2C are circuit diagrams showing the area of the conventional sub-hole 134022.doc 200917271 of the respective memory bank area. Each sub-hole area includes a bit line separation signal (BISH and BISL) generation circuit 10, a sub word line drive signal (FX0, FX2, FX4, and FX6) generation circuit 11, and a bit line equalization signal (BLEQ). One of the generating circuit 12, the one-bit line sense amplifier driving circuit 13, and the input/output switching circuits 14A, 14B, and 14C. Here, the bit line separation signal (BISH and BISL) generation circuit 10, the sub word line drive signals (FX0, FX2, FX4, and FX6) generation circuit 11, the bit line equalization signal (BLEQ) generation circuit 12 and the bit are provided. The circuit of the sense amplifier driving circuit 13 has the same memory bank area regardless of the memory bank area in which the circuits are located. Referring to FIG. 2A, the input/output switching circuit 14A disposed in the sub-hole region in the upper memory bank region includes transistors for equalizing and precharging the segment input/output lines SIO and SIOB (each in its gate) The NMOS transistor for receiving the bit line equalization signal BLEQ at the pole, and for responding to the upper switch control signal IOSWU connecting the segment input/output lines SIO and SIOB with the upper local input/output lines LIOU and LIOBU A first input/output switch 5 5 1A. This is because the connection between the lower local input/output lines LIOD and LIOBD and the segment input/output lines SIO and SIOB is not required in the upper memory bank area. The first input/output switch 5 1A includes two NMOS transistors having gates for receiving the upper switch control signals I 〇 swu and connected to the segment input/output lines SI0 and SIOB and the upper local input. Source/drain of the output lines LIOU and LIOBU. Referring to FIG. 2B, the input/output switching circuit 14B disposed in the sub-hole region in the intermediate memory bank includes equalization and pre-charging of the sector input/output lines SIO and 134022.doc -10- 200917271 SIOB. The transistor, the first input/output switch 5A and a first input/output switch 5 1Β. This is because in the intermediate memory bank area, it is required from the segment input/output lines SIO and SI〇B to the upper local input/output lines LIOU and LIOBU and the lower local input/output lines [1〇〇 and u〇BD connection. The second input/output switch 5丨B includes two NM〇s transistors having a gate for receiving the lower switch control signal I〇SWDi and connected to the segment input/output lines S1〇 and si〇B And the source/nothing of the lower local input/output lines U0D and LIOBD.

参看 Referring to FIG. 2C, the input/output switch circuit 14C disposed in the sub-hole region in the lower memory bank region includes a transistor for equalizing and precharging the segment input/output lines SI〇 and SIOB, and The second input/output switch 51B in response to the lower switch control k number 108\¥0 connection section input/output line 81A and SI〇B and the lower local area input/output lines LIOD and LI0BD. This is because the connection between the upper local input/round lines LI0U and LIOBU and the segment input/output lines 81〇 and 81〇]3 is not required in the lower memory bank area. As described above, the circuits for the input/wheel-out switching circuits 14A, 14B, and 14C disposed in the sub-hole area are different depending on the memory bank hierarchy. 3A, 3B, and 3C are views showing a pattern layout of the sub-hole regions of Figs. 2A, 2B, and 2c, respectively. Here, a plurality of rectangles highlighted by bright colors indicate a transistor. As can be seen in Figures 3A, 3B and 3C, the layout of the sub-hole regions differs according to the upper memory bank area, the intermediate memory bank area, and the lower memory bank area. That is, the sub-hole area in the upper memory area includes only the first input/output switch 5]A and does not include the second input/output switch 5]β. Therefore, the area A for the second input/output switch 51B is occupied by the unused space or another pattern. In contrast, the sub-hole area in the lower memory bank area includes only the second input/output switch 51B and does not include the first input/output switch 51. Therefore, the area 3 for the first wheel input/output switch 51A is occupied by the unused space or the case. ,. As a result, the memory bank requires various layouts for the sub-hole regions including the wheel-in/output switch circuits 14A, 14B, and 14C. Low Under this condition, the diversity of layout patterns during manufacturing can reduce layout efficiency and increase operating time. In addition, the diversity of layout patterns can cause errors in the mask process (4). As a result, productivity and device reliability can be reduced. SUMMARY OF THE INVENTION Embodiments of the present invention are directed to a semiconductor memory device that provides a simple layout pattern having a sub-hole region. According to one aspect of the present invention, the present invention provides a rich conductor memory device, including a segment input/output line, a pair, and a first local input/wheel corresponding to one of the segment input/output lines. Out of line and -筮_

The first local wheel input/output line, the cylinder is separated in response to a first switch control signal, the s God, and the L is selectively connected to the section wheel input/output line and the younger brother a local input/ The input/output switch of the wheel outlet, and the dummy input/wheeling switch connected to a first local input/rim mountain & ^ 4 line but not connected to one of the sector input/round lines. 134022.doc -12- 200917271 «The present invention provides a semiconductor memory device having a plurality of sub-cavity regions, a sub-word line driver block and a bit line sense amplifier region in the plurality of sub-hole regions The blocks intersect each other, the semiconductor memory device including a first sub-bore region including a configuration configured to selectively connect a first segment input / 7 outgoing line with a first switch in response to a first switch control signal a first input/output of the domain input/output line: - and one &, in response to the "second switch control signal" selectively connecting the first sector input/output line with a second local input / Output line - :: In/Out switch; and - Second sub-hole area, which is configured to be. The first switch control signal should be selectively connected:, =, the input/output line - the third input to the second local input/output line but not to the second second input / A first dummy input/output switch of the output line. " In accordance with an exemplary embodiment of the present invention, all of the sub-hole-out switching circuits are in the form of a phase-in-the-middle-side threat or an input/transmission of the same, having the same crystal pattern 'regardless of the location of the thunders. In the memory bank area, why one of the memory bank areas is rounded/recognized, and the pattern of the intermediate memory bank area and the off circuit can also be applied to the upper memory area and the lower memory area. To this end, the lower part of the enamel is set by the social body # 忆 库 库 库 下 下 下 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 忆 忆 忆Preferably, the dummy input is applied without floating - in order to prevent the occurrence of a fault. There is a pre-charge power supply voltage. [Embodiment] Hereinafter, a semiconductor 134022.doc according to the present invention will be described in detail with reference to the accompanying drawings. 13-200917271 Memory device. Fig. 4A, Fig. 4B and Fig. 4C are circuit diagrams illustrating subhole regions of respective memory bank regions according to an embodiment of the present invention. The subhole regions each include a bit line separation signal (BISH and generation). Circuit 1 〇〇, a sub word line drive signal (FX0, FX2, FX4, and FX6) generating circuit ιοί, a bit line equalization signal (BLEQ) generating circuit 1〇2, a bit line sense amplifying driving circuit 103 And one of the input/output switch circuits ι〇4Α, 104B, and 104C. Here, the circuit 1 〇〇, sub word line drive signals (fx〇, fx2) are generated for the bit line separation signals (81811 and BISL). FX4 and FX6) generating circuit 1〇1, bit The circuit of the equal-line equalization signal (bleq) generating circuit 102 and the bit line sense amplifier driving circuit 1〇3 are the same regardless of the memory bank area in which the circuits are located. Referring to FIG. 4B, The input/output switch circuit 1 04B in the sub-hole area in the intermediate memory area includes a first input/output switch 5〇1A and a second input/output switch 5 〇1B connected to the same section input/output line, etc. The pre/charging unit 502 is the same as the conventional input/output switching circuit 14 B shown in Fig. 2B. Here, the 'segment input/output line equalization/pre-charging unit 5〇2 includes nm〇s The crystals MN10, MN11 and MN12. The NMOS transistor MN10 receives a bit line equalization signal BLEq at one pole, and its source and drain are connected to a segment input/output line SIO and a segment input/output. Line SI〇B. The NMOS transistor MN11 has a gate configured to receive the bit line equalization signal BLEQ, a source connected to the segment input/output line SI〇B, and a connection to a precharge voltage The bungee of VPCG. NMOS transistor MN12 134022.doc -14- 200917271 There is a gate configured to receive the bit line equalization signal BLEQ, a source connected to the segment input/output line S10, and a drain connected to a precharge voltage VPCG. The first input/output switch 501A includes NMOS transistors MN14 and MN13. NMOS transistor MN14 receives an upper switching control signal IOS WU at a gate, and its source and drain are connected to the segment input/output line SIO and an upper local area. Input/output line LIOU. The NMOS transistor MN13 receives the upper switch control signal IOSWU at a gate, and its source and 〇 are connected to the sector input/output line SI0B and an upper local input/output line LI0BU. The second input/output switch 501B includes NMOS transistors MN16 and MN1 5. The NMOS transistor MN1 6 receives the lower switch control signal IOS WD at a gate, and its source and drain are connected to the segment input/output line SIO and the lower local input/output line LIOD. The NMOS transistor MN15 receives the lower switch control signal IOSWD at a gate, and its source and drain are connected to the sector input/output line SIOB and the lower local input/output L line LI0BD. Referring to FIG. 4A, the input/output switch circuit 104A disposed in the sub-hole region of the upper memory bank includes the first input/output switch 501A as described above with respect to FIG. 4B, and a dummy second input/output switch. 501C is integrated with the pre-charge/pre-charge unit 502 along with the segment input/output lines as described above with respect to FIG. 4B. The first input-output switch 501A is configured to connect the segment input/output lines SI0 and SI0B with the upper locale input/output lines LI0U and LIOBU in response to the upper switch control signal IOSWU. Faux second input/output switch 134022.doc •15· 200917271 501C is not connected to the section input/output lines SIO and SIOB. Basically, the connection between the sector input/output lines SIO and SIOB and the lower local input/output lines LIOD and LIOBD is not required in the upper memory bank area. However, the addition of the dummy second input/output switch 501C not connected to the section input/output lines SIO and SIOB to the upper memory bank area makes it possible to apply a layout identical to the layout of the intermediate memory bank area to the upper memory. Body area. The dummy second input/output switch 501C includes NMOS transistors MN18 and MN MN17. The NMOS transistor MN18 has a gate configured to receive the lower switch control signal I0SWD, a source connected to the lower local input/output line LIOD, and a drain connected to a supply voltage VDDA. The NMOS transistor MN1 7 has a gate configured to receive the lower switch control signal I0SWD, a source connected to the lower local input/output line LIOBD, and a drain connected to a supply voltage VDDA. Referring to FIG. 4C, the input/output switch circuit 104C disposed in the sub-hole region in the lower memory bank region includes the second input/output switch 501B and a virtual

U sets the first input/output switch 501D, along with the sector input/output line equalization/pre-charging unit 502. The second input-output switch 501B is configured to respond to the lower switch control signal IOSWD to connect the segment input/output lines SI0 and SIOB with the lower local input/output lines LIOD and LIOBD. The dummy first input/output rout switch 501D is not connected to the section input/output lines SIO and SIOB. Basically, the connection between the sector input/output lines SIO and SIOB and the upper local input/output lines LIOU and LI0BU is not required in the lower memory bank area. However, it is not connected to the sector input/output lines SIO and SIOB. The id of the 134022.doc -16- 200917271 input/output switch 5〇lD to the lower part of the 愔鞅 愔鞅 广 a 己 己 己 己 己 己 己 己 己 使得It is possible to apply a layout similar to the layout of the intermediate memory area to the lower memory area. The dummy first-input/output switch 5 includes a NM〇s transistor cholester and a MN19 NMOS electric a-body read 2〇 having a gate configured to receive the upper switch control signal (10) and a connection to the upper local area The input/output line is deleted from the source, and - connected to a power supply voltage. NMOS transistor MN19 has a w able to pull 丨 & Lea

' ^ , , configured to receive the upper switch control signal IOSWU gate, - connected to the upper local input / output line (10) source, and a drain connected to a supply voltage VDDA. It does not matter whether the dummy first input/output switch 501〇 and the dummy second input/output switch 501C are floating, because the segment input/output lines SIO and SIOB corresponding to the same and the local input/output lines do not participate in the actual Data transfer. However, the switches are preferably terminated with a supply voltage of 〇〇8 to prevent malfunction of the transistor. 5A, 5B, and 5C are views for explaining the layout of the sub-hole regions of Figs. 4A, 4B, and 4C, respectively. Here, a plurality of rectangles highlighted by bright colors indicate a transistor. It can be seen from Fig. 5A, Fig. 5B and Fig. 5C that the pattern layout of the transistors is the same. That is, the dummy first wheel in/out switch 50 1 D and the dummy second input/output switch 5〇1C allow all of the sub-hole regions to have the same layout pattern except for one of the contact patterns, regardless of the location Why is the memory bank area in the memory bank area? In other words, the configuration of the transistors in the sub-hole area is the same, and the memory bank area in which the tube 祠 134022.doc -17- 200917271 area is located is not the memory area. Further, the power supply voltage VDDA is applied to the dummy first input/output switch 5〇1D and the dummy second input/output switch 501C which are not connected to the section input/output lines SI〇&SI〇B. Therefore, the contact patterns are slightly different from each other. According to the above exemplary embodiment, the design pattern of all the sub-hole regions is simplified. Therefore, the layout work time can be reduced, and the process error can be reduced due to the repetition of the same pattern. As a result, it is possible to improve productivity and device reliability. The present invention has been described in detail with reference to the specific embodiments thereof, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims. For example, in the above embodiments, the type and configuration of the logic (for example) is based on the fact that both the input signal and the output signal are high active signals. Therefore, if the active polarity of the signal is changed, the logic can be implemented differently. Although such implementations are large, such implementations can be readily devised by those skilled in the art from the foregoing description of the specific embodiments, and thus, a direct description is omitted herein. Further, in the above exemplary embodiment, the unused dummy input 'output switch is described as being terminated with the power supply voltage VDDA. However, the present invention is not limited to this example, and the unused dummy input/wheel-out switch may be terminated or floating with a power supply voltage different from the power supply voltage VDDA. /, [Simple Description of the Drawings] Figs. 1A, 18, and 1C are views showing a semiconductor memory memory library architecture. Eight 134022.doc -18- 200917271 Figure 2A, Figure 2A and Figure 2C are circuit diagrams showing the conventional sub-hole regions of the respective memory banks. 3A, 3B, and 3C are views showing a pattern layout of the sub-hole regions of Figs. 2A, 2B, and 2c, respectively. 4A, 4B, and 4C are circuit diagrams illustrating sub-hole regions of respective memory bank regions in accordance with an embodiment of the present invention. 5A, 5B, and 5C are views for explaining the layout of the sub-hole regions of Figs. 4A, 4B, and 4C, respectively.

Ο [Main component symbol description] 10-bit line separation signal generation circuit 11 Sub-word line drive signal generation circuit 12 Bit line equalization signal generation circuit 13 Bit line sense amplifier drive circuit 14A Input/output switch circuit 14B Input / Output switch circuit 14C input/output switch circuit 51A first input/output switch 51B second input/output switch 100 bit line separation signal generation circuit 101 sub word line drive signal generation circuit 102 bit line specialization signal generation circuit 103 bit Main line sense amplifier drive circuit 104A Input/output switch circuit 104B Input/output switch circuit 134022.doc -19- 200917271 104C Input/output switch circuit 501A First input/output switch 501B Second input/output switch 501C Virtual second Input/output switch 501D dummy first input/output switch 502 section input/output line equalization/precharge unit A area B area { } BISH bit line separation signal BISL bit line separation signal BLEQ bit line equalization signal FXO sub word line drive signal FX2 sub word line drive signal FX4 sub word line drive letter FX6 sub word line drive signal IOSWD lower switch control signal i) IOSWU upper switch control signal LIOBD lower local input/output line LIOBU upper local input/output line LIOD lower local input/output line LIO PRECHARGE precharge unit LIOU upper board Domain input/output line MAT cell array MN10 NMOS transistor 134022.doc -20- 200917271 MNll NMOS transistor MN12 NMOS transistor MN13 NMOS transistor MN14 NMOS transistor MN15 NMOS transistor MN16 NMOS transistor MN17 NMOS transistor MN18 NMOS Crystal 〇 MN19 NMOS transistor MN20 NMOS transistor SIO segment input/output line SIOB segment input/output line VDDA supply voltage 134022.doc -21 -

Claims (1)

200917271 X. Patent application scope: 1. A semiconductor memory device comprising: a segment input/output line; a 'local local wheel input/transmission corresponding to one of the segment wheel input/output lines and a first local input/output line; a first switch control first local input/output switch 'which is configured to respond to the signal selectively connecting the segment input/output line to the/output line And a dummy input/output switch connected to a second local input/output line but not connected to the sector input/output line. 2. The semiconductor memory device of claim 1, wherein the segment input/output line and the first local input/output line and the second local wheel input/output line each comprise a positive line and a The difference line of the negative line. 3. The semiconductor memory device of claim 2, wherein the input/output switch comprises: a first MOS transistor having the positive line respectively connected to the segment input/output line and the first local input a source and a wave of the positive line of the output line and a gate configured to receive the first switch control signal; and a second MOS transistor having a connection to the section input/ The negative line of the output line and a source and a drain of the negative line of the first local input/output line and a gate configured to receive the first switch control signal. 4. The semiconductor memory device of claim 3, wherein the dummy input/output 134022.doc 200917271 is closed to a second MOS transistor having a gate configured to receive a first production control signal a pole, and a source connected to the positive line of the second local input/rounding; and a fourth circuit, having a gate configured to receive the second switching control signal And a source connected to the negative line of the second local input/rounding ^. The i-conductor memory device of claim 4, wherein the third MOS transistor and the drain of the fourth MOS transistor are connected to a power supply voltage. </ RTI> A semiconductor memory device having a plurality of sub-hole regions in which a sub-word line driver block and a bit line-sampling amplifier block intersect each other, the semiconductor memory The device includes: ~ a first sub/same area, including a first configured to selectively connect a first segment input/output line and a first, local input/output line in response to the -th switch control signal An input/output switch, and a second input/output switch configured to selectively connect the first segment input/output line and a first local area input/output line in response to the second switch control signal; And + 'which includes - is configured to selectively connect a sa &amp; the first segment input/output line to the first in response to the first switch control k. The first input/output switch of the domain wheel input/output line, and the first to the first input/output line of the second sector input/output line connected to the local input/wheel ^^ ΛΑ ^ times Wheel input/output switch. 7. The apparatus of claim 6, wherein the first sub-hole region includes a configuration in response to the second off control signal, further comprising a third 134022.doc 200917271 Selectively connecting - a third segment input/output line and: a fourth local input/output line of the second input/output switch, and a connection to the first local local input/output line but not connected to the The second dummy input/output switch of the third section input/output line. The semiconductor memory device of claim 7, wherein the first, the second and second segment input/output lines and the first and second local input/round outlets each comprise a A differential line with a positive line and a negative line. 9. The semiconductor memory device of claim 8, wherein the first input/output switch comprises: a first MOS transistor having the positive line connected to the first segment input/output line and the first a source and a drain of the positive line of a local input/output line, and a pole configured to receive the first switch to control the k wave; and a second MOS transistor having a connection to the The negative line of the first segment input/output line and a source and a drain of the negative line of the first local input/output line, and a gate configured to receive the first switch control signal pole. 10. The semiconductor memory device of claim 9, wherein the second input/output switch comprises: a third MOS transistor having the positive line connected to the first segment input/output line and the first a source and a drain of the positive line of the two local input/output lines, and a gate configured to receive the second switch control signal; and 134022.doc 200917271 a fourth MOS transistor having Connected to the negative line of the first segment wheel input/output line and a source and a drain of the negative line of the second local input/output line, respectively, and configured to receive the second switch Control the number of the Is number. 11. The semiconductor memory device of claim 8, wherein the third input/output switch comprises: a first MOS transistor having the positive line connected to the second segment input/output line and the first a source and a drain of the positive line of a local input/output line, and a gate configured to receive the first switch control signal; and a second MOS transistor 'having a connection to the second The negative line of the second segment input/output line and a source and a drain of the negative line of the first local input/output line, and a gate configured to receive the first switch control signal . 12. The semiconductor memory device of claim 1, wherein the first dummy input/output switch comprises: a second MOS transistor having a gate and a connection configured to receive the second switch control signal a source to the positive line of the second local input/output line; and a fourth MOS transistor having a gate configured to receive the second switch control signal and a connection to the second board The source of the negative line of the domain input/output line. 13. The semiconductor memory device of claim 12, wherein the sM〇s electromorph and the fourth MOS transistor are connected to a supply voltage. 134022.doc -4-200917271 wherein the fourth input/output 14. The semiconductor memory device of claim 8, the switch comprising - a - MOS transistor having a connection to the third segment input/output line, respectively a positive source and a source of the second local input/output line - source and - no pole, and - a gate configured to receive the second switch control signal; and - a second power cut a crystal having a negative line connected to the third section input/output line and the negative line of the second local wheel input/output line, respectively - source and - drain - and a gate configured to receive the second switch control signal. 15. The semiconductor memory device of claim 1, wherein the second dummy input/output switch comprises: a third MOS transistor having a source connected to the positive line of the first local input/output line And a gate configured to receive the first switch control signal; and a fourth MOS transistor having a source connected to the negative line of the first local input/output line and configured Receiving a gate of the first switch control signal. 16. The semiconductor memory device of claim 15, wherein the sM〇s electro-crystal and the fourth MOS transistor are connected to a supply voltage. 17. The semiconductor memory device of claim 6, wherein one of the layout patterns of all of the transistors in the first sub-hole region is the same as the layout pattern of one of the transistors in the second sub-hole region. The semiconductor memory device of claim 7, wherein a layout pattern of all of the transistors in the first sub-hole region 134022.doc 200917271 and a layout pattern of all of the transistors in the second sub-hole region and the first One of all the transistors in the three sub-hole regions has the same layout pattern. 134022.doc -6-