TWI391943B - Semiconductor memory device - Google Patents

Description

Semiconductor memory device

The subject matter pertains to semiconductor memory devices and, more particularly, to transistor layout in a sub-hole region of a semiconductor memory device.

The present invention claims the priority of Korean Patent Application No. 10-2007-0089644 and No. 10-2008-0083862, filed on Sep. 4, 2007, and on August 27, 2008, respectively. The entire text is incorporated herein by reference.

A semiconductor memory device, such as a dynamic random access memory (DRAM), includes an interface region, a core region, and a hierarchical data bus structure for transferring data between the interface region and the core region. The segment input/output lines and local input/output lines are placed in the core area, and the global input/output lines are placed from the interface area to the core area.

The configuration of the data path and cell array varies depending on the size and performance of the semiconductor memory device.

In a conventional cell array structure, data stored in a plurality of cells share a single segment input/output line via respective bit line sense amplifiers (BLSAs). For a bit line sense amplifier array commonly used for a common bit line sense amplifier structure between an upper cell array and a lower cell array, there is a means for selectively connecting a bit line sense amplifier and an upper/lower part element Line bit line connector. Therefore, the data in the two upper cell array blocks and the lower cell array block of the shared bit line sense amplifier can also Shared section input/output line.

The segment input/output line is connected to the local input/output line via an input/output switch. This is to prevent the segment input/output lines from being affected by the extremely high capacitance of the local input/output lines. Therefore, all of the sector input/output lines are connected to the local input/output lines via the input/output switches.

The input/output switch is disposed in a sub-hole region in the semiconductor memory device. The sub-hole region refers to a bit line sense amplifier array horizontally disposed between the upper/lower cell arrays and a sub word line driver array vertically disposed between the left/right cell arrays. region. A bit line sense amplifier driving circuit, a bit line control circuit and a sub word line control circuit, and the above input/output switch are disposed in the sub-hole area.

1A, 1B, and 1C show a typical memory bank architecture of a semiconductor memory device. 1A, 1B, and 1C are portions of a single view. That is, the top of FIG. 1B is coupled to the bottom of FIG. 1A and the bottom of FIG. 1B is coupled to the top of FIG. 1C to form a single view.

Referring to Figures 1A, 1B and 1C, a plurality of cell arrays (MAT) and sub-word line driver arrays are arranged in a matrix. Here, the bit line sense amplifier array is not shown for convenience.

Section input/output lines SIO<0>/SIOB<0> and SIO<2>/SIOB<2> and section input/output lines SIO<1>/SIOB<1> and SIO<3>/SIOB<3 > Arranged in the column direction above and below the cell array MAT, respectively. Local input/output lines LIOU<0>/LIOBU<0>, LIOU<1>/LIOBU<1>, LIOD<0>/LIOBD<0> and LIOD<1>/LIOBD<1> and local input/ lose Outbound LIOU<2>/LIOBU<2>, LIOU<3>/LIOBU<3>, LIOD<2>/LIOBD<2>, and LIOD<3>/LIOBD<3> are respectively arranged between the cell arrays MAT Arrange up.

Even considering only the segment input/output lines SIO<0>/SIOB<0>, SIO<2>/SIOB<2>, SIO<1>/SIOB<1>, and SIO<3>/SIOB<3> Matching of the field input/output lines LIOU<0>/LIOBU<0>, LIOU<1>/LIOBU<1>, LIOD<0>/LIOBD<0>, and LIOD<1>/LIOBD<1> The shape of the input/output line of the input/output line and the local input/output line (placed in the sub-hole area) is different depending on the memory bank area.

In more detail, the intermediate memory bank includes a first input/output switch 51A for connecting the segment input/output lines SIO and SIOB with the upper local input/output lines LIOU and LIOBU, and for connecting the segments The input/output lines SIO and SIOB are combined with the lower local input/output lines LIOD and LIOBD, a second input/output switch 51B.

The upper memory bank area includes only the first input/output switch 51A for connecting the section input/output lines SIO and SIOB with the upper local area input/output lines LIOU and LIOBU.

The lower memory bank area includes only a second input/output switch 51B for connecting the section input/output lines SIO and SIOB with the lower local input/output lines LIOD and LIOBD.

For reference only, the pre-charging unit LIO PRECHARGE is placed in the upper memory bank area at the upper end of the local input/output line.

2A, 2B, and 2C show the conventional sub-holes of the respective memory pool areas. Circuit diagram of the area.

Each sub-hole area includes a bit line separation signal (BISH and BISL) generation circuit 10, a sub word line drive signal (FX0, FX2, FX4, and FX6) generation circuit 11, and a bit line equalization signal (BLEQ). One of the generating circuit 12, the one-bit line sense amplifier driving circuit 13, and the input/output switching circuits 14A, 14B, and 14C. Here, the bit line separation signal (BISH and BISL) generation circuit 10, the sub word line drive signals (FX0, FX2, FX4, and FX6) generation circuit 11, the bit line equalization signal (BLEQ) generation circuit 12 and the bit are provided. The circuits of the line sense amplifier driving circuit 13 are the same regardless of the memory bank area in which the circuits are located.

Referring to FIG. 2A, the input/output switching circuit 14A disposed in the sub-hole region in the upper memory bank region includes transistors for equalizing and precharging the segment input/output lines SIO and SIOB (each in its gate) The NMOS transistor for receiving the bit line equalization signal BLEQ at the pole, and for responding to the upper switch control signal IOSWU connecting the segment input/output lines SIO and SIOB with the upper local input/output lines LIOU and LIOBU A first input/output switch 51A. This is because the connection between the lower local input/output lines LIOD and LIOBD and the segment input/output lines SIO and SIOB is not required in the upper memory bank area. The first input/output switch 51A includes two NMOS transistors having a gate for receiving the upper switch control signal IOSWU and connected to the segment input/output lines SIO and SIOB and an upper local input/output line. The source/bungee of LIOU and LIOBU.

Referring to FIG. 2B, the input/output switch circuit 14B disposed in the sub-hole region in the intermediate memory bank includes equalization of the segment input/output line SIO and The SIOB is precharged with a transistor, a first input/output switch 51A and a second input/output switch 51B. This is because the connection from the segment input/output lines SIO and SIOB to the upper local input/output lines LIOU and LIOBU and the lower local input/output lines LIOD and LIOBD is required in the intermediate memory bank area. The second input/output switch 51B includes two NMOS transistors having gates for receiving the lower switch control signal IOSWD and connected to the segment input/output lines SIO and SIOB and the lower local input/output lines The source/dip of LIOD and LIOBD.

Referring to FIG. 2C, the input/output switching circuit 14C disposed in the sub-hole region in the lower memory bank region includes a transistor for equalizing and precharging the segment input/output lines SIO and SIOB, and for responding The lower switch control signal IOSWD connects the section input/output lines SIO and SIOB with the lower local input/output lines LIOD and the second input/output switch 51B of LIOBD. This is because the connection between the upper local input/output lines LIOU and LIOBU and the segment input/output lines SIO and SIOB is not required in the lower memory bank area.

As described above, the circuits for the input/output switch circuits 14A, 14B, and 14C disposed in the sub-hole area are different depending on the memory bank hierarchy.

3A, 3B, and 3C are views showing a pattern layout of the sub-hole regions of Figs. 2A, 2B, and 2C, respectively. Here, a plurality of rectangles highlighted by bright colors indicate a transistor.

As can be seen in FIGS. 3A, 3B, and 3C, the layout of the sub-hole regions is different according to the upper memory bank area, the intermediate memory area, and the lower memory area.

That is, the sub-hole area in the upper memory area includes only the first input/output switch 51A and does not include the second input/output switch 51B. Therefore, the area A for the second input/output switch 51B is occupied by the unused space or another pattern.

In contrast, the sub-hole area in the lower memory bank area includes only the second input/output switch 51B and does not include the first input/output switch 51A. Therefore, the area B for the first input/output switch 51A is occupied by an unused space or another pattern.

As a result, a single memory bank requires various layouts for the sub-hole regions including the input/output switch circuits 14A, 14B, and 14C.

In this case, the diversity of layout patterns during manufacturing can reduce layout efficiency and increase operation time. In addition, the diversity of layout patterns can cause operational errors in the masking process. As a result, productivity and device reliability can be reduced.

Embodiments of the present invention are directed to a semiconductor memory device that provides a simple layout pattern having a sub-hole region.

According to an aspect of the present invention, a semiconductor memory device includes a segment input/output line, a first local input/output line corresponding to one of the segment input/output lines, and a second local area. An input/output line configured to selectively connect the segment input/output line to an input/output switch of the first local input/output line in response to a first switch control signal, and to connect to a first The two local input/output lines are not connected to one of the sector input/output lines of the dummy input/output switches.

According to another aspect of the present invention, a semiconductor memory device having a plurality of sub-hole regions in which a sub-word line driver block and a bit line sense amplifier block cross each other are provided. The semiconductor memory device includes a first sub-hole region configured to selectively connect a first segment input/output line and a first local input/output in response to a first switch control signal a first input/output switch of the line, and configured to selectively connect the first segment input/output line with a second of a second local input/output line in response to a second switch control signal An input/output switch; and a second sub-hole region configured to selectively couple a second segment input/output line and the first local input/output line in response to the first switch control signal a third input/output switch, and a first dummy input/output switch connected to the second local input/output line but not connected to the second sector input/output line.

In accordance with an exemplary embodiment of the present invention, the input/output switching circuits of all sub-cavity regions have the same transistor pattern regardless of the memory bank region in which the circuits are located. That is, the pattern of one of the input/output switch circuits of an intermediate memory bank can also be applied to an upper memory bank area and a lower memory memory area. To this end, dummy input/output switches not connected to the segment input/output lines are placed in each of the sub-hole regions in the upper memory bank area and the lower memory bank area. Preferably, the dummy input/output switch is applied with a predetermined supply voltage without floating to prevent a fault from occurring.

Hereinafter, a semiconductor according to the present invention will be described in detail with reference to the accompanying drawings Memory device.

4A, 4B, and 4C are circuit diagrams illustrating sub-hole regions of respective memory bank regions in accordance with an embodiment of the present invention.

The sub-hole regions each include a bit line separation signal (BISH and BISL) generation circuit 100, a sub word line drive signal (FX0, FX2, FX4, and FX6) generation circuit 101, and a bit line equalization signal (BLEQ) generation. Circuit 102, one bit line sense amplifier drive circuit 103, and one of input/output switch circuits 104A, 104B, and 104C. Here, the bit line separation signal (BISH and BISL) generation circuit 100, the sub word line drive signal (FX0, FX2, FX4, and FX6) generation circuit 101, the bit line equalization signal (BLEQ) generation circuit 102 and the bit are provided. The circuits of the line sense amplifier driving circuit 103 are the same regardless of the memory bank area in which the circuits are located.

Referring to FIG. 4B, the input/output switch circuit 104B disposed in the sub-hole region in the intermediate memory bank includes a first input/output switch 501A and a second input/output switch 501B connected to the same segment input/output line. The pre/charging unit 502 is the same as the conventional input/output switching circuit 14B shown in FIG. 2B.

Here, the segment input/output line equalization/pre-charging unit 502 includes NMOS transistors MN10, MN11, and MN12. The NMOS transistor MN10 receives a one-bit equalization signal BLEQ at a gate, and its source and drain are connected to a segment input/output line SIO and a segment input/output line SIOB. The NMOS transistor MN11 has a gate configured to receive the bit line equalization signal BLEQ, a source connected to the segment input/output line SIOB, and a drain connected to a precharge voltage VPCG (in the figure) Not shown). NMOS The transistor MN12 has a gate configured to receive the bit line equalization signal BLEQ, a source connected to the segment input/output line SIO, and a drain connected to a precharge voltage VPCG (not shown) display).

The first input/output switch 501A includes NMOS transistors MN14 and MN13. The NMOS transistor MN14 receives an upper switch control signal IOSWU at a gate, and its source and drain are connected to the segment input/output line SIO and an upper local input/output line LIOU. The NMOS transistor MN13 receives the upper switch control signal IOSWU at a gate, and its source and drain are connected to the sector input/output line SIOB and an upper local input/output line LIOBU.

The second input/output switch 501B includes NMOS transistors MN16 and MN15. The NMOS transistor MN16 receives the lower switch control signal IOSWD at a gate, and its source and drain are connected to the segment input/output line SIO and the lower local input/output line LIOD. The NMOS transistor MN15 receives the lower switch control signal IOSWD at a gate, and its source and drain are connected to the segment input/output line SIOB and the lower local input/output line LIOBD.

Referring to FIG. 4A, the input/output switch circuit 104A disposed in the sub-hole region in the upper memory bank region includes the first input/output switch 501A as described above with respect to FIG. 4B, and a dummy second input/output switch 501C together with The sector input/output line equalization/pre-charging unit 502 as described above with respect to FIG. 4B. The first input/output switch 501A is configured to connect the segment input/output lines SIO and SIOB with the upper local input/output lines LIOU and LIOBU in response to the upper switch control signal IOSWU. Virtual second input/output switch 501C is not connected to the segment input/output lines SIO and SIOB.

Basically, the connection between the sector input/output lines SIO and SIOB and the lower local input/output lines LIOD and LIOBD is not required in the upper memory bank area. However, the addition of the dummy second input/output switch 501C not connected to the section input/output lines SIO and SIOB to the upper memory bank area makes it possible to apply a layout identical to the layout of the intermediate memory bank area to the upper memory. Body area.

The dummy second input/output switch 501C includes NMOS transistors MN18 and MN17. The NMOS transistor MN18 has a gate configured to receive the lower switch control signal IOSWD, a source connected to the lower local input/output line LIOD, and a drain connected to a supply voltage VDDA. The NMOS transistor MN17 has a gate configured to receive the lower switch control signal IOSWD, a source connected to the lower local input/output line LIOBD, and a drain connected to a supply voltage VDDA.

Referring to FIG. 4C, the input/output switch circuit 104C disposed in the sub-hole region in the lower memory bank region includes a second input/output switch 501B and a dummy first input/output switch 501D, together with a sector input/output line, etc. / pre-charging unit 502. The second input/output switch 501B is configured to connect the lower switch control signals IOSWD to the segment input/output lines SIO and SIOB and the lower local input/output lines LIOD and LIOBD. The dummy first input/output switch 501D is not connected to the section input/output lines SIO and SIOB.

Basically, the connection between the sector input/output lines SIO and SIOB and the upper local input/output lines LIOU and LIOBU is not required in the lower memory bank area. However, it is not connected to the sector input/output lines SIO and SIOB. The addition of an input/output switch 501D to the lower memory bank area makes it possible to apply a layout identical to the layout of the intermediate memory bank area to the lower memory bank area.

The dummy first input/output switch 501D includes NMOS transistors MN20 and MN19. The NMOS transistor MN20 has a gate configured to receive the upper switch control signal IOSWU, a source connected to the upper local input/output line LIOU, and a drain connected to a supply voltage VDDA. The NMOS transistor MN19 has a gate configured to receive the upper switch control signal IOSWU, a source connected to the upper local input/output line LIOBU, and a drain connected to a supply voltage VDDA.

It does not matter whether the dummy first input/output switch 501D and the dummy second input/output switch 501C are floating, because the sector input/output lines SIO and SIOB and the local input/output lines corresponding thereto do not participate in the actual Data transfer. However, the switches are preferably terminated with a supply voltage VDDA to prevent failure of the transistor.

5A, 5B, and 5C are views each illustrating a pattern layout of the sub-hole regions of Figs. 4A, 4B, and 4C. Here, a plurality of rectangles highlighted by bright colors indicate a transistor.

It can be seen from Fig. 5A, Fig. 5B and Fig. 5C that the pattern layout of the transistors is the same.

That is, the dummy first input/output switch 501D and the dummy second input/output switch 501C allow all of the sub-hole regions to have the same layout pattern except for one of the contact patterns, regardless of the memory bank in which it is located. Body area.

In other words, the configuration of the transistors in the sub-hole area is the same, without the tube hole. The memory bank area where the area is located is the memory area. Further, the power supply voltage VDDA is applied to the dummy first input/output switch 501D and the dummy second input/output switch 501C which are not connected to the section input/output lines SIO and SIOB. Therefore, the contact patterns are slightly different from each other.

According to the above exemplary embodiment, the design pattern of all the sub-hole regions is simplified. Thus, the layout work time can be reduced, and the process error can be reduced due to the repetition of the same pattern. As a result, it is possible to improve productivity and device reliability.

Although the present invention has been described in detail with reference to the embodiments of the present invention, it will be understood that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims.

For example, in the above embodiments, the type and configuration of the logic is based, for example, on the condition of the active signal that both the input signal and the output signal are high. Therefore, if the active polarity of the signal is changed, the logic can be implemented differently. Although such implementations are large, such implementations can be readily devised by those skilled in the art from the foregoing description of the specific embodiments, and thus, a direct description is omitted herein.

Further, in the above exemplary embodiments, the unused dummy input/output switches are described as being terminated with the power supply voltage VDDA. However, the invention is not limited thereto. For example, an unused dummy input/output switch can also be terminated or floating with a power supply voltage different from the power supply voltage VDDA.

10‧‧‧ bit line separation signal generation circuit

11‧‧‧Sub-word line drive signal generation circuit

12‧‧‧ bit line equalization signal generation circuit

13‧‧‧ bit line sense amplifier driver circuit

14A‧‧‧Input/Output Switch Circuit

14B‧‧‧Input/Output Switch Circuit

14C‧‧‧Input/Output Switch Circuit

51A‧‧‧First Input/Output Switch

51B‧‧‧Second input/output switch

100‧‧‧ bit line separation signal generation circuit

101‧‧‧Sub-word line drive signal generation circuit

102‧‧‧ bit line equalization signal generation circuit

103‧‧‧ bit line sense amplifier driver circuit

104A‧‧‧Input/Output Switch Circuit

104B‧‧‧Input/Output Switch Circuit

104C‧‧‧Input/Output Switch Circuit

501A‧‧‧First Input/Output Switch

501B‧‧‧Second input/output switch

501C‧‧‧Dummy second input/output switch

501D‧‧‧Dummy first input/output switch

502‧‧‧ Section input/output line equalization/pre-charging unit

A‧‧‧ area

B‧‧‧Area

BISH‧‧‧ bit line separation signal

BISL‧‧‧ bit line separation signal

BLEQ‧‧‧ bit line equalization signal

FX0‧‧‧Sub-word line drive signal

FX2‧‧‧ sub-word line drive signal

FX4‧‧‧ sub-word line drive signal

FX6‧‧‧ sub-word line drive signal

IOSWD‧‧‧lower switch control signal

IOSWU‧‧‧Upper switch control signal

LIOBD‧‧‧lower local input/output line

LIOBU‧‧‧ upper local input/output line

LIOD‧‧‧lower local input/output line

LIO‧‧‧PRECHARGE pre-charging unit

LIOU‧‧‧ upper local input/output line

MAT‧‧‧cell array

MN10‧‧‧NMOS transistor

MN11‧‧‧NMOS transistor

MN12‧‧‧NMOS transistor

MN13‧‧‧NMOS transistor

MN14‧‧‧NMOS transistor

MN15‧‧‧NMOS transistor

MN16‧‧‧NMOS transistor

MN17‧‧‧NMOS transistor

MN18‧‧‧NMOS transistor

MN19‧‧‧NMOS transistor

MN20‧‧‧NMOS transistor

SIO‧‧‧section input/output line

SIOB‧‧‧section input/output line

VDDA‧‧‧Power supply voltage

1A, 1B, and 1C are views showing a typical memory bank architecture of a semiconductor memory device.

2A, 2B, and 2C are circuit diagrams showing conventional sub-hole regions of respective memory banks.

3A, 3B, and 3C are views showing a pattern layout of the sub-hole regions of Figs. 2A, 2B, and 2C, respectively.

4A, 4B, and 4C are circuit diagrams illustrating sub-hole regions of respective memory bank regions in accordance with an embodiment of the present invention.

5A, 5B, and 5C are views each illustrating a pattern layout of the sub-hole regions of Figs. 4A, 4B, and 4C.

100‧‧‧ bit line separation signal generation circuit

101‧‧‧Sub-word line drive signal generation circuit

102‧‧‧ bit line equalization signal generation circuit

103‧‧‧ bit line sense amplifier driver circuit

104A‧‧‧Input/Output Switch Circuit

501A‧‧‧First Input/Output Switch

501C‧‧‧Dummy second input/output switch

502‧‧‧ Section input/output line equalization/pre-charging unit

BISH‧‧‧ bit line separation signal

BISL‧‧‧ bit line separation signal

BLEQ‧‧‧ bit line equalization signal

FX0‧‧‧Sub-word line drive signal

FX2‧‧‧ sub-word line drive signal

FX4‧‧‧ sub-word line drive signal

FX6‧‧‧ sub-word line drive signal

IOSWD‧‧‧lower switch control signal

IOSWU‧‧‧Upper switch control signal

LIOBD‧‧‧lower local input/output line

LIOBU‧‧‧ upper local input/output line

LIOD‧‧‧lower local input/output line

LIOU‧‧‧ upper local input/output line

MN10‧‧‧NMOS transistor

MN11‧‧‧NMOS transistor

MN12‧‧‧NMOS transistor

MN13‧‧‧NMOS transistor

MN14‧‧‧NMOS transistor

MN17‧‧‧NMOS transistor

MN18‧‧‧NMOS transistor

SIO‧‧‧section input/output line

SIOB‧‧‧section input/output line

VDDA‧‧‧Power supply voltage

Claims (18)

A semiconductor memory device comprising: a segment input/output line; each corresponding to one of the segment input/output lines, a first local input/output line and a second local input/output line; an input / an output switch configured to selectively connect the segment input/output line to the first local input/output line in response to a first switch control signal; and a dummy input/output switch coupled to A second local input/output line is not connected to the sector input/output line. The semiconductor memory device of claim 1, wherein the segment input/output line and the first local input/output line and the second local input/output line each comprise a positive line and a negative line. Differential line. The semiconductor memory device of claim 2, wherein the input/output switch comprises: a first MOS transistor having the positive line respectively connected to the segment input/output line and the first local input/output a source and a drain of the positive line of the line, and a gate configured to receive the first switch control signal; and a second MOS transistor having a connection to the input/output line of the section The negative line and a source and a drain of the negative line of the first local input/output line, and a gate configured to receive the first switch control signal. The semiconductor memory device of claim 3, wherein the dummy input/output The switch includes: a third MOS transistor having a gate configured to receive a second switch control signal, and a source connected to the positive line of the second local input/output line; and a A fourth MOS transistor having a gate configured to receive the second switch control signal and a source connected to the negative line of the second local input/output line. The semiconductor memory device of claim 4, wherein the third MOS transistor and the drain of the fourth MOS transistor are connected to a power supply voltage. A semiconductor memory device having a plurality of sub-hole regions in which a sub-word line driver block and a one-element sense amplifier block cross each other, the semiconductor memory device comprising: a first a sub-hole region including a first input/output switch configured to selectively connect a first segment input/output line and a first local input/output line in response to a first switch control signal, And a second input/output switch configured to selectively connect the first segment input/output line and a second local input/output line in response to a second switch control signal; and a second sub-hole a region including a third input/output switch configured to selectively connect a second segment input/output line to the first local input/output line in response to the first switch control signal, and a connection The first dummy input/output switch to the second local input/output line but not to the second sector input/output line. The semiconductor memory device of claim 6, further comprising a third a sub-hole region, the third sub-cavity region including a fourth input configured to selectively connect a third segment input/output line and the second local input/output line in response to the second switch control signal / output switch, and a second dummy input/output switch connected to the first local input/output line but not to the third sector input/output line. The semiconductor memory device of claim 7, wherein the first, the second and third segment input/output lines and the first and second local input/output lines each comprise a positive line and The difference line of a negative line. The semiconductor memory device of claim 8, wherein the first input/output switch comprises: a first MOS transistor having the positive line respectively connected to the first segment input/output line and the first inning a source and a drain of the positive line of the domain input/output line, and a gate configured to receive the first switch control signal; and a second MOS transistor having a first connection to the first The negative line of the segment input/output line and a source and a drain of the negative line of the first local input/output line, and a gate configured to receive the first switch control signal. The semiconductor memory device of claim 9, wherein the second input/output switch comprises: a third MOS transistor having the positive line and the second line respectively connected to the first segment input/output line a source and a drain of the positive line of the domain input/output line, and a gate configured to receive the second switch control signal; a fourth MOS transistor having a source and a drain connected to the negative line of the first section input/output line and the negative line of the second local input/output line, respectively A gate configured to receive the second switch control signal. The semiconductor memory device of claim 8, wherein the third input/output switch comprises: a first MOS transistor having the positive line connected to the second segment input/output line and the first inning a source and a drain of the positive line of the domain input/output line, and a gate configured to receive the first switch control signal; and a second MOS transistor having a second connection to the second The negative line of the segment input/output line and a source and a drain of the negative line of the first local input/output line, and a gate configured to receive the first switch control signal. The semiconductor memory device of claim 11, wherein the first dummy input/output switch comprises: a third MOS transistor having a gate configured to receive the second switch control signal and a connection to the first a source of the positive line of the two local input/output lines; and a fourth MOS transistor having a gate configured to receive the second switch control signal and a connection to the second local input/ The source of the negative line of the output line. The semiconductor memory device of claim 12, wherein the third MOS transistor and the drain of the fourth MOS transistor are connected to a power supply voltage. The semiconductor memory device of claim 8, wherein the fourth input/output switch comprises: a first MOS transistor having the positive line and the second board respectively connected to the third section input/output line a source and a drain of the positive line of the domain input/output line, and a gate configured to receive the second switch control signal; and a second MOS transistor having a third connection to the third The negative line of the segment input/output line and a source and a drain of the negative line of the second local input/output line, and a gate configured to receive the second switch control signal. The semiconductor memory device of claim 14, wherein the second dummy input/output switch comprises: a third MOS transistor having a source connected to the positive line of the first local input/output line and a gate configured to receive the first switch control signal; and a fourth MOS transistor having a source connected to the negative line of the first local input/output line and configured to receive The first switch controls the gate of the signal. The semiconductor memory device of claim 15, wherein the third MOS transistor and the drain of the fourth MOS transistor are connected to a power supply voltage. The semiconductor memory device of claim 6, wherein one of the layout patterns of all the transistors in the first sub-hole region is the same as the layout pattern of one of all the transistors in the second sub-hole region. The semiconductor memory device of claim 7, wherein the first sub-cavity region One of the layout patterns of all the transistors is the same as one of the layout patterns of all the transistors of the second sub-hole region and one of the layout patterns of all the transistors of the third sub-hole region.