200915579 九、發明說明： L發明所屬之技術領域3 技術領域 本發明係有關於一種薄膜電晶體。更詳言之，係有關 5 於一種包含有由積層結晶質層及非晶質層所構成之氧化物 半導體膜的薄膜電晶體。 I：先前技術3 背景技術 近年來’隨著液晶或電激發光(Electro Luminescence : 10 EL)技術#的進步’平面顯示器（Flat Panel Display : FPD) 正被實用化。該等FPD係藉由場效型薄膜電晶體(Thin Film Transistor : TFT)之主動矩陣電路驅動，該場效型薄膜電晶 體係於活性層中使用設於玻璃基板上之非晶質矽薄膜或多 結晶矽薄膜。為提升該等FPD之更薄型化、輕量化及耐破 15損性，正嘗試以輕量並具有可撓性之樹脂基板取代玻璃基 板。 使用前述矽薄膜之TFT的製造，因需較高溫之熱程 序，故於耐熱性低之樹脂基板上直接形成是困難的。雖有 人揭示了使用可以較矽低溫進行成膜之z n 〇作為材料之氧 20化物半導體薄膜的TFT(專利文獻1)，但使用氧化物半導體 薄膜之TFT無法得到與使用矽薄臈之TFT相同的充分特性。 雖有人揭示了使用以Zn-Sn氧化物(ZTO)、In_Ga_Zn氧 化物（IGZ0)等複合氧化物作為材料之TFT(專利文獻2及 3)，但非晶質氧化物半導體薄膜容易因周圍環境氣體之影 5 200915579 響改變特性，特別是於真空下會大幅改變其特性(非專利文 獻1)。因此，使用非晶質氧化物半導體薄膜之tft容易產生 特性差異，而需嚴密之製造管理。此外，使用非晶質氧化 物半導體薄膜之TFT有容易隨時間產生變化、及熱傳導率不 5佳，而因蓄熱產生劣化等問題。 為解決非晶質氧化物半導體薄膜之問題，亦有人揭示 了藉由化學軋相蒸鍍(CVD)成膜5丨(^膜以包覆活性層，形成 钱刻中止層之方法（非專利文獻2)。然而，使用|虫刻中止層 之方法除了有光罩片數增加、成本增多等問題外，亦有因 10成膜Si〇x膜時之電漿使活性層特性劣化的問題。 又，因非晶質氧化物半導體薄膜為非晶質，故對以PAN 為代表之蝕刻液等的耐藥品性低，而有半導體膜上之金屬 配線未能進行濕式蝕刻、折射率大及多層膜之透射率容易 下降等缺點。又’因非晶質氧化物半導體薄膜為非晶質， 15故會吸附環境氣體中之氧或水等，改變電特性，若不嚴密 管理下個程序之環境氣體，則會有產生特性差異、或產率 下降之疑慮。 前述方法以外，亦有人揭示了積層透明導電膜改良導 電性之方法（專利文獻4)、或使ZnO之一部分結晶化以改良 20 半導體特性之方法（專利文獻5)，但並未有於活性層使用氧 化物，以提升穩定性之研究。 【專利文獻1】特開2003-298062號公報 【專利文獻2】W02005/015643號文獻 【專利文獻3】W02005/088726號文獻 200915579 【專利文獻4】特開平8-43841號公報 【專利文獻5】特開2007-123861號公報 【导g 專利文獻 1】APPLIED PHYSICS LETTERS 90, 192101, 2007, Donghun Kang et al. 5 【非專寿|J 文獻2】APPLIED PHYSICS LETTERS 90, 212114, 2007, Minkyu Kim et al. 本發明之目的係提供一種可防止氧氣分壓等周圍環境 氣體的影響，並顯示穩定之半導體特性的薄膜電晶體。 C發明内容3 10 發明揭示 依據本發明，可提供以下之薄膜電晶體等。 1. 一種薄膜電晶體，係包含有由積層結晶質層及非晶 質層所構成之氧化物半導體膜者。 2. 如1之薄膜電晶體，其中前述結晶質層包含有銦，且 15 除了氧以外’全原子中所佔之前述銦的含有率係90原子％ 以上，1〇〇原子％以下。 3. 如2之薄膜電晶體，其中前述結晶質層更包含有1種 以上之正二價金屬元素。 4. 如3之薄膜電晶體，其中前述結晶質層包含有作為正 20二價金屬元素之鋅。 5. 如2〜4中任一項之薄膜電晶體，其中前述結晶質層顯 不銦之紅綠柱石（bixbite)型結晶構造。 6. 如1〜5中任一項之薄膜電晶髏，其中前述非晶質層包 含銦及鋅中之至少1種。 200915579 及鎵 7·如6之薄膜電晶體，其中前述非晶質層包含有銦、 鋅 8_一種薄膜電晶體，係由透明基材、閘極電極、閘極 絕緣膜、氧化物半導體膜、源極電極及祕電極所構成者， 且前述氧化物半導體膜係結晶質層及非晶質層之積層體 前述非晶質層係與閉極絕緣膜連接，前述結晶質層係心 述非晶質層連接，且隔著通道部與源極電極及沒極^ 連接。 电 10 15 刻中1Γ之薄膜電晶體’其中於前述結晶f層上更具有餘 10.-種薄膜電晶體，係由透明基材 '間極電極 絕緣膜、氧化物半導_、祕電極及祕電極所構成1 且前述氧化物半導體膜係結晶質層及非晶質層之積層體’ 則述非晶質層係與閘極絕緣膜連接，前述結 述非晶質層連接，X，前述薄膜電晶體具有以包 =勿半導體膜方式形叙_緣W通前2 严絕緣膜之通孔，並且前述結晶質層透過前述通孔而料 逑源極電極及沒極電極電連接。 11·一種薄膜電晶體，係由透明基材1極電極、_ 絕緣膜、氧化物半導_、雜電極及祕電 且峨化物半她輪質__之積層\ 別述非晶質層係與閘極絕緣膜連接 :非晶質層連接，前述閘極絕緣膜係以包覆 體膜之方式形成，且前述間極絕緣膜上具有前述閑極電 20 200915579 才系〇 12. 如8〜11中任一之薄膜電晶體，其中前述源極電極及 前述汲極電極係由金屬薄膜所構成。 13. 如8〜11中任一之薄膜電晶體，其中前述源極電極及 5 前述汲極電極係由導電性金屬氧化物薄膜所構成。 14. 如8〜11中任一之薄膜電晶體，其中前述源極電極及 前述汲極電極係由金屬薄膜及導電性金屬氧化物薄膜之積 層體所構成。 15. 如13或14之薄膜電晶體，其中前述導電性金屬氧化 10 物薄膜係由選自於由氧化銦、氧化錫及氧化辞所構成之群 之1種以上金屬氧化物構成。 16. 如12或14之薄膜電晶體，其中前述金屬薄膜係選自 於由Al、Cu、Mo、W、Ni、Cr、Ag及Au所構成之群之1種 以上的金屬構成之合金或積層體。 15 依據本發明，可提供一種可防止氧氣分壓等周圍環境 氣體的影響，並顯示穩定之半導體特性的薄膜電晶體。 圖式簡單說明 第1圖係顯示本發明薄膜電晶體之一實施形態的概略 截面圖。 20 第2圖係顯示本發明薄膜電晶體之其他實施形態的概 略截面圖。 第3圖係顯示本發明薄膜電晶體之其他實施形態的概 略截面圖。 第4圖係顯示本發明薄膜電晶體之其他實施形態的概 9 200915579 略截面圖。 第5圖係顯示本發明薄膜電晶體之其他實施形態的概 略截面圖。 第6圖係顯示本發明薄膜電晶體之其他實施形態的概 5 略截面圖。 第7圖係實施例1中製造之氧化物半導體膜的截面照 片。 第8圖係顯示大氣下及真空下（l(T3Pa)實施例1之薄膜 電晶體的轉移特性的圖。 10 第9圖係顯示大氣下及真空下（10_3Pa)比較例1之薄膜 電晶體的轉移特性的圖。 第10圖係實施例17中製作之薄膜電晶體的概略截面 圖。 第11圖係實施例18中製作之薄膜電晶體的概略截面 15 圖。 【實施方式3 實施發明之最佳形態 以下，參照圖式說明本發明之薄膜電晶體。 第1圖係顯示包含有由積層結晶質層及非晶質層所構 20 成之氧化物半導體膜的本發明薄膜電晶體之第1實施形態 的概略截面圖。 薄膜電晶體1係於基板10及閘極絕緣膜30之間挾持有 閘極電極20，且積層有作為活性層之氧化物半導體膜40， 該氧化物半導體膜4 0係於閘極絕緣膜3 0上積層有由非晶質 10 200915579 層42及結晶質層44所構成者。此外，分別設有源極電㈣ 及汲極電極52，以包覆氧化物半導體膜40 ,且於氧化物” 導體膜4G、源極電極5〇及汲極電極52所包圍之部分形: 道部60。 /成、 另外，第1圖之薄膜電晶m係所謂之通道麵刻 電晶體。 本發明之薄膜電晶體i中’作為活性層之氧化物半導體 膜40具有積層有非晶質層42及結晶質層44的構造。氧化物 半導體膜40因具有結晶質層44，可防止氧氣分壓等周圍環 境氣體之影響，可提升薄膜電晶體r穩定性。提升穩定性 之結果’可形成即使於大氣下及真空下之任_環境氣體 下，場效移動度及。n-off比高，又，顯示㈣且夹止清楚之 薄膜電晶體卜又’因薄膜電晶體i具有高穩定性，故不需 積層蝕刻中止層，而可大面積化。 15 氧化物半導體膜40之膜厚通常係3〜500nm，以5〜2〇〇nm 為佳，更佳者是10〜80nm，特佳者為15〜6〇11111。當氧化物半 導體膜40之膜厚小於3nm時，有不易形成膜質均勻之氧化物 半V體膜的疑慮。另一方面，當氧化物半導體膜4〇之膜厚 大於50〇nm時，因成膜時間變長，而有生產效率下降之疑 20慮、及有薄膜電晶體1成為常開，消耗電力變大之疑慮。 非晶質層42之膜厚通常係1〜2〇〇nm’以2〜1〇〇ηηι為佳， 較佳者是3〜70nm。當非晶質層42之犋厚小於lnm時，有不 易成獏之疑慮。另一方面，畲非晶質層42之膜厚大於2〇〇nm 時，有非晶質層42之加工精準度降低、移動度下降之疑慮。 11 200915579 結晶質層44之膜厚以2nmw上為佳，較佳者是5nm以 上，更佳者係10nm以上，特佳者為2〇nm以上。當結晶質層 44之膜厚小於2nm時，會有無法保護非晶質層心之疑慮。 又’結晶質層44之膜厚上限可舉例如，2〇〇nm。 另外，氧化物半導體膜40只要積層有非晶質層们及結 晶質層44的話，並未受到限定’氧化物半導_爾可^ 例如，具有由3層以上之非晶質層及結晶質層所構成之多層 構造。 於積層非晶質層42及結晶質層44所構成之氧化物半導 10體膜40中，通道形成區域以非晶質層42為佳。當通道形成 區域為非晶質層時，即使於氧化物半導體膜彎曲時，仍可 減少半導體特性之改變。 本實施形態中，形成閘極電極2〇、源極電極5〇及及極 電極52等各電極之材料並未特別限制，可於不損及本發明 效果之範圍内使用眾所周知的材料。可使用例如：ιτ〇、 ΙΖΟ、ΖηΟ、Sn〇2等透明電極；A1、Ag、&、见、μ〇、如、200915579 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to a thin film transistor. More specifically, it relates to a thin film transistor comprising an oxide semiconductor film composed of a laminated crystalline layer and an amorphous layer. I. Prior Art 3 Background Art In recent years, with the advancement of liquid crystal or electroluminescence (Electro Luminescence: 10 EL) technology, a flat panel display (FPD) has been put into practical use. The FPDs are driven by an active matrix circuit of a Thin Film Transistor (TFT), which uses an amorphous germanium film provided on a glass substrate in the active layer or Polycrystalline ruthenium film. In order to improve the thinness, light weight, and breakage resistance of these FPDs, attempts have been made to replace the glass substrate with a lightweight and flexible resin substrate. In the production of a TFT using the above-mentioned tantalum film, it is difficult to form directly on a resin substrate having low heat resistance because a relatively high temperature thermal step is required. Although a TFT using an oxide 20-semiconductor thin film which can form zn 〇 as a material at a low temperature has been disclosed (Patent Document 1), a TFT using an oxide semiconductor thin film cannot be obtained in the same manner as a TFT using a thin tantalum. Fully characterized. Although a TFT using a composite oxide such as Zn-Sn oxide (ZTO) or In_Ga_Zn oxide (IGZ0) as a material has been disclosed (Patent Documents 2 and 3), an amorphous oxide semiconductor film is liable to be affected by ambient gas. Shadow 5 200915579 The change characteristic, especially under vacuum, greatly changes its characteristics (Non-Patent Document 1). Therefore, the use of the amorphous oxide semiconductor thin film tft tends to cause a difference in characteristics, and requires strict manufacturing management. Further, the TFT using the amorphous oxide semiconductor thin film has a problem that it is easy to change with time, and the thermal conductivity is not as good as 5, and deterioration due to heat storage occurs. In order to solve the problem of amorphous oxide semiconductor thin films, it has also been disclosed that a film is formed by chemical vapor deposition (CVD) to coat a film (the film is coated to form an active layer to form a stop layer) (Non-Patent Literature) 2) However, in addition to problems such as an increase in the number of masks and an increase in cost, the method of using the insect-killing layer also has a problem that the characteristics of the active layer are deteriorated by the plasma in the case of a film-forming Si〇x film. Since the amorphous oxide semiconductor thin film is amorphous, the chemical resistance of the etching liquid represented by PAN or the like is low, and the metal wiring on the semiconductor film is not wet-etched, and the refractive index is large and multilayer. The transmittance of the film is likely to decrease, etc. Further, 'the amorphous oxide semiconductor film is amorphous, so it will adsorb oxygen or water in the ambient gas, and change the electrical characteristics, if the environment of the next program is not strictly managed. The gas may have a difference in characteristics or a decrease in yield. In addition to the above methods, a method of improving the conductivity of the laminated transparent conductive film has been disclosed (Patent Document 4), or a part of ZnO is crystallized to improve 20 semiconductors. characteristic (Patent Document 5), but there is no use of an oxide in the active layer to improve the stability. [Patent Document 1] JP-A-2003-298062 [Patent Document 2] WO2005/015643 [Patent Document 3] Japanese Patent Publication No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. Kang et al. 5 [non-special life | J document 2] APPLIED PHYSICS LETTERS 90, 212114, 2007, Minkyu Kim et al. The object of the present invention is to provide an effect of preventing ambient gas such as oxygen partial pressure and showing stability. The present invention discloses a thin film transistor, etc. according to the present invention. 1. A thin film transistor comprising a layer of a crystalline layer and an amorphous layer. 2. The thin film transistor according to 1, wherein the crystalline layer contains indium, and 15 except for oxygen, the content of the indium in the total atom is 90 % or more, 1 〇〇 atomic % or less. 3. The thin film transistor according to 2, wherein the crystalline layer further comprises one or more kinds of positive divalent metal elements. 4. The thin film transistor of 3, wherein the crystalline layer 5. A thin film transistor according to any one of 2 to 4, wherein the crystal layer is a bixbite type crystal structure in which the crystal layer is indium. The thin film transistor of any one of the above-mentioned, wherein the amorphous layer contains at least one of indium and zinc. 200915579 and a thin film transistor of gallium 7 such as 6, wherein the amorphous layer comprises indium and zinc 8 - a thin film transistor, which is composed of a transparent substrate, a gate electrode, a gate insulating film, an oxide semiconductor film, And a layered body of the oxide semiconductor film-based crystalline layer and the amorphous layer, wherein the amorphous layer is connected to the closed-electrode insulating film, and the crystalline layer is amorphous The layers are connected and connected to the source electrode and the gate electrode via the channel portion. A thin film transistor of 1 电 in the electric circuit of 10 ', wherein the film of the above-mentioned crystal f has more than 10.-type thin film transistor, which is composed of a transparent substrate, an interlayer electrode insulating film, an oxide semiconductor, and a secret electrode. The first electrode and the oxide semiconductor film-based crystal layer and the amorphous layer are laminated. The amorphous layer is connected to the gate insulating film, and the amorphous layer is connected. X, the aforementioned The thin film transistor has a through hole in which the first insulating film is formed in the form of a semiconductor film, and the crystalline layer is electrically connected to the source electrode and the electrodeless electrode through the through hole. 11. A thin film transistor consisting of a transparent substrate, a 1-electrode, an insulating film, an oxide semiconductor, an impurity electrode, and a micro-electrode and a germanium semi-circular __ laminate. Connected to the gate insulating film: the amorphous layer is connected, the gate insulating film is formed by covering the film, and the inter-electrode insulating film has the aforementioned idle pole 20 200915579. The thin film transistor according to any one of the eleventh, wherein the source electrode and the drain electrode are made of a metal thin film. 13. The thin film transistor according to any one of 8 to 11, wherein the source electrode and the drain electrode are made of a conductive metal oxide film. 14. The thin film transistor according to any one of 8 to 11, wherein the source electrode and the drain electrode are composed of a laminate of a metal thin film and a conductive metal oxide thin film. 15. The thin film transistor according to 13 or 14, wherein the conductive metal oxide film is made of one or more metal oxides selected from the group consisting of indium oxide, tin oxide, and oxidized. 16. The thin film transistor according to 12 or 14, wherein the metal thin film is an alloy or a laminate composed of one or more metals selected from the group consisting of Al, Cu, Mo, W, Ni, Cr, Ag, and Au. body. According to the present invention, it is possible to provide a thin film transistor which can prevent the influence of ambient gas such as partial pressure of oxygen and exhibit stable semiconductor characteristics. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing an embodiment of a thin film transistor of the present invention. Fig. 2 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. Fig. 3 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. Fig. 4 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. Fig. 5 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. Fig. 6 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. Fig. 7 is a cross-sectional photograph of the oxide semiconductor film produced in Example 1. Fig. 8 is a view showing the transfer characteristics of the thin film transistor of Example 1 under the atmosphere and under vacuum (10 (T3Pa). 10 Fig. 9 shows the thin film transistor of Comparative Example 1 under the atmosphere and under vacuum (10_3 Pa). Fig. 10 is a schematic cross-sectional view of a thin film transistor produced in Example 17. Fig. 11 is a schematic cross-sectional view of a thin film transistor produced in Example 18. [Embodiment 3 BEST MODE Hereinafter, a thin film transistor of the present invention will be described with reference to the drawings. Fig. 1 shows a first embodiment of the thin film transistor of the present invention comprising an oxide semiconductor film composed of a layered crystalline layer and an amorphous layer. A thin-film transistor 1 is provided between the substrate 10 and the gate insulating film 30, and has a gate electrode 20, and an oxide semiconductor film 40 as an active layer is laminated, and the oxide semiconductor film 40 is laminated. A layer of amorphous 10 200915579 layer 42 and a crystalline layer 44 is laminated on the gate insulating film 30. Further, a source (four) and a drain electrode 52 are provided to cover the oxide semiconductor film. 40, and in the oxide The portion surrounded by the film 4G, the source electrode 5A, and the drain electrode 52 is formed by a channel portion 60. In addition, the thin film electro-crystal m of Fig. 1 is a so-called channel surface-etched transistor. In the crystal i, the oxide semiconductor film 40 as the active layer has a structure in which the amorphous layer 42 and the crystalline layer 44 are laminated. The oxide semiconductor film 40 has a crystalline layer 44, and can prevent ambient gas such as partial pressure of oxygen. The effect can improve the stability of the thin film transistor r. The result of improving the stability can form a field effect mobility and a high n-off ratio even under the atmosphere and under vacuum, and display (4) Moreover, since the thin film transistor i has high stability, the thin film transistor i has high stability, so that the etching stop layer is not required to be laminated, and the area can be increased. 15 The film thickness of the oxide semiconductor film 40 is usually 3 to 500 nm. It is preferably 5 to 2 〇〇 nm, more preferably 10 to 80 nm, and particularly preferably 15 to 6 〇 11111. When the film thickness of the oxide semiconductor film 40 is less than 3 nm, it is difficult to form a uniform oxide half. V body film doubts. On the other hand, when the oxide semiconductor film When the film thickness of 4 大于 is more than 50 〇 nm, the film formation time becomes long, and the production efficiency is lowered, and the thin film transistor 1 is normally opened, and the power consumption is increased. The film thickness is usually 1 to 2 〇〇 nm', preferably 2 to 1 〇〇ηηι, and more preferably 3 to 70 nm. When the thickness of the amorphous layer 42 is less than 1 nm, there is a fear that it is unlikely to become a ruthenium. On the other hand, when the film thickness of the amorphous layer 42 is larger than 2 〇〇 nm, the processing accuracy of the amorphous layer 42 is lowered and the degree of mobility is lowered. 11 200915579 The film thickness of the crystalline layer 44 is 2 nmw. Preferably, it is 5 nm or more, more preferably 10 nm or more, and particularly preferably 2 〇 nm or more. When the film thickness of the crystal layer 44 is less than 2 nm, there is a fear that the amorphous layer core cannot be protected. Further, the upper limit of the film thickness of the crystalline layer 44 is, for example, 2 〇〇 nm. In addition, when the amorphous layer and the crystalline layer 44 are laminated, the oxide semiconductor film 40 is not limited to an 'oxide semiconductor'. For example, it has three or more amorphous layers and crystals. The multilayer structure formed by the layers. In the oxide semiconductor film 40 composed of the laminated amorphous layer 42 and the crystalline layer 44, the channel formation region is preferably the amorphous layer 42. When the channel formation region is an amorphous layer, the change in semiconductor characteristics can be reduced even when the oxide semiconductor film is bent. In the present embodiment, the material of each of the electrodes such as the gate electrode 2, the source electrode 5, and the electrode 52 is not particularly limited, and a well-known material can be used without departing from the effects of the present invention. For example, transparent electrodes such as ιτ〇, ΙΖΟ, ΖηΟ, and Sn〇2 can be used; A1, Ag, &, see, μ〇,
Ti、Ta等金屬電極；或包含該等之合金的金屬電極。 閘極電極2〇、源極電極50、汲極電極52等各電極亦可 為積層有相異二層以上之導電層的多層構造。 20 源極電卿錢㈣極52宜為由金制膜構成 極、由導電性金屬氧化物薄膜構成之電極、或由金屬· 及導電性氧化物_之積層體構成的電極。 、 前述金屬薄膜宜為選自於由a metal electrode such as Ti or Ta; or a metal electrode including the alloy. Each of the electrodes such as the gate electrode 2A, the source electrode 50, and the drain electrode 52 may have a multilayer structure in which two or more layers of conductive layers are laminated. 20 Source electrode (4) The electrode 52 is preferably an electrode composed of a gold film, an electrode made of a conductive metal oxide film, or an electrode composed of a metal and a conductive oxide. The foregoing metal film is preferably selected from the group consisting of
AgAAu所構成之群之1種以上金屬構成之合金或積層體。、 12 200915579 ::氧化錫__構成之群 5電極;#2::日厂日體1驅動時，間極電極2G、源極電極50及汲極 =電壓_，以下，以50V以下為佳較佳者 更仏者係5V以下。當該等電極之電壓大於loov /賴電晶體1之消耗電力變大，實用性下降疑慮。 形成閉極絕緣膜3〇之材料並未特別限制。可於不損及 本發明效果之範圍内使用眾所周知的材料。可使用例如： 10 Si02 ' SiNx ' Α1 Ο λ η m Λ1203 Ta2〇5、Tl〇2、Mg〇、Zr〇2、Ce〇2、κ 2〇、认〇、Na2〇、Rb2〇、Sc2〇3、γ2〇3、邱〇3 c趣3An alloy or a laminate of one or more kinds of metals composed of AgAAu. , 12 200915579 :: Tin oxide __ group 5 electrode; #2:: Japanese factory body 1 drive, the electrode 2G, the source electrode 50 and the drain = voltage _, below, preferably below 50V The better ones are more than 5V. When the voltage of the electrodes is greater than the power consumption of the Loov/Lai transistor 1, the practicality is lowered. The material for forming the closed-electrode insulating film 3 is not particularly limited. Well-known materials can be used without departing from the effects of the present invention. For example: 10 Si02 'SiNx ' Α1 Ο λ η m Λ1203 Ta2〇5, Tl〇2, Mg〇, Zr〇2, Ce〇2, κ 2〇, 〇, Na2〇, Rb2〇, Sc2〇3 , γ2〇3, Qiu〇3 c fun 3
Pbh、BaTa2〇6、SrTi〇3、A1N等氧化物（另外，x係例祕 ±〇_ 1)。該等中亦以 si〇2、SlNx、Al2〇3、Υ2〇3、Hf2〇3' CaHf〇3 為佳，較佳者是 Si〇2、SiNx、Υ2〇3、Hf2〇3、CaHf〇3，特佳 15者為SiNx。另外，SiNjUl合有氫為佳。 前述氧化物之氧氣數，亦可未必與化學計算比率相同 (亦可為例如’ Si02或SiOx)。 閑極絕緣膜3 0亦可為積層有相異之2層以上閣極絕緣 膜的構造。又’閘極絕緣膜30亦可為結晶質、多結晶質及 20非晶質之任一者，由容易製造之觀點來看，以多結晶質或 非晶質為佳。 閘極絕緣膜30亦可使用聚（4-乙稀苯 酸)(P〇ly(4_vinylphenol))(PVP)、聚對二甲苯基等有機絕緣膜。 又’閘極絕緣膜3〇亦可具有無機絕緣膜及有機絕緣膜等2層 13 200915579 以上積層構造。 薄犋電晶體1之通道寬度W及通道長度長L之比W/L通 常係0.1〜100，以1〜20為佳，特佳者為2〜8。當W/L大於1〇〇 時’有漏電流增加、0n-0ff比下降之疑慮。另一方面，當 5 W/L小於0.1時，則有場效移動度下降、夾止不清楚之疑慮。 通道長度長L通常係0.1〜ΙΟΟΟμηι，以1〜ΙΟΟμιη為佳，更 佳者係2〜ΙΟμιη。當通道長度L小於0.1 μ時，將不易工業製 造’且有短通道效果顯現、漏電流變大之疑慮。另一方面， 當通道長度L大於，有元件過大、驅動電壓變大 10 等疑慮。 薄膜電晶體1之場效移動度通常係1 cm2/Vs以上，以 5cm2/Vs以上為佳，較佳者是18cm2/Vs以上，更佳者係 30cm2/Vs以上，特佳者為5〇cm2/Vs以上。當薄膜電晶體之 場效移動度小於lCm2/Vs時，有交換速率變慢之疑慮。 15 ㈣電晶體1之〇n-〇ff比通常係1〇3以上，以1〇4以上為 佳，較佳者是105以上，更佳者係1〇6以上，特佳者為ι〇7以 上。 20 薄膜電晶體1之閾值電壓（vth)通常係〇〇ι〜5ν，以 〇_〇5〜3V為佳，較佳者是G」〜2V，更佳者敏2V〜⑽。當 閣值電壓小胸_，有因較讀v小之變動而成為常開 之=。另：方面’當間值電壓大於5V時，有薄膜電晶體 之消耗電力變大的疑慮。 本發明薄膜雷b鞞,> Bn ^ 电日日體1之閾值電壓差△VthbVth(大 氣)-Vth(真空)μχ5ν以下為 q丨土？又仏者疋3V以下，更佳者係 14 200915579 2V以下，特佳者為IV以下。當閾值電壓之差大於5V時，有 閾值差異變大，於顯示器中使用薄膜電晶體時，有需要複 雜之補償電路的疑慮。 第2圖係顯示本發明薄膜電晶體之第2實施形態的截面 5 圖。 以下，將與第1圖相同之構件附上相同之參照號碼，並 省略其說明。 薄膜電晶體2除了於氧化物半導體膜41中，結晶質層及 非晶質層間之邊界並不清楚以外，具有與第一實施形態之 10 薄膜電晶體1相同的構造。 本發明中，氧化物半導體膜只要具有結晶質層及非晶 質層的話，即使層間之邊界並不清楚亦可。亦可為例如， 結晶性、組成等階段性地變化者。 第3圖係顯示本發明薄膜電晶體之第3實施形態的截面 15 圖。 薄膜電晶體3除了於閘極絕緣膜3 0上設置保護膜7 0，以 包覆氧化物半導體膜40、源極電極50、汲極電極52以外， 具有與第1實施形態之薄膜電晶體1相同的構造。 保護膜70可使用例如：由與SiNx、Si02等絕緣膜相同 20 之材料所構成之膜、或醯亞胺、聚對二曱苯基等有機絕緣 膜。又，亦可使用積層及/或混合有無機絕緣膜及有機絕緣 膜之保護膜。 第4圖係顯示本發明薄膜電晶體之第4實施形態的截面 圖。 15 200915579 止層80以了於氣化物半導體膜40上設有姓刻中 I 卜’具有與第1實施形態之薄膜電晶觀目同之構 '專膜電晶體4係所謂之餘刻中止層型薄膜電晶 5 體。 、_中止層8G可舉由SiNx#構成之層為例，藉將其設 置於^化物半導體膜上，可使薄膜電晶體4之穩定性提升。 第5圖係顯示本發明薄膜電晶體之第5實施形態的截面 圖。 薄膜電晶體5具有為包覆氧化物半導體膜40所設置之 層間絕緣膜90，且該層間絕緣膜90具有2個通孔1〇〇。氧化 物半導體膜40透過通孔100，與源極電極50及汲極電極52電 連接’且藉由2個通孔1〇〇源極電極50及汲極電極52成為確 切破分割之構造。具有此種構造之薄膜電晶體係稱為通孔 15型薄膜電晶體，可確切且簡易地製造源極電極50及汲極電 極52 ’改善產率並可預期製造原價之成本下降。 層間絕緣膜90可使用例如：SiNx、Si02等無機物、或 酿亞胺、聚對二甲苯基等有機絕緣物。又，亦可舉例如， 由積層及/或混合有無機物及有機物構成之臈。又，其厚度 20可舉例如，50〜500nm。 第6圖係顯示本發明薄膜電晶體之第6實施形態的截面 圖。 薄膜電晶體6於基板上積層有由非晶質層42及結晶質 層44構成之氧化物半導體膜40。積層有閘極絕緣膜3〇以包 16 200915579 覆該氧化物半導體膜40，且於閘極絕緣膜30上積層有閘極 電極20。 具有此種構造之薄膜電晶體係稱為上部閘極型薄膜電 晶體，因可以較少之製造程序製造，故可期待製造原價之 5 成本下降。 本發明之薄膜電晶體適用於邏輯電路、記憶電路、差 動放大電路等積體電路。此外，本發明之薄膜電晶體適用 於靜電誘發型電晶體、肖特基屏障型電晶體、肖特基二極 體、電阻元件。 10 以下，具體說明本發明薄膜電晶體中使用之由積層結 晶質層及非晶質層所構成之氧化物半導體膜。 本發明中，結晶層係可於電子顯微鏡像中確認包含結 晶之層，而非晶質層係無法於電子顯微鏡像中確認包含結 晶之層。 15 結晶層亦可為單結晶膜、外延膜及多結晶膜之任一 者，由工業生產容易且可大面積化來看，以外延膜及多結 晶膜為佳，特佳者為多結晶膜。 當結晶質層為多結晶膜時’該多結晶膜以由奈米結晶 構成者為佳。由X射線繞射使用Scherrer’ s equation(謝樂方 20 程式）求得之平均結晶粒徑通常為500nm以下，以300nm以 下為佳，較佳者是150nm以下，更佳者係80nm以下。當大 於500nm時，會有將電晶體細微化時之差異變大的疑慮。 結晶質層以包含有銦元素為佳。 當結晶質層包含有銦元素時，除了氧以外，全原子中 17 200915579 所佔之銦元素的含有率係以9〇原子％以上，100原子％以下 為佳’較佳者是91原子％以上，99原子％以下。當銦元素之 含有率小於9〇原子％時，結晶質層之結晶化溫度會變高， 除了有結晶質層之積層變得困難的疑慮，亦有所得之薄膜 5電晶體的移動度下降之疑慮。 結晶質層宜更包含有1種以上之正二價金屬元素。正二 價金屬元素係離子狀態下之價數可取得正二價的元素，當 結晶質層包含有正三價金屬元素之銦時，若結晶質層更含 有正二價金屬元素時，可控制因缺氧而產生之電子’並可 10 保持低載子密度。 前述正二價金屬元素，可舉例如：Zn、Be、Mg、Ca、 Sr、Ba、Ti、V、Cr、Μη、Fe、Co、Ni、Pd、Pt、Cu、Ag、 Cd、Hg、Sm、、Yb等，由有效率地控制載子濃度之觀 點來看，以Zn、Mg、Mn、Co、Ni、Cu及Ca為佳。 15 前述較佳之正二價金屬元素中，由藉由添加以控制载 子效果之觀點來看，較佳者是Cu及Ni，由透射率及能隙寬 度之觀點來看，較佳者是Zn及Mg。 該等正二價金屬元素亦可於不損及本發明效果之範圍 内組合複數使用。 20 當結晶質層包含銦元素及正二價金屬元素時，銦[inj 與正二價金屬元素[X]之原子比[χ/(χ + In)]以〇 〇〇〇 ^ 3 為佳。 當原子比[X/(X +In)]小於〇 〇〇〇1時，正二價金屬元素之 含有率少，有無法控制載子數之疑慮。另一方面，當原子 18 200915579 比[Χ/(Χ + In)]大於0.13時，結晶質層及非晶質層之界面或結 晶質層的表面會容易變質而不穩定，且結晶質層之結晶化 溫度變高，而不易結晶化，載子濃度變高，孔移動度下降， 於使電晶體驅動時有閾值電壓變動、及驅動不穩定之疑慮。 5 又，當結晶質層包含有氧化銦及正二價金屬元素之氧 化物時，通常宜相對於結晶質層質量，將氧化銦及正二價 金屬元素之氧化物的合計質量設為50質量％，以65質量％以 上為佳，較佳者是80質量％以上，更佳者係90質量％以上， 特佳者為95質量％以上。當氧化銦及正二價金屬元素之氧 10 化物的合計質量小於50質量％時，會有氧化物半導體膜之 移動度下降等，無法充分顯現本發明效果之疑慮。 結晶質層亦可更包含有正三價金屬元素。正三價金屬 元素係離子狀態下之價數可取得正三價的元素。 前述正三價金屬元素可舉例如：Ga、A卜La、Ce、Pr、 15 Nd、Pm、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu 等。亦可包含有2種以上之正三價金屬元素。 當結晶質層更含有微量之Sn等正四價金屬元素時，Zn 等正二價金屬元素會相對於正三價金屬元素之銦，取得價 數之均衡，可達成結晶質層之穩定化。但是，當結晶質層 20 包含有多量之正四價金屬元素時，載子密度會過多，於作 為薄膜電晶體時，有關閉電流變高之疑慮。正四價金屬元 素之含有量宜為結晶質層所包含之正三價金屬元素的0.01 原子％〜10原子％。 當以質量定義正四價金屬元素之含有量時，正四價金 19 200915579 屬元素之含有量相對於結晶質層全體的質量，以3質量％以 下為佳，較佳者是2質量％以下，特佳者為1質量％以下。當 正四價金屬元素之含有量大於3質量％時，有無法將載子密 度控制成低濃度之疑慮。 5 例如，藉由使結晶質層包含選自於由銦、鋅(正二價金 屬元素）、鎵(正三價金屬元素）及錫（正四價金屬元素)所構成 之群之至少1種以上，可實現高移動度。另外，可藉由調整 結晶質層成膜時之環境氣體中的氧氣分壓、及環境氣體中 的H20及H2含有量，控制結晶質層之移動度。 10 結晶層以顯不铜之紅綠柱石型結晶構造為佳。糟使結 晶層為紅綠柱石構造，可提高孔移動度。可藉由X射線繞射 確認紅綠柱石型結晶構造。 非晶質層以包含有銦、鋅、錫及鎵中至少1種為佳，較 佳者是包含有銦、辞及鎵。當非晶質層包含有大如5S執道 15 之銦時，即使為非晶質仍可得移動度高之氧化物半導體 膜。另一方面，當非晶質層包含有鋅時，可為非晶質層之 結晶化溫度上升、移動度不下降，且穩定之非晶質層。此 外，當非晶質層包含有鎵時，非晶質層之載子密度會輕易 地減少，可穩定作為氧化物半導體膜之半導體的性能。 20 包含有結晶質層及非晶質層之元素的組合，宜為結晶 質層包含有銦及鋅，且非晶質層包含有銦、辞及鎵之組合。 本發明中，以結晶質層之導電率低於非晶質層之導電 率為佳。藉使結晶質層之導電率低於非晶質層之導電率， 可減小源極·汲極間之漏電流。 20 200915579 本發明中，以結晶質層之載子密度低於非晶質層之載 子密度為佳。藉使結晶質層之載子密度低於非晶質層之載 子密度，可減小源極·汲極間之漏電流。 結晶質層之比電阻及非晶質層之比電阻並無限制，但 5 當結晶質層之比電阻高於非晶質層之比電阻時，可減小源 極·汲極間之漏電流故為佳。 氧化物半導體膜之比電阻以10·1〜108Ω cm為佳，較佳者 是ΗΓ1〜107Qcm，特佳者為101〜106Qcm。氧化物半導體膜 之比電阻可藉由四探針法測定。 10 當氧化物半導體膜之比電阻小於10_1Ω cm時，電容易 於氧化物半導體膜中流動，而有氧化物半導體膜未能進行 作為半導體薄膜機能之疑慮。另一方面，當氧化物半導體 膜之比電阻大於108Ω cm時，氧化物半導體膜會有不施加強 大電場的話，便無法進行作為半導體機能之疑慮。 15 氧化物半導體膜之載子密度以小於1018cm_3為佳，較佳 者是小於2xl017cm_3，更佳者係小於1017cm_3，特佳者為小 於2xl016cm_3。當氧化物半導體膜之載子密度為1018cm_3以 上時，會有無法驅動薄膜電晶體、或即使驅動仍成為常開 使消耗電力變大之疑慮。 20 氧化物半導體膜之載子密度的下限可舉例如， 1014cm"3 ° 氧化物半導體膜之導電帶及價電子帶之能量帶間隙以 2_86¥以上為佳，較佳者是3.(^¥以上，更佳者係3.：^¥以 上，特佳者為3.5eV以上。當前述能量帶間隙小於2.8eV時， 21 200915579 於照射可見光時，氧化物半導體膜之價電子帶的電子被激 發而顯示導電性，有容易產生漏電流之疑慮。 另外’前述能量帶間隙之上限可舉例如，4.5eV。 本發明之由積層結晶質層及非晶質層所構成之氧化物 5半導體膜可藉由以下方法製造，係使用第1目標物於基板上 形成非晶質層，並於成膜的同時藉由基板溫度加熱處理非 晶質層’以作為結晶質層’再使用第2目標物於結晶質層上 形成非晶質層的方法。 具體而言，可使用以下方法製造，係使用包含有預定 1〇成分之(例如，銦元素及正二價金屬元素）目標物，於高溫之 基板上开)成非晶質氧化物半導體膜，並於成膜的同時藉由 基板溫度進行加熱處理，以作為結晶質層，再使用包含有 預定成分之其他目標物於該結晶質層上形成非晶質氧化物 半導體膜（非晶質層）的方法。 15 本發明之由積層有結晶㈣及m層所構成之氧化 物半導體_可藉“下方法製造，係錢w目標物於基 板上形成第㈣晶質層，再使用第2目標物於第（非晶質層上 形成第2非晶質層，並將由第i非晶質層及第2非晶質層才減 之積層體進行加熱處理的方法。 2〇具體而言，使用包含有預定成分之目標物於基板上形 成非晶質氧化物半導體膜，再使用其他目標物更於該非晶 2氧化物半導體膜上形成非晶f氧化物半導體膜，以成為 含有成分相異之2層非晶質氧化物半導體膜，最後藉加熱處 理僅使表面結晶化，可製造由積層有結晶質層及非晶質層 22 200915579 所構成之氧化物半導體膜。 另外，於刖述該等氧化物半導體膜之製造方法中，亦 可連續使用相同之目標物。 J用基板度可於形成非晶質氧化物半導體膜時同時 5、”σΒΘ化’積層結晶質層之方法可使製造程序簡略化。另-^面’藉由於形成非晶質氧化物半導體膜後，進行加熱處 里而作n aa貝層之方法，除了可提高所得之結晶質層的 移動度及結晶性、降低氧化物半導體膜之膜應力，亦可均 勻地於大面積結晶化，可輕易地控制載子。 ίο 本發明中’因可得優良之氧化物半導體膜，故宜使用 藉於形成非晶質氧化物半導體膜後，進行加熱處理而作為 結晶質層之方法，製造氧化物半導體膜。 成膜方法可使用例如：噴霧法、浸潰法、CVD法等化 學成膜方法；或濺鍍法、真空蒸鍍法、離子蒸鍍法、脈衝 15雷射沉積法等物理成膜方法。因可輕易控制載子密度、及 提升膜質’故以使用物理成膜方法為佳，較佳者是使用生 產性高之濺鍍法。 本發明中使用之濺鍍法可舉例如：DC濺鍍法、RF濺鍍 法、AC滅鍵法、ECR濺鑛法、對向目標物激鑛法（facing 2〇 target sputter)等，以DC濺鍍法、AC濺鍍法、ECR濺鍍法、 對項目標物濺鍍法為佳。 另外，滅鍍法亦可使用共錢鑛、交互減鑛（co-sputter) 及反應性滅鑛。 DC濺鍍法及AC濺鍍法生產性高、及可輕易降低載子濃 23 200915579 度。ECR蘭法及對向目標物賴法可㈣㈣膜質，且 可抑制因成膜造成之界面劣化、抑制漏電流、及提升on_off 比等氧化物半導體膜特性。 以下’記述使用濺鍍法作為成膜方法時，具體之成膜 5 條件。 濺鍍時目標物與基板之距離(S T距離），通常係150mm 以下，以110mm以下為佳，特佳者為8〇mm以下。 當s-τ距離為珂述距離時，藉於濺鍍時將基板曝置於電 激中’使目標物含有正二價金屬元素時，可期待正二價金 0屬70素之活性化。另一方面，當S-T距離大於150mm時，有 成膜速度下降、不適合工業化之疑慮。 極限壓力通常係5xi〇-2pa以下，以5xl〇-3Pa以下為佳， 較佳者是5xl〇-4pa以下，更佳者係lxl〇-4pa以下，特佳者為5 xl〇_5Pa以下。 §極限壓力大於5χΐ〇 2卩3時，會有大量自環境氣體中之 ΗζΟ等供應的氫原子’而有氧化物半導體膜之移動度下降之 疑慮。其可推測係因被供應之氫原子使氧化物半導體膜中 之結晶構造產生變化之故。 濺鍍時環境氣體中之氧氣分壓通常係4 〇 χ丨〇 _ 3 p a以下， 20以l5xl〇3paa下為佳，較佳者是7xl〇-3Pa以下，特佳者為1 xlO_3Pa以下。 當環丨兄氣體中氧氣分壓大於，會有氧化物 半導體膜之移動度下降、載子濃度不穩定等疑慮。其可推 測係因當成膜時環境氣體中氧氣分壓過高（氧濃度過高） 24 200915579 時’進入氣化物半導體膜中之晶格間的氧變多而散亂、或 氧谷易自祺中脫離使氧化物半導體膜不穩定化。 錢錢時環境氣體中H20及H2之濃度通常係1.2vol%以 下以1 .〇V〇1°/q以下為佳，較佳者是0· lvol%以下，特佳者為 5 〇·〇 lvol%以下。 虽3衣境氣體中H20及H2之濃度大於ι.2ν〇1%時，有氧化 物半導體犋之孔移動度下降的疑慮。 於截錢時’為均勻地形成半導體膜，可使用使固定基 板之摺疊機旋轉，並使磁鐵動作而擴大侵蝕範圍等方法。 1〇 於形成非晶質氧化物半導體膜的同時以基板溫度結晶 化’作為結晶質層時的基板溫度通常係250〜550。(：，以 300〜5〇〇°C為佳’較佳者是320~40(TC。當基板溫度小於250 C時’有結晶質層之結晶性低，且載子密度變高之疑慮。 令一方面’當基板溫度大於55(TC時，有製造成本變高、或 15 基板變形之疑慮。 藉由於形成非晶質氧化物半導體膜後進行加熱處理， 以作為結晶質層時的基板溫度通常小於25〇。(：，以200t以 下為佳’較佳者是15〇t以下，更佳者是係lOOt以下，特 佳者為50。(：以下。當基板溫度係250t以上時，因無法充分 發揮成膜後之加熱處理效果，故有不易控制氧化物半導體 膜之載子濃度及移動度的疑慮。 藉由於形成非晶質氧化物半導體膜後進行加熱處理， 以作為結晶質層之方法中，形成非晶質氧化物半導體膜後 之加熱溫度通常係80〜650°C，以180〜450。(：為佳，較佳者是 25 200915579 230〜400°C。當加熱溫度小於8〇°C時，有結晶化不充分、或 於結晶化花費過多時間的疑慮。另一方面，當加熱溫度大 於65(TC時，基板會有變形之疑慮。 又，加熱處理時間通常係0.5〜12000分鐘，以1〜1200分 5 鐘為佳，較佳者是2〜600分鐘。當加熱處理時間小於〇.5分 鍾時，有結晶化不充分之疑慮。另一方面，當加熱處理時 間大於12000分鐘時，則需大規模之處理裝置，有損及生產 效率之疑慮。 於前述加熱處理時，亦可使用臭氧處理、或施加高頻 10 波、電磁波、紫外線、電漿等其他能源。 結晶化使用之加熱處理裝置並未特別限定，可使用燈 退火裝置(LA : Lamp Annealer)、快速退火裝置(RTA : Rapid Thermal Annealer)、或雷射退火裝置。 本發明之氧化物半導體膜可適用於各種場效型電晶 15體。本發明之氧化物半導體膜通常係使用於η型區域，但亦 可使用於與ρ型Si系半導體、ρ型氧化物半導體、ρ型有機半 導體等各種P型半導體組合2PN接合型電晶體等半導體裝 置中。 [實施例] 20 實施例1 (1)濺鍍目標物之製造 原料係將氧化銦、氧化鋅、氧化鎵之粉末混合成原子 *In/(In + Zn + Ga)=〇.4u&Zn/(In + Zn+Ga)=0.2l 子比Ga/(In + Zn + Ga)=〇.4 ,並將該混合粉末供應至濕式球 26 200915579 磨機，進行混合粉碎72小時，調製原料細粉末。 將所得之原料細粉末造粒，壓模成形為直徑l〇cm，厚 度5mm之尺寸’得到成形體。將該成形體加入烘爐，以145〇 C ’ 12小時之條件燒製，得到濺鍍目標物工。 5 與目標物I同樣地’得到原子比In/(In + Zn)=0.93，原子 比Zn/(In+Zn)=0.07之濺鍍目標物η。 (2)氧化物半導體膜之製造 將所得之濺鍍目標物丨及丨〗裝設於RF磁控濺鍍成膜裝 置。該RF磁控濺鍍成膜裝置係於相同腔室具有複數陰極之 1〇 成膜裝置。 首先’使用濺鍍目標物I，於玻璃基板（圓錐1737)上形 成膜厚約30nm之氧化物薄膜I。於使用ICP發光分析裝置測 定該氧化物薄膜I之元素比時，係與目標物I之組成大致相 同。 15 其次，繼續於真空下使用濺鍍目標物II，於氧化物薄膜 I上形成膜厚約40nm之氧化物薄膜II。於使用ICP發光分析 裝置測定該氧化物薄膜II之元素比時，係與目標物II之組成 大致相同。 另外，目標物I及II之濺鍍條件係如以下。Oxides such as Pbh, BaTa2〇6, SrTi〇3, and A1N (in addition, x is a secret example ±〇_1). Preferably, Si〇2, SlNx, Al2〇3, Υ2〇3, Hf2〇3' CaHf〇3 are preferred, and Si〇2, SiNx, Υ2〇3, Hf2〇3, CaHf〇3 are preferred. The best 15 is SiNx. In addition, SiNjUl is preferably hydrogen. The oxygen number of the oxide may not necessarily be the same as the stoichiometric ratio (may also be, for example, 'SiO 2 or SiO x ). The dummy insulating film 30 may have a structure in which two or more layers of barrier insulating films are laminated. Further, the gate insulating film 30 may be any of crystalline, polycrystalline, and amorphous, and is preferably polycrystalline or amorphous from the viewpoint of easy production. As the gate insulating film 30, an organic insulating film such as poly(4-ethylene benzoate) (PVP) or polyparaphenylene can also be used. Further, the gate insulating film 3 may have a two-layer structure such as an inorganic insulating film or an organic insulating film. The ratio W/L of the channel width W and the channel length length L of the thin germanium transistor 1 is usually 0.1 to 100, preferably 1 to 20, and particularly preferably 2 to 8. When W/L is greater than 1 ’, there is a concern that the leakage current increases and the 0n-0ff ratio decreases. On the other hand, when 5 W/L is less than 0.1, there is a concern that the field effect mobility is lowered and the pinch is unclear. The length L of the channel is usually 0.1 to ΙΟΟΟμηι, preferably 1 to ΙΟΟμιη, and more preferably 2 to ΙΟμιη. When the channel length L is less than 0.1 μ, it is difficult to industrially manufacture and there is a concern that the short channel effect appears and the leakage current becomes large. On the other hand, when the channel length L is larger than that, the components are too large, and the driving voltage becomes large. The field effect mobility of the thin film transistor 1 is usually 1 cm 2 /Vs or more, preferably 5 cm 2 /Vs or more, preferably 18 cm 2 /Vs or more, more preferably 30 cm 2 /Vs or more, and particularly preferably 5 〇 cm 2 . /Vs or more. When the field effect mobility of the thin film transistor is less than lCm2/Vs, there is a concern that the exchange rate becomes slow. 15 (4) 〇n-〇ff of transistor 1 is more than 1〇3, usually 1〇4 or more, preferably 105 or more, more preferably 1〇6 or more, especially ι〇7 the above. 20 The threshold voltage (vth) of the thin film transistor 1 is usually 〇〇ι~5ν, preferably 〇_〇5~3V, preferably G"~2V, and more preferably 2V~(10). When the value of the cabinet is small, the chest is _, and it becomes normally open because of the change in the reading v. On the other hand, when the inter-value voltage is greater than 5 V, there is a concern that the power consumption of the thin film transistor becomes large. The film of the present invention has a threshold voltage difference of ΔVthbVth (atmospheric)-Vth (vacuum) μχ5 ν or less. The latter is less than 3V, and the better is 14 200915579 2V or less, and the best one is below IV. When the difference between the threshold voltages is larger than 5 V, the threshold difference becomes large, and when a thin film transistor is used in the display, there is a concern that a complicated compensation circuit is required. Fig. 2 is a cross-sectional view showing a second embodiment of the thin film transistor of the present invention. Hereinafter, the same members as those in Fig. 1 are denoted by the same reference numerals, and their description will be omitted. The thin film transistor 2 has the same structure as that of the tenth thin film transistor 1 of the first embodiment except that the boundary between the crystalline layer and the amorphous layer is not clear in the oxide semiconductor film 41. In the present invention, as long as the oxide semiconductor film has a crystalline layer and an amorphous layer, the boundary between the layers may not be clear. For example, crystallinity, composition, and the like may be changed stepwise. Fig. 3 is a cross-sectional view showing a third embodiment of the thin film transistor of the present invention. The thin film transistor 3 is provided with a protective film 70 on the gate insulating film 30 to cover the oxide semiconductor film 40, the source electrode 50, and the drain electrode 52, and has the thin film transistor 1 of the first embodiment. The same construction. For the protective film 70, for example, a film made of a material similar to that of an insulating film such as SiNx or SiO 2 or an organic insulating film such as quinone or polyphenylene phenyl can be used. Further, a protective film in which an inorganic insulating film and an organic insulating film are laminated and/or mixed may be used. Fig. 4 is a cross-sectional view showing a fourth embodiment of the thin film transistor of the present invention. 15 200915579 The stop layer 80 is provided with a surname in the vaporized semiconductor film 40, and has the same structure as the thin film electrocrystal of the first embodiment. Type thin film electro-crystal 5 body. The _stop layer 8G can be exemplified by a layer composed of SiNx#, and by setting it on the semiconductor film, the stability of the thin film transistor 4 can be improved. Fig. 5 is a cross-sectional view showing a fifth embodiment of the thin film transistor of the present invention. The thin film transistor 5 has an interlayer insulating film 90 provided to cover the oxide semiconductor film 40, and the interlayer insulating film 90 has two through holes 1?. The oxide semiconductor film 40 is electrically connected to the source electrode 50 and the drain electrode 52 through the via hole 100, and the source electrode 50 and the drain electrode 52 are cut and divided by the two via holes. The thin film electro-crystal system having such a structure is called a through-hole type 15 thin film transistor, and the source electrode 50 and the drain electrode 52' can be manufactured accurately and simply to improve the yield and can be expected to reduce the cost of manufacturing the original price. As the interlayer insulating film 90, for example, an inorganic substance such as SiNx or SiO 2 or an organic insulating material such as acrylonitrile or parylene may be used. Further, for example, it may be composed of a laminate and/or an inorganic material and an organic material. Further, the thickness 20 thereof is, for example, 50 to 500 nm. Fig. 6 is a cross-sectional view showing a sixth embodiment of the thin film transistor of the present invention. The thin film transistor 6 has an oxide semiconductor film 40 composed of an amorphous layer 42 and a crystalline layer 44 laminated on a substrate. A gate insulating film 3 is laminated, and the oxide semiconductor film 40 is covered with a package 16 200915579, and a gate electrode 20 is laminated on the gate insulating film 30. The thin film electro-crystal system having such a structure is called an upper gate type thin film transistor, and since it can be manufactured with a small number of manufacturing processes, it is expected that the cost of manufacturing the original price is lowered. The thin film transistor of the present invention is suitable for use in an integrated circuit such as a logic circuit, a memory circuit, or a differential amplifier circuit. Further, the thin film transistor of the present invention is suitably used for an electrostatic induction type transistor, a Schottky barrier type transistor, a Schottky diode, and a resistance element. 10 Hereinafter, an oxide semiconductor film composed of a laminated crystal layer and an amorphous layer used in the thin film transistor of the present invention will be specifically described. In the present invention, the crystal layer can confirm the layer containing the crystal in the electron microscope image, and the amorphous layer cannot confirm the layer containing the crystal in the electron microscope image. 15 The crystal layer may be any of a single crystal film, an epitaxial film, and a polycrystalline film. It is easy to be industrially produced and can be large in area, and an epitaxial film and a polycrystalline film are preferable, and a polycrystalline film is particularly preferable. . When the crystalline layer is a polycrystalline film, the polycrystalline film is preferably composed of nanocrystals. The average crystal grain size obtained by X-ray diffraction using Scherrer's equation (Xie Le Fang 20) is usually 500 nm or less, preferably 300 nm or less, preferably 150 nm or less, and more preferably 80 nm or less. When it is larger than 500 nm, there is a fear that the difference in the case where the crystal is fined becomes large. The crystalline layer preferably contains indium. When the crystalline layer contains indium, in addition to oxygen, the content of indium in the total atomic 17 200915579 is 9 〇 atom% or more, preferably 100 atom% or less, preferably 91 atom% or more. , 99 atom% or less. When the content of the indium element is less than 9 atom%, the crystallization temperature of the crystal layer becomes high, and the mobility of the obtained film 5 crystal is lowered in addition to the doubt that the layer of the crystal layer becomes difficult. doubt. The crystalline layer preferably further contains one or more kinds of positive divalent metal elements. The valence of the divalent metal element in the ionic state can obtain a positive divalent element. When the crystalline layer contains indium of a positive trivalent metal element, if the crystalline layer further contains a positive divalent metal element, the hypoxia can be controlled. The resulting electrons' and 10 maintain low carrier density. The positive divalent metal element may, for example, be Zn, Be, Mg, Ca, Sr, Ba, Ti, V, Cr, Μη, Fe, Co, Ni, Pd, Pt, Cu, Ag, Cd, Hg, Sm, From the viewpoint of efficiently controlling the concentration of the carrier, Yb or the like is preferably Zn, Mg, Mn, Co, Ni, Cu or Ca. In the above preferred divalent metal element, Cu and Ni are preferred from the viewpoint of controlling the effect of the carrier, and Zn is preferably used from the viewpoint of transmittance and energy gap width. Mg. These normal divalent metal elements may also be used in combination in plural amounts without departing from the effects of the present invention. 20 When the crystalline layer contains indium and a divalent metal element, the atomic ratio of indium [inj to the divalent metal element [X] [χ/(χ + In)] is preferably 〇 〇〇〇 ^ 3 . When the atomic ratio [X/(X + In)] is less than 〇 〇〇〇1, the content of the positive divalent metal element is small, and there is a concern that the number of carriers cannot be controlled. On the other hand, when the atom 18 200915579 is larger than [Χ/(Χ + In)] by more than 0.13, the interface between the crystalline layer and the amorphous layer or the surface of the crystalline layer is easily deteriorated and unstable, and the crystalline layer is The crystallization temperature becomes high, it is not easy to crystallize, the carrier concentration becomes high, and the pore mobility decreases, which causes a threshold voltage fluctuation and a drive instability when the transistor is driven. In addition, when the crystalline layer contains an oxide of indium oxide and a divalent metal element, the total mass of the oxide of the indium oxide and the divalent metal element is preferably 50% by mass based on the mass of the crystalline layer. It is preferably 65 mass% or more, more preferably 80 mass% or more, still more preferably 90 mass% or more, and particularly preferably 95 mass% or more. When the total mass of the indium oxide and the oxygen compound of the divalent metal element is less than 50% by mass, the degree of mobility of the oxide semiconductor film may be lowered, and the effect of the present invention may not be sufficiently exhibited. The crystalline layer may further contain a positive trivalent metal element. The positive trivalent metal element is a valence in the ion state to obtain a positive trivalent element. Examples of the positive trivalent metal element include Ga, A, La, Ce, Pr, 15 Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and the like. It may also contain two or more kinds of positive trivalent metal elements. When the crystalline layer further contains a trace amount of a positive tetravalent metal element such as Sn, a positive divalent metal element such as Zn is equal to the indium of the positive trivalent metal element, and a valence is obtained to achieve stabilization of the crystalline layer. However, when the crystalline layer 20 contains a large amount of a positive tetravalent metal element, the carrier density is excessive, and when it is used as a thin film transistor, there is a concern that the shutdown current becomes high. The content of the positive tetravalent metal element is preferably 0.01 atom% to 10 atom% of the positive trivalent metal element contained in the crystalline layer. When the content of the tetravalent metal element is defined by the mass, the content of the element of the tetravalent gold 19 200915579 is preferably 3% by mass or less, more preferably 2% by mass or less, based on the total mass of the crystalline layer. The best is 1% by mass or less. When the content of the tetravalent metal element is more than 3% by mass, there is a concern that the carrier density cannot be controlled to a low concentration. For example, the crystalline layer may include at least one selected from the group consisting of indium, zinc (positive divalent metal element), gallium (positive trivalent metal element), and tin (positive tetravalent metal element). Achieve high mobility. Further, the mobility of the crystal layer can be controlled by adjusting the partial pressure of oxygen in the ambient gas when the crystalline layer is formed and the content of H20 and H2 in the ambient gas. 10 The crystal layer is preferably a beryl-type crystal structure which is not copper. The crystal layer is a beryl structure, which improves the mobility of the pores. The beryl-type crystal structure can be confirmed by X-ray diffraction. The amorphous layer preferably contains at least one of indium, zinc, tin, and gallium, and more preferably contains indium, rhodium, and gallium. When the amorphous layer contains indium as large as 5S, the oxide semiconductor film having high mobility can be obtained even if it is amorphous. On the other hand, when the amorphous layer contains zinc, the crystallization temperature of the amorphous layer is increased, the mobility is not lowered, and the amorphous layer is stable. Further, when the amorphous layer contains gallium, the carrier density of the amorphous layer is easily reduced, and the performance as a semiconductor of the oxide semiconductor film can be stabilized. 20 A combination of elements comprising a crystalline layer and an amorphous layer, preferably wherein the crystalline layer comprises indium and zinc, and the amorphous layer comprises a combination of indium, rhodium and gallium. In the present invention, the conductivity of the crystalline layer is lower than that of the amorphous layer. If the conductivity of the crystalline layer is lower than the conductivity of the amorphous layer, the leakage current between the source and the drain can be reduced. 20 200915579 In the present invention, the carrier density of the crystalline layer is preferably lower than the carrier density of the amorphous layer. By making the carrier density of the crystalline layer lower than the carrier density of the amorphous layer, the leakage current between the source and the drain can be reduced. The specific resistance of the crystalline layer and the specific resistance of the amorphous layer are not limited, but when the specific resistance of the crystalline layer is higher than the specific resistance of the amorphous layer, the leakage current between the source and the drain can be reduced. Therefore, it is better. The specific resistance of the oxide semiconductor film is preferably from 1.01 to 108 Ω cm, more preferably from 1 to 107 Qcm, and particularly preferably from 101 to 106 Qcm. The specific resistance of the oxide semiconductor film can be measured by a four-probe method. When the specific resistance of the oxide semiconductor film is less than 10_1 Ω cm, electricity easily flows in the oxide semiconductor film, and the oxide semiconductor film fails to function as a semiconductor film. On the other hand, when the specific resistance of the oxide semiconductor film is more than 108 Ωcm, the oxide semiconductor film may not be subjected to a strong electric field, and thus the semiconductor function cannot be considered. The oxide semiconductor film has a carrier density of less than 1018 cm 3 , preferably less than 2 x 10 17 cm 3 , more preferably less than 10 17 cm 3 , and particularly preferably less than 2 x 10 16 cm 3 . When the carrier density of the oxide semiconductor film is 1018 cm_3 or more, there is a fear that the thin film transistor cannot be driven, or the power consumption becomes large even if the driving is normally turned on. The lower limit of the carrier density of the oxide semiconductor film is, for example, that the energy band gap of the 1014 cm " 3 ° oxide semiconductor film and the valence band is preferably 2 to 86 yen or more, preferably 3. (^¥ More preferably, the above is 3.:^¥ or more, especially preferably 3.5 eV or more. When the energy band gap is less than 2.8 eV, 21 200915579, when the visible light is irradiated, the electrons of the valence band of the oxide semiconductor film are excited. In addition, the upper limit of the energy band gap is, for example, 4.5 eV. The oxide 5 semiconductor film composed of the laminated crystalline layer and the amorphous layer of the present invention can be used. The first target is used to form an amorphous layer on the substrate, and the amorphous layer is heated by the substrate temperature to form a crystalline layer by using the substrate temperature to re-use the second target. A method of forming an amorphous layer on a crystalline layer. Specifically, it can be produced by using a target containing a predetermined one-component (for example, an indium element and a positive divalent metal element) at a high temperature basis. Forming an amorphous oxide semiconductor film, and performing heat treatment at the substrate temperature while forming the film to form a crystalline layer, and then using a target containing a predetermined component to form a non-form on the crystalline layer A method of a crystalline oxide semiconductor film (amorphous layer). In the present invention, an oxide semiconductor composed of a layer of crystals (4) and an m layer can be produced by the following method, which is a method for forming a (4) crystal layer on a substrate, and then using a second target in the first ( A method of forming a second amorphous layer on an amorphous layer and heat-treating the laminated body from which the i-th amorphous layer and the second amorphous layer are reduced. 2 Specifically, the use includes a predetermined component. The target material forms an amorphous oxide semiconductor film on the substrate, and an amorphous f oxide semiconductor film is formed on the amorphous 2 oxide semiconductor film by using other targets, so as to become a two-layer amorphous material having a different composition. The oxide semiconductor film is finally crystallized by heat treatment, and an oxide semiconductor film composed of a layered crystalline layer and an amorphous layer 22 200915579 can be produced. Further, the oxide semiconductor film will be described. In the manufacturing method, the same target can be continuously used. The substrate degree of J can be used to form a thin film of the amorphous oxide semiconductor film at the same time, and the method of simplifying the manufacturing process can be simplified. -^ 'A method of forming a naa shell layer by heating in an amorphous oxide semiconductor film, in addition to improving the mobility and crystallinity of the obtained crystal layer and reducing the film stress of the oxide semiconductor film, It is also possible to crystallization in a large area uniformly, and the carrier can be easily controlled. ίο In the present invention, since an oxide semiconductor film which is excellent in use can be used, it is preferable to use heat treatment after forming an amorphous oxide semiconductor film. An oxide semiconductor film is produced as a method of crystallizing a layer. For the film formation method, for example, a chemical film formation method such as a spray method, a dipping method, or a CVD method; or a sputtering method, a vacuum evaporation method, or an ion evaporation method can be used. A physical film forming method such as a pulsed 15 laser deposition method. Since the density of the carrier can be easily controlled and the film quality is improved, it is preferable to use a physical film forming method, and it is preferable to use a sputtering method having high productivity. The sputtering method used in the above may be, for example, DC sputtering, RF sputtering, AC de-bonding, ECR sputtering, facing 2 〇 target sputter, etc., by DC sputtering. Method, AC sputtering method, E The CR sputtering method and the target sputtering method are preferred. In addition, the de-plating method can also use co-spray, co-sputter and reactive ore. DC sputtering and AC sputtering It has high productivity and can easily reduce the concentration of the carrier 23 200915579. The ECR blue method and the opposite target can be used to prevent the interface degradation caused by film formation, suppress leakage current, and increase the on_off ratio. The characteristics of the semiconductor film are as follows: When the sputtering method is used as the film formation method, the film formation 5 conditions are specifically described. The distance between the target and the substrate (ST distance) during sputtering is usually 150 mm or less, preferably 110 mm or less. The best one is 8 〇mm or less. When the s-τ distance is a distance, the substrate is exposed to electric shock during sputtering. When the target contains a positive divalent metal element, positive divalent gold can be expected. It is the activation of 70. On the other hand, when the S-T distance is more than 150 mm, there is a concern that the film formation speed is lowered and it is not suitable for industrialization. The ultimate pressure is usually 5 xi 〇 -2 Pa or less, preferably 5 x l 〇 -3 Pa or less, preferably 5 x l 〇 -4 Pa or less, more preferably lxl 〇 -4 Pa or less, and particularly preferably 5 x l 〇 _ 5 Pa or less. § When the ultimate pressure is greater than 5 χΐ〇 2 卩 3, there is a large amount of hydrogen atoms supplied from cesium or the like in the ambient gas, and there is a concern that the mobility of the oxide semiconductor film is lowered. It is presumed that the crystal structure in the oxide semiconductor film is changed by the supplied hydrogen atoms. The partial pressure of oxygen in the ambient gas during sputtering is usually 4 〇 _ _ 3 p a or less, 20 is preferably 15xl 〇 3paa, preferably 7xl 〇 -3Pa or less, and particularly preferably 1 x lO_3Pa or less. When the oxygen partial pressure in the ring gas is larger than that, there is a concern that the mobility of the oxide semiconductor film is lowered and the carrier concentration is unstable. It can be presumed that the oxygen partial pressure in the ambient gas is too high (the oxygen concentration is too high) when the film is formed. 24 200915579 'The oxygen entering the vaporized semiconductor film becomes more scattered and the oxygen valley is easy to self-degenerate. The intermediate detachment destabilizes the oxide semiconductor film. In the case of money, the concentration of H20 and H2 in the ambient gas is usually 1.2 vol% or less, preferably 1. 〇V 〇 1 ° / q or less, preferably 0·lvol% or less, and particularly preferably 5 〇·〇lvol. %the following. When the concentration of H20 and H2 in the gas of the clothing is greater than ι.2ν〇1%, there is a concern that the mobility of the pores of the oxide semiconductor is lowered. At the time of cutting the money, in order to uniformly form the semiconductor film, a method of rotating the folding machine of the fixed substrate and operating the magnet to expand the etching range can be used. The substrate temperature at which the amorphous oxide semiconductor film is formed while crystallizing at the substrate temperature as the crystalline layer is usually 250 to 550. (:, 300~5〇〇°C is preferred. The preferred one is 320~40 (TC. When the substrate temperature is less than 250 C, the crystallinity of the crystalline layer is low, and the carrier density becomes high). On the one hand, when the substrate temperature is greater than 55 (TC, there is a problem that the manufacturing cost becomes high, or 15 substrates are deformed. The substrate temperature when used as a crystalline layer by heat treatment after forming an amorphous oxide semiconductor film Usually less than 25 〇. (:, preferably less than 200t 'better is 15〇t or less, more preferably less than lOOt, especially good is 50. (: below. When the substrate temperature is above 250t, due to Since the heat treatment effect after film formation cannot be sufficiently exhibited, there is a concern that it is difficult to control the carrier concentration and mobility of the oxide semiconductor film. The amorphous oxide semiconductor film is formed and then heat-treated to form a crystalline layer. In the method, the heating temperature after forming the amorphous oxide semiconductor film is usually 80 to 650 ° C, and is 180 to 450. (: preferably, preferably 25 200915579 230 to 400 ° C. When the heating temperature is less than 8 At 〇 ° C, there is insufficient crystallization or crystallization On the other hand, when the heating temperature is greater than 65 (TC, the substrate will be deformed. Also, the heat treatment time is usually 0.5 to 12000 minutes, preferably 1 to 1200 minutes and 5 minutes. The best is 2 to 600 minutes. When the heat treatment time is less than 〇.5 minutes, there is a doubt that crystallization is insufficient. On the other hand, when the heat treatment time is more than 12,000 minutes, a large-scale treatment device is required, which is harmful. In the above heat treatment, ozone treatment or other high-frequency energy such as high-frequency 10 waves, electromagnetic waves, ultraviolet rays, or plasma may be used. The heat treatment device used for crystallization is not particularly limited, and a lamp may be used. Annealing device (LA: Lamp Annealer), rapid annealing device (RTA: Rapid Thermal Annealer), or laser annealing device. The oxide semiconductor film of the present invention can be applied to various field effect type electric crystal 15 bodies. The semiconductor film is usually used in an n-type region, but can also be used in combination with various P-type semiconductors such as a p-type Si-based semiconductor, a p-type oxide semiconductor, or a p-type organic semiconductor. [Examples] 20 Example 1 (1) The raw material of the sputtering target is a powder of indium oxide, zinc oxide, or gallium oxide mixed into an atom *In/(In + Zn + Ga)=〇.4u&Zn/(In + Zn+Ga)=0.2l sub-ratio Ga/(In + Zn + Ga)=〇.4 , and the mixed powder is supplied to the wet ball 26 200915579 mill, The raw material fine powder was prepared by mixing and pulverizing for 72 hours. The obtained raw material fine powder was granulated and compression-molded into a size of 10 cm and a thickness of 5 mm to obtain a molded body. The formed body was placed in an oven and fired at 145 ° C ' for 12 hours to obtain a sputtering target. 5 A sputtering target η having an atomic ratio of In/(In + Zn) = 0.93 and an atomic ratio of Zn / (In + Zn) = 0.07 was obtained in the same manner as the target I. (2) Production of oxide semiconductor film The obtained sputtering target and 丨 were mounted on an RF magnetron sputtering film forming apparatus. The RF magnetron sputtering film forming apparatus is a one-inch film forming apparatus having a plurality of cathodes in the same chamber. First, an oxide film I having a film thickness of about 30 nm was formed on a glass substrate (cone 1737) by using the sputtering target I. When the element ratio of the oxide film I is measured by using an ICP emission spectrometer, it is substantially the same as the composition of the object I. 15 Next, an oxide film II having a film thickness of about 40 nm is formed on the oxide film I by using the sputtering target II under vacuum. When the element ratio of the oxide thin film II is measured by an ICP emission spectrometer, it is substantially the same as the composition of the target II. Further, the sputtering conditions of the targets I and II are as follows.
20 基板溫度：30°C20 substrate temperature: 30 ° C
極限壓力：lxlO_5Pa 環境氣體：Αγ/02=99·5%/〇·50/0 濺鍍壓力（全壓）：^xlO^Pa 投入電力：100W 27 200915579 於大氣中將所得之由玻璃基板、氧化物薄膜i及氧化物 薄膜II構成之積層體以300°c加熱2小時。使用穿透式電子顯 微鏡(TEM)觀察所得之積層體之截面時，於氧化物薄膜I並 未觀察到繞射像，且未確認為結晶質，於氧化物薄膜II中則 5 觀察到繞射像，並確認為結晶質。積層由此得到之氧化物 薄膜I及氧化物薄膜II所形成之積層體，確認為由非晶質層 及結晶質層構成之氧化物半導體膜。第7圖係前述氧化物半 導體膜之截面照片（倍率，40萬倍）。 又，藉由X線結晶構造解析確認所得之結晶質層係顯示 10 紅綠柱石型結晶構造的氧化物。 (3)氧化物半導體膜之評價 使用孔測定裝置（Resi Test8310，股份有限公司東洋 TECHNICA製）測定所得之氧化物半導體膜的載子濃度。結 果，氧化物半導體膜之載子濃度係9xl016cm·3。又，四探針 15 法測得之氧化物半導體膜的比電阻值係35000Ω cm。 另外，載子濃度之測定條件係如以下。 測定溫度：室溫P5°C)Limit pressure: lxlO_5Pa Ambient gas: Αγ/02=99·5%/〇·50/0 Sputtering pressure (full pressure): ^xlO^Pa Input power: 100W 27 200915579 In the atmosphere, the glass substrate will be oxidized. The laminate of the film i and the oxide film II was heated at 300 ° C for 2 hours. When the cross section of the obtained laminate was observed by a transmission electron microscope (TEM), no diffraction image was observed on the oxide film I, and no crystallinity was observed, and a diffraction image was observed in the oxide film II. And confirmed as crystalline. The laminate formed of the oxide thin film I and the oxide thin film II thus obtained was confirmed to be an oxide semiconductor film composed of an amorphous layer and a crystalline layer. Fig. 7 is a photograph of a cross section of the foregoing oxide semiconductor film (magnification, 400,000 times). Further, it was confirmed by X-ray crystal structure analysis that the obtained crystal layer showed an oxide of 10 beryl-type crystal structure. (3) Evaluation of oxide semiconductor film The carrier concentration of the obtained oxide semiconductor film was measured using a pore measuring apparatus (Resi Test 8310, manufactured by Toyo TECHNICA Co., Ltd.). As a result, the carrier concentration of the oxide semiconductor film was 9 x 1016 cm·3. Further, the specific resistance value of the oxide semiconductor film measured by the four-probe 15 method was 35,000 Ω cm. Further, the measurement conditions of the carrier concentration are as follows. Measuring temperature: room temperature P5 ° C)
測定磁場：0.5T 測定電流：HT12〜1(Γ4Α 20 測定模式：AC磁場孔測定 使用分光光度計測定所得之氧化物半導體膜的透明 性，確認波長400nm光線之光線透射率係85%，並具有優異 之透明性。 又，確認氧化物半導體膜之能量帶間隙為相當大之 28 200915579 3.6eV。 ⑷薄膜電晶體之製造 將1目於無驗坡璃基板上形成厚度150nm之膜，再使用 光刻法圖案成形作為閘極電極。接著，使用電漿化學氣相 5 ’儿積法(PECVD；^SiNx(x=4/3)形成厚度細⑽之膜，作為 間極、”邑緣膜。使用⑴中製造之目標物，與⑺同様地於 閘極絶緣膜上形成由積層非晶質層及結晶質層構成之氧化 物半^體膜。使用拆離(lift-off)以Pt(100nm)/Ti(10nm)作為 源極電極及沒極電極。如此，得到㈣㈣、之具有 ίο第1圖構造的薄膜電晶體。 (5)薄膜電晶體之評価 測定所得之薄膜電晶體的閾值電壓差△ Vth(=Vth(大 氣）Vth(真空)）。結果，所得之薄膜電晶體的閾值電壓差△ Vth係〇.2V。 15 於第8圖顯示大氣下及真空下dG.3Pa)之薄膜電晶體的 轉移特性。由第8圖可確認本發明之薄膜電晶體幾乎不會因 測定環境而改變半導體特性。 實施例2〜16 除了以表1及表2記載之組成作為目標物之組成以 20外’與實施例1同樣地製造目標物I及π。接著，使用所得之 目標物I及II，除了以表1及表2記載之值作為環境氣體的組 成、氧氣分壓、及氧化物薄膜I及II之膜厚以外，與實施例J 同樣地製造氧化物半導體膜及薄膜電晶體。與實施例i同樣 地5平價所得之氧化物半導體膜及薄骐電晶體。於表1及表2 29 200915579 顯不結果。 【表1】 實施 例1 實施 例2 實施 例3 實施 例4 實施 例5 實施 例6 實施 例7 實施 例8 氧化物 薄膜I (非晶質 層） 目標物 I之組 成 In 0.4 0.4 0.4 0.4 0.34 0.37 0.369 0.37 Zn 0.2 0.2 0.2 0.2 0.33 0.5 0.5 0.5 Ga 0.4 0.4 0.4 0.4 0.33 0.13 0.13 0.13 A1 Sn 0.001 環境氣 體(％) Ar 99.5 99.5 99.5 99.5 99.5 99.5 95 99.5 〇2 0.5 0.5 0.5 0.5 0.5 0.5 5 0.5 氧氣分壓 (xlO'3Pa) 2.5 2.5 2.5 2.5 2.5 2.5 25 2.5 膜厚(nm) 30 30 30 30 30 30 30 30 氧化物 薄膜II (結晶質 層） 目標物 II之組 成 In 0.93 0.93 0.95 0.98 0.93 0.93 0.929 0.93 Zn 0.07 0.07 0.05 0.02 0.07 0.07 0.07 0.06 Ga 0.01 Sn 0.001 Mg Cu Co Ni 環境氣 體(％) Ar 99.5 99.5 99.5 99.5 99.5 99.5 99 99.5 〇2 0.5 0.5 0.5 0.5 0.5 0.5 1 0.5 氧氣分壓 (xlO'3Pa) 2.5 2.5 2.5 2.5 2.5 2.5 5 2.5 膜厚(nm) 40 20 40 40 40 40 40 40 TFT特性 △ Vth(V) 0.2 0.4 0.3 0.4 0.2 0.2 0.2 0.2 移動度 (cm2/Vs) 11 14 12 13 13 16 19 14 30 200915579 【表2】 ----- 實施 例9 實施 例10 實施 例11 實施 例12 實施 例13 實施 例14 實施 例15 實施 例16 氧化物 薄膜I (非晶質 層） 目標物I 之組成 In 0.4 0.4 0.4 0.4 0.4 0.4 0.4 Zn 0.6 0.6 0.2 0.2 0.2 0.2 0.2 0.2 Ga 0.4 0.4 0.4 0.4 0.4 A1 0.4 Sn 0.4 環境氣 體(％) Ar 99.5 99.5 99.5 99.5 99.5 99.5 99.5 99.5 〇2 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 氧氣分壓 (xl〇'3Pa) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 膜厚(nm) 30 30 30 30 30 30 30 30 氧化物 薄膜II (結晶質 層） 目標物 II之組 成 In 0.93 0.93 0.93 0.98 0.98 0.98 0.98 0.93 Zn 0.07 0.07 0.07 0.05 Ga Sn Mg 0.02 0.02 Cu 0.02 Co 0.02 Ni 0.07 環境氣 體（％) ~~.— Ar 99.5 99.5 99.5 99.5 99.5 99.5 99.5 99.5 〇2 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 軋氣分壓 (xl〇_3Pa) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 膜厚(nm) 40 40 40 40 40 40 40 40 △ Vth(V) 0.2 0.6 0.2 0.2 0.2 0.2 0.2 0.3 i FT特性 移動度 (cm2/Vs) 23 0.8 8 10 9 9 9 10 比較例1〜3 矛、了以表3 sg*載之組成作為目標物I的組成以外，與實 施例1同様地製造目標物丨。接著，使用所得之目標物〗，以 5表3記載之厚度作為氧化物薄膜】之膜厚，除了未形成氧化 物薄獏II、及未進行加熱處理以外，與實施例i同樣地製造 氧化物半導體膜及薄膜電晶體。與實施例！同樣地評價所得 之僅由非晶質層構成的氧化物半導體膜。於表3顯示結果。 31 200915579 【表3】 比較例1 比較例2 比較例3 In 0.4 0.34 0.37 氧化物薄獏I (非晶質層） 目標物I 之組成 Zn 0.2 0.33 0.5 Ga 0.4 0.33 0.13 A1 Sn 膜厚(nm) 30 30 30 TFT特性 Γ Δ Vth(V) 45 40 40 L移動度(cm2/Vs) 11 13 14 _ 於第9圖顯示大氣下及真空下（1 〇_3pa)之比較例1薄膜 私日日體的轉移特性。由第9圖可確認比較例1薄膜電晶體會 因測疋％境而大幅改變半導體特性。 5 實施例17 使用電漿化學氣相沉積法(PECVD)將Si02於導電性石夕 (間極電極）形成厚度300nm之膜，以作為閘極絕緣 膜。使用替从 夏她例4中製造之目標物I及II，與實施例4同樣地 ^問極絕緣膜上形成由結晶質層及非晶質層構成之氧化物 10 半導體膜。伸用、 ^用拆離以厚度5〇nm之Au作為源極電極及沒極 電極。如此’得到W=50(^m、L=10(Vm之具有第10圖構造 的薄膜電晶體。 所句·之薄祺電晶體於大氣下之場效移動度係 12cm /VS、及大氣下之on-off比係106以上，並顯示常閉特 15性。又’所得之薄膜電晶體的輸出特性顯示清楚之夾止。 即使於真空下（1(r3Pa)，仍幾乎不會改變。 所得之薄膜電晶體的閾值電壓差ΔνΛ係0.4V，且良 好。 比較例4 20 較例1之目標物I，與比較例1同樣地於閘極 32 200915579 絕緣膜上形成僅由非晶質層構成之氧化物半導體膜以外， 與實施例17同樣地製造薄膜電晶體。 所得之薄膜電晶體於大氣下之場效移動度係 13cm2/Vs、及大氣下之on-off比係106以上，並顯示常閉特 5 性。又，所得之薄膜電晶體的輸出特性顯示清楚之夾止。 然而，該等半導體特性於真空下（10_3Pa)，場效移動度係 8cm2/Vs、及on-off比係104以上，並顯示常開特性。因此， 確認真空下之半導體特性劣於大氣下之特性。 又，所得之薄膜電晶體之閾值電壓差AVtli係35V，確 10 認受測定時之環境氣體影響很大。 實施例18 使用電漿化學氣相沉積法(PECVD)將Si02於導電性矽 基板上（閘極電極)形成厚度300nm之膜作為閘極絕緣膜。使 用拆離使厚度50nm之Au作為源極電極及汲極電極。使用實 15 施例5中製造之目標物I及II，與實施例5同樣地於閘極絕緣 膜、源極電極及汲極電極上形成由結晶質層及非晶質層構 成之氧化物半導體膜。如此，得到\ν=500μηι、ί=100μηι之 具有第11圖構造的薄膜電晶體。 所得之薄膜電晶體於大氣下之場效移動度係 20 4cm2/Vs、及大氣下之on-off比係105以上，並顯示常閉特 性。又，所得之薄膜電晶體的輸出特性顯示清楚之夾止。 該等半導體特性即使於真空下（l(T3Pa)，仍幾乎不會改變。 所得之薄膜電晶體的閾值電壓差AVtli係0.4V，且良 好。 33 200915579 比較例5 除了使用比較例2之目標物I，與比較例2同樣地於閘極 絕緣膜、源極電極及汲極電極上形成僅由非晶質層構成之 氧化物半導體膜以外，與實施例18同樣地製造薄膜電晶體。 5 所得之薄膜電晶體於大氣下之場效移動度係 3cm2/Vs、及大氣下之on-off比係105以上，並顯示常閉特 性。又，所得之薄膜電晶體的輸出特性顯示清楚之夾止。 然而，該等半導體特性於真空下（l〇_3Pa)，場效移動度係 2cm2/Vs、及on-off比係103以上，並顯示常開特性。因此， 10 確認真空下之半導體特性劣於大氣下之特性。 又，所得之薄膜電晶體的閾值電壓差ΔνΛ係40V，確 認受測定時環境氣體影響很大。 產業上利用之可能性 本發明之半導體薄膜可廣泛作為薄膜電晶體等場效型 15 電晶體中使用之半導體薄膜利用。 C闽式簡單說明3 第1圖係顯示本發明薄膜電晶體之一實施形態的概略 截面圖。 第2圖係顯示本發明薄膜電晶體之其他實施形態的概 20 略截面圖。 第3圖係顯示本發明薄膜電晶體之其他實施形態的概 略截面圖。 第4圖係顯示本發明薄膜電晶體之其他實施形態的概 略截面圖。 34 200915579 第5圖係顯示本發明薄膜電晶體之其他實施形態的概 略截面圖。 第6圖係顯示本發明薄膜電晶體之其他實施形態的概 略截面圖。 5 第7圖係實施例1中製造之氧化物半導體膜的截面照 片。 第8圖係顯示大氣下及真空下（10_3Pa)實施例1之薄膜 電晶體的轉移特性的圖。 第9圖係顯示大氣下及真空下（10_3Pa)比較例1之薄膜 10 電晶體的轉移特性的圖。 第10圖係實施例17中製作之薄膜電晶體的概略截面 圖。 第11圖係實施例18中製作之薄膜電晶體的概略截面 圖。 15 【主要元件符號說明】 1,2,3,4,5,6...薄膜電晶體 50…源vt亟電極 10…基板 52…沒極電極 20...閘極電極 60…通道部 30…閘極絕緣膜 70".保護膜 40,41…氧化物半導體膜 80...触刻中止層 42...非晶質層 90...層間絕緣膜 44…結晶質層 100·. 通孔 35Measurement magnetic field: 0.5T Measurement current: HT12 to 1 (Γ4Α 20 Measurement mode: AC magnetic field measurement: The transparency of the oxide semiconductor film was measured by a spectrophotometer, and it was confirmed that the light transmittance of light having a wavelength of 400 nm was 85%, and Excellent transparency. Also, it is confirmed that the energy band gap of the oxide semiconductor film is considerably large. 200915579 3.6eV. (4) Fabrication of thin film transistor A film having a thickness of 150 nm is formed on the substrate without a test, and light is used. The lithographic pattern was formed as a gate electrode. Next, a film having a thin thickness (10) was formed by a plasma chemical vapor phase 5' (PECVD; ^SiNx (x = 4/3)) as a memrist, "ruthenium film." Using the target object produced in (1), an oxide half film composed of a laminated amorphous layer and a crystalline layer is formed on the gate insulating film in the same manner as (7). Lift-off is used to Pt (100 nm). /Ti (10 nm) is used as the source electrode and the electrodeless electrode. Thus, (4) (4), the thin film transistor having the structure of Fig. 1 is obtained. (5) The threshold voltage difference of the thin film transistor obtained by the evaluation of the thin film transistor △ Vth (= Vth (atmosphere) Vth (vacuum As a result, the threshold voltage difference ΔVth of the obtained thin film transistor is 〇.2V. 15 The transfer characteristics of the thin film transistor of dG.3Pa under the atmosphere and under vacuum are shown in Fig. 8. It can be confirmed from Fig. 8. The thin film transistor of the present invention hardly changes the semiconductor characteristics due to the measurement environment. Examples 2 to 16 The target product was produced in the same manner as in Example 1 except that the composition shown in Tables 1 and 2 was used as the composition of the target. I and π. Next, using the obtained target materials I and II, the values shown in Tables 1 and 2 are used as the composition of the ambient gas, the oxygen partial pressure, and the film thicknesses of the oxide thin films I and II, and examples. J. An oxide semiconductor film and a thin film transistor were produced in the same manner. The oxide semiconductor film and the thin germanium transistor obtained by the same price as in Example i were shown in Table 1 and Table 2 29 200915579. [Table 1] Example 1 Example 2 Example 3 Example 4 Example 5 Example 6 Example 7 Example 8 Oxide film I (amorphous layer) Composition of target I In 0.4 0.4 0.4 0.4 0.34 0.37 0.369 0.37 Zn 0.2 0.2 0.2 0.2 0.33 0.5 0.5 0.5 Ga 0.4 0.4 0.4 0.4 0.33 0.13 0.13 0.13 A1 Sn 0.001 Ambient gas (%) Ar 99.5 99.5 99.5 99.5 99.5 99.5 95 99.5 〇2 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Oxygen partial pressure (xlO'3Pa) 2.5 2.5 2.5 2.5 2.5 2.5 25 2.5 Film thickness (nm) 30 30 30 30 30 30 30 30 Oxide film II (crystalline layer) Composition of target II In 0.93 0.93 0.95 0.98 0.93 0.93 0.929 0.93 Zn 0.07 0.07 0.05 0.02 0.07 0.07 0.07 0.06 Ga 0.01 Sn 0.001 Mg Cu Co Ni Ambient gas (%) Ar 99.5 99.5 99.5 99.5 99.5 99.5 99 99.5 〇2 0.5 0.5 0.5 0.5 0.5 0.5 1 0.5 Oxygen partial pressure (xlO'3Pa) 2.5 2.5 2.5 2.5 2.5 2.5 5 2.5 Film thickness (nm) 40 20 40 40 40 40 40 40 TFT characteristics △ Vth(V) 0.2 0.4 0.3 0.4 0.2 0.2 0.2 0.2 Mobility (cm2/Vs) 11 14 12 13 13 16 19 14 30 200915579 [Table 2] ----- Implementation Example 9 Example 10 Example 11 Example 12 Example 13 Example 14 Example 15 Example 16 Oxide film I (amorphous layer) Composition of target I In 0.4 0.4 0.4 0.4 0.4 0.4 0.4 Zn 0 .6 0.6 0.2 0.2 0.2 0.2 0.2 0.2 Ga 0.4 0.4 0.4 0.4 0.4 A1 0.4 Sn 0.4 Ambient gas (%) Ar 99.5 99.5 99.5 99.5 99.5 99.5 99.5 99.5 〇2 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Oxygen partial pressure (xl〇' 3Pa) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Film thickness (nm) 30 30 30 30 30 30 30 30 Oxide film II (crystal layer) Composition of target II In 0.93 0.93 0.93 0.98 0.98 0.98 0.98 0.93 Zn 0.07 0.07 0.07 0.05 Ga Sn Mg 0.02 0.02 Cu 0.02 Co 0.02 Ni 0.07 Ambient gas (%) ~~.— Ar 99.5 99.5 99.5 99.5 99.5 99.5 99.5 99.5 〇2 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Rolling partial pressure (xl〇_3Pa) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Film thickness (nm) 40 40 40 40 40 40 40 40 △ Vth(V) 0.2 0.6 0.2 0.2 0.2 0.2 0.2 0.3 i FT characteristic mobility (cm2/Vs) 23 0.8 8 10 9 9 9 10 Comparative Examples 1 to 3 Spears were prepared in the same manner as in Example 1 except that the composition of Table 3 sg* was used as the composition of the target I. Next, using the obtained target material, the thickness of the oxide film described in Table 5 was used as the film thickness of the oxide film, and an oxide was produced in the same manner as in Example i except that the oxide thin layer II was not formed and the heat treatment was not performed. Semiconductor film and thin film transistor. With the embodiment! The obtained oxide semiconductor film composed only of the amorphous layer was evaluated in the same manner. The results are shown in Table 3. 31 200915579 [Table 3] Comparative Example 1 Comparative Example 2 Comparative Example 3 In 0.4 0.34 0.37 Oxide Thin I (Amorphous Layer) Composition of Target I Zn 0.2 0.33 0.5 Ga 0.4 0.33 0.13 A1 Sn Film Thickness (nm) 30 30 30 TFT characteristics Δ Δ Vth(V) 45 40 40 L mobility (cm2/Vs) 11 13 14 _ Figure 9 shows the film of the comparative example 1 in the atmosphere and under vacuum (1 〇 _3pa) Transfer characteristics of the body. From Fig. 9, it was confirmed that the thin film transistor of Comparative Example 1 greatly changed the semiconductor characteristics due to the measurement of the % environment. 5 Example 17 SiO 2 was formed into a film having a thickness of 300 nm on a conductive stone (interelectrode electrode) by plasma chemical vapor deposition (PECVD) to serve as a gate insulating film. In the same manner as in the fourth embodiment, an oxide 10 semiconductor film composed of a crystalline layer and an amorphous layer was formed on the electrode insulating film in the same manner as in the fourth embodiment. For the extension, the Au with a thickness of 5 〇 nm is used as the source electrode and the electrodeless electrode. Thus, 'w=50 (^m, L=10 (Vm) has a thin film transistor with the structure of Fig. 10. The field effect mobility of the thin 祺 transistor in the atmosphere is 12 cm / VS, and under the atmosphere. The on-off ratio is above 106, and shows the normally closed characteristic. Moreover, the output characteristics of the obtained thin film transistor show a clear pinch. Even under vacuum (1 (r3Pa), it hardly changes. The threshold voltage difference Δν 薄膜 of the thin film transistor is 0.4 V, which is good. Comparative Example 4 20 The target I of Comparative Example 1 is formed of only an amorphous layer on the insulating film of the gate 32 200915579 as in Comparative Example 1. A thin film transistor was produced in the same manner as in Example 17 except for the oxide semiconductor film. The field effect mobility of the obtained thin film transistor in the atmosphere was 13 cm 2 /Vs, and the on-off ratio of the atmosphere was 106 or more, and was displayed. Normally closed, the output characteristics of the obtained thin film transistor show a clear pinch. However, these semiconductor characteristics are under vacuum (10_3Pa), the field effect mobility is 8cm2/Vs, and the on-off ratio is Above 104, and shows the normally open characteristic. Therefore, confirm the semiconductor under vacuum Inferior to the characteristics of the atmosphere. Moreover, the threshold voltage difference of the obtained thin film transistor AVtli is 35V, and it is confirmed that the ambient gas has a great influence on the measurement. Example 18 Using plasma chemical vapor deposition (PECVD) A film having a thickness of 300 nm was formed on the conductive germanium substrate (gate electrode) as a gate insulating film, and Au having a thickness of 50 nm was used as a source electrode and a drain electrode by using detachment, and the target manufactured in Example 5 was used. In the materials I and II, an oxide semiconductor film composed of a crystalline layer and an amorphous layer was formed on the gate insulating film, the source electrode, and the drain electrode in the same manner as in Example 5. Thus, ?ν=500μηι, ί=100μηι has a thin film transistor having the structure of Fig. 11. The resulting thin film transistor has a field-effect mobility of 20 4 cm 2 /Vs under atmospheric conditions and an on-off ratio of 105 or more in the atmosphere, and exhibits normally closed characteristics. Moreover, the output characteristics of the obtained thin film transistor show a clear pinch. The semiconductor characteristics are hardly changed even under vacuum (l(T3Pa). The threshold voltage difference of the obtained thin film transistor is AVtli 0.4V. And good. 33 20 0915579 Comparative Example 5 In addition to the target material I of Comparative Example 2, an oxide semiconductor film composed of only an amorphous layer was formed on the gate insulating film, the source electrode, and the gate electrode in the same manner as in Comparative Example 2, and In the same manner as in Example 18, a thin film transistor was produced in the same manner. 5 The field effect mobility of the obtained thin film transistor in the atmosphere was 3 cm 2 /Vs, and the on-off ratio of the atmosphere was 105 or more, and the normally closed characteristic was exhibited. The output characteristics of the thin film transistor show a clear pinch. However, these semiconductor characteristics are under vacuum (10 Å to 3 Pa), the field effect mobility is 2 cm 2 /Vs, and the on-off ratio is 103 or more, and the normally-on characteristics are exhibited. Therefore, 10 confirms that the semiconductor characteristics under vacuum are inferior to those in the atmosphere. Further, the threshold voltage difference Δν 所得 of the obtained thin film transistor was 40 V, and it was confirmed that the influence of the ambient gas was large at the time of measurement. Industrial Applicability The semiconductor film of the present invention can be widely used as a semiconductor film used in a field effect type 15 transistor such as a thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing an embodiment of a thin film transistor of the present invention. Fig. 2 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. Fig. 3 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. Fig. 4 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. 34 200915579 Fig. 5 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. Fig. 6 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. 5 Fig. 7 is a cross-sectional photograph of the oxide semiconductor film produced in Example 1. Fig. 8 is a graph showing the transfer characteristics of the thin film transistor of Example 1 under atmosphere and under vacuum (10_3 Pa). Fig. 9 is a graph showing the transfer characteristics of the film 10 transistor of Comparative Example 1 under atmosphere and under vacuum (10_3 Pa). Fig. 10 is a schematic cross-sectional view showing a thin film transistor produced in Example 17. Fig. 11 is a schematic cross-sectional view showing a thin film transistor produced in Example 18. 15 [Description of main component symbols] 1, 2, 3, 4, 5, 6... Thin film transistor 50... Source vt 亟 electrode 10... Substrate 52... No-electrode electrode 20... Gate electrode 60... Channel portion 30 ...gate insulating film 70" protective film 40, 41... oxide semiconductor film 80...etch stop layer 42...amorphous layer 90...interlayer insulating film 44...crystal layer 100·. Hole 35