JP2010267705A - Semiconductor memory cell and manufacturing method thereof - Google Patents

Abstract

A semiconductor memory cell having excellent switching characteristics and a small cell size is provided.
A ferroelectric device includes a memory element composed of a MFSFET whose gate insulating film is composed of a ferroelectric film, and a selective switching element composed of a MISFET whose gate insulating film is composed of a paraelectric film. The film 4 and the paraelectric film 9 are laminated via the amorphous semiconductor film 5, the first gate electrode 3 of the MFSFET 21 is formed on the ferroelectric film 4 side, and the paraelectric film 9 side is formed. A second gate electrode 10 of the MISFET is formed. The amorphous semiconductor film 5 constitutes a common channel layer for the MFSFET 21 and the MISFET 22, and a source electrode 6 and a drain electrode 8 common to the MFSFET 21 and the MISFET 22 are formed on the main surface of the amorphous semiconductor film 5.
[Selection] Figure 10

Description

  The present invention relates to a semiconductor memory cell comprising a field effect transistor having a gate insulating film made of a ferroelectric film.

  There are two types of nonvolatile memories using ferroelectrics: a capacitor type and a field effect transistor (FET) type in which a gate insulating film is formed of a ferroelectric film.

  The capacitor type has a structure similar to that of a dynamic random access memory (DRAM), and holds a charge in a ferroelectric capacitor, and distinguishes between 0 and 1 states of data depending on the polarization direction of the ferroelectric. When data is read, the stored data is destroyed, so that a data rewrite operation is required. For this reason, the polarization is inverted every time reading is performed, and polarization inversion fatigue becomes a problem. In this structure, since the polarization charge is read by the sense amplifier, a charge amount (typically 100 fC) that is greater than the detection limit of the sense amplifier is required. A ferroelectric has a polarization charge per area inherent to the material, and even when the memory cell is miniaturized, the electrode area needs to have a certain size as long as the same material is used. Therefore, it is difficult to reduce the capacitor size in proportion to the miniaturization of the process rule, which is not suitable for increasing the capacity.

  On the other hand, FET-type ferroelectric memory (MFSFET: Metal-Ferroelectric-Semiconductor FET) reads data by detecting the conduction state of the channel that changes depending on the direction of polarization of the ferroelectric film. Data can be read out. Further, the output voltage amplitude can be increased by the amplification action of the FET, and miniaturization depending on the scaling law is possible. Therefore, it can be remarkably miniaturized as compared with the capacitor type.

  By the way, in a memory cell array in which FET type ferroelectric memories are arranged in a matrix, binary data is written into the ferroelectric memory by using a gate electrode connected to the word line of the selected memory cell, a source This is done by applying a voltage pulse between the source electrodes connected to the line. However, at that time, a voltage is also applied to the non-access target memory cell connected to the word line and the source line of the selected memory cell, so that erroneous data writing occurs. For this reason, in general, a selection switch element made of, for example, a MISFET (Metal-Insulator-Semiconductor FET) is inserted between the word line and the gate electrode and / or between the source line and the source electrode to prevent erroneous writing. ing. With such a configuration, random access to each memory cell becomes possible (see, for example, Patent Document 1).

  However, when the MISFETs that are the selection switch elements are arranged in a plane on the MFSFET that is the memory element, at least a region that electrically isolates the gate electrodes of these FETs is required, which increases the cell size. There is a problem.

In response to such a problem, the applicant of the present application has proposed a semiconductor memory cell having a new structure with a small cell size (Patent Document 2). The semiconductor memory cell of this new structure is composed of a ferroelectric film that forms the gate insulating film of the MFSFET that is a memory element, and a paraelectric film that forms the gate insulating film of the MISFET that is a selective switching element. The semiconductor film is used as a common channel layer for the MFSFET and the MISFET. With such a configuration, the first gate electrode of the MFSFET that forms the memory element and the second gate electrode of the MISFET that forms the selective switching element can be arranged close to each other in plan view, thereby reducing the cell size. Can do. Ideally, the cell size can be reduced to 6F ² (F is the minimum processing dimension).

Japanese Patent Laid-Open No. 5-205487 JP 2008-263019 A

  In the semiconductor memory cell disclosed in Patent Document 2, a first gate electrode of an MFSFET is usually formed on a substrate, and then a ferroelectric film and a semiconductor film are stacked on the substrate. It is manufactured by forming a paraelectric film after forming the drain electrode.

  By the way, considering connection with peripheral circuits (decoders, column amplifiers, etc.) for driving the memory cells, these memory cells are formed on a silicon substrate on which a CMOS (Complementary Metal Oxide Semiconductor) device can be easily formed. It is desirable. Moreover, if a silicon substrate can be used, it will also lead to cost reduction.

  However, it is not easy to deposit an oxide thin film such as a ferroelectric film or a semiconductor film, which is a constituent element of a semiconductor memory cell, on a silicon substrate (or a silicon oxide film formed on the silicon substrate) with good crystallinity. Therefore, there is a problem that an FET element with good switching characteristics cannot be easily obtained.

  The present invention has been made in view of such problems, and a main object thereof is to provide a semiconductor memory cell having excellent switching characteristics and a small cell size.

  In order to solve the above-described problems, the present invention provides a ferroelectric film that forms a gate insulating film of a MFSFET that is a memory element, and a paraelectric film that forms a gate insulating film of a MISFET that is a selective switching element. In a semiconductor memory cell which is stacked via a semiconductor film and the semiconductor film is a common channel layer for MFSFET and MISFET, a configuration using an amorphous semiconductor film as the semiconductor film is employed.

  A semiconductor memory cell according to one aspect of the present invention includes a memory element including a first field effect transistor having a gate insulating film formed of a ferroelectric film, and a second element having a gate insulating film formed of a paraelectric film. The ferroelectric film and the paraelectric film are stacked via an amorphous semiconductor film, and the first field effect transistor of the first field effect transistor is provided on the ferroelectric film side. The second gate electrode of the second field effect transistor is formed on the paraelectric film side, and the amorphous semiconductor film is formed of the first field effect transistor and the second field effect transistor. And a common source electrode for the first field effect transistor and the second field effect transistor on the main surface of the amorphous semiconductor film. Fine drain electrode are formed.

  With such a configuration, since the surface of the amorphous semiconductor film becomes flat, a selective switching element (second field effect transistor) having excellent switching characteristics can be obtained. In addition, even when the semiconductor film is made of a material having spontaneous polarization, the spontaneous polarization can be made zero because the semiconductor film is not crystallized. For this reason, carriers are not spontaneously generated at the interface of the amorphous semiconductor film constituting the channel layer, and a selective switching element having no variation in threshold voltage can be obtained.

  In another aspect of the present invention, the amorphous semiconductor film is preferably made of a metal oxide. As a result, when the ferroelectric film and the paraelectric film constituting the gate insulating film of the semiconductor memory cell are made of a metal oxide, the dielectric film and the amorphous semiconductor film constituting the channel layer are made of the same oxide. Due to the bonding, a reaction layer is hardly formed at the interface. Therefore, a good interface can be obtained, and a semiconductor memory element (first field effect transistor) and a selective switching element (second field effect transistor) having excellent switching characteristics can be obtained.

  In another aspect of the present invention, the amorphous semiconductor film is preferably made of a metal oxide containing at least one of indium (In), gallium (Ga), and zinc (Zn). Accordingly, a channel structure with high mobility can be obtained even though the semiconductor film is amorphous. As a result, the on-resistance of the semiconductor memory element and the selective switching element is increased, so that the difference in output voltage during data reading is increased, and the S / N ratio can be improved. Here, the amorphous semiconductor film is preferably made of an In—Ga—Zn—O-based metal oxide. Thereby, the mobility equivalent to that of the polycrystalline ZnO film can be obtained.

In another aspect of the present invention, the amorphous semiconductor film preferably has a carrier concentration of 10 ¹⁸ cm ⁻³ or less. Thereby, the off-state current of the semiconductor memory element and the selective switching element can be reduced. Therefore, the difference in output voltage at the time of data reading becomes large, and the S / N ratio can be improved.

  According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor memory cell, comprising: forming a first gate electrode on a substrate; and forming a ferroelectric film on the substrate so as to cover the first gate electrode. A step (b), a step (c) of forming an amorphous semiconductor film on the ferroelectric film, a step (d) of forming a source electrode and a drain electrode on the amorphous semiconductor film, and a source electrode and a drain A step (e) of forming a paraelectric film on the amorphous semiconductor film so as to cover the electrode, and a step (f) of forming a second gate electrode on the paraelectric film are included.

  By such a method, the semiconductor memory cell having a small cell size can be easily manufactured.

  In another aspect of the present invention, the method further includes a step of smoothing the surface of the ferroelectric film after the step (b) and before the step (c). By such a method, even when the ferroelectric film is formed as a film having a large surface undulation (for example, a polycrystalline film), the interface with the amorphous oxide semiconductor film can be sharpened. Since the scattering of conduction electrons is suppressed at the steep interface, the on-current of the semiconductor memory element (first field effect transistor) can be increased, thereby increasing the difference in output voltage when reading data. , S / N ratio can be improved.

  According to the present invention, an amorphous semiconductor film is used as a semiconductor film constituting a common channel layer of a semiconductor memory element (MFSFET) and a selective switching element (MISFET), thereby providing a semiconductor memory cell having excellent switching characteristics and a small cell size. Can be realized.

2A and 2B are diagrams illustrating a configuration of a semiconductor memory cell disclosed in Patent Document 2, in which FIG. 3A is a cross-sectional view thereof, and FIG. (A)-(d) is sectional drawing which showed the preparation procedures of MFSFET in a semiconductor memory cell. It is the graph which showed the drain current-gate electrode characteristic of MFSFET in a semiconductor memory cell. (A)-(c) is sectional drawing which showed the preparation procedures of MISFET in a semiconductor memory cell. It is the graph which showed the drain current-gate electrode characteristic of MISFET in a semiconductor memory cell. It is sectional drawing of the semiconductor memory cell which showed the measurement site | part of the surface roughness of a ZnO film | membrane. (A)-(d) is the AFM image which showed the measurement result of the surface roughness of a ZnO film | membrane. (A) And (b) is the diffraction image which showed the result of having measured the crystallinity of the PZT film | membrane and the ZnO film | membrane by EBSD. (A) is a crystal schematic diagram of ZnO, (b) is a cross-sectional view of a semiconductor memory cell, and (c) is an enlarged cross-sectional view of a region where a MISFET is formed. (A) is sectional drawing which showed the structure of the semiconductor memory cell in one Embodiment of this invention, (b) is the equivalent circuit schematic. (A)-(d) is sectional drawing which showed the manufacturing process of the semiconductor memory cell in one Embodiment of this invention. (A)-(c) is sectional drawing which showed the manufacturing process of the semiconductor memory cell in one Embodiment of this invention. (A)-(d) is an AFM image which showed the measurement result of the surface roughness of the IGZO film | membrane in one Embodiment of this invention. (A) And (b) is the diffraction image which showed the result of having measured the crystallinity of the PZT film | membrane and IGZO film | membrane in one Embodiment of this invention by EBSD. It is the graph which showed the drain current-gate electrode characteristic of MISFET in one Embodiment of this invention. (A) is sectional drawing which showed the structure of the semiconductor memory cell in other embodiment of this invention, (b) is the equivalent circuit schematic. (A) is sectional drawing which showed the structure of the semiconductor memory cell in other embodiment of this invention, (b) is the equivalent circuit schematic. It is a table | surface explaining operation | movement of the semiconductor memory cell in this embodiment. (A) And (b) is sectional drawing explaining operation | movement of the semiconductor memory cell in this embodiment. 1 is a circuit diagram showing a configuration in which semiconductor memory cells according to an embodiment are arranged in an array.

  Before describing the embodiments of the present invention, the background to the idea of the present invention will be described.

  1A and 1B are diagrams showing a configuration of a semiconductor memory cell 120 disclosed in Patent Document 2 by the applicant of the present application. FIG. 1A is a cross-sectional view thereof, and FIG. 1B is an equivalent circuit diagram thereof. is there.

  As shown in FIG. 1A, a ferroelectric film 104 and a paraelectric film 109 are stacked on a substrate 101 with a semiconductor film 105 interposed therebetween. The MFSFET gate electrode 103 is formed, and the MISFET gate electrode 110 is formed on the paraelectric film 109 side. The semiconductor film 105 forms a channel layer common to the MFSFET and the MISFET, and the source electrode 106, the drain electrode 108, and the intermediate electrode 107 common to the MFSFET and the MISFET are formed on the semiconductor film 105. Yes.

  That is, the semiconductor memory cell 120 has a structure in which a bottom gate type MFSFET (memory element) and a top gate type MISFET (selective switching element) are stacked as shown in FIG. Specifically, as shown in FIG. 1B, the MFSFET 121 and the MISFET 122 are connected in series.

  Data is written to the memory element by applying a predetermined voltage to the gate electrode 110 of the MISFET 122 to turn on the selective switching element and applying a predetermined voltage between the gate electrode 103 and the drain electrode 108 of the MFSFET 121. Thus, an electric field is generated in the ferroelectric film 104, thereby changing the polarization state of the ferroelectric film 104.

  To read data written in the memory element, a predetermined voltage is applied to the gate electrode 110 of the MISFET 122 to turn on the selective switching element, and a predetermined voltage is applied between the source electrode 106 and the drain electrode 108. The detection is performed by detecting the current flowing through the channel layer (semiconductor film 105) in accordance with the polarization state of the ferroelectric film 104.

  The inventors of the present invention fabricated a semiconductor memory cell having the above structure on a silicon substrate, and evaluated the characteristics of the MFSFET 121 and the MISFET 122.

  First, in order to evaluate the characteristics of the MFSFET 121, an MFSFET was fabricated on a silicon substrate by the procedure shown in FIGS.

As shown in FIG. 2A, after forming a silicon oxide film (SiO ₂ ) 102 on a silicon substrate 101, a gate electrode 103 made of a laminated film of platinum and strontium ruthenate (SRO) was formed.

Next, as shown in FIG. 2B, a gate insulating film (ferroelectric film) made of a titanium / lead zirconate (Pb (Zr, Ti) O ₃ , hereinafter referred to as PZT) film on the SiO ₂ film 102. 104 was deposited. At this time, the PZT film 104 at a position overlapping the gate electrode 103 in a plane was unidirectionally oriented in the (111) direction, but the surface roughness (RMS) was as large as about 10 nm. Therefore, the surface of the PZT film 104 was smoothed by chemical mechanical polishing, and the surface roughness (RMS) was set to about 0.6 nm at the atomic layer level.

  Next, as shown in FIG. 2C, a semiconductor film 105 made of a ZnO film having a thickness of 30 nm was deposited on the PZT film 104. At this time, the ZnO film 105 at a position overlapping the gate electrode 103 in a plane was unidirectionally oriented in the (0001) direction.

  Next, a source electrode 106, an intermediate electrode 107, and a drain electrode 108 made of a laminated film of platinum and titanium were formed on the ZnO film 105 by a lift-off method, and an MFSFET was manufactured.

  In order to evaluate the characteristics of the fabricated MFSFET, the voltage of the gate electrode 103 is changed from −10 V to +10 V with the source electrode 106 grounded and a voltage of 0.1 V applied to the intermediate electrode (corresponding to the drain electrode) 107. The drain current was measured by sweeping.

  FIG. 3 is a graph showing drain current-gate electrode characteristics. The drain current draws a hysteresis loop in a counterclockwise direction with respect to the gate voltage, and is greatly modulated according to the reversal of the spontaneous polarization of the ferroelectric. Furthermore, the on / off ratio of the channel when the gate electrode 103 was 0 V was 5 digits or more. This is a characteristic that can clearly distinguish the polarization state written in the ferroelectric gate insulating film, and it was confirmed that the MFSFET formed on the silicon substrate has sufficient characteristics as a memory element.

  Next, in order to evaluate the characteristics of the MISFET 122, the MFSFET 121 was fabricated, and then the MISFET 122 was fabricated according to the procedure shown in FIGS. 4 (a) to 4 (c).

  As shown in FIG. 4A, a gate insulating film (paraelectric film) 109 made of a silicon nitride film (SiNx) was formed on the semiconductor film 105. Thereafter, as shown in FIG. 4B, a gate electrode 110 made of a laminated film of gold and titanium was formed on the SiNx film 109 by a lift-off method. Further, as shown in FIG. 4C, electrodes 111a to 111c that are in contact with the source electrode 106, the intermediate electrode 107, and the drain electrode 108 were formed to manufacture a MISFET.

  In order to evaluate the characteristics of the manufactured MISFET, the voltage of the gate electrode 103 is changed from −10 V to +10 V with the intermediate electrode (corresponding to the source electrode) 107 grounded and a voltage of 0.1 V applied to the drain electrode 108. The drain current was measured by sweeping.

  FIG. 5 is a graph showing the drain current-gate electrode characteristics. The drain current was modulated only by about two digits with respect to the gate voltage, and the threshold value was also shifted to the negative bias side. Furthermore, although the gate insulating film 109 is a paraelectric, the drain current shows a hysteresis history. That is, it was found that the manufactured MISFET had insufficient characteristics as a selective switching element.

  As a result of further examination of the reason why the switching characteristics of the manufactured MISFET are not excellent, the present inventors have obtained the following knowledge.

  First, the surface roughness of the ZnO film 105 constituting the channel was evaluated. FIG. 6 is a diagram showing the measurement site of the surface roughness. In the region A that overlaps the gate electrode 103 of the MFSFET and the region B that overlaps the gate electrode 110 of the MISFET, The surface roughness of the ZnO film 105 at the interface X with the film 105 and at the interface Y between the ZnO film 105 and the SiNx film 109 was measured using an AFM (Atomic Force Microscope).

  FIG. 7 is an AFM image showing the result. At the interface X, the surface roughness (RMS) of the regions A and B was as small as 0.6 nm (FIGS. 7C and 7D). In the interface Y, the surface roughness (RMS) is 1.8 nm (see FIG. 7A) in the region A, and the surface roughness (RMS) is 1.3 nm in the region B (FIG. 7B). It was great. The reason why the surface roughness is small at the interface X is that the surface of the PZT film 104 is polished. On the other hand, the surface roughness at the interface Y is large because the ZnO film 105 formed on the polycrystalline PZT film 104 grows in polycrystal and the surface roughness due to the crystal grains is generated. This is presumably one of the reasons why the switching characteristics of the MISFET were not excellent.

  Next, the crystallinity of the ZnO film 105 was evaluated using electron beam backscatter diffraction (EBSD). 8A and 8B are diffraction images showing the results, FIG. 8A is a diffraction image in the region A and the region B of the PZT film 104, and FIG. 8B is a ZnO film. It is the diffraction image in 105 area | region A and area | region B. FIG.

In the region A, the PZT film 104 was single-oriented in the (111) direction, the ZnO film 105 was single-oriented in the (0001) direction, and the crystal grain size was 150 nm to 250 nm. On the other hand, in the region B, a diffraction image was not obtained, and the PZT film 104 and the ZnO film 105 were amorphous or microcrystalline. This is because the crystallinity of platinum constituting the gate electrode 103 of the MFSFET is good, and the PZT film 104 and the ZnO film 105 deposited thereon are crystallized, whereas in the region without the gate electrode 103, the base is This is probably because the amorphous SiO ₂ film 102 was difficult to crystallize. If the ZnO film 105 is insufficiently crystallized, oxygen vacancies are easily formed, and the carrier concentration becomes high. If the carrier concentration is high, the carrier cannot be freely modulated, so it is presumed that the switching characteristics are not excellent in the region B where the MISFET is formed.

  Next, spontaneous polarization, which is a property unique to the ZnO film 105, was examined. 9A is a schematic diagram of ZnO crystal, FIG. 9B is a cross-sectional view of a semiconductor memory cell, and FIG. 9C is an enlarged cross-sectional view of a region where a MISFET is formed.

As shown in FIG. 9A, since ZnO has a spontaneous polarization Ps with a magnitude of 5.5 μC / cm ^{2 in} the [0001] direction, the surface of the ZnO film 105 has 3 × 10 ¹³ / cm. ^Two carriers are stored. Therefore, as shown in FIG. 9C, since the spontaneous polarization of the ZnO film 105 formed with the (0001) orientation on the PZT film 104 faces the SiNx film 109 side, no voltage is applied to the gate electrode 110. Even in this state, it is considered that electrons are stored at the interface between the ZnO film 105 and the SiNx film 109. This is presumed to be the reason why the threshold value of the MISFET has shifted to the negative bias side.

  As a result of various studies based on the above findings, the present inventors have made the semiconductor film 105 constituting the channel an amorphous semiconductor material that has few irregularities and hardly generates residual carriers even when crystallinity is poor. As a result, it has been found that the factors that deteriorate the switching characteristics of the MISFET can be eliminated, and the present invention has been conceived.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following embodiment. Moreover, it can change suitably in the range which does not deviate from the range which has the effect of this invention. Furthermore, combinations with other embodiments are possible.

  FIG. 10A is a cross-sectional view schematically showing the configuration of the semiconductor memory cell 20 in one embodiment of the present invention, and FIG. 10B is an equivalent circuit diagram thereof.

  As shown in FIGS. 10A and 10B, the semiconductor memory cell 20 includes a memory element composed of a first field effect transistor (MFSFET) 21 having a gate insulating film made of a ferroelectric film 4, and a gate. And a selective switching element including a second field effect transistor (MISFET) 22 having an insulating film made of a paraelectric film 9. The ferroelectric film 4 and the paraelectric film 9 are laminated via the amorphous semiconductor film 5, and the first gate electrode 3 of the MFSFET 21 is formed on the ferroelectric film 4 side. On the film 9 side, the second gate electrode 10 of the MISFET 22 is formed. Here, the amorphous semiconductor film 5 constitutes a common channel layer of the MFSFET 21 and the MISFET 22. A source electrode 6 and a drain electrode 8 common to the MFSFET 21 and the MISFET 22 are formed on the main surface of the amorphous semiconductor film 5.

  That is, the semiconductor memory cell 20 in the present embodiment has a structure in which a bottom gate type MFSFET (memory element) 21 and a top gate type MISFET (selective switching element) 22 are stacked. The MFSFET 21 and the MISFET 22 are connected in series.

  Here, the data is written into the memory element 21 by applying a predetermined voltage to the gate electrode 10 of the MISFET 22 to turn on the selective switching element 22, and then a predetermined voltage between the gate electrode 3 and the drain electrode 8 of the MFSFET 21. By applying a voltage, an electric field is generated in the ferroelectric film 4, thereby changing the polarization state of the ferroelectric film 4.

  To read data written in the memory element 21, a predetermined voltage is applied to the gate electrode 10 of the MISFET 22 to turn on the selective switching element, and a predetermined voltage is applied between the source electrode 6 and the drain electrode 8. The detection is performed by detecting the current flowing through the channel layer (semiconductor film 5) in accordance with the polarization state of the ferroelectric film 4.

  Next, with reference to FIGS. 11A to 11D and FIGS. 12A to 12C, a method for manufacturing the semiconductor memory cell 20 in the present embodiment will be described.

First, as shown in FIG. 11A, after a silicon oxide film (SiO ₂ ) 2 is formed on a silicon substrate 1, a first gate electrode 3 made of a laminated film of platinum and strontium ruthenate (SRO) is formed. Form.

Next, as shown in FIG. 11B, a gate insulating film (ferroelectric film) made of a titanium / lead zirconate (Pb (Zr, Ti) O ₃ , hereinafter referred to as PZT) film on the SiO ₂ film 2. 4 is deposited. At this time, the PZT film 4 at a location overlapping the first gate electrode 3 in a plane is unidirectionally oriented in the (111) direction.

  Next, after smoothing the surface of the PZT film 4 by chemical mechanical polishing, an amorphous semiconductor film 5 made of an InGaZnO (IGZO) film having a thickness of 20 nm is formed on the PZT film 4 as shown in FIG. accumulate.

  Next, as shown in FIG. 11D, the source electrode 6, the intermediate electrode 7 and the drain electrode 8 made of a laminated film of platinum and titanium are formed on the IGZO film 5 by the lift-off method to form the MFSFET 21. To do.

  Next, as shown in FIG. 12A, a second gate insulating film (paraelectric film) 9 made of a silicon nitride film (SiNx) is formed on the IGZO film 5. Thereafter, as shown in FIG. 12B, a gate electrode 110 made of a laminated film of gold and titanium is formed on the SiNx film 9 by a lift-off method. Further, as shown in FIG. 12C, electrodes 11a to 11c that are in contact with the source electrode 6, the intermediate electrode 7, and the drain electrode 8 are formed, and the MISFET 22 is formed. Thereby, the semiconductor memory cell 20 having a structure in which the MFSFET (memory element) 21 and the MISFET (selective switching element) 22 are stacked is completed.

  FIG. 13 is an AFM image showing the result of measuring the surface roughness of the IGZO film 5 constituting the channel. As shown in FIG. 10A, the surface roughness is a region A that overlaps the first gate electrode 3 of the MFSFET 21 in a plane and a region B that overlaps the second gate electrode 10 of the MISFET 22 in a plane. Thus, the surface of the ZnO film 105 at the interface X between the PZT film 4 and the IGZO film 5 and the interface Y between the IGZO film 5 and the SiNx film 9 was measured.

  As shown in FIG. 13, at the interface Y, the surface roughness (RMS) in the region A and the region B is about 0.6 to 0.7 nm, which is the surface roughness in the region A and the region B at the interface X. (RMS) was approximately the same as 0.6 nm. This is presumably because the IGZO film 5 is amorphous and thus the surface roughness due to the crystal grains did not occur.

  FIGS. 14A and 14B are diffraction images showing the results of measuring the crystallinity of the PZT film 4 and the IGZO film 5 by electron beam backscatter diffraction (EBSD). FIG. 14A is a diffraction image in the region A and the region B of the PZT film 4, and FIG. 14B is a diffraction image in the region A and the region B of the IGZO film 5.

  The PZT film 4 was crystallized in the region A and not crystallized in the region B as shown in FIG. On the other hand, as shown in FIG. 14B, the IGZO film 5 was not crystallized because no diffraction image was obtained in both the region A and the region B. That is, the IGZO film 5 was in a uniform amorphous state regardless of the crystallinity of the underlying PZT film 4.

  When the drain current-gate voltage characteristics of the MISFET 22 of the formed semiconductor memory cell 20 were measured by the same method as that shown in FIG. 5, good switching characteristics without hysteresis were obtained as shown in FIG. 15. .

  This is because by making the semiconductor film 5 constituting the channel amorphous, 1) the surface roughness of the semiconductor film 5 is reduced, and 2) the semiconductor film 5 does not depend on the crystallinity of the underlying ferroelectric film 4. It is considered that the amorphous state is uniform with few residual carriers, and 3) the spontaneous polarization of the semiconductor film 5 becomes zero.

  In the present invention, the material of the amorphous semiconductor film 5 is not particularly limited, but a material made of a metal oxide is preferably used. When the ferroelectric film 4 and the paraelectric film 9 constituting the gate insulating film of the semiconductor memory cell are made of metal oxide, the dielectric film and the amorphous semiconductor film 5 constituting the channel layer are made of the same oxide. Due to the bonding, a reaction layer is hardly formed at the interface. Therefore, a good interface can be obtained, and MFSFET and MISFET having excellent switching characteristics can be obtained.

Moreover, in the said embodiment, although the IGZO film was used as the amorphous semiconductor film 5, it is not restricted to this, The material which consists of a metal oxide containing at least 1 sort (s) of indium (In), gallium (Ga), and zinc (Zn) May be used. Although the semiconductor film 5 made of these materials is amorphous, it has high mobility (typically 15 to 20 cm ² / V · s), so that the on-resistance of the semiconductor memory element and the selective switching element is reduced. Can be bigger. Thereby, the difference in output voltage at the time of data reading becomes large, and the S / N ratio can be improved. The amorphous semiconductor film 5 preferably has a carrier concentration of 10 ¹⁸ cm ⁻³ or less. Thereby, the off current of the semiconductor memory element and the selective switching element can be reduced. Therefore, the difference in output voltage at the time of data reading becomes large, and the S / N ratio can be improved.

  Further, as the material of the amorphous semiconductor film 5, non-oxide silicon or germanium may be used in addition to the metal oxide. The amorphous semiconductor film 5 can be formed by a method such as a PLD (Pulse Laser Deposition) method, a MOCVD (Metal Organic Chemical Vapor Deposition) method, a sputtering method, or a vacuum deposition method.

In the present embodiment, the ferroelectric film 4 is a PZT film, but is not limited to this. For example, lanthanum (La), niobium (Nb), vanadium (V), tungsten (W), praseodymium ( PZT films to which elements such as Pr) and samarium (Sm) are added may be used. By adding other elements, the crystallization temperature is lowered, so that formation at a low temperature is possible, and the effect of reducing repetitive polarization reversal fatigue is also obtained. In addition, bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ), bismuth lanthanum titanate (Bi _3.25 La _0.75 Ti ₃ O ₁₂ ), strontium bismastantalate (Sr (Bi, Ta) ₂ O ₉ ), bismuth ferrite ( BiFeO ₃ ), yttrium manganite (YMnO ₃ ) or the like may be used.

  The ferroelectric film 4 is preferably formed as a polycrystalline film. This is because it is not easy to epitaxially grow a ferroelectric film on a silicon substrate on which a CMOS circuit necessary for a memory chip driver or the like is formed. Therefore, an element integrated with a drive circuit by using a polycrystalline ferroelectric film It is because it can obtain. For example, there is a configuration in which polycrystalline platinum is used as the first gate electrode and polycrystalline PZT is used as the ferroelectric film via an interlayer insulating film between the CMOS circuit and the memory element.

  In the present invention, the semiconductor memory cell 20 is not limited to the structure shown in FIG. For example, as shown in FIGS. 16A and 16B, the intermediate electrode 7 may be omitted. In this case, it is preferable that the first gate electrode 3 and the second gate electrode 10 have a region partially overlapping in plan view. Further, as shown in FIGS. 17A and 17B, the first gate electrode 3 and the second gate electrode 10 may be arranged to face each other. In this case, as shown in FIG. 17B, the MFSFET 21 and the MISFET 21 are configured to be connected in parallel, and an operation as a NAND type memory becomes possible.

  Next, the operation of the semiconductor memory cell will be described with reference to FIG. 18 and FIGS. 19 (a) and 19 (b). Here, a semiconductor memory cell having the structure shown in FIGS. 16A and 16B will be described as an example.

  In the non-access state, the first gate electrode 3, the second gate electrode 10, and the source electrode 6 are grounded. By grounding the second gate electrode 10, the MISFET 22 is in an OFF state, and even if an arbitrary voltage is applied to the drain electrode 8, no erroneous writing occurs in the MFSFET 21.

  In the data writing operation, a positive voltage (for example, 12 V) is applied to the second gate electrode 10 to turn on the MISFET 22, a voltage is applied to the drain electrode 8 and the first gate electrode 3, and the channel layer 5 A write voltage is applied between the first gate electrodes 3. For example, when data “1” is written, the drain electrode 8 is grounded and a positive voltage (for example, 10 V) is applied to the first gate electrode 3. When writing data “0”, the first gate electrode 3 is grounded and a positive voltage (for example, 10 V) is applied to the drain electrode 8. Thus, when data “1” is written, the polarization of the gate insulating film 4 of the MFSFET is directed upward (channel layer 5 direction) and data “0” is written as shown in FIG. 19B. In this case, the polarization of the gate insulating film 4 is directed downward (in the direction of the first gate electrode 3) as shown in FIG.

  To read data, the first gate electrode 3 is grounded, a positive voltage (for example, 12V) is applied to the second gate electrode 10 to turn on the MISFET 22, and a voltage (between the drain electrode 8 and the source electrode 6 ( For example, if 1V) is applied and the flowing drain current is large, "1" can be read and if it is small, "0" can be read.

  FIG. 20 is a circuit diagram showing a configuration in which semiconductor memory cells 20 are arranged in an array. FIG. 20 shows an example in which the semiconductor memory cells 20 are arranged in 4 rows × 4 columns. In each semiconductor memory cell 20, the first gate electrode of the MFSFET (semiconductor memory element) is the first word line WL1 on the row decoder 30 side, and the second gate electrode of the MISFET (selective switching element) is the second word. The drain electrode is connected to the line WL2, the drain electrode is connected to the bit line ML on the column decoder 31 side, and the source electrode is connected to the source line (not shown). In the present embodiment, the MFSFETs are alternately inverted in the column direction so that the semiconductor memory elements adjacent in the vertical direction share the source electrode and the drain electrode. Thereby, the cell occupation area can be reduced. In addition, since MFSFET and MISFET in this embodiment are transparent with respect to visible light, a memory function and a switching function can be added with respect to the use as which transparency is requested | required, such as electronic paper.

  As mentioned above, although this invention was demonstrated by suitable embodiment, such description is not a limitation matter and of course various modifications are possible.

  The present invention is useful for an ultra-high-integrated memory switching device using a ferroelectric.

1 Silicon substrate 2 SiO ₂ film 3 First gate electrode 4 Ferroelectric film (gate insulating film)
5 IGZO film (amorphous semiconductor film)
6 Source electrode 7 Intermediate electrode 8 Drain electrode 9 Paraelectric film (gate insulating film)
DESCRIPTION OF SYMBOLS 10 2nd gate electrode 11a-11c Electrode 20 Semiconductor memory cell 21 MFSFET (1st field effect transistor)
22 MISFET (second field effect transistor)
30 Row decoder 31 Column decoder

Claims (10)

A memory element comprising a first field effect transistor having a gate insulating film made of a ferroelectric film;
A semiconductor memory cell comprising a selective switching element comprising a second field effect transistor having a gate insulating film made of a paraelectric film,
The ferroelectric film and the paraelectric film are laminated via an amorphous semiconductor film,
A first gate electrode of the first field effect transistor is formed on the ferroelectric film side;
A second gate electrode of the second field effect transistor is formed on the paraelectric film side;
The amorphous semiconductor film constitutes a common channel layer of the first field effect transistor and the second field effect transistor,
A semiconductor memory cell, wherein a source electrode and a drain electrode common to the first field effect transistor and the second field effect transistor are formed on a main surface of the amorphous semiconductor film. Applying a predetermined voltage to the second gate electrode to turn on the selective switching element;
The data is written to the memory element by applying a predetermined voltage between the first gate electrode and the drain electrode to change a polarization state of the ferroelectric film. Semiconductor memory cell. Applying a predetermined voltage to the second gate electrode to turn on the selective switching element;
Reading a data written in the memory element by applying a predetermined voltage between the source electrode and the drain electrode and detecting a current flowing through the channel layer according to a polarization state of the ferroelectric film. The semiconductor memory cell according to claim 1, wherein:   The semiconductor memory cell according to claim 1, wherein the amorphous semiconductor film is made of a metal oxide.   The semiconductor memory cell according to claim 4, wherein the amorphous semiconductor is made of a metal oxide containing at least one of indium (In), gallium (Ga), and zinc (Zn).   The semiconductor memory cell according to claim 5, wherein the amorphous semiconductor film is made of an In—Ga—Zn—O-based metal oxide. The amorphous semiconductor film, the carrier concentration is ¹⁰ 18 ^{cm -3} or less, the semiconductor memory cell of claim 1. A method of manufacturing a semiconductor memory cell according to claim 1, comprising:
Forming (a) the first gate electrode on a substrate;
Forming the ferroelectric film on the substrate so as to cover the first gate electrode (b);
Forming the amorphous semiconductor film on the ferroelectric film (c);
Forming the source and drain electrodes on the amorphous semiconductor film (d);
Forming the paraelectric film on the amorphous semiconductor film so as to cover the source electrode and the drain electrode (e);
And (f) forming a second gate electrode on the paraelectric film.   9. The method of manufacturing a semiconductor memory cell according to claim 8, further comprising a step of smoothing the surface of the ferroelectric film after the step (b) and before the step (c).   9. The method of manufacturing a semiconductor memory cell according to claim 8, wherein in the step (b), the ferroelectric film is formed as a polycrystalline film.