200903508 九、發明說明： 【發明所屬之技術領域】 本發明一般係有關於記憶體儲存裝置，尤指一種在動態隨 機存取§己憶體(Dynamic Random Access Memory，DRAM)裝置 之定址期間實施省電之設計結構。 【先前技術】 dram積體電路陣列已應用多年，透過先進的半導體製 私與電路sxs十技術’它們的儲存容量也大幅增加。半導體製程 與電路設計技術的快速發展，同樣也使得^合程度越來越高， 讓把憶體_大小域本獲敎幅賴，且製錄料得以提 dram記憶格(memory cell)一般包括像是一存取電晶體 (開關）與利用電荷形式儲存二進位資料位元的-電容器之基 本元件。基本上，電容器所儲存的一第一電壓代表邏輯 或二進位的T (例如VDD)，而儲存電容器上的第二電壓代表 邏輯LOW或二進㈣，Ό”餘（例如接地）。dram裝置的一 個基本缺點是電容_電荷最後會漏掉，因此必須「更新」電 谷電荷，调記憶格所儲存_料位元就會遺失。 由於f Μ彡、制功率需求提升，0此會不_需要節省功 ^的新方法。最近的研究顯示在—記㈣快取(_。7咖㈣ ’所有的記憶體存取巾有最多95%是發生在僅25%的快取 200903508 内，如此造成相當數量的記憶體裝置係經常性處於待命的狀 態，所以會消耗功率。在現行的DRAM架構中，為了顧及某 些類型的應用之效能，通常需要長（大）頁面存取(deep (iarge) page access)。然而，對大頁面定址會讓DRAM陣列内的許多 裝置都收到列位址命令，對於記憶體系統來說會消耗相當大的 功率。第一圖所示為一示範的DRAM架構1〇〇，其中說明啟 動列裝置會造成相當大的功率消耗。 在所示的簡化範例中，第一圖的DRAM架構1〇〇為一個 4x4記憶格(cell)102的陣列，每一格包括一儲存電容器1〇4與 一存取電晶體106 (然而，現代的DRAM在長寬方面都可能 有數千個記憶格）。在讀取操作(read operation)中，所選擇的記 憶格的列會啟動，每一個耦接至該列的字元線(word line)1〇8 之電晶體會導通’並將該列的電容器連接至關聯的感測線 (sense line)110 ’而感測線110再（選擇性地）輕接至感測放大 器112’而感測放大器112辨別與鎖存(latch)代表儲存的〇或1 之訊號。來自適當的行之放大的數值會選擇並連接至輸出。在 讀取週期結束時，列數值會復原至在讀取過程中放電的電容器 104。寫入操作(write operation)係藉由啟動該列並將要寫入的 資料數值連接至感測線110 ’由感測線11 〇將記憶格電容器1 〇4 充電至所需的數值。在對一特定記憶格進行寫入的過程中，會 讀出整個列，改變一個數值，然後整列會重新寫入。 在一些應用中，有可能將存取列的動作「步級化(step)」， 200903508 以有效地讓啟動整烟的轉最佳化。然而，在許多應用中， 存取本身的IW機性會抵銷頁面長度^age ^印也)的優點，這是因 為有些系統從來不會用到大頁面存取，或者沒有辦法「步級化」 足夠的行數’以補償先前通電之舰置的數目。因此，一般來 說’有需要提供在-記憶财統巾降低用來主動地定址資料的 功率之方法。 ' 有一種降低功率消耗的方法是將DRAM設置於一「降級 (degrade)」模式，其中DRAM會進入關閉的待命狀態如 state)。有關此方法的進一步資訊可參考美國專利申請案，由 Gooding 提出之 US2〇〇6/〇〇47493 一案。特別是'，在 US2006/GG47493 -案巾提到了對於複數個揮發性真實記憶體 部分使用真實記麵科之财低雜(deep p_ d_)模 式，而不會造成資料流失。 ·由上所述，較佳的方式為能夠持續存取DRAM，同時節 ^功率，在某個程度上也不會因為要將DRAM從潛伏的待命 模式唤醒，而花費額外的時間。 【發明内容】 以上所討論到的問題或前案的缺失可於示範實施例加以 克服或纾解，其中如—種包括將個·憶格(m_^聊 列成行與列的_ (arTay)之隨機存取記憶體裝置㈣⑽ access memory device)，每—記憶格具有與其關聯之一存取裝 200903508 置，陣列的每一列更包括與其關聯之複數N字元線，其中N ，應至陣列之獨立地可存取分區的_數目，其中在一給定列的 每-存取裝置健1¾接至觸該些N字元、_其巾—條，以 及與陣列峨ittfl德輯碼H麟，配置（eGnfigured)用 :接收複數侧仙：位元’並為了魏些列健位元所識別的 要求列而決定’在要求列内的該些N個分區有哪些要存取， 以致不啟動在-選擇助但是不在—要存取的分區内之該些 存取裝置。 、、，在另一實施例中，一種降低一隨機存取記憶體裝置的功率 雜之方法係包括減用於一記憶體陣列之一要求位址，記憶 體陣列包含排列成行與列的個別記憶格，每一記憶格具有與其 ，聯之-存取裝置；P車觸每—列更包括與其關聯之複數N 字元線，其中N對應至陣列之獨立地可存取分區的一數目， 其中在-給定_每-存取裝置_接至觸 N字元線 的其中-條，以及為了純括於該要求位址之複數個列位址位 ^所識別的-要求列而決定，在要求列内的該些N個分區有 :15些要存取；以及啟動要求列的N條字元線的其巾之一或更 多條’以便僅啟動對應至要存取的N個分區的其中一個或更 多之該些存取裝置會啟動，其林啟動任何對應至沒有要存取 的N個分區的其中一個或更多之存取裝置。 理。。i又ρ實施例中一種運算紐包括—處驾；可由處 理讀行之-記憶體控·(ιηεηκ)ΓΥ eGntrofc)，其係與具有 200903508 將個別記憶袼排列成行與列的陣列之一隨機存取記憶體裝置 通訊’每-記憶格具有與其關聯之一存取農置；陣列的每一列 更包括與其關聯之複數N字元線，其中N對應至陣列之獨立 =可存取分區的-數目，其中在蚊列的每—存取裝置顯 接至該列的該些N字元、_其中—條；以及與_訊號通訊 之位址解碼I·，配置仙接收複_顺錄元，並為了 由該些列健位元所朗的—要求列而決定，在要求列内的今 些N個分區有哪些要存取，以致不啟動在一選擇列内但是^ 在一要存取的分區内之該些存取裝置。 以上所討論朗問題或前案的缺失可於*範實施例加以 克服或轉’其中提出-種具體實施於—設計流程·之一機 器可讀媒動驗計結構包括—_存取記鋪裝置，其包括 一將個別記憶格排列成行與列的陣列，每一記憶格具有與其關 聯之-存取裝置的每一列更包括與其關聯之複數N字 疋線，其中N對應至陣列之獨立地可存取分區的一數目.，其 中在一給定列的每―存取裝置僅祕至列的該些Ν字元線的 其中一條，以及與陣列訊號通訊之位址解碼器邏輯，配置用以 接收複數_位雜元，並為了由舰址侃賴別的一 要求列而決定，在要求列内的該些Ν個分區有哪些要存取， 以致不啟動在-選擇列内但是不在一要存_分區内之該些 存取裝置。 本电明的上述與其他目的 '特點、以及優點將可透過以下 10 200903508 更特別的較佳實施例加以了解，並以附屬的圖表搭配說明。 【實施方式】 本發明在此所揭示的是在DRAM裝置的定址期間實施省 電之設計結構。簡而言之，dram陣列是透過每列複數字元 線而分割為複數個分區(partition)，對於不需要用到所有與傳統 伺服器架構關聯之位址（或頁面長度^age depth))空間之應用 來說，可節省電力。此外，降低功率消耗並不代表需要降低可 用的記憶體空間·，反之，所有的位址都仍有效，並可在自我更 新的操作中維持資料，而在省電模式下，同一時間可存取的分 區數目會減少。為了個別地為特定的列分區定址，會使用支援 控制邏輯(supporting control logic)來個別為每一分區解碼、選 擇、與定址。以下將詳細說明，支援控制邏輯可整合於一獨立 5己憶體控制器内’作為單獨的邏輯，或嵌入於DRAm中。 參考第二圖，其中所示為現有DRAM架構1〇〇的另一示 思圖，說明傳統的列選擇操作(r〇W_Select〇perati〇n)。當列位址 選通(row address strobe, RAS)訊號為作動中(active)，一組列位 址位元Α[0:η]所呈現的位址會轉譯為在陣列内的一列位置。當 陣列的列解多工器「”R0W Demux’，」電路(r〇w demultiplexer circuitry)114解碼時，選擇列的每一存取電晶體會導通（成為 操作中消耗功率最多的部分）。接著，選擇所需的行。當行位 址選通(column address strobe, CAS)訊號為作動中(active”__ 組行位址位元A[n:m]所呈現的位址會透過行選擇器電路U6 200903508 轉澤為在陣列内的-行位置，而資料會讀出至資料線〇陶。 如上所示，即使不需要存取陣列的全寬度，但是在傳統的 列架構中’整列的存取裝置仍齡在操作狀態下。所以，根據 本發明的一實施例所提出的一種DRAM架構，其陣列具有只 要在架構規定不需要利用較大的資料組時，可以僅存取 DRAM晶片的位址的部分分區的能力。舉例來說，藉由分割 列存取命令（在對DRAM定址時會用掉大部分的作動功率）， 裝置允許僅存取在現行架構下會存取的列分區的1/2 (舉例）， 藉此省下在操作過程中1/2的列存取功率。然而，本發明還可 實施進一步的部分分區（例如1/3、1/4、1/5等）。 第二圖所示為根據本發明的一實施例，用以實施列分區的 DRAM架構300之示意圖。以下將說明的是，陣列的每一列 包括一對字元線（列選擇線）3〇2A、302B，其有效地將陣列 分割為·一對列分區A、B，在虛線304的二側。在此，如簡例 所述，其中有二個分區，因此每列有二條字元線，陣列的最左 行的記憶格耦接至關聯的一條字元線3〇2A，而陣列的最右行 的記憶格耦接至關聯的一條字元線3〇2B。對於N個分區來 說，N可為不同數目，每一列會有字元線。更應可了解的 是，在一給定列的記憶格的數目不一定在N個分區都是一樣 的，例如，在一個256行的裝置中，分區A可包括耦接至字 元線302A的192個記憶格，而分區b可包括剩下耗接至字元 線302B的64個記憶格。 12 200903508 為了要能夠獨立地選擇-特定列的字元線3〇2a、3㈣的 其中之-（或兩者），位址解碼器邏輯3〇6配置用以接收列位 址位疋A[0:n]並決定要啟動哪一列。位址解瑪器邏輯％ 陣列的地圖310以進-步決定要啟動列分區的那一個（例如 A、B或兩者）。根據容納於陣列内的分區數目位址解碼器 邏輯306提供至少-個額外訊號3〇8給列解多卫器電路⑴ 進一步指定要啟動那個（些）分區。在此實施辦，可包括位 C. 址解碼器邏輯306在DRAM上的列解多工器電路114内，或 選替地’包括在-獨立的記憶體控制器中（第三圖未顯示 由於實施分區’ -列中少於總數的存取裝置會啟動，同時減少 在感測/鎖存電路(sense/latch circuitry)U2與行選擇器電路 11ό中的裝置數目，如此可達到省電的目標。 17 力最後，第四圖所示為適用於第三圖的降低功率之dram 架構之示範運算系統之方塊圖。示範運算系統400包括處理器 f 402，其可進一步包含多個cpu (中央處理單元）404A、404B。 I 處理器402係由第一匯流排4〇8雛至記憶體控制器.。記 憶體控制器406執行像是提取(fetch)與儲存操作，維持快取一 致性，並儲存記錄記憶體頁面在真實記憶體的那一位置。此 外，記憶體係透過第二匯流排仍減至記憶體控制器 406。 如第四圖所述，記憶體41〇更包括作業系統(〇perating system)414、§己|思體部分資料(1116111〇1^ p〇rti〇n data)4i6、以及 13 200903508 使用者私式與資料418。在所示的示範實施例中，記憶體41〇 係由真實5己憶體部分，像是包含記憶體晶片（例如晶 片）的卡、或雙直列記憶體模組(dual inline memory module， DIM=)、或任何其他適合的記憶體單元所構成。舉例來說， 一運算系統可具有由四條12g MB DIMM所構成之記憶體 41〇。記憶體部分資料416包含有關記憶體41〇中的真實記憶 體部分之資訊。 在示範運算系統4〇〇中，處理器4〇2係-由第三匯流排42〇 福接至各種1/0裝置，例如I/O控制器422、磁帶控制器424、 以及網路控制器426，但不以此為限。1/〇控制器422係搞接 至硬碟428 (其可為整個硬碟子系統），以及CD R〇M 43〇。 其他I/O裝置，像是DVD (未顯示於圖中）也可使用。在所 示的實施例中，磁帶控制器424係進一步耦接至磁帶單元 432，而在選替的實施例中可包括整個磁帶子系統，具有任何 數目之實體磁帶機。此外，網路控制器426係麵接至區域網路 〇x>eal Area Network，LAN)434與網際網路連線436。應可了解 的是’有許多方式可用來配置運算系統，而運算系統4〇〇僅作 為舉例之用。 如上所示’第二圖中的支援控制邏輯可整合至記憶體 控制器406，作為獨立的邏輯，或者嵌入至記憶體裝置41〇。 舉例來說’記憶體控制器406可設計用以藉由建構分區記憶體 的位址之總犯數目，來使用位址分區(address partiti〇n)的功 14 200903508 =。接著，記憶體控制器4〇6可根據個別的應用來調整分區功 月b三對於需要長頁面長度的應用，分區會關閉（在選擇列的所 有字元線會啟動），而可能會發生全顺取的卿。對於不需 要大頁面長度（較多隨機存取）的應用來說，可開啟分區功能， ，到，存取過程中省電的目的。在分區狀態下，所有的資料都 可正常存取’剩下的分區再有需要的喃也可使用，但是可能 需要較長的存取時間。 第五圖所示為一設計流程500之流程圖。設計流程5〇〇 可根據所設計的1C的_而有不同，舉絲說，用以建構特 殊應用IC(ASIC)的設計流程500和為了設計標準組件的設計 "il程500並不相同’設計結構51〇較佳為一設計流程52〇的輸 入，可由ip提供者、核心開發者(coredevel〇per)、或其他設計 公司提供’或者可由設計流程的操作者產生，或者來自其他來 源。設計結構510包含概要圖或HDL，一種硬體描述語言（例 如Venlog、VHDL、C等）的形式之電路實施例·。設計結 構51〇可包含於-或更多個機器可讀媒财。舉例來說，設計 結構510可以是第三圖所示的電路實施例5〇〇的文字槽案或圖 形表示。設計流程520將電路實施例3〇〇合成（或轉譯）為網 路連線表(netlist)530，其中網路連線表53〇例如接線、電晶體、 邏輯閘、控制電路、I/O、以及模型等的列表，並描述與積體 電路設計巾的其他元件與電路的賴，記齡至少—個機器可 s賣媒體上。设计流程可能是反覆的，其中網路連線表$兕會重 新合成-或更纽，視魏觸的設計規格與參數而定。 200903508 3又计流程520包括使用各種輸入’例如，來自包括·—組常 用元件、電路、以及裝置’包括模型、布局、和符號表示之元 件庫元件(library element)535的輪入，以用於一給定的製造技 術（例如不同的技術節點’ 32nm、45 nm、90nn等）、設計規 格（design specification)540、特性化資料（characterization data)550、驗證資料(veriflcati〇n data)560、設計規則(design rule)570、以及包括測試型態與其他測試資訊之測試資料檔案 580。設計流程520進一步包括，例如，標準電路設計流程es such as像是時序分析(timing analysis)、驗證工具、設計規則 核對器（design mle checker)、以及布局與繞線(place and r〇ute) 工具等。熟悉積體電路設計的人應可了解與用於設計流程520 的電子設計自動化工具和應用相關之範圍，而不會脫離本發明 的精神與範疇。發明實施例的設計結構並不限於任何特定的設 計流程。 叹什流耘520較佳地將第三圖所示的本發明實施例，以及 任何額外的積體電路設計或資料（若可行的話），轉譯為第二 ，計結構590。第二設計結肖59〇係位於儲存媒體，作為用以 交換積體電路的布局資料所用的資料格式（例如，用以儲存此 種設計結構的GDSII (GDS2)、GH、〇娜、或任何其他合適 才二式所，存的資成）。第二設計結構59〇可包含像是測試資料 才备案、设計内容齡、製造資料、布局參數 、 ^=、形狀、_料等製造生產線上所_=二 料體4造商所需的其他資料，以便讓半導體製造商用來生產 16 200903508 如第二圖所示之本發明實施例。第二設計結構獨接 至階段595。舉例來說，第二設計結構獨 j (tape-out)、交付生產、交付光罩廠疋案 送回給客戶等等。 ^另4公司、以及 f 藝j可了解’在本發明的範相，可對本發明種 :=動與等效的替代，此外，可針對特定的情況或： 離本發_實質顧。因此，本發明並不限 有==之實施例，附屬的申請專利範圍可視為涵蓋所 【圖式簡單說明】 ^以下示範_式中，類似的標號代表類似的元件。 第一圖所示為一示範的DRAM架構之示意圖； 圖所示為第一圖的DRAM架構之另:示意圖，其中 特別、，'a示了傳統的列選擇操作； 圖所示為根據本發明的一實施例，用以實施列分區的 RAM架構之示意圖； -伙第Γ圖所示為適用於第三圖的降低功率之dram架構之 塊圖；以及 ^第五圖所示為用於半導體設計、製造、及/或測試之一示 靶設計流程之流程圖。 〆、 17 200903508200903508 IX. Description of the Invention: [Technical Field] The present invention generally relates to a memory storage device, and more particularly to a provincial implementation during the location of a Dynamic Random Access Memory (DRAM) device. The design structure of electricity. [Prior Art] Dram integrated circuit arrays have been used for many years, and their storage capacity has also increased significantly through advanced semiconductor manufacturing and circuit sxs technology. The rapid development of semiconductor process and circuit design technology has also made the degree of harmony higher and higher, so that the size of the memory cell is greatly improved, and the recording material can be promoted. The memory cell generally includes images. It is a basic component of an access transistor (switch) and a capacitor that stores binary data bits in the form of a charge. Basically, a first voltage stored by the capacitor represents a logical or binary T (eg VDD), while a second voltage on the storage capacitor represents a logical LOW or binary (four), Ό" (eg ground). A basic disadvantage is that the capacitor_charge will eventually leak out, so the battery charge must be "updated" and the memory bit stored in the memory cell will be lost. Since f Μ彡 and system power demand increase, 0 will not need to save a new method. Recent research has shown that in the (four) cache (_. 7 coffee (four) 'all of the memory access towels have up to 95% occurring in only 25% of the cache 200003508, thus causing a considerable number of memory devices often Sex is on standby, so it consumes power. In the current DRAM architecture, long (iarge) page access is usually required to account for the performance of certain types of applications. Page addressing allows many devices in the DRAM array to receive column address commands, which consumes considerable power for the memory system. The first figure shows an exemplary DRAM architecture, which illustrates the boot column. The device can cause considerable power consumption. In the simplified example shown, the DRAM architecture 1 of the first figure is an array of 4x4 cells 102, each cell including a storage capacitor 1〇4 and a Accessing the transistor 106 (however, modern DRAMs may have thousands of memory cells in terms of length and width.) In a read operation, the columns of selected memory cells are activated, each coupled to The character line of the column (wor d line) The transistor of 1〇8 turns "on" and connects the capacitor of the column to the associated sense line 110' and the sense line 110 is (optionally) lightly connected to the sense amplifier 112' The amplifier 112 identifies and latches the signal representing the stored chirp or 1. The amplified value from the appropriate row is selected and connected to the output. At the end of the read cycle, the column value is restored to the reading process. The capacitor 104 in the middle discharge. The write operation is performed by starting the column and connecting the data value to be written to the sensing line 110'. The memory cell capacitor 1 〇4 is charged by the sensing line 11 至 to the desired value. In the process of writing to a specific memory cell, the entire column is read, a value is changed, and the entire column is rewritten. In some applications, it is possible to "step" the action of accessing the column (step ), 200903508 to effectively optimize the start-up of the whole smoke. However, in many applications, access to the IW's own nature will offset the advantages of page length, because some systems Never use a big page Take, or there is no way sufficient number of lines "step level of '' ship-compensation to energize the previous number. Therefore, it is generally said that there is a need to provide a method for reducing the power used to actively address data in a memory. There is a way to reduce power consumption by setting the DRAM in a "degrade" mode where DRAM enters a closed standby state such as state. Further information on this method can be found in the US patent application, US2〇〇6/〇〇47493 by Gooding. In particular, in US2006/GG47493 - the case towel refers to the use of the real punctuation section of the deep p_d_ mode for a plurality of volatile real memory parts without causing data loss. From the above, the preferred way is to be able to continuously access the DRAM while saving power, and to some extent not spending extra time due to waking up the DRAM from the latent standby mode. SUMMARY OF THE INVENTION The problems discussed above or the deficiencies of the foregoing can be overcome or solved in the exemplary embodiments, wherein the _ (arTay) is included in the list of columns and columns. A random access memory device (4) (10) access memory device), each memory cell has one of its associated access devices 200903508, each column of the array further includes a plurality of N-character lines associated with it, where N is independent of the array The number of __accessible partitions, where each access device in a given column is connected to the N-character, _ its towel--, and array 峨ittfl code H Lin, configuration (eGnfigured): Receive the plural side: bit ' and determine the number of the N partitions in the required column to be accessed for the required columns identified by the Wei column. Select the access devices that are assisted but not in the partition to be accessed. In another embodiment, a method for reducing the power of a random access memory device includes subtracting a required address for a memory array, the memory array including individual memories arranged in rows and columns Each memory cell has its associated-access device; the P-vehicle-per-column further includes a plurality of N-character lines associated therewith, where N corresponds to a number of independently accessible partitions of the array, wherein Deciding at - the given - per-access device - connected to the N-type line of the N-character line, and for the -required column identified by the plurality of column address bits ^ purely included in the required address, The N partitions in the request column are: 15 to be accessed; and one or more strips of the N character lines of the request column are started to enable only the N partitions corresponding to the N partitions to be accessed. One or more of the access devices are activated, and the forest initiates any access device corresponding to one or more of the N partitions that are not to be accessed. Reason. . In the embodiment of the invention, the operation of the operation includes: - driving; reading and processing - memory control ((ηηεηκ) ΓΥ eGntrofc), which is stored in an array with 200903508 arrays of individual memories arranged in rows and columns. The memory device communication 'per-memory cell has one of its associated accesses; each column of the array further includes a plurality of N-character lines associated with it, where N corresponds to the array independent = number of accessible partitions , wherein each of the access devices of the mosquito net is connected to the N characters, _ among the strips of the column; and the address of the communication with the _ signal is decoded, and the configuration receives the complex _ record, and In order to be determined by the column-requested columns of the columns, what are the N partitions in the required column to access, so that they do not start in a selected column but in a partition to be accessed These access devices are within. The lang problem or the circumstance of the previous discussion may be overcome in the syllabary embodiment or it may be implemented in a design process. The machine readable media structure includes a _ access device. , comprising an array of individual memory cells arranged in rows and columns, each memory cell having associated with each of its access devices further comprising a plurality of N-shaped lines associated therewith, wherein N corresponds to the array independently Accessing a number of partitions, wherein each of the access devices in a given column is only one of the plurality of character line lines of the column, and the address decoder logic for communicating with the array signal is configured to Receiving a complex _ bit cipher, and in order to be determined by the ship's other requirements, which of the two partitions in the request column are to be accessed, so that the in-selection column is not activated but not in one The access devices in the _ partition. The above and other objects of the present invention will be understood by the more specific preferred embodiments of the following 10 200903508 and will be described in the accompanying drawings. [Embodiment] The present invention disclosed herein is a design structure that implements power saving during addressing of a DRAM device. In short, the dram array is partitioned into multiple partitions through each column of complex digital lines, without the need to use all the address (or page length) associated with the traditional server architecture. For applications, power can be saved. In addition, reducing power consumption does not mean that you need to reduce the available memory space. Conversely, all addresses are still valid, and data can be maintained in the self-updating operation, while in the power saving mode, the same time can be accessed. The number of partitions will be reduced. In order to individually address a particular column partition, support control logic is used to individually decode, select, and address each partition. As will be explained in more detail below, the support control logic can be integrated into a separate 5 memory controller as a separate logic or embedded in the DRAm. Referring to the second figure, there is shown another diagram of an existing DRAM architecture, illustrating a conventional column selection operation (r〇W_Select〇perati〇n). When the row address strobe (RAS) signal is active, the address represented by a set of column address bits Α[0:η] is translated into a column position within the array. When the array demultiplexer ""R0W Demux'," circuit (r〇w demultiplexer circuitry) 114 is decoded, each access transistor of the selected column is turned on (becoming the most power-consuming part of the operation). Next, select the desired row. When the column address strobe (CAS) signal is active (active)__ group address bit A[n:m], the address will be translated by the row selector circuit U6 200903508. The position of the row in the array, and the data will be read out to the data line. As shown above, even if the full width of the array is not required to be accessed, in the conventional column architecture, the entire array of access devices is still in operation. Therefore, a DRAM architecture according to an embodiment of the present invention has an array having the ability to access only a partial partition of an address of a DRAM wafer as long as the architecture does not require the use of a larger data set. For example, by splitting the column access command (which uses most of the operating power when addressing the DRAM), the device allows access to only 1/2 of the column partitions that are accessed under the current architecture (for example). Thereby, the column access power of 1/2 during operation is saved. However, the present invention can also implement further partial partitioning (for example, 1/3, 1/4, 1/5, etc.). DRAM architecture for implementing column partitioning in accordance with an embodiment of the present invention A schematic diagram of 300. It will be explained that each column of the array includes a pair of word lines (column selection lines) 3〇2A, 302B that effectively divide the array into a pair of column partitions A, B, at dashed line 304. On the two sides, here, as shown in the simple example, there are two partitions, so each column has two word lines, and the memory cell of the leftmost row of the array is coupled to the associated one word line 3〇2A, and The memory cell of the rightmost row of the array is coupled to an associated word line 3〇2B. For N partitions, N can be a different number, and each column will have a word line. It should be understood that The number of memory cells in a given column is not necessarily the same in all N partitions. For example, in a 256-line device, partition A may include 192 memory cells coupled to word line 302A, while partition b It may include 64 memory cells remaining to be swapped to word line 302B. 12 200903508 In order to be able to independently select - (or both) of - a particular column of word lines 3 〇 2a, 3 (four), address decoding Logic logic 3〇6 is configured to receive the column address bits 疋A[0:n] and decide which column to start. Address lexicon logic The map 310 of the array determines, in a further step, which one of the column partitions to start (e.g., A, B, or both). At least one additional signal 3 〇 8 is provided based on the number of partitions contained in the array. The column decoder circuit (1) further specifies which partition(s) to boot. In this implementation, bit C. address decoder logic 306 may be included in the column demultiplexer circuit 114 on the DRAM, or alternatively 'Included in the -independent memory controller (the third figure does not show due to the implementation of the partition' - less than the total number of access devices will be activated, while reducing the sense/latch circuitry U2 The number of devices in the row selector circuit 11 is such that the goal of power saving can be achieved. 17 Finally, the fourth diagram shows a block diagram of an exemplary computing system for the reduced power dram architecture of Figure 3. The exemplary computing system 400 includes a processor f 402 that can further include a plurality of CPUs (Central Processing Units) 404A, 404B. The I processor 402 is formed by the first bus 4〇8 to the memory controller. The memory controller 406 performs, for example, fetch and store operations, maintains cache coherency, and stores the location of the recorded memory page in the real memory. In addition, the memory system is still reduced to the memory controller 406 through the second bus. As shown in the fourth figure, the memory 41 further includes a operating system 414, a severing part data (1116111 〇 1^ p〇rti〇n data) 4i6, and 13 200903508 user private With information 418. In the exemplary embodiment shown, the memory 41 is comprised of a real 5 memory portion, such as a card containing a memory chip (eg, a wafer), or a dual inline memory module (DIM= ), or any other suitable memory unit. For example, an computing system can have a memory 41 constructed of four 12g MB DIMMs. The memory portion data 416 contains information about the real memory portion of the memory 41. In the exemplary computing system 4, the processor 4〇2 is connected to the various 1/0 devices by the third bus bar 42, such as the I/O controller 422, the tape controller 424, and the network controller. 426, but not limited to this. The 1/〇 controller 422 is connected to the hard disk 428 (which can be the entire hard disk subsystem), and the CD R〇M 43〇. Other I/O devices, such as DVDs (not shown), can also be used. In the illustrated embodiment, the tape controller 424 is further coupled to the tape unit 432, and in the alternate embodiment may include the entire tape subsystem, with any number of physical tape drives. In addition, the network controller 426 is connected to the regional network ealx>eal Area Network (LAN) 434 and the Internet connection 436. It should be understood that there are many ways to configure the computing system, and the computing system 4 is for example only. The support control logic in the second figure shown above can be integrated into the memory controller 406 as separate logic or embedded in the memory device 41. For example, the memory controller 406 can be designed to use the work of the address part (2009 part 508) by constructing the total number of addresses of the partition memory. Then, the memory controller 4〇6 can adjust the partitioning power month b according to the individual application. For applications requiring a long page length, the partition will be closed (all word lines in the selected column will be activated), and the transaction may occur. Take the Qing. For applications that do not require large page lengths (more random access), the partitioning function can be turned on, to save power during access. In the partition state, all data can be accessed normally. The remaining partitions can be used again, but may require longer access times. The fifth diagram shows a flow chart of a design flow 500. The design flow 5〇〇 can be different depending on the 1C design. According to the wire, the design flow 500 for constructing an application specific IC (ASIC) and the design for designing standard components are not the same. The design structure 51 is preferably an input to a design flow 52, which may be provided by an ip provider, core developer, or other design company' either by an operator of the design process or from other sources. Design structure 510 includes a schematic or HDL, a circuit embodiment in the form of a hardware description language (e.g., Venlog, VHDL, C, etc.). The design structure 51 can be included in - or more machine readable media. For example, design structure 510 can be a text slot or graphical representation of circuit embodiment 5A shown in the third figure. The design flow 520 synthesizes (or translates) the circuit embodiment 3 into a network list 530, such as a wiring, a transistor, a logic gate, a control circuit, an I/O, And a list of models, etc., and describe the other components and circuits of the integrated circuit design towel, at least one machine can be sold on the media. The design process may be repeated, where the network connection table $兕 will be re-synthesized - or more, depending on the design specifications and parameters of the Wei touch. 200903508 3 The recalculation process 520 includes the use of various inputs 'e.g., from the inclusion of a set of common components, circuits, and devices' including model, layout, and symbolic representations of library elements 535 for use in A given manufacturing technique (eg different technology nodes '32nm, 45nm, 90nn, etc.), design specification 540, characterization data 550, verification data (veriflcati〇n data) 560, design A design rule 570, and a test data file 580 including test patterns and other test information. The design flow 520 further includes, for example, a standard circuit design flow such as timing analysis, verification tools, design mle checker, and place and r〇ute tools. Wait. Those skilled in the art of circuit design should be aware of the scope associated with electronic design automation tools and applications for design process 520 without departing from the spirit and scope of the present invention. The design structure of the inventive embodiment is not limited to any particular design flow. The streamer 520 preferably translates the embodiment of the invention shown in the third figure, as well as any additional integrated circuit design or material (if applicable), into a second, metering structure 590. The second design is located in the storage medium and serves as a data format for exchanging layout data of the integrated circuit (for example, GDSII (GDS2), GH, 〇na, or any other for storing such a design structure) Appropriate only two styles, the deposit of funds). The second design structure 59 can include other materials such as test data, record design, manufacturing materials, layout parameters, ^=, shape, material, etc. Information for use by semiconductor manufacturers to produce 16 200903508 embodiments of the invention as shown in the second figure. The second design structure is unique to stage 595. For example, the second design structure is unique (tape-out), delivery production, delivery of the mask factory, return to the customer, and so on. ^ The other 4 companies, and f art j can understand that in the scope of the present invention, the invention can be used: = dynamic and equivalent substitution, in addition, can be specific to the situation or: from the present invention. Therefore, the present invention is not limited to the embodiment of ==, and the scope of the accompanying claims is to be construed as covering the accompanying drawings. The first figure shows a schematic diagram of an exemplary DRAM architecture. The figure shows another schematic diagram of the DRAM architecture of the first figure, wherein, in particular, 'a shows a conventional column selection operation; An embodiment of a RAM architecture for implementing column partitioning; - a block diagram of a reduced power dram architecture suitable for the third diagram; and a fifth diagram for a semiconductor Design, manufacture, and/or test a flow chart showing the target design flow. 〆, 17 200903508
【主要元件符號說明】 DRAM架構 100 記憶格 102 儲存電容器 104 存取電晶體 106 字元線 108 感測線 110 感測放大器 112 列解多工器電路 114 行選擇器電路 116 DRAM架構 300 字元線 302A、302B 虛線 304 位址解碼器邏輯 306 額外訊號 308 地圖 310 示範運算系統 400 處理器 402 CPU 404A、404B 記憶體控制器 406 第一匯流排 408 記憶體 410 第二匯流排 412 作業系統 414 200903508 記憶體部分資料 416 使用者程式與資料 418 第三匯流排 420 I/O控制器 422 磁帶控制器 424 網路控制器 426 硬碟 428 CD ROM 430 磁帶單元 - 432 區域網路 434 網際網路連線 436 設計流程 500 設計結構 510 设計流程 520 網路連線表 530 元件庫元件 535 設計規格 540 特性化資料 550 驗證育料 560 設計規則 570 測試資料檔案 580 弟二設計結構 590[Main component symbol description] DRAM architecture 100 memory cell 102 storage capacitor 104 access transistor 106 word line 108 sensing line 110 sense amplifier 112 column multiplexer circuit 114 row selector circuit 116 DRAM architecture 300 word line 302A 302B dotted line 304 address decoder logic 306 additional signal 308 map 310 exemplary computing system 400 processor 402 CPU 404A, 404B memory controller 406 first bus 408 memory 410 second bus 412 operating system 414 200903508 memory Partial data 416 User program and data 418 Third bus 420 I/O controller 422 Tape controller 424 Network controller 426 Hard disk 428 CD ROM 430 Tape unit - 432 Regional network 434 Internet connection 436 Design Process 500 Design Structure 510 Design Flow 520 Network Connection Table 530 Component Library Component 535 Design Specification 540 Characterization Data 550 Validation Nursing 560 Design Rule 570 Test Data File 580 Brother II Design Structure 590