JP2008234662A - Structure and method for implementing power saving in addressing of dram architecture - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure and a method for implementing power saving in addressing of a DRAM device. <P>SOLUTION: A random access memory device includes an array of individual memory cells arranged into rows and columns, and each memory cell has a corresponding access device. Assuming N as the number corresponding to the number of independently accessible partitions of the array, each row of the array further includes a corresponding plurality of N word lines, and each access device in a given row is coupled to only one of the N word lines of the rows. An address decoder communicating with the array receives a plurality of row address bits, and determines which of the N partitions in a requested row must be accessed on the requested row identified by the row address bits, and does not activate the access device within the selected row but not within the partition to be accessed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates generally to memory storage devices, and more particularly to structures and methods for implementing power savings during dynamic random access memory (DRAM) device addressing.

  DRAM integrated circuit arrays have existed for several years, and dramatic increases in their storage capacity have been achieved through advances in semiconductor manufacturing and circuit design techniques. Significant advances in these two technologies have also resulted in increasingly higher levels of integration that allow dramatic reductions in memory array size and cost and increased yields.

DRAM memory cells typically include, as basic components, an access transistor (switch) and a capacitor for storing binary data bits in charge form. Typically, the first voltage is stored in a capacitor to represent a logic HIGH or binary “1” value (eg, V _DD ), and the storage capacitor second voltage is a logic LOW or binary “0”. "Represents a value (eg, ground). The fundamental disadvantage of DRAM devices is that the capacitor charge eventually leaks and therefore provisions must be made to “refresh” the capacitor charge, otherwise the data bits stored by the memory cell. Is lost.

  As the power demand in computer systems increases, new ways to save power are always in demand. Recent studies have shown that up to 95% of all memory accesses in a memory cache can occur with only 25% of the cache. This results in a large number of memory devices that are always “ready” and thus consumes power. In current DRAM architectures, from a performance perspective, it is generally desirable to have long (large) page accesses for certain types of applications. However, large page size addressing results in row address commands that are applied to a large number of devices in the DRAM array, which consumes a large amount of effective power in the memory system. FIG. 1 illustrates an exemplary DRAM architecture 100 that illustrates that row device activation results in relatively high power consumption.

  In the simplified example shown, the DRAM architecture 100 of FIG. 1 is an array of 4 × 4 cells 102 each containing one storage capacitor 104 and one access transistor 106 (however, in recent years. DRAM devices can be thousands of length / width cells). During a read operation, the row of the selected cell is activated, each of the transistors coupled to the word line 108 of the row is turned on, and the capacitor of that row is connected to the associated sense line 110. The sense line 110 is then (optionally) coupled to the sense amplifier 112, thereby distinguishing and latching the stored signal representing 0 or 1. The amplified value from the appropriate column is then selected and connected to the output. At the end of the read cycle, the row value is restored to the capacitor 104 that was discharged during the read. A write operation is performed by activating a row and connecting the data value to be written to the sense line 110 to charge the cell capacitor 104 to the desired value. While writing to a particular cell, the entire row is read, one value is changed, and then all rows are written back.

  In some applications, access can be “stepped” through a row to efficiently optimize the power consumed to activate the entire row. However, in many applications, random access does not use large page access or because it cannot "step" through enough columns to make up for the number of row devices initially powered. May offset the benefits of paging. Accordingly, a method for reducing power associated with active addressing of data in a memory system is generally desirable.

  One approach to reducing power consumption involves placing the DRAM in a “reduced” mode, where the DRAM enters an inactive standby state. Additional information on this can be found in US Pat. Specifically, Patent Document 1 introduces the use of a deep power-down mode of a real memory portion within a plurality of volatile real memory portions without data loss.

US Patent Application Publication US2006 / 0047493

  In view of the above, it is possible to continue to allow access to the DRAM while saving power and in a way that does not take additional time to bring the DRAM out of hibern standby mode. It is desirable.

  The disadvantages and deficiencies of the prior art discussed above are an array of individual memory cells arranged in rows and columns, each memory cell having a corresponding access device, and N is independent of the array. Each row of the array further includes a corresponding plurality of N word lines, and each access device in a given row includes a number of N word lines in the row. An array of memory cells coupled to only one and an address decoder in communication with the array for receiving a plurality of row address bits and for the requested row identified by the row address bits, the requested row Determine which of the N partitions in the list should be accessed, and that are in the selected row but not in the partition to be accessed. Seth device from being activated, and an address decoder, a random access memory device comprising, are overcome or alleviated in an exemplary embodiment.

  In another embodiment, a method for reducing power consumption of a random access memory device is the step of receiving a requested address for a memory array, wherein the memory array includes rows and columns. , Each memory cell having a corresponding access device, where N is a number corresponding to the number of independently accessible partitions of the array, and each row of the array Further includes a corresponding plurality of N word lines, each access device in a given row being coupled to only one of the N word lines in the row, and included in the requested address For a requested row identified by a plurality of row address bits, a thread that determines which of the N partitions in the requested row should be accessed. And activating one or more of the N word lines of the requested row so as to activate only the access device corresponding to one or more of the N partitions to be accessed. None of the access devices corresponding to one or more of the N partitions that contain and should not be accessed are activated.

  In yet another embodiment, the computing system is a processor and a memory controller executable by the processor, the memory controller having a random array having an array of individual memory cells arranged in rows and columns. Communicating with an access memory device, each memory cell has a corresponding access device, where N is a number corresponding to the number of independently accessible partitions in the array, and each row of the array corresponds A memory controller and an address decoder in communication with the array, wherein each access device in a given row is coupled to only one of the N word lines in the row. A request that receives multiple row address bits and is identified by the row address bits Determine which of the N partitions in the requested row should be accessed, so that there is an access device that is in the selected row but not in the partition to be accessed. And an address decoder for preventing activation.

  In the several figures, reference is made to the exemplary drawings in which like elements are similarly numbered.

  Disclosed herein are structures and methods for implementing power savings during addressing of DRAM devices. Briefly stated, DRAM arrays are divided into multiple partitions by multiple word lines per row so that power is saved for applications that do not need to use the entire addressing (or paging) associated with traditional server architectures. It is divided into. Furthermore, this reduction in power does not reduce the total available memory. Rather, all addresses remain valid and can contain data in a self-refresh operation, reducing the number of partitions that can be accessed at one time during the power saving mode. In order to individually address a particular row partition, support control logic is used to individually decode, select, and address each partition. As described in more detail below, support control logic may be integrated into a separate memory controller as stand-alone logic or embedded on a DRAM.

  Referring now to FIG. 2, another schematic diagram of an existing DRAM architecture 100 is shown that illustrates a conventional row selection operation. When the row address strobe (RAS) signal is active, the address presented in the group of row address bits A [0: n] is converted to a row position in the array. Decoding by the array row demultiplexer circuit 114 turns on each access transistor in the selected row (resulting in the operating portion consuming the most power). The column of interest is then selected. When the column address strobe (CAS) signal is active, the address presented in the group of column address bits A [n: m] is converted through selector circuit 116 to a column position in the array, and the data is Read on data line D [0: x].

  However, as described above, even during operation where the full width of the array need not be accessed, all rows of the access device are still operated under the conventional row architecture. Thus, according to one embodiment of the present invention, the array was given the ability to access a partial partition of the address of a DRAM chip whenever the architecture instructed that a larger data set need not be used. A DRAM architecture is presented here. For example, by partitioning row access commands (which is the majority of the active power during DRAM addressing), the device is only (for example) half the row partition previously accessed in the current architecture. Is allowed to save 1/2 of the row access power during its operation. However, yet another partial partition can also be implemented. (For example, 1/3, 1/4, 1/5, etc.)

  FIG. 3 is a schematic diagram of a DRAM architecture 300 that implements row partitioning, in accordance with an embodiment of the present invention. As noted, each row of the array includes a pair of word lines (row select lines) 302A, 302B that efficiently divide the array into a set of row partitions A, B on either side of dotted line 304. Again, in the simple example shown, there are two partitions per row, and thus two word lines. The cell in the leftmost column of the array is associated with the associated word line 302A, and the cell in the rightmost column of the array is associated with the associated word line 302B. However, there will be n word lines per row for a different number, N partitions. Furthermore, it should be understood that the number of cells in a given row need not be allocated equally among the number of partitions, N. For example, in a 256 column device, partition A may include 192 cells coupled to word line 302A and partition B may include the remaining 64 cells coupled to word line 302B.

  Address decoder 306 receives row address bits A [0: n] to allow independent selection of a predetermined one (or both) of word lines 302A, 302B of a particular row. And configured to determine which line to activate. The address decoder 306 uses the array map 310 to further determine which of the row partitions (eg, A, B, or both) to activate. Depending on how many partitions are incorporated into the array, address decoder 306 provides at least one additional signal 308 to row demax circuit 114 to further identify which partitions are to be activated. In one embodiment, the address decoder 306 may be incorporated into the row demax circuit 114 on the DRAM, or alternatively may be incorporated into the memory controller (not shown in FIG. 3) itself. . As a result of partitioning, power is saved by having fewer devices whenever fewer access devices are activated than the total number of access devices in a row, and in the entire sense / latch circuit 112 and column select circuit 116. Realized.

  Finally, FIG. 4 is a block diagram of an exemplary computer system 400 suitable for use with the power reduction DRAM architecture of FIG. The exemplary computer system 400 includes a processor 402, which may further include a plurality of CPUs (Central Processing Units) 404A, 404B. The processor 402 is coupled to the memory controller 406 by a first bus 408. The memory controller 406 performs functions such as fetch and store operations, maintains cache coherency, and tracks where pages of memory are stored in real memory. Further, the memory 410 is coupled to the memory controller 406 by a second bus 412.

  As further shown in FIG. 4, the memory 410 further includes an operating system 414, memory portion data 416, and user programs and data 418. In the illustrated exemplary embodiment, the memory 410 is a card that includes a memory chip (eg, a DRAM chip), or a DIMM (Dual Inline Memory Module), or any other suitable memory unit. It consists of real memory parts like For example, the computing system may have a memory 410 made of four 128 MB DIMMs. Memory portion data 416 includes information about the real memory portion implemented in memory 410.

  Within the exemplary computing system 400, the processor 402 is represented by a third bus 420, including but not limited to an I / O controller 422, a tape controller 424, and a network controller 426. Coupled to a new I / O device. The I / O controller 422 is coupled to a hard disk 428 (which can be the entire hard disk subsystem) and a CD ROM 430. Other I / O devices such as a DVD (not shown) are also contemplated. In the illustrated embodiment, the tape controller 424 is further coupled to a magnetic tape unit 432, and in an alternative embodiment, a magnetic tape subsystem having any number of physical magnetic tape drives. The whole can be included. In addition, the network controller 426 is coupled to a LAN (Local Area Network) 434 and an Internet connection 436. It will be appreciated that there are numerous ways to configure a computing system, and computing system 400 is shown for exemplary purposes only.

  As described above, the support control logic 306 shown in FIG. 3 may be integrated into the memory controller 406 as stand-alone logic or may be incorporated into the memory device 410. For example, by building all possible numbers of addresses for partitioned memory, the memory controller 406 can be designed to use address partitions. The memory controller 406 can then adapt the partition on a “per application” basis. In applications that require long paging, the partition can be disabled (because all word lines in the selected row are activated) and full row access can occur. For other applications that do not require large paging (more random access), the partition can be enabled to save power during access. In the partitioned state, all data remains available for normal access. The remaining partitions can be used as needed, but longer access times may be required.

  FIG. 5 is a block diagram illustrating an example of a design flow 500. The design flow 500 is highly dependent on the type of integrated circuit (IC) being designed. For example, the design flow 500 is different for standard parts and ASICs. The design structure 510 is preferably an input of the design process 520, which is input from an IP provider, core developer, or other design company, and is obtained from the design flow operator or other resources. The design structure 510 includes an example circuit 300 in diagram format, HDL format, or hardware representation language (eg, Verilog, VHDL, C, etc.). The design structure 510 is included on one or more machine-readable storage media. For example, the design structure 510 is a text file or a diagram of an example circuit described in FIG. The design process 520 synthesizes (translates) the circuit example 300 into the netlist 530. Here, the netlist 530 is, for example, a list of wirings, transistors, logic gates, control circuits, I / Os, models, etc., and describes connection relationships with other components and circuits in the integrated circuit, and at least Encoded on one machine readable storage medium. The netlist 530 is synthesized (translated) with the design process 520 repeatedly one or more times according to design specifications and circuit parameters.

  The design process 520 accepts a variety of inputs. The input includes, for example, commonly used elements, circuits, devices including models, a set of layouts and manufacturing technology-specific expressions (for example, different technology nodes, 32 nm, 45 nm, 90 nm, etc.) Input from library element 535, input from design specification 540, input from characteristic data 550, input from verification data 560, input from design rule 570, from test data file 580 including test pattern and other test information There is input. The design process 520 further includes standard design processes such as timing analysis, verification tools, design rule checkers, location (placement) and route processes. A designer of an integrated circuit will readily understand the design automation tools that can be used in the design process 520 and the scope of their application without departing from the spirit and spirit of the present invention. Further, the design structure of the embodiment of the present invention is not limited to a specific design flow.

  The design process 520 translates the embodiment of the present invention shown in FIG. 3 into a second design structure 590 with any additional integrated circuit design and data (if possible). The second design structure 590 is stored in the storage medium in a format for converting layout data of the integrated circuit (for example, GDSII (GDS2), GL1, OASIS, or a format corresponding thereto). The second design structure 590 includes, for example, test data files, design content files, manufacturing data, layout parameters, wiring, metal layer levels required by the semiconductor manufacturer who manufactures the embodiment of the present invention shown in FIG. It may include vias, shapes, data for flowing to the production line, or any other data. The second design structure 590 then proceeds to stage 595, for example to tape-out, used for manufacturing, sent to a mask house or other design house, or sent back to the customer.

  Although the present invention has been described with reference to preferred embodiments, those skilled in the art will recognize that various modifications can be made and equivalents may be substituted for those elements without departing from the scope of the invention. I will. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the basic scope. Accordingly, the invention is not limited to the specific embodiments disclosed as the best mode contemplated for carrying out the invention, but the invention includes all implementations within the scope of the appended claims. It is intended to include forms.

1 is a schematic diagram of an exemplary DRAM architecture. FIG. 3 is another schematic diagram of the existing DRAM architecture of FIG. 1 specifically illustrating a conventional row selection operation. 1 is a schematic diagram of a DRAM architecture implementing row partitioning, according to an embodiment of the invention. FIG. FIG. 4 is a block diagram of an exemplary computing system 400 suitable for use with the power reduction DRAM architecture of FIG. It is a figure which shows the flow of the exemplary design process in the design, manufacture, or test of a semiconductor.

Explanation of symbols

112: Sense latch circuit 114: Row demax circuit 116: Column selection circuit 300: DRAM architecture 302: Word line 306: Address decoder 308: Signal 310: Array map

Claims (18)

An array of individual memory cells arranged in rows and columns, each memory cell having a corresponding access device, wherein N is a number corresponding to the number of independently accessible partitions of the array Each row of the array further includes a corresponding plurality of N word lines, and each access device in a given row is coupled to only one of the N word lines of the row. An array of memory cells,
An address decoder in communication with the array, which receives a plurality of row address bits, and for a requested row identified by the row address bits, which of the N partitions in the requested row are accessed An address decoder that determines whether it should be activated and prevents an access device that is in the selected row but not in the partition to be accessed from being activated;
Random access memory devices.   The memory device of claim 1, wherein the array of individual memory cells includes dynamic random access memory (DRAM) cells.   The memory device of claim 1, wherein the address decoder uses an array map to determine which of the N partitions in the request row are to be accessed.   The address decoder sends the plurality of row address bits to a row demultiplexer circuit associated with the word line, and further indicates at least which of the N partitions in the requested row is to be accessed. The memory device of claim 1, wherein one additional signal is sent to the row demultiplexer circuit.   The memory device of claim 4, wherein the address decoder is embedded in circuitry of the array.   The memory device of claim 4, wherein the address decoder resides in a separate memory controller corresponding to the array. A method for reducing power consumption of a random access memory device, comprising:
Receiving a requested address for a memory array, said memory array comprising individual memory cells arranged in rows and columns, each memory cell having a corresponding access device; , N is a number corresponding to the number of independently accessible partitions of the array, each row of the array further includes a corresponding plurality of N word lines, and each access in a given row The device is coupled to only one of the N word lines of the row; and
Determining, for a requested row identified by a plurality of row address bits contained within the requested address, which of the N partitions in the requested row should be accessed;
Activating one or more of the N word lines of the requested row so as to activate only an access device corresponding to one or more of the N partitions to be accessed;
Including
None of the access devices corresponding to one or more of the N partitions that should not be accessed are activated
Method.   The step of determining which of the N partitions in the requested row is to be accessed is performed by an address decoder in communication with the array, the address decoder comprising the plurality of row address bits. The method of claim 7, wherein:   The method of claim 7, wherein the array of individual memory cells includes dynamic random access memory (DRAM) cells.   9. The method of claim 8, wherein the address decoder uses an array map to determine which of the N partitions in the request row are to be accessed.   The address decoder sends the plurality of row address bits to a row demultiplexer circuit corresponding to the word line, and further indicates at least which of the N partitions in the requested row is to be accessed. 9. The method of claim 8, wherein one additional signal is sent to the row demultiplexer circuit.   The method of claim 8, wherein the address decoder is embedded in circuitry of the array.   The method of claim 8, wherein the address decoder resides in a separate memory controller for the array. A processor;
A memory controller executable by the processor, wherein the memory controller communicates with a random access memory device having an array of individual memory cells arranged in rows and columns, each memory cell comprising: Each row of the array further includes a corresponding plurality of N word lines, with corresponding access devices, where N is a number corresponding to the number of independently accessible partitions of the array; A memory controller, wherein each access device in a given row is coupled to only one of the N word lines of the row;
An address decoder in communication with the array, which receives a plurality of row address bits, and for a requested row identified by the row address bits, which of the N partitions in the requested row are accessed An address decoder that determines whether it should be activated and prevents an access device that is in the selected row but not in the partition to be accessed from being activated;
Including a computing system. A design structure stored in a storage medium used in the memory device design process,
An array of individual memory cells arranged in rows and columns, each memory cell having a corresponding access device, wherein N corresponds to the number of independently accessible partitions of the array If numbered, each row of the array further includes a corresponding plurality of N word lines, and each access device in a given row is coupled to only one of the N word lines of the row. An array of memory cells,
An address decoder in communication with the array, which receives a plurality of row address bits, and for a requested row identified by the row address bits, which of the N partitions in the requested row are accessed A design structure that includes an address decoder that determines whether to prevent an access device that is in a selected row but not in a partition to be accessed from being activated.   The design structure of claim 15, further comprising a netlist describing the memory device.   The design structure according to claim 15, wherein the design structure is stored in a storage medium in a data format used for conversion of layout data of an integrated circuit.   The design structure of claim 15 further comprising at least one of test data, characteristic data, verification data, program data, and design specifications.

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