TW200907971A - Multiple level cell phase-change memory devices having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices - Google Patents

Abstract

A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

Description

。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 This application is a multi-stage cell phase change memory device with a controlled resistance drift parameter, which is applied by Chang-Wook Jeong et al. and the case in the same period and shared with this application. The memory system of the device, ''first. Multiple-Level Cell Phase-Change Memory Devices Having Controlled

Resistance Drift Parameter, Memory Systems Employing

Such Devices, and Method of Reading Memory Devices, " US Patent Application Serial No. (SAM- 1116), the entire contents of which is incorporated herein by reference. This application is related to a multi-stage cell phase change memory device with a post-programmed operation resistance drift saturation, which is applied by Chang-Wook Jeong et al. and the present application in the same period and shared with this application. Memory system of such devices, and method of reading memory devices (Multiple-

Level Cell Phase-Change Memory Devices Having Post-

Programming Operation Resistance Drift Saturation, Memory Systems Employing Such Devices, and Method of

Reading Memory Devices, Inc., U.S. Patent Application Serial No. <RTIgt; </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Memory or phase change (PRAM) is also known in the art as a phase change. U ^ (〇 UM &gt; ovonic view ^ Μ 01). The 〇 UM unit is based on the volume of the bowl compound alloy, and after heating and cooling, it adopts one of the two, ――J Spear-type phases _ U or amorphous. The resistance of the first phase (Yi's D ^ ', Q day and phase) is relatively low, and the second phase (that is, the amorphous one's electrocardiogram and relative enthalpy. Stylize the singularity into logic One (1) is still a # a — α Μ brother's private volume of the 2 digits of the volume, and fine is determined by measuring its resistance. Crystallization or conduction state is called "set" or "〇,, away. # a ..."舌^^' is not split, or has a resistance non-conducting state to hang "%" or "!" '' state. In order to make the programmable volume amorphous, it can be added by resistance Heating beyond its refining point. In order to crystallize the programmable volume, it can be heated in a short period (for example, '5 〇 加热 加热 加热 加热 加热 加热 加热 加热 加热 加热 加热 加热 加热 加热 加热 加热 、 、 、 、 、 、 、 、 、 、 、 、 When the heater is turned off, the volume (4) is cold!: is a stable amorphous or stable crystalline state. This is made by staging the early 7L into a crystalline or amorphous state: the programmed pair of units The reading can be performed by the resistance of the sense amplifier = single. The key to the phase change memory is chalcogenide. Historically, the device consists of an alloy of 锗 (4), 录 (Sb), and hoof (Te), which is commonly referred to as (10) Hemu... because it is between stable amorphous and crystalline when heated and cooled. The ability to quickly switch is particularly suitable for incorporation into a memory device. The memory cell with a chalcogenide material typically includes a top electrode '130882.doc 200907971 Case layer or chalcogenide material volume and acts as a resistive Heating the element electrode. Figure 1 is a schematic diagram illustrating a memory cell 1 using a programmable chalcogenide material. The cell 10 includes a conductive top electrode 12 formed over the programmable phase metamorphic material 14. Conductive Bottom electrode contacts (BEcm are formed below the programmable material 14. The bottom electrode contacts (formed by a more resistive material such as TiA1N, TiN, and the like) such that when current flows through the BEC The heat is generated and operated as a resistive adder. The access transistor 20 (see Fig. 2 and Fig. 8 is connected to the bottom electrode contact 16 for controlling the flow of current through the cell 1 。. Accessing the transistor 汕It The pole is typically connected to the word line WL of the memory device of unit 10. Figure 2A and Figure 2B are diagrams illustrating the unit 1〇 in each of the two programmed states. In Figure 2A 'The display unit 1 is in the conductivity setting or the τ state. In this state, the portions of the programmable material 14 that are in contact with the coffee are in a crystalline state. In Figure 2, the display unit 处于 is in a resistance reset or In this state, some portions of the programmable material 14 that are in contact with the BEC are in an amorphous state. Figure 3 is a schematic diagram illustrating the electrical configuration of the unit 1 。. The gate of the crystal 20 controls the flow of current through the cell 1 . The start of the bit current IcELL flowing through the cell and the bit line BL connected to the top electrode 12 of the cell 10 is used for writing or stylizing. The state of the unit (7) is programmed during operation and acts as a parameter for reading the state of the unit 1 读取 during a read or sense operation. Figure 4 is a timing diagram illustrating the programming of a memory cell comprising a volume of a programmable chalcogenide material (e.g., of the type illustrated and described above in connection with Figures 1 through 3). d The description is in the conventional reference: the graph shows the temperature vs. time, and the thermal stylized pulse of the reset (the amorphous trr stylizes the material to the set (crystalline) state). Explain the time-reset pulse of the reset pulse (also the curve of the egg field, the curve of the material to the reset (amorphous) shape::: degree pulse); and the curve labeled μ; (d) ((iv) 'Time-temperature relationship for staging the material to the set (crystal), B-pulse). Looking at the curve labeled 22 in Figure 4, in order to change the integrable of the chalcogenide material to an amorphous phase (reset 嶋, the sulphur-like alloy is heated to its sleek point by the resistance J (Tm) The temperature above. The heating pulse is applied in a relatively short period of time (for example, a few nanoseconds). When the heating is turned off, the alloy is rapidly cooled to a lower temperature on the time period (four) (called the quenching period). The temperature of the crystallization temperature Tc of the volume. After the quenching cycle, the volume of the chalcogenide material is placed in a stable amorphous state. See Figure 4 for the curve of 'D main to 24', in order to program the volume Change to crystal phase (set state) 'The alloy can be heated by a resistive heater: a temperature lower than its melting point Tm, for example 'heated to a temperature between the crystallization temperature Tc of the material and the melting temperature Tm. The temperature is longer than the time period Ti for a period of time T2' to allow partial crystallization of the alloy, that is, the atoms in the δδ 材料 material are aligned in their crystalline structure. When the heater is turned off, the alloy rapidly cools below Crystallization temperature of the volume The temperature of L. After the crystallization is reached, the set heating pulse is removed and the material is cooled to a stable crystalline state. The fabrication of a PRAM device having a plurality of programmable states has been performed 130882.doc 200907971 (i. 'Although the above example shows a PRA with two states two: :: (reset) and crystallized (set)... The example has been used with a number of so-called 'amorphous' and amorphous, and the most Experiments were carried out in the PRMA unit of the 5 or intermediate state. ' 叮J only tested. In the intermediate state

’. The stylized volume portion is amorphous and partially crystalline, and the resulting resistance of the early enthalpy can be controlled by controlling the relative percentage of the amorphous and crystalline volume of the programmable material. In this way, each _received list can be considered to have multiple programmable states or multiple orders, each corresponding to a unique resistance value. Research in the field of multi-stage PRAM has been carried out by Ltd et al., entitled "Analysis of phase-transformation dynamics and estimation 〇f amorphous-chalcogenide fraction in phase-change memories" (IEEE 42nd Annual International Reliability Physics) Announcement (Annual International Reliability Physics Symposium) &gt; 2004, Phoenix, pp. 209-215, the contents of which are incorporated herein by reference. Others have determined that the resistance value of the programmed chalcogenide volume can be Change with time. For example, see Pirovano et al., "Low-Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials" (IEEE Transactions on Electron Devices, May 2004 No. 5, No. 51 Vol., pp. 714-719), the contents of which are incorporated herein by reference. The resulting &quot;resistance drift&quot; is in the amorphous state of the second order PRAM cell and in the amorphous intermediate state of the multi-stage PRAM cell and is completely non- This is especially noticeable in the crystalline state. 130882.doc -10- 200907971 In an attempt to control the resistance drift, others have studied the resistance drift power of this sorrow, for example, see Lelmini et al., Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memoriesi, (Journal of IEEE Electronic Devices (ieee Ding (10) Plus - on Electron Devices), February 2007, Vol. 2, vol., pp. 3-8 to 1515, the contents of which are hereby incorporated by reference. Resistance drift is still a difficult problem to solve 'especially in multi-step slant tilting devices.

Embodiments of the present invention are directed to a multi-step, single-to-one memory memory device, a memory system using the same, and a method of reading a memory device, wherein a resistance drift of the device selected for reading is performed by Immediately after it is read, the resistance of the element is controlled to return the resistance of the cell to its vicinity of the initial resistance before the read operation. In a tube, the heat energy pulse is applied to the unit about 100 _ before the reading operation. Immediately before reading the pair of cells = the resistance of the cell is timed to its drift (four) resistance (four) near. In another embodiment, the unit is a multi-level memory unit. The element in the -^ sample, the middle...the S memory device includes: a plurality of memory single-magnification mother Z-invisible body early-inclusive--having a preliminary work in response to the stylized current added in the stylized operation嗲浐p ^ 5 of the memory element material, in the formula (4), the day-to-day (four) week (four), the resistance is changed from the initial resistance 'and the wire of each electric device of the bean, the wire is used in Two:: connected to the memory stream to program the corresponding memory unit to apply the stylized electric application read current to read the corresponding and used to read the resistor in the read operation. An adjustment 130882.doc 200907971 The circuit adjusts the memory cell before the read operation of the memory cell in the plurality of memory cells selected for the read operation - the resistance returns to near the initial resistance. The resistor U is embodied in the memory unit material comprising chalcogenization. In another embodiment, each memory unit is in thermal communication with the corresponding memory unit material of the memory unit and the thermal element A stylized current is received to heat the corresponding record, and the beta cell memory cell material has an initial resistance. The heating element in the embodiment is comprised of an electrode that is in contact with the material of the respective memory, the heating element comprising a component that generates a thermal resistive material. Tiandian--the heating 2: In the embodiment, each memory unit is utilised by the stylizing operation to occupy one of a plurality of states, and the I-state includes a resistance range independent of the range of the adjacent resistance. , wherein the memory is programmed by the stylized operation to occupy more than two states. In another embodiment, the low state of the plurality of states corresponds to a state of the lowest resistance range, wherein the high state pair of the plurality of states is in a state having the highest resistance range, and at least one of the plurality of states The middle two' corresponds to at least one state having a resistance range greater than the lowest resistance range of the low state and less than the highest resistance range of the chirp state. In another example, the adjustment circuit adjusts the resistance of the memory unit by applying an energy pulse to the wire before the memory unit is taken, and wherein the memory unit borrows Programmized by the stylized operation to 4 intermediate state #, the conditioning circuit applies the energy pulse, and when 130882.doc -12· 200907971 the memory unit is programmed to the low state by the stylizing operation or In the south state, the adjustment circuit does not apply this energy pulse. In another embodiment, the wire includes a bit line, and wherein the adjusting circuit adjusts the resistance of the memory cell by applying an energy pulse to the bit line before the reading operation on the memory cell. . In another embodiment, the energy pulse train is applied by a sense amplifier circuit lying down to the bit line. In another embodiment, the energy pulse is generated by a control circuit of the memory device and initiated by a clamp transistor of the sense amplifier circuit. In another embodiment, the energy pulse is applied by a write driver circuit coupled to the bit line. In still other examples, the energy pulse is generated by a control packet of the memory device and initiated by a switching circuit in the write driver circuit. In another embodiment, the energy pulse is applied to the bit line during a precharge operation of the memory cell, wherein the bit line is precharged prior to application of the energy pulse. In another aspect, a read-memory device (the memory device includes a plurality of memory cells, each memory cell including an initial determined in response to a stylized current applied in a stylized operation) The memory cell material of the resistor, the resistance of the memory cell changes from the initial resistance during a time period after the wire-forming operation, and each memory cell is connected to the wire of the dragon device, and the (four) is used for A stylized current is applied in the stylization operation to program the resistance of the corresponding memory unit, and is used to read the current + W in the read operation + wire to take the corresponding memory unit 130882.doc -13 - 200907971 The method includes: adjusting the resistance of the memory unit to return the resistance to the vicinity of the initial blocking resistance before the reading operation of the memory selected for the reading operation; and performing (4) reading the memory unit operating. The memory cell material in 1_' contains a chalcogenide material. In another embodiment, each of the memory units further includes, and stays with the ship - the hole becomes 5

a heating element that is in thermal communication with the corresponding memory cell material, and the method further comprises applying the programmed current to the heating element to add a corresponding memory cell such that the memory cell material has the In the first embodiment, the 'each memory cell is occupied by the stylized operation to occupy a plurality of states, and the # state includes a resistance range independent of the adjacent resistance range of the adjacent one. , wherein the initial resistance of the memory unit occupies an initial state after the stylized operation, and the ancient mysterious 憎 σ, A adjusts the memory selected for the read operation before taking the operation of the surface The resistance of the body unit returns its resistance to the vicinity of the initial resistance to return the resistance of the unit to the resistance corresponding to the initial state. In the alternative, in another embodiment, the memory unit is programmed to occupy more than two states by the stylizing operation. Wang=In another embodiment, the low state of the plurality of states corresponds to a state having a lowest resistance range, and the high state of the plurality of states corresponds to a state having a gamma resistance range, and the plurality of states At least the intermediate Γ U corresponds to at least one bear having a resistance range greater than the lowest resistance range of the low state and less than the highest resistance range of the sinusoid. I30882.doc -14· 200907971 In another embodiment, when the memory unit is programmed to the intermediate state by the stylizing operation, performing an adjustment of the resistance of the memory unit, and when the memory unit borrows When the stylized operation is programmed to the low state or the rfj state, the resistance of the memory cell is not adjusted. In another embodiment, adjusting the resistance comprises adjusting the resistance of the memory unit by applying an energy pulse to a bit line of the memory device connected to the memory unit prior to the reading operation of the memory unit. .

In another embodiment, the energy pulse is applied within about 100 ns before the read current is applied to perform a read operation on the memory cell. The energy pulse is applied to the bit line during the precharge operation of the memory cell, which precharges the bit line prior to application of the energy pulse. In a state where the π and 吣m hip devices comprise a plurality of memory cells, each memory cell includes - having a response to the stylized current applied during the stylized operation t: initial absence: a state of chalcogenide material, the defect state of the memory cell changing from the initial defect state during a time period after the stylizing operation: a wire connected to the memory device per memory cell, The wire is used to apply a stylized current in the stylizing operation to program the defect state of the corresponding memory grass, and i is used to apply a read power in the read operation. The method includes: adjusting a side state of the body prior to the reading operation of the memory unit for the read operation to return the defect state to the vicinity of the initial state; and performing a reading of the memory unit Take the operation. 130882.doc • 15- 200907971 In another aspect, an electronic device includes a memory system including a memory controller configured to be coupled to a data bus, The data bus is transferred to the data signal; and a memory device connected to the memory controller, which stores and retrieves the data. The memory device includes a plurality of memory cells, each of the memory cells including - a memory cell material having an initial resistance determined in response to a programmed electrical vertical flow applied in the stylizing operation. During a period of time after the stylization operation, the resistance of the memory cell changes from the initial resistance, and each memory cell is connected to one of the wires of the memory device, and the wire is used to be stylized in the stylization operation. The current is programmed to encode the resistance of the corresponding memory cell and is used to apply a read current during the read operation to read the resistance of the corresponding memory cell. An adjustment circuit adjusts the resistance of the memory cell to return its resistance to the vicinity of the initial resistance before the read operation of one of the plurality of memory cells selected for reading. In the example, the memory cell material comprises a chalcogenide material. In another embodiment, each of the memory cells further includes a heating element in thermal communication with a corresponding memory cell material of the memory cell, the device receiving the current of the memory to heat the corresponding memory Body unit, making Hai. The ‘1:3⁄4 body material has an initial resistance. In another embodiment, the heating element includes an electrode in contact with the corresponding memory material, the heating element comprising - a resistive material that generates heat when current flows through the heating element. In another embodiment, each memory unit is utilised by the stylized operation to occupy one of a plurality of states, each state including adjacent to the adjacent state. A range of resistance independent of the resistance range, wherein the memory unit is programmed to occupy more than two states by a 5 liter stylization operation. In another embodiment, the low state of the plurality of states corresponds to a state having a lowest resistance range, and the high state of the plurality of states corresponds to a state having a most resistive range, and at least one of the plurality of states The intermediate: state corresponds to at least one state having a resistance range greater than the lowest resistance range of the low state and less than the highest resistance range of the n state. In another embodiment, the adjustment circuit adjusts the resistance of the memory cell by applying an energy pulse to the wire before the read operation of the memory cell and wherein the memory cell is borrowed from the @ The adjustment circuit applies the energy pulse when the program is programmed to the edge intermediate state, and when the secret single TG is programmed to the low state or the high state by the stylization operation, the adjustment circuit This energy pulse is not applied. In another embodiment, the wire includes a one-dimensional line, and wherein the adjustment circuit adjusts the resistance of the memory cell by applying an energy pulse to the bit line before the reading operation on the memory cell. . In another embodiment, the energy pulse is applied by a sense amplifier circuit that is coupled to the bit line. In another embodiment, the energy pulse is generated by a control circuit of the memory device and activated by a clamp transistor of the sense amplifier circuit. In another embodiment, the energy pulse is applied by a write driver circuit coupled to the bit line. In another embodiment, the energy pulse is generated by the control of the memory device 130882.doc 200907971 and initiated by a switching circuit in the write driver circuit. In another embodiment, the energy pulse is applied to the bit line during a precharge operation of the memory cell, wherein the bit line is precharged prior to application of the energy pulse. [Embodiment] The foregoing and other features, features and advantages of the embodiments of the present invention will be more readily described in the preferred embodiments of the invention described herein. Throughout the drawings, the same reference numerals are used throughout the drawings. The image of the present invention is not necessarily to scale, but the emphasis is on the principle of the invention. Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. The same numbers indicate the same elements throughout the specification. It should be understood that although the terms used herein are used to describe various components, the terms are not limited by the five^2 seeking. These terms are used to feed one piece to another element into the file. For example, a first element may be a second element, and similarly, a first element may be referred to as a first element, departing from the scope of the invention. In this article, instead of T1, the term "sI/" is used in the term &quot;and/or associated items. And any and all combinations of the same. It will be understood that when an element is referred to as being "connected" to another element, "on" or "connected" or "coupled" can be directly connected to another element. Or you can ο8·W cattle on the line or coupled to "directly" in the other __ _ sub) into the π pieces. Conversely, when an element is referred to as "directly on" or "directly" or "directly coupled" to another 130882.doc * 18-200907971, there is no intervening element. Other terms of the relationship between components should be interpreted in the same way (for example, &quot; between .., . . . , and directly between &quot;," adjacent, and, directly adjacent," and many more). When an element is referred to herein as being in another element, "above", it may be on or under another element, and may be directly connected to another element or an intervening element may be present, or the element may be a void Or separated by gaps. The use of the present invention is for the purpose of describing the specific embodiments and is not intended to limit the invention. As used herein, the singular forms "-" and "the" are intended to include the plural, and the singular and singular unless the context clearly indicates otherwise. It should be further understood that the term "inclusive" male / + 匕 3 And/or, including, as used herein, the designation of the features, the whole, the operation of the steps, the components and/or components, but does not exclude one or the other features, the whole, the steps The operation of 'components, components and / or its group exists or added. Figure 5 A is for the second-order phase 辔泞 „ „ α α α „ „ 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己FIG. 5B is a schematic diagram of a plurality of different states for a phasic phase change memory cell (in this case, a fourth-order cell) and FIG. 5C is for FIG. 5: As many as ~ 丨丨 eight pills ^ Yang and 5 have a memory of 7L early resistance value / knife for a number of different state of the concept map, m 夂 ..,, explain the effect of resistance drift. ★ Figure A, drawing 1 A second-order unit such as the makeup power of a standard second-order phase change memory cell is called "this technique" in this technology. Footpath, ... - how. After this stylization, the distribution of the obtained resistance values is 1 in the first place, and then in the two states | 丨〇丨丨 and 丨, 丨 由 | Any resistance value belonging to the square of the programmed unit is determined as &quot;〇&quot;, and the blade curve 32 属于 belongs to the range of the second distribution curve 32B ^ the unit of the programmed unit The value of the resistance is judged as "丨,, shape 130882.doc -19- 200907971. In this case, the resistance values corresponding to the first distribution curve 32A and the second distribution curve 3 2B can be easily separated by the boundary resistance value 34. That is, if the determined resistance value is less than the boundary value 34', it is considered to correspond to the "〇&quot; state, and if the determined resistance value is greater than the boundary value 34, it is considered to correspond to the state, Γ, state. Referring to Figure 5, the state of the fourth-order phase change memory cell is depicted. After the unit is privateized, the resulting resistance value can belong to one of the four states &quot;〇〇,&quot;〇1,,, and the actual. The &quot;00" and "u&quot; states are referred to herein. "Become sad" because it corresponds to the resistance at the lower and upper ends of the resistance value range. The final state of the "00" corresponds to the crystalline state of the cell, and the &quot;u &quot; final state corresponds to the amorphous form of the cell. State. The "Q1&quot; and "1G" states correspond to the amorphous state of the middle portion of the single turn, and the "&1" state corresponds to the unit that is programmed to have relatively less amorphous material, and, 1〇 The state corresponds to and has a relatively large number of units of amorphous material. Since more than two can be programmed into a single-unit, multi-level units are beneficial for system integration, although &quot;00&quot; "1 1 " can be a female + mountain, the heart is referred to in this article as corresponding to the "crystal,, and "amorphous" state, but the device's 笪 笪 θ Μ荨,, the state does not have to correspond to "completely Crystallization and "completely amorphous" state Where the volume of the stylizable material is completely crystalline or completely amorphous. On the contrary, the final states can equally correspond to the partial crystallization and the partial # a #彡日日的之, as in the intermediate state, where "”" "final state main A surname a. for", mouth day That is, it contains more crystalline materials than other states, and the final state of "11" is mainly amorphous, that is, contains more amorphous materials than other states. The singularity of the stylized unit belongs to the range of the first distribution curve 36 VIII. 130882.doc •20- 200907971 The resistance value is dissipated to w, the state, the unit of the stylized unit belongs to the second distribution curve 36B Any resistance value within the range is determined to be "〇1&quot; state, and any resistance value of the unit of the mashed unit belonging to the third distribution curve 36C is judged as "1G&quot; state, and the unit to be stylized Any resistance value in the range of the fourth distribution curve 36D is determined as &quot;u,, state&quot; in this case

By the corresponding boundary resistance values 38A, 38C, it is easy to correspond to the first distribution curve of the final state ''(Η)" and "U" and the resistance value of the fourth distribution curve 36D and the adjacent distribution curve 36B. For example, it is considered to correspond to "〇〇" If the determined resistance value is less than the boundary value of 3 8 A, and the resistance value determined by the right is greater than the boundary value 38c, it is considered to correspond. In the "11&quot; state. However, the resistance values of the second distribution curve 36B and the third distribution curve 36C belonging to the intermediate state &quot;01&quot; and &quot;10&quot; are more susceptible to resistance drift phenomena. The susceptibility of this increase is explained. In Fig. 5C, the township sees Figure 5C' to see the effect of resistance drift on the distribution curves 36A, 36B, 36C, 36D corresponding to the four states &quot;〇〇&quot;, 〇1 1〇, "11" in time After the period, the unstable defect in the chemical lattice due to the programmable volume transitions to a more stable defect, and the resistance value corresponding to the drift of the pre-drift distribution curve 36A shifts the curve to the post-drift distribution curve 36A. Ground, corresponding to before drift Distribution curve so that the resistance value drift curve 36B

Shift to the drift distribution curve 36B; corresponding to the pre-drift distribution curve 36C, the resistance value you shift shifts the curve to the post-drift distribution curve 36ci; and the resistance value corresponding to the drift of your shift profile 36D shifts the curve After the drift distribution curve 36D, it can be seen in Η that the 'drift distribution curve 3 6 Α' has been relative to its drift 130882.doc -21 · 200907971

The shift profile 36Λ drifts by a relatively small amount. This is because the resistance value associated with the first eight curve 36A is a result of containing a relatively large amount of crystallized material: a programmable volume formed entirely of crystallized material. Since the crystal lattice of the crucated material contains relatively few unstable defects than the corresponding crystal lattice of the amorphous material, the crystallized material will experience a relatively small resistance drift. = 5C can also be seen that the 'second drift distribution curve 36b, the third drift distribution curve 36C' and the fourth drift distribution curve 36D have been relatively large drift relative to the pre-drift distribution curves 36B, 36C, 36D. the amount. The amount of resistance drift is usually related to the increased amorphous content of the stylized material volume: plus. In the case of a second-order unit (see 圊5A), it is easier to manage the resistance shift because the resistance values corresponding to the two: sorrow and &quot;1&quot; are substantially mutually Separated so that even after a large resistance drift occurs in a long period of time, the #晶形的""

After the drift, the resistance value is still higher than the boundary resistance value 34, and the resulting drift resistance value of the crystalline H is still lower than the boundary resistance value 34. Since only two states are required, resistance drift is not a major concern in standard: order cells. . In the case of multi-level cells having states such as those depicted in Figures 5B and 5C, the management of resistance drift is important. For the "〇〇" and 11 final states, it is easy to manage the resistance drift by setting the appropriate boundary values 38A, 38C. For example, if the boundary value 38 is selected to clearly define the resistance value corresponding to the first-distribution curve 36A (known to be more susceptible to resistance drift), the final state can be easily managed. Resistance drift tube I30882.doc -22· 200907971. Similarly, if the boundary value 38C is selected to greatly exceed the highest of the resulting post-drift resistance values corresponding to the prediction of the third distribution curve 36C', then the ratio can be determined. All of the resulting resistance values for this boundary value 38C are corresponding to the final state "11&quot; 'which is independent of the amount of resistance drift experienced by the resistance value for the fourth drift profile. However, in this example, the slopes ^A, Λn, J T for the 01, and "10" intermediate states require management of the resistance drift. For example, the fastness of the lake before the second drift distribution "more causes the second drift after the distribution curve 36β| passes through the predetermined boundary separating the second intermediate state "01" from the third intermediate state &quot;10, The value is fine. Similarly, the resistance drift of the third pre-drift distribution curve 36C causes the third post-drift distribution curve 36C' to pass through the third state (ie, the intermediate state fourth state (ie, the final state "11,)) The predetermined boundary value of the opening is 38 C. In the case of proper management of the phenomenon of the stimuli, it can be seen that an inappropriate state determination may occur during the subsequent reading operation. The mechanism behind the resistance drift phenomenon is well described in In the paper cited above, it is attributed to the chemical matrix in the stylized volume of chalcogenide during stylization = no release... time lapse 'according to the following chemical relationship, the initial instability is not good (such as 'no Stable C, structure, in which the C table: the compound atom) is transformed into a more stable structure (all: c丨-structure): C3 and 2 c30-^c3++cr are the density pairs of unstable defects ( 1) Therefore, the ^^ body of the material The resistance of the product has a direct effect; the resulting resistance of the Wanghua volume can vary. These instability 130882.doc •23- 200907971 The defect is less common, that is, in the crystallization state, it has a lower density, which is the resistance The drift is more insignificant for stylized to crystallization than for devices programmed to have a certain percentage of amorphous material. μ Includes multi-level cell phase change memory devices, memory using such devices Embodiments of the present invention for a body system and a method of reading a memory device by: adjusting a resistance of a memory cell selected for reading immediately prior to a read operation to cause the cell to be immediately prior to a read operation The resistor returns to its vicinity of its initial resistance (ie, near its initial programmed resistance) to manage the resistance drift of the cell. This operation restores the density of unstable defects in the material to after stylization and before drifting. In the vicinity of the value, in one embodiment, an energy pulse is applied to the cell within about 100 nS before the read operation to heat the cell to achieve this recovery of the resistance value. The effect of the ohmic resistance drift is illustrated in Figures 6A through 6c, and Figures 6A through 6C correspond to the fourth-order element examples illustrated above in Figures 5B and 5C. Referring to Figure 6A, the stylization of the immediately following unit is illustrated. The unit may be sorrowful. The first to fourth states are possible &quot;〇〇, &quot;〇丨,,,, 1〇, and 11, where each of the four states corresponds to a resistance value First to fourth respective distribution curves 36A, 36B, 36C, 36D. As described above, the states are separated by resistance boundary values 38A, 38B, 38c. At this point, immediately after stylization, it can be programmed The volume of the chemical lattice contains relatively high concentrations of unstable defects. For this reason, the programmable volume can be considered to occupy the first metastable state. ~ Referring to FIG. 6B, as described above, as a result of the instability defect becoming a more stable J30882.doc -24-200907971, natural resistance drift occurs in time, so that the second drift distribution curve 36B, the third drift The front distribution curve 36C and the fourth pre-drift distribution curve 36D may become shifted to the second drift distribution curve 36β1, the third drift distribution curve 36C', and the fourth drift distribution curve 36D, thereby causing the above problem. During this time, the stylized volume can be considered to be in a stable state. Referring to Figure 6C, to compensate for the resistance drift, an electrical pulse % is applied to the cell to apply energy to the volume of the programmable material in the cell immediately prior to the read operation. The resulting pulse is operated to bring the cell back almost to its initial resistance value. For example, the second drifting resistance distribution curve 36B, the third drifting resistance distribution curve 36C, and the fourth drifting resistance distribution curve 36D' are immediately shifted to correspond to the recovered second resistance distribution curve. The lower resistance value of the three resistance distribution curve 40C and the fourth resistance distribution curve 4〇D. The class ' can also be returned to the recovered first resistive profile 4GA closer to its initial value in terms of the extent to which the shovel resistance profile 3 6 A is subject to resistance drift. The obtained first-distribution curve, the second distribution curve 40B, the second distribution curve 4〇c and the fourth distribution curve are well defined between the initially defined resistance boundary value 38A, then, between the tears, so that the reading of the single ^ The take operation will achieve reliable results. The pulse is operable to reduce stability: the number of ' 'returns many or all of them to their initial stylized shape' reduces the density of stable defects and increases the density of unstable money. The stylized volume is considered to occupy the second metastable state prior to the read operation. In some embodiments, the electrical pulse is passed to the multi-level memory cell to reference 130882.doc -25.200907971: the resistive response is performed by circuitry connected to the bit line of the cell. In a real "in the example" this operation is performed by a read circuit or sense amplifier connected to the bit line of the memory cell. In another real money, the operation is performed by a bit line connected to the = memory cell. The write driver circuit is executed. Other configurations for transferring electrical pulses to the memory cells immediately prior to the capture operation are equally applicable to the principles of embodiments of the present invention.

▲ Figure 7 is a block diagram of a memory device 2 including a PRAM cell array 210 having a plurality of multi-level phase changeable programmable memory cells, in accordance with an embodiment of the present invention. The pRAM cell array includes an X selector circuit 22G and a Y selector circuit 230 in accordance with a standard memory device configuration. The X selector circuit 22 (), also referred to as a column decoder, receives a column address (RA) signal, and the Y selector circuit, also referred to as a row decoder, receives a row address (CA) signal. Referring to Fig. 7, a phase change memory device 2 according to the present embodiment includes an array of memory cells (4) storing N bits of το (where ^ is 2 or more). A plurality of memory cells are arranged in the memory cell array 21A in a column (e.g., a word line) and in a row (e.g., along a bit line). Each memory unit can be composed of a - switching element and a resistive element. The switching element can be formed of various elements such as MOS transistors, diodes, and the like. The resistive element can be reddish to include a phase change film comprising the gst material described above. Each of the 5 memories can be written to the memory unit. Exemplary resistive elements are disclosed in U.S. Patent Nos. 6,928, 〇22, 6, 967, 865, and 6, 982, 913 each incorporated herein by reference. With continued reference to FIG. 7, column selector circuit 220 is configured to select one of the columns (or word lines) in response to a column address (RA) signal, and row selector circuit 130882.doc -26-200907971 230 The state selects some rows (or bit lines) in response to a row address (CA) signal. Control logic 240 is configured to control the overall operation of multi-level phase change memory device 200 in response to external read/write commands. High voltage generator circuit 250 is controlled by control logic 240 and is configured to generate high voltages for column selector circuit 220 and row selector circuit 230, sense amplifier circuit 260, and write driver circuit 280. For example, a high voltage generator circuit 250 can be implemented using a charge pump. Those skilled in the art will be aware that

The implementation of the high voltage generator circuit 25 is not limited to the embodiment 0 described herein. The sense amplifier circuit 260 is controlled by the control logic 240 and is configured to pass the row (or bit) selected by the row selector circuit 230. Line) Sensing unit data. The sensed lean SAOUT can be externally output via the data input/output buffer circuit 270. The sense amplifier circuit 26 is coupled to the data bus ο: and is configured to supply the sense current I_SENSE to the data bus DL during a read operation. Write driver circuit 280 is controlled by control logic 240 and is configured to supply write current to the data sheet based on the information provided via input/output buffer circuit 270. The bias voltage generator circuit 290 is controlled by the control region 24G and is configured to generate a bias voltage to be supplied to the sense amplifier circuit 260 and the write driver circuit 28A. In accordance with an embodiment of the multi-level phase change memory device of the present invention, in detail, the throttle logic 240 can control the sense amplifier circuit 26 and/or the write driver; the path 280 causes the return current pulse to be applied prior to the sensing operation. Supply to the selected memory unit' to prevent read errors due to resistance drift. In the example: In the embodiment, the amount of the return current can be determined such that the initial resistance value of the respective data state is restored after the supply response = 130882.doc -27.200907971 pulse. The resistance value of the resistive element in each of the selected memory cells can be restored to its initial resistance value by supplying a return current to the selected memory cell immediately prior to the read operation of the cell (also That is, the resistance value that is initially determined when the unit is programmed or the resistance value before the resistance drift occurs). This operation is referred to herein as the reply operation &quot;. After this recovery operation, it is possible to accurately sense the multi-level data from the selected memory cell by supplying the sense current to the remote δ memory unit. Figure 8 is a schematic circuit diagram of one embodiment of a sense amplifier S A 260 of the memory device of Figure 7 in accordance with an embodiment of the present invention. In Figure 8-8, it can be seen that each of the memory cells in one of the rows of PRAM cell arrays 21 is connected to a common bit line BL, which in turn is selectively coupled by a gamma selector circuit 23 Connected to the data line D1 of the memory device 2〇〇. A clamp transistor 263 (in this example, an NM〇s transistor) is coupled between the data line DL and the sense node NSA of the sense amplifier 264. The gate of the clamped electric crystal 263 receives the clamp control signal VCLp. The clamp transistor μ operates so that the data line DL and the connected bit line BL have voltage levels suitable for the read operation of the memory cells. The sense amplifier 264 compares the voltage of the sense node NSA with the reference voltage %^ to provide the output signal S?τ to the data buffer 27A. A precharge transistor 265 (in this case, a PM〇s transistor) is connected between the precharged power level Vpre and the sense node NSA. The gate of the precharge transistor 65 is coupled to the pre & electrical control signal npRE to precharge the sense node NSA to a precharge voltage level during the precharge mode. 130882.doc • 28-200907971 Although only a single sense amplifier circuit corresponding to a single bit line is illustrated in FIG. 8A, it will be apparent to those skilled in the art that additional sense amplifier circuits can be further provided to correspond to the device. Bit organization. For example, in the case where the bit organization of the device is x8, eight sense amplifier circuits can be used. In the case where the bit organization of the device is xl 6, 16 sense amplifier circuits can be used. However, the number of sense amplifier circuits required does not have to be equal to the number of bit structures of the device. Referring to Figure 8A, in this example, sense amplifier circuit 260 in accordance with the present invention includes PMOS transistors 261, 262, and 265, NMOS transistors 263, 266, and 267, and a sense amplifier 264. PMOS transistors 261 and 262 are connected in series between power terminal 268 and sense node NS A at the input terminal of sense amplifier 264. A power supply voltage VCC or a voltage VSA greater than VCC can be applied to the power terminal 268. In this context, the VSA voltage can be a voltage higher than the supply voltage by the threshold voltage of the diode; however, it will be apparent to those skilled in the art that it is not necessary to limit the V S A voltage in this manner. The PMOS transistor 261 is turned on/off in response to the control signal nPBAIS indicating the sensing period, and the PMOS transistor 262 is turned on/off in response to the bias voltage VBIASi (i = 1 to 3). The control signal nPBAIS can be provided from the control logic 240 of Figure 7, and the bias voltage VBIASi can be supplied from the bias voltage generator circuit 290 of Figure 7. The NMOS clamp transistor 263 is connected between the sense node NAS and the row selector circuit 230 (or the data line DL), and is controlled by a clamp control signal or a clamp voltage VCLP to limit the voltage of the bit line BL· or The current applied to the bit line BL is limited. The clamp voltage VCLP operates to maintain the voltage of the bit line below a threshold voltage at which the reset of the corresponding phase change material 130882.doc -29-200907971 volume can be changed. And a return current pulse (eg, 'in quantity greater than the sense current) is supplied to the bit line during the recovery period. The sense amplifier 264 senses whether the voltage present on the bit line b1 is lower or higher than the reference voltage VREF via the row selector circuit 23, and outputs the sensed result to the data input/output buffer circuit 27 7 . In an example, sense amplifier 264 can be configured to sense whether a memory cell is programmed to be in two states. Alternatively, sense amplifier 264 can be configured to sense whether the memory cells are programmed to occupy more than one (greater than two) states. It will be apparent to those skilled in the art that the structure of the sense amplifier 246 can be suitably configured to sense based on the number of programmable states in the multi-order p r m a configuration. PMOS pre-charge transistor 265 is coupled between pre-charge voltage v and sense node NSA&apos; and is controlled in response to pre-charge control signal npRE (e.g., as generated by control logic 24 of Figure 7). The nm〇s transistor is coupled between row selector circuit 230 (i.e., data line DL) and grounded ink and is controlled in response to control signal PDIS (e.g., as generated by control logic 240 of FIG. 7). The NM〇s transistor is connected between the sensing node NSA and the ground voltage, and the PMOS transistors 261 and 262 are controlled in response to the control signal 卩(10) to form a sensing current supply portion, which will be biased during sensing. The current amount or sense current I_SENSE determined by the VBIASi is supplied to the sensing node NSA, that is, the bit line bl. During the sensing period, the sense current L can be shared to the memory by a bit line. The PMOS transistor 265 can constitute a precharge current supply portion that supplies a precharge current to the signal line NSA during the precharge period. Application I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Yuan line. The first home voltage is lower than the second home and should be higher than the ground voltage, and will be described in detail below. It has been determined that the application of the return pulse in the clamp control signal VCLP is relatively α 疋 具有 具有 具有 具有 具有 具有 具有 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约 约The threshold voltage of the multi-level memory cell having a final state corresponding to the highest resistance value (eg, the final state &quot;η&quot; in the example of Figure 6 above). General and ancient, (10) mvkw. In addition, it has been determined that in order to effectively read the ?-resonant element after the return of the resistance drift, the application of the return pulse should be no more than 1 ns prior to the read operation. Figure 2 is a block diagram of a control logic circuit 240 of the above Figure 7 in accordance with an embodiment of the present invention, including a clamp voltage generating circuit 2". Referring to Figure 9, the clamp voltage generating circuit 241 can include a pulse. a generator (10) and a = shifter 241b. The pulse generator 24U is configured to generate a pulse in response to the word line. The level shifter 24A responds to the output of the pulse generator 241a. The first clamp voltage level π and the first-clamp voltage level V2 are operated and supplied. In an embodiment, when the pulse generator 2 output has a low level, the level shifter 241b output has a first The clamp control signal VCLP of the position level vi, and when the output of the pulse generator 2仏 has a high level, outputs a clamp control signal VCLp having the second clamp voltage level V2. According to FIG. 8B For the operation, the home control signal vCLP can be applied to the thin surface of the sense amplifier circuit of FIG. 8A. The clamp 130882.doc • 31 · 200907971 The idle pole of the transistor 263. This example is only for the description of the appropriate pulse number. NM〇s(4) crystal applied to the sense amplifier plus Other suitable mechanisms for the mouth can equally be applied to the principles of the present disclosure. 譲 is a timing diagram illustrating the operation of the sense amplification 260 of FIG. 8a during a read operation in accordance with an embodiment of the present invention. Before describing the read operation, it should be noted that depending on the encoding mode of the plurality of states, the sensing operations to be described below may be performed one or more times. According to an embodiment of the present invention, the first sensing may be performed. (4) Executing ___ times before, which is independent of the number of sensing operations to be performed. Alternatively, the response can be performed before each sensing operation. For more convenience, the multi-order phase change is recorded. The read operation of the L-body device will be described as a packet recovery operation prior to the single-sensing operation. The read operation of the multi-level phase change memory device according to an embodiment of the present invention may include a pre-charge cycle and - sensing Cycle: Before the pre-charging of the bit line BL/sensing point NSA, that is, before the pre-charging period, the control unit has a high level, and the control signal capsule has a low level. The bit voltage VCLp has a first home voltage ^ (example) , 2·2 V). Under this bias condition, 'turn off the crystals of the sense amplifier circuit 260' and the 62 and 265, and turn on the transistor of the sense amplifier circuit 260 and 267 the data line DL and The sensing node NSA is discharged to the ground voltage. At the beginning of the reading operation of the memory unit of the device, the initial pre-charging 预 pre-charges the 70-line BL, the cooling line DL and the sensing node NSA. The appropriate voltage level for the operation is taken. This is initiated by initiating the precharge control letter 130882.doc •32·200907971 nPRE (in this example, by transitioning from "H" to &quot;L&quot;). During the precharge cycle, the control signals nPR]E and pDIS have low levels and the control signal nPBIAS has a high level. When the row select signal γΑ is activated, the bit line TL BL is connected to the data line DL by the switch 230. At this time, the clamp control signal VCLP is at the first clamp voltage level greater than the ground voltage level.

Vl (e.g., 2.2 V) ' causes the clamp transistor 263 to be activated. In this bias strip

Under the precharge period, the data line DL, the connected bit line BL and the sense node NSA are similarly precharged to the appropriate voltage level. In this example, it can be charged to a precharge voltage VpRE equal to the reference voltage VREF applied to the sense amplifier. During the precharge cycle, word line WL becomes active and a resume cycle is initiated to recover the resistance level of the programmable volume in the corresponding memory cell to compensate for the resistance drift in the memory cell. During this recovery period, during the -time period, the clamp control signal mvcLp is pulsed to

The second clamp voltage level V2 (e.g., '3.0 v). The applied pulse of the clamp control signal VCLP is referred to herein as a return pulse. In one embodiment, the second clamp voltage level V2 is greater than the first clamp voltage level... and has sufficient voltage And duration to cause sufficient current to flow through the memory cell via the (10) home transistor 263 to restore the resistance level of the cell to its pre-drift level. At the same time, the second borrow voltage level is not large enough. V2 and its duration are not sufficient to cause sufficient current flow to induce an integratable phase change of the memory cell. During the recovery period, the signal nPRE is kept active. Only the brother's path is after the clamp voltage VLP is free from the recovery period. The initial sensing period 130882.doc -33· 200907971 The second clamping voltage V2 is lowered to the first clamping voltage (as illustrated in FIG. 8b), the control signal nP_low level is converted to a high level, and the control signal nPBIASI is high. The quasi-conversion to the low level. This day, the appropriate bias voltage VBIASi is supplied to the PMOS transistor 262 〇 under this section. ^

Under these conditions, the sense current flowing through the pM〇s transistors- and 262 is supplied to the bit line BL via the NMOS clamp transistor 263 and the row selector circuit 23G. At this time, as shown in Figure 4 (4)

The voltage of the bit line sensing node NSA can be changed to be greater than or less than the reference voltage according to the programmed state of the memory unit. The voltage change of the sense node NSA is sensed by the sense amplifier 264. The sensed data S AOUT is supplied to the data wheel input/output buffer circuit 27A to thereby complete the sensing operation. In another example, the resistive drift recovery operation is performed by a write driver circuit connected to the bit line of the memory cell. Referring to Figure 1 and referring to Figure 7, in accordance with a standard memory device configuration, sense amplifier SA 26 and write driver circuit WD 280 are both coupled to data line DL of memory device 2. In the embodiment described above in connection with Figures 8A, 8B, and 9, sense amplifier circuit 260 and associated clamp voltage generation circuit 241 are responsible for generating a reply pulse signal to effect self-resistance drift recovery. In the present embodiment of Fig. 1, the operation of the sense amplifier circuit 260 is conventionally known, and the write driver circuit WD is responsible for generating a reply pulse signal. The write driver circuit 28 is adjusted to accommodate this additional responsibility. Figure 11A is a schematic circuit diagram of one embodiment of a write driver circuit WD 280 of the memory device of Figure 7 in accordance with another embodiment of the present invention. In Fig. 10 and Fig. 11A, it can be seen that 130882.doc • 34- 200907971 in one row of the 卩尺八河 unit array 21〇 each memory unit is connected to the common bit line BL, and the bit line muscle is borrowed again. The data line 记忆B is coupled to the memory device 2 by the γ selector circuit 230. Referring to FIG. 11A, the write driver circuit 28A can include a driver controller, a selection portion 282, a MOS transistor 283 operating as a pull-up driver, and a transistor 284 operating as a pull-down driver. An NMOS transistor 285. An exemplary embodiment of the driver controller 28 is disclosed in U.S. Patent No. 7, G12,834, the disclosure of which is hereby incorporated by reference herein In detail, in the case of the present embodiment, during the read operation, the drive signal from the drive benefit controller 281 (as in the case of the write operation) is not driven by the transfer via the selection portion 282. A signal is used to control the pull up driver 283. The selection portion 282 receives the reply control signal nRcv and selectively outputs the return control signal nRCV to the pull-up driver 283 and the pull-down driver 284 via the NMOS transistor 285 in accordance with an operation mode. Herein, the reply control signal nRCV is a pulsed signal configured in accordance with a resistance drift recovery operation and may be supplied, for example, by the control logic 240 illustrated in FIG. Continuing to refer to Figure 11A, the selection portion 282 can include a driver "~ and a switch 282b. In response to the mode of operation signal RM, the switch "connects the output of the driver 282a to the gate of the pull-up transistor 283 and the pull-down transistor 2. In this case, when the operation mode signal RM indicates the read operation, the switch 282b is activated, and when the operation mode signal RM indicates the write operation, the start switch 282b is deactivated. In response to the return control signal nRCV, driver 282a drives pull-up transistor 283 and pull-down transistor 284 via switch 282b. I30882.doc • 35- 200907971 For example, when the return control signal nRCV has a low level, the pull-up transistor 283 is turned off and the pull-down transistor 284 is turned on. On the other hand, when the return control signal nRCV has a high level, the pull-up transistor 283 is turned on and the pull-down transistor 284 is turned off. In this paper, the pull/pull drive capability of the driver 2仏 can be set to be greater than the capability of the driver controller 2812PM〇s transistor tr7 and the inverter INV1. As in the above implementation, the effective pulse of the return control signal nRCV can be set to have a duration of about 1 〇 ns_10 及 and an amplitude of about vth_〇 3 volts to about Vth + CM volts, wherein vth is determined to have a corresponding The threshold voltage of the multi-level memory cell of the final state of the highest resistance value (eg, the final state &quot;n&quot; in the example of Figure 6 above). In this manner, the write driver circuit 28 is configured to connect to the data line DL to perform a conventional write drive utility during a write operation, but also to connect the data line DL for supplying a reply control signal during the capture operation. ^ See, the meal will be obvious to the skilled person, the electrical interconnection between the data line and the write drive circuit is not limited to the above configuration, and is used to connect the write driver circuit 28〇 to the data during the read operation. Other configurations of the line for supplying the return control signal nRCV as a pulse signal for recovering the resistance drift of the programmable volume are equally applicable to embodiments of the present disclosure. . . 1B is a timing diagram illustrating the operation of the sense amplifier of FIG. 1Q and FIG. 11A for the write drive to operate during a read operation. As mentioned above, it is in the device. In the read operation of the memory cell, the initial precharge cycle is initiated by the sense node NSA to the appropriate voltage level for the read operation. 130882.doc •36- 200907971 This is initiated by starting the precharge control signal nPRE. At this time, the clamp control nickname VCLP is at a first clamp voltage level VI that is greater than the ground voltage level to activate the clamp transistor 263. The clamp control signal VCLP remains at this first clamp voltage level VI for the duration of the read operation. As a result, during the precharge period, the data line 及1 and the connected bit line BL are similarly precharged to the appropriate level. After the precharge cycle, word line WL becomes active and a recovery period is initiated for retrieving the resistance level in the programmable volume of the corresponding memory cell to compensate for the resistance drift in the memory cell. During this recovery period, the return control signal nRCv is pulsed to a low voltage level for a period of time. The return control signal „〇〇¥ of the applied pulse is referred to herein as a complex pulse”. Via the write driver circuit 280, the selection portion 282 applies the control signal nRCV to the pull-up driver 283. That is, a recovery current pulse is supplied to the selected bit line via the pull-up driver 283. When the recovery current pulse is supplied to the selected bit line B via the pull-up driver 283, the resistance level of the corresponding resistive element of the memory cell can be restored to the initial resistance value. After the return current pulse is supplied to the selected bit line within a given time, the control signal nRCV returns from the low level to the high level, which cancels the pull-up pull driver 283 to be turned off, and I completes the reply operation. The start of a sensing period after the recovery period, and then the normal operation of the sense amplifier for the resistance of the programmable volume in the body unit (and, therefore, the state of the memory unit). Figure 12 is a block diagram of a sub-device 100 comprising a semiconductor device pRAM cell array 130882.doc -37- 200907971 comprising a plurality of multi-level phase changeable programmable memory cells in accordance with an embodiment of the present invention. In various examples, an electronic device (10) can be used as a wireless communication device, that is, a PDA, a laptop, a (four) computer, a connection, a web tablet, a mobile phone, a digital music player, or configured to Any device that transmits and/or receives information in a wireless environment. The electronic device 1A may include an input/output device (4), a memory device 13A, a wireless interface 14A, and a controller 11A that communicate via the bus bar 15G. The controller ιι〇 includes at least one of a (microprocessor) microprocessor, a digital signal processor, or a microcontroller. The input device 12 can include, for example, a keypad, a keyboard, and a display unit. The memory 130 can be used to store commands executed by the controller 11 or can be used to store user data. Memory! The buckle can be advanced to include various β fe bodies. The electronic device (10) can receive data from the wireless communication network using a wireless interface (10) or transmit the data to the network (e.g., via an rf signal). The wireless interface 140 can include, for example, an antenna, a wireless transceiver, and other necessary equipment for poetry wireless communication. The electronic device 100 according to the present invention can be used as a communication interface protocol such as a third generation communication system, that is, CDMA, GSM, NADC, E_TDMA, WCDMA, cdma2_. In an exemplary embodiment, the programmable volume of the memory unit can comprise a chalcogenide material, 丨^, x c . For example, it is composed of Te, Se, S, a combination thereof or an alloy thereof. Alternatively, the 'chalcogenide material may be a material obtained by adding an impurity (e.g., s, C, N, hydrazine, etc.) to Te, Se, S, a combination thereof, or an alloy thereof. Alternatively, the chalcogenide material may be composed of a material selected from the group consisting of Ge, Sb, ; b, Te, Se, S, combinations thereof, and alloys thereof. Or 'chalcogenide material can be added by selecting impurities (for example, 1 C, N, hydrazine, etc.) to select from Ge, Sb, Sn, As, 130882.doc -38-200907971, θ Se s, combinations thereof A material composition obtained from one of the alloy groups. Although the present invention has been shown and described with reference to the preferred embodiments of the present invention, it will be understood that those skilled in the art will understand that the spirit and scope of the invention as defined in the appended claims is not In this case, various changes in form and detail can be made in this document. Although the above embodiment describes a multi-order unit that can be used in two or four units per unit, other numbers of states are conceivable, and - can be applied to the principles of the present disclosure. For example, the I-unit can have a multi-order state of a number that is a multiple of two, such as four, eight, sixteen, and eight equal-shaped carvings. Also - - π &amp; and early can have a number of multiples of a multiple of two, such as three ' _ ^, three three, six, seven equal bears. [Simple description of the figure] ~ θ is a schematic diagram of the element of the programable chalcogenide material used in the brother and sister; [the hidden body early Fig. 2 and Fig. 26 are schematic diagrams illustrating the conventional memory unit in the two passes; Figure 3 is the schematic diagram of the conventional body of Figure 1, Figure 2A and Figure 2B. Figure, · σύ U body early 兀 equivalent circuit Figure 4 is a description of the inclusion of @- private compounding material Stylized timing diagram; (4) Early body; ^ a same. The enthalpy β value W knife is the general view of two different states, the public figure, Figure 5B is for the multi-order single address ^ early 兀 (in this case, The fourth-order unit) divides the resistance value into conceptual diagrams of multiple different states.

Figure 9A, Figure 6B and Figure 6C illustrate the effect of resistance drift; Figure 6A, Figure 6B and Figure 6C illustrate Example of managing the effect of resistance drift prior to a read operation; FIG. 7 is a block diagram of a 5 memory device including a pram cell array in accordance with an embodiment of the present invention; FIG. 8A is an implementation in accordance with the present invention For example, a schematic circuit diagram of one embodiment of the sensing amplification of the memory device of FIG. 8B is a timing diagram illustrating the operation of the sense amplifier of FIG. 8a in accordance with an embodiment of the present invention; FIG. 9 is an embodiment of a control logic circuit of the memory device of FIG. 7 in accordance with an embodiment of the present invention. Figure 1A is a block diagram showing the connection of a sense amplifier and a write driver circuit of a memory device to a data line; Figure 11A is a diagram of the memory device of Figure 7 in accordance with another embodiment of the present invention; A schematic circuit diagram of an embodiment of an input driver circuit. Figure 1β is a timing diagram illustrating the operation of the write driver circuit and the sense amplifier circuit of Figures 1A and 9A in accordance with an embodiment of the present invention; Figure 2 is an illustration of an embodiment of the present invention including A block diagram of an electronic device of a plurality of multi-stage phase change programmable memory cell PRAM cell arrays. [Main component symbol description] 10 Memory unit 12 Conductive top electrode 4 Programmable phase change chalcogenide material/programmable material 130882.doc •40· 200907971 Material 16 Conductive bottom electrode contact (BEC) 20 Take the transistor 22 curve 24 curve 32A first distribution curve 32B second distribution curve 34 boundary resistance value 36A first distribution curve / first drift front resistance distribution curve 36A' after drift distribution curve 36B second distribution curve / second drift before Resistance distribution curve 36B' After drift distribution curve 36C Third distribution curve / Third drift before resistance distribution curve 36C' After drift distribution curve 36D Fourth distribution curve / Fourth drift before resistance distribution curve 36D' After drift distribution curve 38A Resistance boundary Value 38B Resistance Boundary Value 38C Resistance Boundary Value 40A First Resistance Distribution Curve 40B Second Resistance Distribution Curve 40C Third Resistance Distribution Curve 40D Fourth Resistance Distribution Curve 100 Electronic Device 130882.doc -41 - 200907971 110 Controller 120 Input/Input Device 130 memory 140 wireless interface 150 bus bar 200 memory device 210 PR AM cell array 220 X selector circuit / column selector circuit 230 Y selector circuit / row selector circuit 240 control logic 241 clamp voltage generating circuit 241a pulse generator 241b level shifter 250 high voltage generator circuit 260 sense Amplifier circuit 261 PMOS transistor 262 PMOS transistor 263 NMOS clamp transistor 264 sense amplifier 265 PMOS precharge transistor 266 NMOS transistor 267 NMOS transistor 268 power terminal 270 data input / output buffer circuit 130882.doc - 42- 200907971 280 Write Driver Circuit 280' Write Driver Circuit 281 Driver Controller 282 Select Section 282a Driver 282 b Switch 283 Pull Up Transistor / Pull Up Driver / PMOS Transistor 284 Pull Down Transistor / Pull Down Driver / NMOS Transistor 285 NMOS transistor 290 bias voltage generator circuit BL bit line CA row address DL data line ICELL current flowing through the cell INV1 inverter ISENSE sense current nPBIAS control signal nPRE precharge control signal nRCV control signal NSA sense Node PDIS Control Signal RA Column Address RM Operation Signal SAOUT sensed data/output signal 130882.doc -43- 200907971 τι Time period Τ2 Time period Tc Crystallization temperature Tm Melting point/melting temperature TR7 PMOS transistor VI First clamp voltage level / first clamp voltage V2 Second Clamp Voltage Level / Second Clamp Voltage VBIASi Bias Voltage VCLP Clamp Control Signal / Clamp Voltage V PRE Precharge Voltage Level VREF Reference Voltage VSA Voltage WL Word Line YA Row Select Signal 130882.doc -44 -

Claims (1)

200907971 X. Patent application scope: 1. A memory device comprising: a plurality of memory cells, each memory cell containing - having a programmed current applied in a - stylized operation The memory cell material of the initial resistance, the resistance of the memory cell changes from the initial resistance during a period of time after the stylizing operation, and the mother-memory unit is connected to the wire of the memory device, $ The wire is used to apply the stylized current in the stylizing operation to (4) the resistance of the corresponding memory unit, and to apply a read current in the read operation to the Jing Gan # ', #电抓To. Be the first to remember the memory of Yang: "The side of Pingyi is the electric tower, which has one of the memory units, and the complex number is _ ', and the complex number is one of the first reading operations. This resistance of the body unit is restored so that the complex p ^ is close. ...return to the initial resistance of the 也 丨 sc sc sc remembrane unit material spoon a chalcogenide material. w η包 3. The memory device of claim 1, which is programmed to occupy the complex memory unit by the alpha symbol in a plurality of states - the state includes an adjacent state Each circumference, in which the memory unit is surrounded by ..., the resistance of the circuit is programmed to operate more than two states. Redding to account for 4. The memory device of claim 3, wherein 130882.doc 200907971 one of the plurality of states has a low state corresponding to a state having a minimum battery range. One of the plurality of states corresponds to a state having a highest power range, and at least one of the plurality of states corresponds to having the lowest resistance range greater than the low state and less than the high state At least one state of the resistance range of the highest resistance range. 5. The memory device of claim 4, wherein the adjustment circuit adjusts the resistance of the memory cell by applying an energy pulse to the wire before reading the one of the delta memory cells. And wherein when the memory unit is programmed to the intermediate state by the stylizing operation, the adjusting circuit applies the energy pulse 'and when the memory unit is programmed to the low state by the stylizing operation or In the high state, the conditioning circuit does not apply the energy pulse. 6. The memory device of claim 1, wherein the wire comprises a bit line, and wherein the adjusting circuit applies an energy pulse to the bit line before reading the memory cell. The resistance of the memory unit is adjusted. 7. The memory device of claim 6, wherein the energy pulse is applied by a sense amplifier circuit coupled to the bit line. 8. The memory device of claim 7, wherein the energy pulse is generated by a control circuit of one of the memory devices and is activated by one of the sense amplifier circuits. 9. The memory device of claim 8, wherein the energy pulse is applied by a coupling 130882.doc 200907971 to the bit node + #, ,, a good write driver circuit. 10. As requested in Item 6 of the case. An invisible device, wherein the energy pulse system device generates - and is activated by the write driver circuit - the switch circuit. 11. The memory device of claim 6, wherein the energy pulse body unit is applied to the bit line during a precharge operation, wherein the bit line is applied before the application of the meniscus pulse Precharged. ~ 12. A method of reading-memory device, the memory device includes a memory to stay-Λ· sigh one. The body saponin, the mother-memory unit comprises a memory cell material having an initial resistance determined in response to the stylized current applied in the singulation operation, one time period Z after the stylization operation The resistance of the body unit changes from the initial resistance, and each memory unit is connected to one of the wires of the memory device, and the wire is used to apply the stylized current in the red patterning operation to program the corresponding memory. Body single - it. And a resistor for applying a read current in a read operation to 'take the resistor of the corresponding memory cell, the method comprising: reading one of the memory cells selected for a read operation Take operation 4 to adjust the resistance of the 5 memory unit to return its resistance to the vicinity of the initial resistance; and execute the word · one reading operation of the memory unit. The method of claim 1, wherein the memory cell material comprises a chalcogenide material. 14. The method of claim 12, wherein each memory unit is programmed by the stylizing operation to occupy one of a plurality of states, each state package 130882.doc 200907971 2:, the second phase A range of resistances independent of the range of adjacent resistances, where: ΙΓ the initial resistance after the stylized operation (four)-initial:! state::: the operation of the memory selected for the -read operation 7L early Pre-adjusting the memory star _t^0$. The resistor of the body is early to cause the resistance of the memory cell to return to the resistance within a range corresponding to the initial state. . 15. If the method of item 14 is printed, 苴 from the 一 Τ Τ ° α 己 己 己 早 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉. Formulated to occupy more than two states. The method of claim 15 wherein: the plurality of states - the low state corresponds to the state of having - the lowest resistance dry circumference, and one of the plurality of states corresponds to one having one a state of a highest resistance dry circumference, and at least an intermediate state of the plurality of states corresponds to a resistance range having a minimum resistance range greater than the low level and less than the highest resistance range of the still state At least one state. 17_If the method of claim 16 is used, - Υ田0哀0己隐身早7L by the stylized stay: 程式 and stylized to the intermediate state, performing the adjustment of the memory unit&quot; * When the memory unit is programmed to the low state or the high state by the stylizing operation, the resistance of the memory unit is not adjusted. 1 8. The method of claim 12, and ', the mid-tone, ie, the s-shear resistance, comprises applying a pulse to the connection by reading a read operation from the one of the 'L body units. The singularity of the hexaural unit is adjusted to the bit line of the U body device to adjust the resistance of the memory 130882.doc 200907971 unit. 1 9. If the request item 1 $ $古, &lt; 万法' where the reading current is applied to perform on the memory single 亓 # & & 早 早 早 早 早 早 早 早 早 早 早 早 早 早 早 早This energy pulse is applied within ns. 20. The method of claim 18, wherein the energy pulse is applied to the bit line during a precharge operation of the memory cell, wherein the bit line is precharged prior to application of the energy pulse. 21. A method of mastering a memory device, the memory device comprising a plurality of memory cells, each memory cell comprising a decision having a response to a stylized current applied in a stylized operation The chalcogenide material in the initial defect state, the defect state of the 5 Xuan S memory element changes from the initial defect state, and each memory cell is connected to the memory in one week/month after the stylization operation a wire of the device for applying the stylized current in the stylizing operation to program the defect state of the corresponding memory cell for use in a read operation Applying a read current to read the defective cancer of the corresponding memory unit', the method comprising: adjusting the memory unit in a read operation of a memory unit selected for a read operation The defect state returns its defect state to the vicinity of the initial defect state; and performs a pair of read operations of the memory cell. 22. An electronic device comprising a memory system, the memory system comprising: a memory controller configured to connect to a data bus, 130882.doc 200907971 to transfer a data signal at a data bus; And the memory device, which stores and is connected to the memory of the memory controller, takes a data signal, the memory device includes: a plurality of memory units, and the mother-S memory unit includes one The 5th memory cell material of the initial resistance determined in response to a stylized current applied in a stylized operation 'in one time period after the stylizing operation' is the resistance of the memory cell from the initial resistance Changing, and each memory cell is coupled to one of the wires of the memory device, the wire being used to apply the stylized current in the stylizing operation to program the resistor of the corresponding memory cell and to Applying a read current during the continuation operation to read the resistance of the corresponding memory unit; and - Adjustment circuit Several memory single i sections are near the memory i. 130882.doc