TW200907380A - Semiconductor device, a method of manufacturing a semiconductor device and a testing method of the same - Google Patents

Abstract

A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device.; In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

Description

200907380 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, and a method for measuring a semiconductor device, such as a semiconductor wafer, such as a microcomputer, and a dynamic RAM. A technique in which a semiconductor wafer (random access memory) is mounted on a multi-wafer configuration of one package, a multi-layer laminated system-in-package structure, or a device of a plurality of semiconductor packages. [Prior Art]

Advances in semiconductor technology have opened up the directionality of a technology for forming a semiconductor device in a package type as a whole for a plurality of semiconductor wafers for forming an electronic system for a microchip or a dram wafer. For example, when a microprocessor or a dynamic RAM (DRAM) is used to select a combination of semiconductor chips that are closely related to each other, a "solid system can be mounted in a package to implement a so-called Slp (System in Package). An example of a +-conductor device having a multi-wafer structure is disclosed in Japanese Laid-Open Patent Publication No. 2004-235352. On the other hand, as an example of using a built-in ICE (circuit emulation debugger) module in an aging test system for a microcomputer chip and an aging test method, there is a Japanese Patent Publication No. 2006-038678. As a semiconductor package which is different from the above-described type of SiP, there is a package stack described in Japanese Laid-Open Patent Publication No. Hei. No. 2-123454 (Package on the above-mentioned SlP on which a plurality of wafers are mounted on a block wiring substrate, for example, A wiring board structure for mounting a microcomputer chip = a package including a wiring board on which a memory chip is mounted, and a wafer to be connected to each other to form a laminated package of the system. 1308I9.doc 200907380 [Patent Japanese Unexamined Patent Application Publication No. Publication No. No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. Publication No. No. Problem] In the SiP semiconductor device as described above, it is necessary to perform the test of whether the microcomputer chip and the dram perform the function correctly before shipment in the SiP assembled by screening the good wafer. The progress of the DRAM by the semiconductor technology, 1 The wafer has a memory capacity as large as, for example, 256 M. In the inventors of the present invention, 'in order to easily perform a test of a memory circuit having such a large memory capacity, As shown in Fig. 23, the test external terminal connected to the address terminal ad of the S-remembrance circuit and the control terminal CN' data terminal DT is set at 8 kg, and the address busbar and the control are provided on the test substrate. The ## and data bus are connected to a plurality of tested devices SiP1~SiPn'. The test device directly performs the test of the memory circuits of the tested devices SiP1~SiPn. However, as the above memory circuit, the use of double data rate is used. Synchronous DRAM (Double Data Rate-Synchronous Dynamic Random

In a high-speed memory circuit such as Access Memory (hereinafter referred to as ddR-SDRAM), it is necessary to use an expensive high-speed test device. Therefore, in the inventor of the present invention, etc., in order to be suitable for having such a high-speed memory circuit, 130819.doc 200907380

SiP, probe + 4 due. 'J is the test system shown in Figure 24. The peripheral circuit formed by the FPGA (Field Programmable Gate Array) and the flash memory FLH storing the test program are set on the test substrate corresponding to the device to be tested to SiPn. The peripheral circuit is mounted on the test substrate, and the test procedure is taken out by the flash memory FLH to test each of the tested devices sipi~sipn at the actual operating frequency, and the determination result is sent to the test device. However, in this configuration, since the peripheral circuit composed of the FPGA is mounted on the test substrate, the price of the test substrate is increased, and the number of devices to be tested that can be mounted on the test substrate is also limited, so that the test efficiency is also improved. difference. This is also the same in the semiconductor device of the P〇P structure. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device for miniaturizing Sip or p〇p and a method of manufacturing the same. Another object of the present invention is to provide a test method suitable for implementing Sip or p〇p for system, system simplification and efficiency. The above and other objects and novel features of the present invention will become apparent from the description and appended claims.

[Technical means for solving the problem] One of the embodiments of the method for manufacturing a semiconductor device disclosed in the present invention is as follows. A second semiconductor device having a first memory circuit is formed. An electrical test of the first semiconductor device described above is performed, and a good product is screened. A second semiconductor device having a signal processing circuit for performing signal processing in accordance with a program and a second memory circuit is formed. Performing the second semiconductor device

Ha m cool one by one _, called the industry good. The above-described first semiconductor device and the second semiconductor device are integrally formed, and the respective terminals are connected to each other. The semiconductor device having the above-described structure of 1308I9.doc 200907380 is mounted on a test substrate and subjected to an electrical test to determine whether or not the semiconductor device is good or not. In the determination of the quality of the semiconductor device, the test substrate is provided with an oscillation circuit that supplies a clock signal corresponding to the actual operation of the semiconductor device to the plurality of semiconductor devices in a common manner. In the first! In the operation, the first semiconductor device will be implemented by the test device! Test program for memory circuit operation test: The second memory circuit of the second semiconductor device. In the second operation, the signal processing circuit of the second semiconductor device is configured to perform the first semiconductor device in accordance with the test program written in the second memory circuit in accordance with the pulse-receiving number. The action test of the body circuit. In the third embodiment, the result of the determination of the quality of the second operation is output to the embodiment of the test method of the semiconductor device disclosed in the present invention. The semiconductor device integrally constitutes the first semiconductor package and the semiconductor device, and includes a connection mechanism for connecting the corresponding terminals to each other. The first semiconductor device includes a first memory circuit, and the second semiconductor device includes a second memory circuit, a signal processing circuit for performing a program operation, a two-sided circuit connectable to the first memory circuit, and The user debugs the interface circuit. The above-described semiconductor device is mounted on the test substrate with a vibrating circuit s which forms a clock signal corresponding to the actual operation of the semiconductor device, and the clock signal is supplied. In the i-th operation, the test program for performing the operation of the i-th memory of the i-th memory by the test device is written into the second memory circuit of the semiconductor farm via the user-interrupting interface circuit. In the second operation, the operation test of the second memory circuit is performed in accordance with the above-described written test program in response to the clock signal by the 130819.doc 200907380 nickname processing circuit. In the third operation, the result of the determination of the quality of the second operation is output to the test device. One of the embodiments of the semiconductor device disclosed in the present case is as follows. In the semiconductor device, the terminals corresponding to the first semiconductor device and the second semiconductor device are connected to each other and integrally formed. The first semiconductor device includes a first memory circuit, and the second semiconductor device includes a second memory circuit, a signal processing circuit for performing a signal processing operation according to a program, and a interface circuit connectable to the first memory circuit and The user debugs the interface circuit. The user error debugging interface circuit can be used to store the S-resonance test program of the second hidden circuit in the second memory circuit, and the external terminal does not have direct access to the second semiconductor device. 1 External terminal of the memory circuit. ~ [Effects of the Invention] Since the microcomputer chip performs the test of the memory chip in accordance with the program of the built-in memory circuit of the microcomputer, the external terminal for testing is not required, and the semiconductor device for SiP or P〇P can be miniaturized and The test system is simplified and streamlined. [Embodiment] FIG. 1 is a schematic flow chart for explaining an embodiment of a method of manufacturing a semiconductor device of the present invention. In the step (1), a plurality of CPU chips are formed on the semiconductor wafer. Thus, at the time of forming the cpu wafer on the semiconductor wafer, a tester (1) is performed by the tester. The CPU described above has a δ 忆 体 体 n n n j j j j j j j j j j j j j j j j j j j j j j j j j j j j j (10) From the user's (4) break, etc., the interface is used to form a memory chip. This is the same as the formation of a memory chip on the semiconductor wafer. (3) Ten-Λ 探测 Detecting test (2) 叼 (1), sieving β 仃 forming a slice of the semiconductor wafer after the above CPU chip. The above probe test (1) is judged to be a good CPU crystal ==) The semiconductor wafer after the memory chip is in the above-mentioned probe test (1), and the memory is determined to be a good product. In the step (7), the cpu wafer which is determined to be good in the above step (3) is In the step (4), the memory wafer determined to be good is loaded on one of the load substrates, and the internal wiring formed on the load substrate is connected to each other, and C: is connected to the external terminal. The resin is sealed and assembled as a semiconductor device in appearance. In the step (6), the screening test after the assembly is performed, and if necessary, the aging test is also performed. When the test substrate used in the screening test is loaded The generating circuit CKG supplies a high-speed clock signal corresponding to an actual operation to the semiconductor device (PKG) configured by the above (10) mounted on the test socket. The tester is a plurality of tested devices mounted on the test substrate. KG, accessing the CPU chip via the user debug interface circuit, and writing the test program of the memory chip into the built-in I308I9.doc 200907380 memory circuit. Thereafter, the CPU chip is activated and stored in the above Built-in memory, and access to the memory chip according to the program, obtain the good/decision result' to transfer it to the tester. The test of the CPU chip itself also accesses the ICE via the above-mentioned user debug interface circuit (circuit simulation debugging) The module performs a test of the peripheral circuit including the CPU and the built-in memory circuit. From the test result, the shipped CPU chip and the memory chip are judged to be good SiP. In the screening test of this embodiment In the same manner as the above-mentioned Sip actual action, the CPU chip repeatedly performs writing/reading of the suffix cell corresponding to the clock signal described above. The memory chip is subjected to a memory test. The input of the program for the test is performed by the tester simultaneously on the plurality of SiPs mounted on the test substrate, and in the plurality of SiPs loaded on the test substrate, according to Each of the input programs performs the test of the memory chip in parallel at the same time, so that the memory circuit as described above can be terminated in a short time and even if it is a circuit having a large memory capacity. Fig. 2 shows one of the sips of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a schematic cross-sectional view, and FIG. 2(B) is a top view showing a microcomputer chip 2 as described above and a DDR-SDRAM wafer 3 as described above. On the surface side of the loading plate 1, The microchip wafers 2 are mounted, and are respectively connected to the wiring patterns provided on the upper surface of the mounting substrate by the bonding wires 4. The microcomputer chip 2 and the DDR_SDRAM wafer 3 are made of a so-called bare wafer and are soldered to the mounting substrate. The above microcomputer chip 2 may also have a plurality of bump electrodes which are surface-attachable to the mounting substrate. For example, if necessary, it is also possible to form an insulation which can be formed by, for example, a polyimide resin on a circuit formation surface of a semiconductor wafer after completion of components and wiring through a so-called area array 130819.doc -12-200907380 The wiring of the pad electrode (solder pad) is further disposed on the film, and the wiring is formed by a technique of forming a pad electrode (a bump surface electrode for bump connection). By the technique of the above-mentioned area array pad, the pad electrodes which are arranged at a small pitch of several tens of μm to 1 pitch as the external terminals of the micro-shadow film 2 can be converted into a path of, for example, 0 J mm to 0 2 mm, and A pad arrangement of a larger pitch of 400 μηι to 600 μιη pitch. The mounting substrate 1 is formed with an insulating substrate made of glass epoxy or glass, a thin internal wiring formed of a multilayer wiring formed on the insulating substrate, and an electrode for wire bonding. The main surface side of the loading microchip 2 and the DDR-SDRAM wafer 3 on the loading substrate 1 includes a bonding wire 4 and is closed by the sealing body 5. A solder ball 6 as an external terminal is provided on the back side of the loading substrate 丨. . Figure 3 is a block diagram showing an internal block of one embodiment of the Sip of the present invention. In the same figure, the relevant part of the aforementioned screening test is centered. The semiconductor device (SiP) 1 of the present invention is composed of a microcomputer chip 2 and a memory chip 3. In addition to the cpu (central processing unit), the microcomputer chip 2 has a built-in ICE (circuit simulation debugger: self-diagnostic circuit) module. The coffee module is not particularly limited, but has a JTAG interface circuit and is connected to the external terminal JTAG. Further, in the microcomputer chip 2, in addition to the built-in memory and peripheral circuits of the static RAM, a memory interface circuit MIF corresponding to the memory chip 3 is provided, and the memory interface circuit MIF is directly connected. To the above memory chip 3. The memory chip 3 is not particularly limited, but is composed of a DDR-SDRAM having a high speed and a large memory capacity of 130819.doc -13 - 200907380. The input/output terminal I/O is an external terminal provided for separately testing the memory chip 3. The external terminal I/O is not required as the screening test itself of the present invention, but it can be used, for example, as an input terminal for performing an aging test before the screening test as a memory chip. Figure 4 is a block diagram showing the internal block of one embodiment of the SiP of the present invention. In the same figure, the connection relationship between the microcomputer chip 2 and the memory chip 3 is shown centering. The memory chip 3 is a DDR-SDRAM. Terminal CKE is the clock input terminal. The terminal CSB is a wafer selection input terminal. Terminal BA[1:0] is the stack address input terminal. Terminal A[11:0] is the address input terminal. Terminal DQ[31:0] is the data input and output terminal. Terminal RASB series address strobe input terminals. The terminal CASB is the row address strobe input terminal. The terminal WEB is written to the valid input terminal. Terminal DQS[3:0] is the data strobe input and output terminal. DQM[3:0] is the DQ write hood effective input terminal. Terminals CLK and C L K B are clock input terminals. In the microcomputer chip 2, each of the output terminals DDRCKE, DDRCS_N, DDRBA[1:0], DDRA[11:0], DDRRAS-N which are directly connected to the input terminal and the output terminal of the DDR-SDRAM as described above, respectively. DDRCAS_N, DDRWE_N, DDRRDM[3:0], DDRCK, DDRCK-N, with each input and output terminal DDRD[31:0], DDRDQS[3:0]. In the same figure, in the memory chip 3, a B is attached to the terminal name as in the case of CSB, and a bar signal indicating that the low level is an effective level is indicated. Corresponding to this, in the microcomputer chip 2, as the DDRCS_N, the _:^ is attached to the end of the terminal name to indicate a negative signal for making the low level an effective level. 130819.doc 14 200907380 In the present embodiment, in a semiconductor device such as a SiP, a test for connecting the wiring between the electro-cured wafer 2 and the memory chip 3 is provided by using the test. For the terminal, for example, the memory chip can be directly accessed. The microcomputer chip 2 is provided with a terminal JTAG connected to the user interface circuit of the microcomputer chip 2. Fig. 5 is a block diagram showing an embodiment of a screening test for the semiconductor device shown in Fig. 4. On the test substrate, a clock generation circuit CKG for supplying a clock signal corresponding to the actual operation of the sipi to sipn of the device under test is provided. In the test substrate, the test devices sipi~sipn do not connect the test terminals (address terminal AD, control terminal cn, and data terminal DT) to the aforementioned test device, and the JTAG terminals are commonly connected to the test device. Although there is no special restriction, when the aging test is performed, the operating voltage higher than the actual operating voltage can be supplied. In the high temperature atmosphere, the test terminal address AD, the control CN terminal, and the data terminal 〇7' are used for the above test. The device performs memory access at a frequency lower than the actual action to find initial failure. Further, the test terminal is quite convenient in performing a test for confirming the direct current connection between the memory chip 14 and the cpu chip 12. Figure 6 is a diagram showing the internal block of another embodiment of the SiP of the present invention. In the same figure, 'the connection relationship between the microcomputer chip 2 and the memory chip 3 is shown. In the present embodiment, the test terminals connected to the memory chip 3 as shown in Fig. 4 described above are omitted. That is, the memory chip 3 terminal CKE, terminal CSB, terminal ΒΑ [ι: 〇], terminal A [11: 〇], DQ [31: 0], terminal RASB, terminal CASB, terminal WEB, terminal I30819. Doc -15- 200907380 DQS[3:0], DQM[3:0], and CLK and CLKB are respectively connected to the terminals DDRCKE, DDRCS_N, DDRBA[1:0], DDRA[11:0] of the microcomputer chip 2, DDRD[31:0], DDRRAS_N, DDRCAS N ' DDRWE-N, DDRDQS[3:0], DDRRDM[3:0], DDRCK, DDRCK-N are only connected to each other. Fig. 7 is a block diagram showing an embodiment of the screening test of the semiconductor device shown in Fig. 6 described above. On the test substrate, a clock generation circuit CKG' is provided for supplying a clock signal corresponding to the actual operation of SiP1 to SiPn of the device under test as described above. On the test substrate, the test devices SiP1 to SiPn commonly connected the JTAG terminals to the test device. In the present embodiment, as described above, the screening test of the memory chip 3 is performed by the above-described JTAG, and the memory test terminal is not required in the memory chip 3, so that it can be omitted. By using the manufacturing method of Sip including the screening test procedure for the memory chip 3 using the above-described JTAG microcomputer chip 2, it is possible to greatly reduce, for example, about 6 外部 external terminals in the Sip manufactured thereby. As a result of the reduction of such an external terminal, the size of the package can be reduced in the semiconductor device (SiP) 1. Further, since wiring suitable for the memory terminal for connecting the wiring between the microcomputer chip 2 and the memory chip 3 is not required, the wiring layer of the portion can be reduced. Therefore, as the mounting substrate of the SiP, it is possible to use a mounting substrate which is inexpensive and has a small number of wiring layers, and it is possible to greatly reduce the parasitic electric valley between the microcomputer chip 2 and the memory chip 3. Such a reduction in the parasitic capacitance makes it possible to reduce the current of the microcomputer chip 2 and the output circuit of the memory chip 3 which are charged/discharged, so that the operation speed can be increased and the power consumption can be reduced. 130819.doc -16 - 200907380 (1) The microcomputer chip 2 is generally provided with a user-debug interface circuit such as HUDI (High Performance User Debug Interface) as sold by the SH series of microcomputer chips sold by the applicant. The HUDI can perform read and write of a scratchpad with internal memory based on a few pins of jtag. The memory test program of the memory chip 3 can be stored in the internal memory of the microcomputer chip 2 by using the user debugging circuit, and the memory test program is executed by the CPU of the microcomputer chip 2 to perform the memory chip. Screening test. Of course, the user debugs the internal circuitry of the microcomputer chip 2 used to perform the original function. The outline of the procedure for writing and executing the memory test program of the internal memory of the microcomputer chip 2 is as follows (): (:1)1; the "reset hold" state is set. (2) Write the data to ASERAM. (3) Execute "HUDI Startup" (4) Write the δ 忆 体 测 s program to the internal RAM. (5) Confirm that the memory test program has been written normally. (6) Start the memory test program. (?) Wait for the memory test to end and confirm the result. In order to execute the memory test program, it is necessary to write the memory test program to the internal memory of the microcomputer chip 2 in advance. Consider the capacity of the memory test program. Suppose that the memory test program is written to the internal RAM of the microcomputer chip 2 (for example, static random access memory). For example, in the "SH micro-electric" chip, in order to perform writing to the internal ram using the HUDI, there is a "HUDI write command" or a "ASERAM write command". The "ASERAM Write Command" is a write command dedicated to ASERAM. In order to perform writing to the internal RAM, the "HUDI Write Command" can be used, but this command cannot be used if it is not in the state of the CPU execution. In order to make the 130819.doc 200907380 CPU in motion, it is only necessary to reset the CPU and then start it. However, when it is reset without preparation, the program executed by the CPU becomes uncertain and does not know how to perform the action. In the writing of the memory test program, the CPU may unexpectedly stop responding, and may also overwrite the written data. If only the CPU is reset and then restarted, writing with the "HUDI Write Command" and confirming the written data with the "HUDI Read Command", it is expected that the written data will not be read. Therefore, in the present embodiment, "reset hold" and "HUDI start" are utilized. "Reset Hold" is a state in which the program is written to ASERAM in order to reset the CPU and "HUDI Start" is a means of executing a program written in ASERAM. Write the program to ASERAM with "ASERAM Write Command". During this execution, the memory test program is written to the internal RAM. It is also possible to read the data in the "reset hold" state and confirm the written data. Fig. 8 is a view showing a state transition diagram of the JTAG TAP (Test Access 使用) used in the present invention. In the same figure, the '0' or 'Γ' next to the arrow indicates the TMS (test mode) terminal or the state when the signal is or 'Γ. In general, the C ^ " TAP control transition diagram is more abstract and difficult to understand, but it is only written to the command register (hereafter referred to as IR), and the implementation of the data register (hereinafter referred to as DR) Read and write only. Both the command code and the data read and write have multiple bits, so it means that only one TDI (test data input) terminal inputs data in the shift state series. State (1) (Test-Logic-Reset) is a HUDI reset that causes the TMS signal to be at a high level to generate 5 TCK (Test Clock) signals to this state (HUDI reset). State (2) (Run-Test/Idle) is a pass point. The test logic without ic is only activated when there is a special order of 130819.doc -18- 200907380. For example, if the self-test is activated by a command, this command is executed when this state is rendered. In addition, the test logic is rendered idle. State (3) (Select_DR_Scan) is the read/write state of DR. The lower side of the graph (TMS = 0) is the execution state, and the right side (TMS = 1) is the non-executing state. State (8) (Select-IR-Scan) is the read/write state of IR. The lower side of the figure (TMS=0) is the execution state, and the lower side (1^8 = 1) is the non-execution state. 'Return to the above state (1) . The state (4) (Capture-DR) reads the state of the data. The state (9) (Capture-IR) is the state in which the data is read. State (5) (Shift-DR) is the setting state of reading and writing data. The state (l〇) (Shift-IR) is a setting state of reading and writing data. State (6) (Exit-DR) is a simple passing point state. The state (ll) (Exit-IR) is simply the passing point state. Status (7) (Update-DR) is the write status of the data set. Status (12) (Update-IR) is the write status of the data set. Figure 9 is a waveform diagram showing an embodiment of a JTAG TAP (Test Access 使用) used in the present invention. In the same figure, an example of reading and writing data registers is shown. The read and write of the scratchpad can be completed at the necessary length, in this case set to 8 bits. First, the TMS signal is held at the high level 1') 5 times after the TCK share, and the TAP is reset (state R). Thereafter, when the rising edge of the generation is reached, the TMS signal is changed to |〇·-|1|-|〇, and the state is changed to the above state (2) (Run-Test/Idle)_

State (3) (Select-DR-Scan) - State (4) (Capture-DR) ° Briefly indicate its status as I-S-C. In the above state (4) (CaPture-DR), the data is fetched, and in the next state (5) (Shift-DR), the data to be fetched is output from the TD (test data output) terminal, and the data to be written is set. . State 130819.doc •19- 200907380 (5) (Shift-DR) includes 8 cycles of SO to S7 'Data of DiO to Di7 input by TDI serially' D_0 to D〇7 are output by TDO. After the 8th cycle (S7) of this state (5) (Shift-DR), the TMS signal is changed to '1' - and the state is changed (6) (Exit-DR) - state (7) (Update-DR ) - State (2) (Run-Test / Idle). The state is briefly indicated in the manner of E-U-I. Therefore, when the scan of one time is completed, the state (2) (Run-Test/Idle) is returned in advance, and it is easy to understand. The set data is updated in Status (7) (Update-DR). The above-mentioned "reset hold" means that the state of writing to the ASERAM can be performed by the "ASERAM write command" although the CPU is in the reset state. The transition method causes the terminals or signals /RESET and /TRST to be low. When switching between the product chip mode and the EVA chip mode, when using the HUDI function, it is necessary to switch to the EVA chip mode in advance. As described above, the reset/hold state can be set by setting the terminals /RESET and /TRST to a low level for a certain period of time. This reset period requires a certain amount of time. Fig. 10 is a waveform diagram showing the HUDI startup. In order to perform HUDI startup, it is only necessary to set the "HUDI Startup Command" to IR when resetting the hold state. The IR system is a 16-bit scratchpad. The lower bit is any value (don't care), so only the upper 8 bits are set. Similarly to the above-described FIG. 9, the state R (Test-Logic-Reset)-I (Rim-Test/Idle)-SD (Select-DR_Scan)-SI (Select-IR-Scan)-C (Capture-IR) is performed. When the above state (l〇) (Shift-IR) is executed while changing, a fixed value can always be output from the TDO (test data output) terminal. When observing this TDO terminal, you can know that the IR path has been executed. When the "HUDI Start Command" is executed, it becomes "ASE interrupt 130819.doc -20- 200907380 mode" and is executed by the address written to the start address of ASERAM. At this time, since the ASE interrupt flag has been set, it is confirmed that the ASE interrupt mode has been presented when the flag is viewed using the "HUDI read command". Figure 11 is a flow chart showing one embodiment of an ASERAM write mode. First, in step (1), the SI (S elect-IR-Scan) state is set and the command is written. In step (2), the address to be written is set. Configure the set data at the start and end addresses. For example, the above bits of 16 bits specify the start address, and the following bits of 16 bits specify the end address. The upper 12 bits of the address are fixed in the area where the ASERAM is configured. After setting the data to DR in steps (3) to (6), repeat SD (Select-DR-Scan) until the transfer flag is set. Figure 12 is a flow chart showing one embodiment of a HUDI write mode. HUDI writes have separate mode and continuous mode, with write byte number 1, 2, and 4 byte patterns, respectively. An example of continuous mode writing is shown in the same figure. In step (1), the SI (Select-IR-Scan) state is set and the command is written. In step (2), set the address to be written. In steps (3) to (6), in HUDI write ί ) j, it is confirmed that the flag is set once for the first time, and the flag is set twice after the second time, and the DR of the first and second times is changed. -Scan number. - Figure 13 is a flow chart showing one embodiment of the HUDI read mode. There are separate modes and continuous modes as well as HUDI writes, and each has a write byte number of 1, 2, and 4 byte patterns. In the same figure, as in the writing of Fig. 12, it is only the continuous mode. In step (1), the SI (Select-IR-Scan) state is set and the command is written. The readout is such that the test result is generally a hypothetical digit level, so it is confirmed that the flag can be read. Therefore, in the steps (3) to (6), when the "HUDI read command" is used for 130819.doc -21 - 200907380, the individual read of each DUT is used. The test operation of the external memory chip using the aforementioned ICE module is as described in the following (1) to (6). (1) As described above, the CPU chip is placed in the reset state. In this state, the data can be written to the RAM (ASERAM) in the ICE module of the CPU chip. To perform this operation, the tester controls the aforementioned terminals of the JTAG specification and the dedicated terminals of the CPU chip. (2) Write the program to the above RAM in the ICE module. This program is used to support the transfer of test programs. The tester uses the JTAG pin for writing. (3) Execute the program written to the above RAM in the ICE module. The tester uses the JTAG pin for writing and sends dedicated commands to the CPU chip. (4) Write to the internal memory and write to the memory test program. The tester uses the JTAG pin for writing. (5) The program written in the RAM in the ICE module is divided into the above memory test program. The tester uses the JTAG pin for writing. (6) The end of the test monitor test. After the test is over, the judgment result is read. Since the PoP is connected to each other after the semiconductor wafer is mounted on each of the mounting substrates, the connection state between the semiconductor wafer and the mounting substrate can be determined before the step of connecting the semiconductor devices to each other, and the finished assembly material of the package is reduced by a considerable amount. effective. In addition, compared with SiP, it can also flexibly cope with the small amount of multi-system needs. However, similarly to the SiP shown in FIG. 22, in the memory circuit of the PoP, as shown in FIG. 25, a test 130819.doc connected to the address terminal AD, the control terminal CN, and the data terminal DT is provided. -22- 200907380 The external terminals are inspected, and the test devices p〇p 1~p〇Pn connected to the address bus, control 及 and negative bus on the test substrate are directly connected to the test device. In the case of performing the test of the memory circuit of each of the devices to be tested p〇p 1 to 'there is a problem of using a high-speed test device. Fig. 4 is a schematic view showing the steps for explaining another embodiment of the method of manufacturing the semiconductor device of the present invention. In step (1), a plurality of CPU chips are formed on the semiconductor wafer. For example, at the time of forming the (10) wafer on the semiconductor wafer, the tester (1) is performed by the tester. The CPU chip has a memory circuit as will be described later, and a user-debug interface 2 (7)' for self-diagnosis or the like and a plurality of bio-deposited wafers formed on the semiconductor wafer. This memory chip is, for example, operated at a high speed such as DDR_SDRAM. When the memory wafer is formed on the semiconductor wafer in this way, the precision tester performs the detection test (7).

Ci 2;^3)' performs the cutting of the semiconductor wafer after the formation of the CPU chip, and is judged to be a good h in the probe test (1). The semiconductor wafer wafer after the formation of the above-mentioned memory crystal moon is selected in the probe test (1), and the memory is judged to be a good product = 5) base: it is judged as good in the above step (7). . _ Wheat is loaded on the loading substrate. The mounting substrate has a multi-layer wiring layer) surface-mounted CPU chip, and A JL is formed on the /, / surface (on the outer side thereof to form an electrode for connection with a semiconductor device of (4) memory chip 130819.doc -23-200907380] 6) The memory crystal which is determined to be good in the above step (4) is placed on the loading substrate. The memory chip is mounted on the surface of the substrate by a plurality of gold lines of the same green, t*H' The signal connected to the surface is used in the side of the solder ball corresponding to the electrode formed on the loading substrate on which the wafer is mounted. In step (7), the half of the loaded wafer assembled in the above step (7) is applied.

Screening test for conductor placement (1). In this screening test (1), an aging test is also performed as necessary. In step (8)', the teacher test (2) of the semiconductor device loaded with the memory chip assembled in the above step (6) is performed. In this screening test (7), an aging test is also performed as necessary. In the step (7), the semiconductor device mounted on the upper portion of the semiconductor chip which is determined to be a good cpu wafer in the above step (7) is superimposed and mounted on the semiconductor device which is determined to be a good (4) wafer in the above step (8), and is assembled via the solder ball connection. A multi-layer package of a two-layer structure in which the CPU chip and the CMOS chip correspond to each other. In the step (10), the above-described test of the assembled PgP is carried out. On the test substrate used in this test, the clock generation circuit ckg was loaded, and a high-speed clock signal equivalent to the actual operation was supplied to the test to be mounted on the test socket. The above semiconductor device (p〇p) of the device. The tester pairs the test device P〇p mounted on the test substrate, accesses the CPU chip via the user debug interface circuit, and writes the test program of the memory chip into the built-in memory circuit. Thereafter, the CPU chip is booted and stored in the built-in memory of I30819.doc •24-200907380, and the result is determined by accessing the memory chip according to the program, and the result is transferred to the tester. The test of the CPU chip itself also accesses the ICE (circuit emulation debugger) module via the above-mentioned user debug interface circuit, and performs the test of the peripheral circuit including the CPU and the built-in memory circuit. The above steps (1) (10) is not particularly limited except for being implemented by all semiconductor manufacturers. However, the above steps (1), (3), (5), and (7) may be performed by a semiconductor manufacturer that forms a CPU chip. The second semiconductor manufacturer that forms the memory chip different from the above-mentioned i-th semiconductor manufacturer performs the above steps (2), (4), (6), and (8). Further, each of the steps (1), (3), (5), and (7) of manufacturing the semiconductor device in which the CP1J chip is mounted, and the steps (2), (4), ( 6), (8) may also be suitably implemented by a plurality of vendors. The above step (9) can also be carried out by a setting manufacturer such as a mobile phone device. In this case, the test of the above step (1) is carried out by the above-mentioned setting manufacturer which is the same as the above step (9). In the test of the step (1) of the present embodiment, the semiconductor device loaded with the CPU chip is repeatedly executed to write to the memory cell corresponding to the above-mentioned day pulse number in the same manner as the actual operation state of the above p〇p. The memory test was performed on the semiconductor device on which the semiconductor wafer was mounted by reading. The input of the program for this test is performed by the tester simultaneously for the plurality of P〇P loaded on the test substrate, and in the plural P〇P loaded on the test substrate, according to the program of each input. Simultaneously, the memory chip is tested in parallel, so that the memory circuit as described above can be terminated in a short time and even if it has a large memory capacity. 130819.doc -25- 200907380 The semiconductor device loaded with the CPU chip and the semiconductor device loaded with the memory chip perform the screening test which itself contains the aging test, but the test of the monomer state of the test is not assembled into the above Pop. The state of the test. In the semiconductor device of the P〇P structure, two semiconductor devices are stacked in a stacked manner at a narrow interval, so that heat generation is expected to strongly influence each other. Therefore, the memory test for performing the clock corresponding to the actual operation of assembling the state of the semiconductor device as the Pop structure has been a test which is required to ensure the performance of the CPU and the memory of the semiconductor device of the above-described Pop structure. Fig. 15 is a schematic cross-sectional view showing an embodiment of a semiconductor device to which the p〇p structure of the present invention is applied. The second mounting substrate 13 on which the CPU chip 2 is mounted and the second mounting substrate 15 on which the memory chip 14 is mounted are electrically connected to the first loading substrate via a plurality of solder balls 22 formed on the back surface of the second mounting substrate 15 13 corresponding electrode. Since the CPU wafer 12 is attached to the central portion of the surface of the second loading substrate 13, the solder balls 22 are disposed along the outer peripheral portion of the back surface of the second loading substrate 15. On the outer peripheral portion (the outer side of the CPU wafer 12) of the surface of the second loading substrate ^, electrode pads for connecting the solder balls 22 are formed. The memory chip 14 is not particularly limited, but the ddr_SDRAM ' is connected to the solder pad of the second loading substrate by a gold wire (welding wire) 26. The solder pads and the electrode pads on the back surface of the second load substrate 15 are electrically connected via signal wirings on the surface of the substrate and via holes. The memory chip 14, the gold wire 26, and the electrode pad are hermetically sealed by a molding resin. The CPU wafer 12 is flip-chip bonded (face-down connection) to the electrode pads on the surface of the loading substrate 13 via a plurality of solder balls 21 130819.doc -26- 200907380 formed on the main surface (below) thereof. The main surface of the CPU wafer 12 is hermetically sealed by an underfill resin. On the back surface of the above-mentioned first loading substrate 13, a plurality of electrode pads for external external input arrays arranged on the grid are formed, and solder balls 23 are connected to the electrode pads. The signal pad on the surface of the first loading substrate 13 and the external input signal pad on the back surface are electrically connected via signal wiring on the surface of the substrate, signal wiring of the inner layer, and via holes connecting the electrodes. Fig. 16 is a schematic view showing another embodiment of a semiconductor device to which the p〇p structure of the present invention is applied. In the present embodiment, two memory chips 14 are mounted on a semiconductor device mounted on the upper side of the memory chip. That is to say, by loading two DDR_SDRAMs of the same memory capacity, the memory capacity twice as shown in Fig. 15 can be realized. The two memory chips 14 are laminated via a dummy wafer 25 as a spacer. Thereby, the dummy wafer 25 is secured to the space of the gold wire 26 of the memory chip 14 on the lower side. The other configuration is the same as that of Fig. 15 described above. Fig. 17 is a schematic cross-sectional view showing another embodiment of a semiconductor device to which the p〇p structure of the present invention is applied. In the present embodiment, three types of memory chips 14 are stacked in a semiconductor device mounted on the upper side of the memory chip. For example, it is composed of three kinds of memory chips such as DDR_SDRAM, SDRAM, and a whole batch of non-volatile memory (flash memory). In this case, a larger-sized memory chip is provided on the lower side to secure a space for solder pads and gold lines provided in the memory chip. When the size of the memory chip is substantially the same, as shown in FIG. 16 described above, it is only necessary to form a laminated structure of three kinds of memory chips via a dummy wafer. In this case, the cpu wafer 12 on the lower side can be directly connected to the above three types. The interface circuit of the memory chip. The other structure is the same as that of the previous 130819.doc •27· 200907380 and FIG. Figure 18 is a cross-sectional view showing an embodiment of the semiconductor device corresponding to the aforementioned Fig. 16. The semiconductor device of the P〇P structure of the present embodiment is mounted on the upper surface of the mounting substrate (first wiring substrate) i3 on which the cpu chip 12 is mounted, and the mounting substrate on which the caution wafer 14 is mounted (second wiring) A laminate type package having a two-layer structure of a substrate) 15. The CPU chip 12 has, for example, a microcomputer chip of the SH series sold by the applicant in the same manner as described above, and has a user debugging interface circuit called HUDI (High Performance User Interruption Interface). The HUDI can perform reading and writing in a temporary state with internal memory based on a few pins of JTAG. By using the user debugging interface circuit, the memory test program of the memory chip 14 can be stored in the internal memory of the CPU chip 12, and the memory test program is executed by the CPU of the CPU chip 12 to perform the memory chip. 14 test. Of course, the user debugs the internal circuitry of the CPU chip 12 used to perform the original function. In the CPU chip 12, in addition to the built-in memory and peripheral circuits of the static RAM, a memory interface circuit (DDR-SDRAM, SDRAM, and bulk erase type non-volatile) corresponding to the memory chip 14 is provided. The memory is directly connected to the corresponding memory chip 14 via the memory interface circuit. The semiconductor device of this embodiment realizes a memory capacity of about 1 billion bits on the surface (on the surface) of the substrate 12 by stacking two DDR-SDRAM wafers 14 of about 5 12 bits by the dummy wafer 25. The memory capacity and the number of sheets of the memory chip 14 mounted on the load substrate 丨 5 can be appropriately changed. That is, the semiconductor device of the p 〇p structure can change the memory capacity and the number of slices of the memory chip 14 mounted on the memory-loading substrate 15 with little change, and the cpu-chip I2 is hardly changed as a substrate. A plurality of semiconductor devices are manufactured to the specifications of the side of the substrate 13 to be mounted. The carrier substrate 13 is, for example, a multilayer wiring board having six layers of wiring (surface wiring, back wiring, and four inner wirings) manufactured by an assembly method, and an insulating layer that electrically electrically separates wiring layers from each other Glass fiber or carbon fiber is impregnated with resin semi-cured film. The 6-layer wiring is composed of, for example, a conductive film mainly composed of copper (Cu). In FIG. 18, the illustration of the wirings is omitted, and only the electrode pads 16p, np, and 18p formed on the surface (upper surface) of the mounting substrate 13 and the external input/output electrode pads 1 formed on the back surface of the mounting substrate 13 are exemplified. The 9p ° CPU chip 12 is flip-chip bonded (face-down connection) to the electrode pads 16p, 17p on the surface of the mounting substrate 13 via a plurality of solder balls 21 formed on the main surface (lower surface) thereof. The main surface of the CPU wafer 12 is hermetically sealed by an underfill resin. Although not shown in the drawings, the number of terminals of the CPU wafer 12 is extremely large, so the solder pads (and the solder balls 21 connected to the surface thereof) are along the cpu wafer! The four sides of the main surface of 2 are arranged in two rows, and the solder pads on the inner side and the solder pads on the outer side are arranged in a staggered manner. On the back surface of the mounting substrate U, a plurality of external input/output electrodes 塾 19P ' are formed to electrically connect the solder balls 23 to the surface. The semiconductor device of the p〇p structure is mounted on the mother board of the clothing and the Beitong k terminal device via the solder balls 23. Here, the external input/output electrode 塾 19p on the back surface of the wiring spot on the surface of the substrate 13 is electrically connected to each other via the inner layer wiring and the via hole. 1308l9.doc -29-200907380 The memory-loading substrate i5 of the two memory chips 14 is composed of a resin substrate having an insulating layer of glass or the like. The two memory chips 14 are mounted on the surface of the memory substrate 15 with one surface facing upward, and the other is laminated on the memory wafer 14 via the dummy wafer 25. The two memory chips 14 are electrically connected to the electrode pads 27 on the surface of the memory chip i 4 via gold wires 26. The two memory chips 14, the dummy wafers 25, the gold wires 26, and the electrode pads 27 are molded. The plastic resin 3 is hermetically sealed. The electrode pad 28 electrically connected to the electrode pad 27 via a via hole (not shown) is formed on the surface of the memory-mounting substrate 15, and the solder ball 22 is electrically connected to the surface. The electrode pads 27, 28 are respectively arranged in two rows along the opposite outer peripheral portions of the memory-loading substrate 15, for example. The solder balls 22 connected to the electrode pads 28 of the memory-loading substrate 15 are also electrically connected to the electrode pads 18p formed on the outer periphery of the surface of the carrier substrate 3, thereby electrically connecting the mounting substrates on which the cpu wafers 12 are mounted. 13 and a memory loading substrate 15 on which the memory chip 14 is mounted. The solder ball 22 has a diameter larger than the total thickness of the solder balls 21 formed on the main surface of the CPU wafer 12 and the thickness of the cpu wafer 12 so as to be mounted on the upper surface of the CPU wafer 12 mounted on the substrate 13 and the memory loading substrate. Under 15 is not in contact. As described above, the external input/output electrode 塾19P is formed on the back surface of the mounting substrate 13, so that the solder ball 23 is connected to the external input/output electrode 塾19p. Fig. 19 is a partially enlarged sectional view showing an embodiment of the semiconductor device shown in Fig. 8; In the example shown in FIG. 19, the k-th terminal corresponding to the CPU chip 12 and the memory chip 14 is formed by the surface wiring 31, the via hole 32, and the second layer cloth integrally formed with the electrode pads 1 on the outer side. Line 33 is connected by electrical I308I9.doc -30- 200907380. Due to the limitation of the wiring design rule, it is possible to electrically connect the CPU chip 12 and the memory chip 14 by the electrode 塾1 7p of the outer row. The CPU chip can be electrically connected via the electrode pad 16 6 of the inner row. 12 and the hidden scorpion 1 4 . For example, cpu chip 12 and memory chips! The electrode pad 16p on the inner side may be electrically connected to the second layer wiring extending inwardly from the via hole 32 and the electrode pad 17p on the outer side. Although there is no special (four) system, the test electrode pad which can directly access the memory chip 14 is not provided on the substrate 13 to be mounted. Therefore, between the cpu chip and the memory chip 14, the test leads are connected and the wiring for connection is used. Therefore, the size of the mounting substrate 13 can be reduced to form the test electrode pad and used for connection. In addition to the area required for wiring, it is also possible to reduce the amount of noise generated by signal transmission between the cpu chip 12 and the memory chip 14 and the noise generated by reflection and coupling of signals. Signal transmission in high-speed memory like DDR_SDRAM. Further, since the amount of the wiring layer formed on the mounting substrate 13 can be reduced, it is possible to suppress the distortion of the mounting substrate 13 caused by the difference in thermal expansion coefficient between the wiring layer and the insulating layer (prepreg). Figure 20 is a diagram showing the internal block of one embodiment of the p〇p of the present invention. P 〇 P of the present embodiment corresponds to the semiconductor device of Fig. 16 described above. In the same figure, the connection relationship between the CPU chip 12 and the memory chip 14 is shown centering. The memory chip 14 is a DDR-SDRAM. Terminal CKE is the clock input valid input terminal. The terminal CSB is a wafer selection input terminal. Terminal ba[1:〇] is the stack address input terminal. Terminal A[l1:0] is the address input terminal. Terminal DQ[31:0] is the data input and output terminal. Terminal raSB series address gate wheel 130819.doc -31 - 200907380 Input terminal. The terminal CASB is the row address strobe input terminal. The terminal WEB is written to the valid input terminal. Terminal DQS[3:〇] is the data strobe input and output terminal. DQM[3:0] is the DQ write hood effective input terminal. Terminals CLK and CLKB are clock input terminals. In the same figure, there is no particular limitation, but since there are two DDR-SDRAMs of about 5 12M (million) bits, the overall memory capacity is about 1 billion bits. The above two DDR-SDRAMs can be written/read in 64-bit units by connecting the terminals DQ[31:0] to the corresponding 64-bit data input/output terminals of the CPU chip 12. Alternatively, the terminals DQ[31:0] are connected in parallel to the corresponding 32-bit data output terminal of the CPU chip 12. In this case, for example, the CPU chip 12 supplies a selection signal to the chip selection terminals CSB of the above two DDR-SDRAMs to select one of the two DDR-SDRAMs. Alternatively, the extended address signal may be supplied to the address terminal to select one of the two DDR-SDRAMs. In the CPU chip 12, each of the output terminals DDRCKE, DDRCS-N, DDRBA[1:0], DDRA[11:0], DDRRAS_N which are directly connected to the input terminal and the output terminal of the DDR-SDRAM as described above, respectively. DDRCAS_N, DDRWE_N, DDRRDM[3:0], DDRCK, DDRCK-N, with each input and output terminal DDRD[31:0], DDRDQS[3:0]. In the same figure, in the memory chip 14, as in the case of CSB, the B is attached to the end of the terminal name to indicate a bar signal which causes the low level to be an effective level. Corresponding to this, in the CPU chip 12, as the DDRCS_N, the end of the terminal name is attached with a signal indicating that the low level becomes a valid level. In the present embodiment, in the semiconductor device such as P 〇 P, a signal path test terminal connected between the CPU chip 12 and the memory chip 14 of 130819.doc - 32 - 200907380 is provided. By using this test terminal, for example, the memory chip 14 can be directly accessed. The CPU chip 12 is provided with a terminal JTAG connected to the user circuit of the CPU chip 12 for debugging. The above test terminals are quite convenient in performing a test for confirming the direct current connection of the solder balls 22 between the memory chip 14 and the CPU wafer 12. However, the memory test of the clock corresponding to the actual operation of assembling the state of the semiconductor device as the PoP structure as described above by the terminal JTAG may not require the CPU and the memory of the semiconductor device of the above PoP structure to be simultaneously ensured. Performance and high cost test equipment. Figure 21 is a block diagram showing an internal block of another embodiment of the PoP of the present invention. The PoP of this embodiment corresponds to the semiconductor device of the aforementioned FIG. In the same figure, the connection relationship between the CPU chip 12 and the memory chip 14 is shown centering. In the present embodiment, the test terminals connected to the memory chip 14 as shown in Fig. 20 described above are omitted. That is, the terminal CKE, the terminal CSB, the terminal BA[1:0], the terminal A[11:0], the DQ[31:0], the terminal RASB, the terminal CASB, the terminal WEB, the terminal DQS of the memory chip 14 [ 3:0], Ο J DQM[3:0], and CLK and CLKB are only connected to the terminals DDRCKE, DDRCS_N, DDRBA[1:0], DDRA[11:0], DDRD[31: 0], DDRRAS_N, DDRCAS_N, DDRWE_N, DDRDQS[3:0], DDRRDM[3:0], DDRCK, DDRCK_N are connected to each other. The other configuration is the same as that of Fig. 20 described above. Fig. 22 is a block diagram showing an embodiment of the operation test of the semiconductor device shown in Fig. 21; In the test substrate, a clock generation circuit CKG is provided in the same manner as described above, and a clock signal corresponding to the actual operation of PoP1 to P〇Pn 130819.doc • 33 - 200907380 of the device under test is supplied. On the test substrate, the JTAG terminals of the devices PoP1 to ΡοΡη are connected in common to the test device. In the present embodiment, the operation test of the memory slab 14 described above is performed by the JTAG described above, and the memory test terminal is not required in the memory chip 14, and therefore can be omitted. By using the manufacturing method shown in FIG. 14 including the p〇p of the operation test procedure of the memory chip 14 by the CPU chip 12 using the above jtag, it is possible to greatly reduce, for example, about 60 in the p〇p manufactured thereby. Support external terminals. As a result of such reduction of the external terminals, the size of the package can be reduced in the semiconductor device (P〇P). In other words, the test solder ball or the test electrode provided on the back side of the load substrate 13 shown in Fig. 16 and the wiring for connection are not required, so that the size of the load substrate 13 can be reduced. Further, as shown in the block diagram of FIG. 20 described above, since it is not necessary to be suitable for the wiring for the memory terminal which is connected to the wiring between the CPU chip 12 and the memory chip 14, the portion can be reduced. The wiring layer. Therefore, as the P 〇 P mounting substrate, the substrate can be mounted at a low cost with a small number of wiring layers, and the load of the mounting substrate 13 due to the difference in thermal expansion coefficient between the wiring layer and the insulating layer (prepreg) can be suppressed. By suppressing the warpage, the mechanical stress applied to the solder balls 22 between the load substrate 13 and the load substrate 15 can be reduced, and a connection that is still sinful can be performed. The parasitic capacitance between the CPU chip J 2 and the § memory wafer 14 can be greatly reduced. Such a reduction in parasitic capacitance allows the current of the output circuit of the CPU chip 1 2 and the memory chip 丨 4 to be charged/discharged to be small, so that the operation speed can be increased and the power consumption can be reduced. Doc • 34- 200907380 The aforementioned CPU chip 1 2, as described above, the microcomputer chip of the SH array sold by the applicant of the present application has a fault of a user called HUDI (High Performance User Debugging Interface). Use interface circuit. The HUDI can perform read and write of a scratchpad with internal memory according to a few pins of JTAG. By using the user debugging circuit, the memory test program of the memory chip 14 can be stored in the internal memory of the CPU chip 12, and the memory test program is executed by the CPU of the CPU 12 to perform the memory chip. % of the action test. Of course, the user debugs the internal circuitry of the microcomputer chip 2 used to perform the original function. The outline of the program for executing the writing of the memory test program of the internal memory of the CPU chip 12 is similar to the above-described S i P as described below, and the cpu is placed in the "reset hold" state. (2) Write the data. 〇) Execute "HUDI Startup". (4) Test the internal size of the memory test program. (7) Confirm that the memory test program has been written normally. (4) Start the memory test program. (7) Wait for the memory test to end and confirm the result. U. In order to execute the memory test program, it is necessary to write the memory test program j to the internal memory of the CPU chip 12 in advance. Considering the memory test program, the error test 5 is written into the internal RA^ of the CPU chip 12 (for example, static random access memory). For example, in the above-mentioned "micro-electric" film, in order to perform the writing of the internal (10) using HUDI, there is a "H-reading person command" or a "(four) sub-writing command" 0 body 2'. The inventions of the present invention have been made in accordance with the embodiments, but the invention is not limited to the foregoing embodiments, and various changes can of course be made without departing from the gist of 130819.doc-35-200907380. For example, The ICE module set on the microcomputer chip can be implemented in various implementation modes. The interface circuit for starting the ICE module can use any interface circuit besides JTAG. The memory chip can be either SDRAM or SRAM except DDR-SDRAM. 'It can also be a memory wafer of another type such as a flash memory (a whole batch of non-volatile memory). In addition to the wafers mounted on the surface of the substrate as shown in Figure 2 above, SiP also It is possible to assemble a plurality of wafers into a laminated structure. [Industrial Applicability] The present invention can be widely applied to SiP, p〇p or multi-chips including a microcomputer chip (CPU chip) and a memory chip. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing an embodiment of a method for fabricating a semiconductor device of the present invention. Fig. 2(A) and Fig. 2(B) are SiP of the present invention. Figure 3 is an internal block diagram of one embodiment of the SiP of the present invention. Figure 4 is an internal block diagram of one embodiment of the yp of the present invention. Figure 5 is an illustration of Figure 4 Figure 6 is a block diagram of another embodiment of the sip of the present invention. Figure 6 is an illustration of an internal block of the semiconductor device of Figure 6; Figure 8 is a state transition diagram of the jTAG TAP used in the present invention. 130819.doc -36- 200907380 Figure 9 is a waveform diagram of one embodiment of the jTag TAP used in the present invention. Figure 1 is a flow diagram of one embodiment of a HUDI write mode. Figure 13 is a flow diagram of one embodiment of a HUDI read mode. Figure 14 is a diagram showing a method of manufacturing a semiconductor device of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 15 is a schematic cross-sectional view showing an embodiment of a semiconductor device to which the P〇p structure of the present invention is applied. FIG. 16 is a semiconductor to which the p〇p structure of the present invention is applied. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 17 is a schematic cross-sectional view showing another embodiment of a semiconductor device to which the PoP structure of the present invention is applied. Fig. 18 is an embodiment of a semiconductor device corresponding to Fig. 16. FIG. 19 is a partial plan view showing an embodiment of the semiconductor device shown in FIG. 18.

Figure 21 is an internal block diagram of another embodiment of p〇p of the present invention. Fig. 22 is a block diagram showing an example of the operation test of the semiconductor device shown in Fig. 21. Only her Figure 23 is a block diagram of the test system first explored by the present invention. Blocks of the Tongzhi Block Figure 24 is a test system suitable for SiP that was first explored by the present invention. Figure 25 is a test system suitable for p〇p which is first explored by the present invention. 130819.doc • 37- 200907380. [Description of main component symbols] 1 2 3 4 5 6 12 13 14 15 1 6p, 1 7p, 1 8p, 19p 21, 22, 23 24 25 26 27, 28 30 31 32 33

CPU

MIF Loading Substrate Microcomputer Chip Memory Chip (DDR-SDRAM) Soldering Wire Sealing Body Solder Ball CPU Chip As Substrate Loading Substrate Memory Chip Memory Loading Substrate Electrode Pad Solder Ball Underfill Resin Fake Wafer Gold Wire Electrode Pad Molding Resin Surface Wiring via hole 2nd layer wiring central processing unit (microprocessor) memory interface circuit 130819.doc -38- 200907380 ICE circuit simulation debugger

SiP1~SiPn, PoPl~PoPn semiconductor device (tested device) CKG clock generation circuit TST1~TSTn test circuit FSM flash memory 〇

J 130819.doc -39-

Claims (1)

200907380 X. Patent application scope: 〇 L: A method of manufacturing a semiconductor device, comprising: a first step of forming a second semiconductor device having a first memory circuit; and a second step of performing an electrical test of the first semiconductor device, and screening the good a third step of forming a second semiconductor device having a signal processing circuit and a second memory circuit for performing signal processing according to a program; and a fourth step of performing the signal processing circuit of the second semiconductor device and An electrical test of the second memory circuit and screening of the good product; and a fifth step of physically forming the second semiconductor device and the second semiconductor selected by the fourth step; And the sixth step of mounting the semiconductor device having the body structure described above on the test substrate, and performing an electrical test to determine whether the semiconductor device is good or not; and the sixth step is for the test The substrate is provided with an oscillation circuit that supplies a clock signal corresponding to the actual operation of the semiconductor device to the plurality of semiconductor devices in common, and includes: In the first operation, the test device writes a test program for testing the operation of the second memory device of the i-th semiconductor device to the second memory circuit of the second semiconductor device; the second operation is based on the above The signal processing circuit 2 of the semiconductor device performs the operation of the heart memory circuit 2 operation test m of the i-th semiconductor device in accordance with the test program written in the first memory device in response to the clock signal, 2 The result of the determination of the goodness of the action is output to the above test device. In the above first step 2. The method for manufacturing a semiconductor device according to claim 1, 130819.doc 200907380 包含 includes a second step of forming a plurality of (10) body charges on the first wafer. 2] Steps, which will be formed in the above! The plurality of memory circuits on the wafer are respectively subjected to an electrical test to determine whether the quality is good or not; and in the second step (2), the βth memory circuit formed on the wafer is divided into the first semiconductor wafers, and the screen is selected as described above. a semiconductor wafer that is determined to be a good product in the determination result of the second step; the third step includes a third step of forming a second memory circuit and performing a signal according to the program. a plurality of semiconductor circuits of the processed signal processing circuit; wherein the fourth step includes a step of determining an electrical test by performing an electrical test on each of the plurality of semiconductor circuits formed on the second wafer; and the fourth step The semiconductor circuit formed on the upper wafer is divided into the respective second semiconductor wafers, and the semiconductor wafer is determined to be a good 2 semiconductor wafer in the determination result of the fourth step; the fifth step includes the fifth a step of integrally forming the first semiconductor wafer that has been screened as a good product in the second step 2-2 and the second semiconductor crystal substrate that has been screened as a good product in the fourth step -2 as a package The semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the self-diagnosis circuit is built in the first wafer, and the operation of the sixth step includes a first step of causing the second semiconductor wafer a process of re-establishment ((10) heart (4) state, and the input of the test program to the memory circuit provided in the self-breaking circuit by the above test device; and the second step, which is performed according to the above program The method of manufacturing a semiconductor device according to claim 2, wherein the test substrate used in the sixth step includes a plurality of semiconductor devices that can be loaded with a plurality of semiconductor devices. The socket, the clock formed by the oscillating circuit is commonly supplied to the semiconductor device mounted on the plurality of sockets. 5. The method of manufacturing the semiconductor device according to claim 3, wherein the second semiconductor wafer includes a user according to JTAG a debug interface circuit, wherein in the sixth step, the user debugging circuit is connected to the test device, and the first action is performed 6. The input of the test program and the output of the third operation of the third operation. 6. The method of manufacturing the semiconductor device according to claim 5, wherein in the fifth step, the common substrate includes the connection of the second semiconductor wafer and the (2) The internal wiring of the semiconductor chip corresponding to the external wiring of the semiconductor device, wherein the internal wiring is not connected to the external terminal of the integrally formed semiconductor device. 7. The method of manufacturing the semiconductor device according to claim 6, wherein the third semiconductor is The first semiconductor chip is a microcomputer having a interface circuit directly connectable to the dynamic RAM. The method for manufacturing a semiconductor device according to the above claims, wherein the first step includes the first Step -1, which forms a plurality of memory circuits on the first wafer, and steps 1-2, which perform electrical tests on the plurality of memory circuits formed on the second wafer to determine whether the quality is good or not: a third step of dividing the second memory circuit formed on the first wafer into the first semiconductor wafers and screening them The first semiconductor wafer determined to be a good product in the determination result of the step _2, and the ith i_4 step pair 130819.doc 200907380 Ο 9. The first semiconductor wafer determined to be good in the above-mentioned step 3 The first semiconductor device having the solder ball as an external terminal is assembled; and the second step includes a second step of performing the first memory of the first semiconductor device including the step of the fourth step The electrical test of the body circuit and the screening of the good product; the third step includes the third step of forming a plurality of semiconductor circuits including the second memory circuit and the signal processing circuit for performing signal processing according to the program on the second wafer The first step of determining the quality of the plurality of semiconductor circuits formed on the second wafer by electrical test, and the step of the third step of dividing the plurality of semiconductor circuits formed on the second wafer into Each of the second semiconductor wafers 'i screens the second semiconductor wafer that is determined to be good in the determination result of the third step 2; and the third step 4' The second semiconductor wafer which is determined to be a good second semiconductor wafer in the above-described third step of the mounting substrate of the solder ball of the i-th semiconductor device is mounted as the second semiconductor device; the fourth step includes In the fourth step, the electrical test of the second memory circuit including the second semiconductor device assembled in the above step 3-4 is performed, and the good product is screened; and the fifth step includes the W step, which is In the above-mentioned step W, the solder ball of the & conductor device selected by Xue is connected to the corresponding connection electrode of the second semiconductor device which is selected as the good product in the above-mentioned step 4] As i semiconductor devices. The method of manufacturing a semiconductor device according to Item 8, wherein the second semiconductor device includes a self-decorating circuit, and the sixth step of the correcting operation package 130819.doc 200907380 includes a first step of "making the second semiconductor Writing the program to the memory circuit provided in the self-diagnostic circuit and writing the test program to the memory circuit provided in the self-diagnostic circuit; and the step of writing the test program according to the above program The second memory circuit according to claim 9, wherein the test substrate used in the sixth step includes a plurality of sockets capable of loading a plurality of semiconductor devices ' The clock is commonly supplied to a semiconductor device mounted on the plurality of sockets. η. The method of manufacturing a semiconductor device according to claim 037, wherein the conductor is disposed to include a user interface according to JTAG, In the above step, the user debugging interface circuit is connected to the device, and the above (9) is performed. The input of the test program and the output of the determination result of the third operation. The test method of the 12 semiconductor devices, wherein the semiconductor is mounted with the first semiconductor device and the second semiconductor device, and includes the corresponding ones. a connection mechanism; the second semiconductor device includes eight (1) memory circuits, and the second semiconductor device includes a second memory circuit, and a signal processing circuit for performing a signal processing operation according to a program and an interface of the first memory circuit a circuit and a user debug interface circuit; the test method includes: an operation for supplying the semiconductor device to the test substrate corresponding to the clock signal of the actual operation of the semiconductor device No. The test program of the above-mentioned first memory circuit operation test I30819.doc 200907380 is written by the test device to the second memory circuit of the second semiconductor device via the user debug interface circuit; 'It is in the above signal processing circuit, corresponding to the above clock signal in accordance with the above written The test program performs the operation test of the first memory circuit; and the third operation 'outputs the result of the determination of the second operation to the test device. 13' Β|Ιμ The test method of the dry conductor device, wherein the first semiconductor device is the first derivative _1|*ay, f, ί j , ... the younger conductor cymbal, the second semiconductor device 2 Semiconductor wafer The first semiconductor wafer and the second semiconductor wafer are connected to each other via a (four) wiring as the connection mechanism formed in the common substrate, and the corresponding terminals are integrally connected to each other to form the semiconductor device. 14. The method of testing a semiconductor device according to claim 13, wherein said second semiconductor wafer has a self-diagnostic Thunder circuit, and said third operation includes a second step of: said second semiconductor wafer Writing a reset state, and writing, by the device 4, to a memory circuit provided in the self-diagnostic circuit, a program for inputting a test program; and a second step of writing the test program according to the program The second memory circuit 0. The method of claim 1, wherein the test substrate comprises a plurality of sockets for loading the plurality of semiconductor devices, and the clock circuit formed by the i-shock circuits The ground is supplied to the semiconductor package respectively mounted on the plurality of sockets, and in the third operation, the human test program is written in parallel to the plurality of semiconductor devices, and the test is performed in the above-mentioned 130819.doc 200907380 3 The output of the quality determination result is successively performed between the device and one semiconductor device. The method of testing a semiconductor device according to claim 15, wherein the user debugging interface circuit is based on a JTAG interface circuit, and the third test operation is performed at the input of the test program of the first operation and the third operation. The clock used in the output of the result is different from the clock signal of the second operation described above, and the frequency is lowered. 1. The method of testing a semiconductor device according to claim 1, wherein the internal wirings of the terminals of the first semiconductor wafer and the second semiconductor wafer that are connected to the common substrate are not connected to each other by the package. The external terminal of the semiconductor device. 1 . The method of testing a semiconductor device according to claim 7, wherein said second semiconductor wafer is a dynamic RAM, and said second semiconductor wafer has a microcomputer which can be directly connected to said dynamic RAM. The method of testing a semiconductor device according to claim 2, wherein said jth semiconductor device comprises a first load substrate, said first semiconductor wafer having said second memory circuit, and said second semiconductor wafer loaded with solder The ball constitutes an external terminal, and the second semiconductor device includes a first semiconductor wafer including the second memory circuit, the signal processing circuit, the interface circuit, and a user-interrupting interface circuit, and the second loading substrate, the surface of which is adhered The first semiconductor wafer includes a connection electrode of a solder ball corresponding to the first semiconductor device and an internal wiring of a connection mechanism that is connected to an electrode corresponding to the interface circuit via the connection electrode; and the first semiconductor The solder balls of the device are connected to the second semiconductor package 130819.doc 200907380, and the corresponding connection electrodes* are assembled as one semiconductor device. 20. The method of testing a semiconductor device according to claim 19, wherein said first semiconductor wafer has a self-diagnostic circuit built therein, said first! The operation includes a first printing step of causing the second semiconductor wafer to be in a reset state, and writing the program to the memory circuit of the self-diagnostic circuit by the measuring device 4; and In the second step, the system is configured to write the test program to the second memory circuit 0. The method for testing a semiconductor device according to claim 20, wherein the test substrate comprises a plurality of the semiconductor devices The plurality of sockets are commonly supplied to the semiconductor device respectively mounted on the plurality of sockets by the clocks formed by the plurality of oscillation circuits, and the test program is written in parallel to the plurality of semiconductor devices in the third operation In the third operation described above, the output of the quality test result is performed successively between the semiconductor device of the test device. 22. The test method of the semiconductor device according to claim 21, wherein the user debug interface circuit is based on JTAG. The interface circuit is the same as the third operation described above when the test program of the first operation is input The clock used in the output of the determination result is different from the clock signal of the second operation, and the frequency is lowered. 23. The method of testing a semiconductor device according to claim 22, wherein the second substrate is connected The internal wiring of the terminals corresponding to the semiconductor wafer and the second semiconductor wafer is not connected to the external terminal of the semiconductor device integrally constituting 130819.doc 200907380. The semiconductor device 4 is a semiconductor The terminals corresponding to the second semiconductor device are integrally connected to each other, and the first semiconductor device includes a first memory circuit, and the second semiconductor device includes a second memory circuit and performs a signal processing operation according to the program. a signal processing circuit, a interface circuit connectable to the first memory circuit, and a user debug interface circuit, wherein the memory test program of the first memory circuit can be stored in the user debug interface circuit In the second memory circuit, the external terminal does not have direct access to the first memory of the semiconductor device The external device of the invention, wherein the i-th semiconductor device is a first semiconductor wafer, the second semiconductor device is a second semiconductor wafer, and the first semiconductor wafer and the second semiconductor wafer are The semiconductor device of claim 25 is mounted on a common substrate having internal wirings that connect the corresponding terminals to each other. The semiconductor device of claim 25 is wherein the user interface circuit is based on a JTAG interface circuit. 27. The semiconductor device according to claim 24, wherein said second semiconductor device package 3 has a first semiconductor wafer, said first memory circuit, and a first loading substrate, said first semiconductor wafer being mounted thereon, said solder ball The second semiconductor device includes a second semiconductor circuit including the second memory circuit, the signal processing circuit, the interface circuit, the user debug interface circuit, and the second load substrate, and the surface is adhered to the second semiconductor substrate. a semiconductor wafer having a solder electrode corresponding to the solder of the above-mentioned semiconductor device 130819.doc 200907380 An internal wiring of a connection mechanism in which the electrodes corresponding to the escape interface circuit are connected to each other via the connection electrode, and the solder ball of the first semiconductor device is connected to the corresponding connection electrode of the second semiconductor device The semiconductor device of claim 27 is integrally assembled as the semiconductor device of claim 27, wherein the user interface circuit for debugging is based on a JTAG interface circuit. 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