JPH06338200A - Method and device for inspecting electrical characteristic of semiconductor storage device - Google Patents

Abstract

(57) [Summary] [Purpose] Testing a large number of EEPROMs simultaneously. [Arrangement] An algorithmic pattern generator 23 for simultaneously performing a data write verify test on each cell of a plurality of EEPROMs 2, and an input end thereof is connected to an output end of an ALPG 23, and an expected value signal from the ALPG 23 and a test are performed. The output signal from the target cell is compared, and when both signals match, it is judged as good, and when they are different, it is judged as defective, and its input end is connected to the output end of the comparator 24. A retry counter 25 that counts the current number of retries based on the current count and compares the count value with a set value, and its output end is simultaneously connected to each cell of the plurality of EEPROMs 2, and its input end is connected to the output end of the comparator 24. A chip enable that is connected and retries to write-protect the cell for which writing has been confirmed. And a bull control circuit 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for inspecting electrical characteristics of a semiconductor memory device (hereinafter, sometimes referred to as a memory), and more particularly to a data write verify inspecting technique for confirming a data write operation of a memory.
EEPROM (Electrically Erasa)
ble programmable ROM) aging technology.

[0002]

2. Description of the Related Art Generally, an EEPROM has a different data writing time for each device. Also, EEP
In the ROM, writing to the cell of the same address may not be normally performed at one time.
Rewriting (retry) processing may be executed several times to several tens of times. Therefore, in the EEPROM data write verify test, a retry process of the data write verify test is required for each device.

Therefore, conventionally, in the data write verify test of the EEPROM, a retry process is executed for each EEPROM device by an expensive LSI memory tester.

An example of a memory tester described is "Electronic Materials 1989" published by Kogyo Kenkyukai Co., Ltd.
Issue, November issue, issued on November 10, 1989, P141
There is ~ P147.

[0005]

In the conventional data write verify test of the EEPROM, the expensive L
SI tester is used, one for each EEPROM device
The present inventor has revealed that the following problems occur because each device is tested individually. (1) Since a long time is consumed for testing, workability is reduced. (2) If the number of retries that can be performed is ignored and a large number of tests are performed at the same time, the product yield decreases. (3) When the processing speed or the processing flow is different for each device, it is not possible to perform a large number of inspections simultaneously.

It is an object of the present invention to provide a technique for inspecting the electrical characteristics of a semiconductor memory device, which enables simultaneous testing of a large number of semiconductor memory devices.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in a method of inspecting electrical characteristics of a semiconductor memory device in which a data write verify test is performed on a semiconductor memory device, after a data write verify test is simultaneously performed on each cell of a plurality of semiconductor memory devices. , Of the plurality of semiconductor memory devices to be inspected, the data write prohibition process is performed on the inspection target cell that has been verified that the data writing has been normally performed, and then the data write verify inspection is performed. It is characterized in that the same cell of the semiconductor memory device is simultaneously retried.

[0009]

According to the above-mentioned means, when the data write verify test is simultaneously performed on the plurality of semiconductor memory devices, it is verified that the data write is normally performed among the plurality of semiconductor memory devices. By prohibiting the write operation for the test target cell, even if the data write verify test is retried to the plurality of semiconductor memory devices at the same time, it is possible to prevent the actual writing of data in the test target cell in which the write is prohibited. Therefore, even if the data write verify test is retried many times, it is possible to avoid the number of retries from reducing the practical number of data write operations in a normal semiconductor memory device.

When the data write verify test is simultaneously retried for a plurality of semiconductor memory devices, the data write verify test is retried under the same condition, so that it is not necessary to change the write condition or the verify condition for each retry. Therefore, it is possible to suppress an increase in testing time and testing cost.

Since the data write verify test can be simultaneously performed on a plurality of semiconductor memory devices, the workability of the data write verify test can be greatly improved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an EEPROM which is an embodiment of the present invention.
FIG. 3 is a schematic view showing the aging device of FIG. FIG. 2 is a flow chart showing an aging method of the EEPROM which is an embodiment of the present invention. FIG. 3 is a timing waveform diagram at the time of the data write verify inspection.

In the present embodiment, the electrical characteristic inspection device for a semiconductor memory device according to the present invention is configured as an aging device for an EEPROM for implementing the aging method for the EEPROM.

The aging device 1 of this EEPROM is
A constant temperature bath 10 and a testing unit 20 are provided. The constant temperature bath 10 is constructed so as to create and maintain a constant temperature environment or the like necessary for carrying out the aging method, and a plurality of aging boards 11 (only one is shown in FIG. 1), It is configured to be housed.

The aging board 11 is provided with a base 12 which is made of a material having an insulating property and a heat resistance and is formed into a substantially square flat plate shape, and a large number of sockets (not shown) are provided on the base 12. Individually, they are mounted vertically and horizontally. Further, a pair of male connectors 13 and 14 is formed on one end side of the base 12, and both male connectors 1
3 and 14 are electrically connected to the respective sockets via electric wiring (not shown).

On the other hand, the constant temperature bath 10 has a pair of female connectors 1
5 and 16 are opened, and the female connectors 15 and 16 are configured so that the male connectors 13 and 14 of the aging board 11 are inserted and electrically connected. On the other hand, the female connectors 15 and 16 are electrically connected to the respective constituent parts of the testing section 20.

When carrying out the aging method,
The aging board 11 has EE as an object to be aged.
A large number of PROM devices (hereinafter sometimes referred to as devices) 2 are removably mounted through the respective sockets. Aging board 1 with devices 2 installed
1, the male connectors 13 and 14 are electrically connected to the female connectors 15 and 16. By this connection, the EEPROM devices 2 are electrically connected to the testing section 20 in parallel with each other.

A testing board 29 is detachably mounted on the testing section 20, and the testing board 29 has an EEPROM as an object to be aged.
A power supply 21 for supplying power to the device 2, a timing signal generator 22, an algorithmic pattern
A generator (hereinafter referred to as ALPG) 23, a comparator 24, a retry counter 25, a retry register 26, and a chip enable (hereinafter C).
It is called E. ) A control circuit 27 and a defective device information latch circuit 28 are mounted.

The testing board 29 is electrically connected to a central processing unit (hereinafter referred to as CPU) 30, and the CPU 30 controls each component on the testing board 29 in an integrated manner. Is built to be able to.

Power supply 21 and timing signal generator 22
Is electrically connected to each of the EEPROM devices 2 on the aging board 11 via the respective connectors 13, 14, 15, 16.

ALPG23 is an object to be aged, EE
An address signal applied to the PROM device 2, a data signal (including an expected value and a command), and an EEPR.
It is configured to generate signals (out enable signal, word enable signal, etc.) for controlling the OM device 2. These signals are selected in advance in accordance with the electrical characteristic inspection condition and the aging condition for the EEPROM device 2 and stored in the memory of the ALPG 23.

One output terminal of the ALPG 23 is connected to each of the EEPROM devices 2 on the aging board 11, the testing board 29 and the aging board 11,
They are electrically connected in parallel via the respective connectors 13, 14, 15, 16 and are adapted to simultaneously transmit the various signals described above to the respective EEPROM devices 2.

Further, the ALPG 23 is electrically connected to the comparator 24 at the other output end, and transmits the expected value signal to the comparator 24. Incidentally, the expected value signal is a signal that expects a preset predetermined action and may be considered to be equal to the data signal.

The comparator 24 compares the expected value signal from the ALPG 23 with the output signal of each cell to be inspected, which is sent from the EEPROM device 2 through the aging board 11, to judge the pass / fail. Has been done. That is, the comparator 24 determines that the output signal from each inspection target cell is good when the output signal matches the expected value signal, and determines the defect when the output signal is different from the expected value signal.

A retry counter 25 is electrically connected to the comparator 24.
The determination result is transmitted to the counter 25.

The retry counter 25 is configured to count the current number of retries based on the judgment result transmitted from the comparator 24 and hold the counted value. The retry counter 25 counts the current number of retries, compares the count value with a preset value set in the register 26, and outputs the comparison result to the CE signal control circuit 27 and the defective device information latch circuit 28. And is configured to send to.

The value preset in the retry register 26 is a value set based on the guaranteed number of practical retries for the EEPROM device 2 and is the maximum number of retries allowed for the inspection.

The output terminal of the CE control circuit 27 is electrically connected in parallel to each of the EEPROM devices 2 on the aging board 11 via the testing board 29, the aging board 11, and the connectors 13, 14, 15, and 16. It is supposed to be done. Then, the CE control circuit 27
At the time of rewriting, the CE signal is transmitted to the cell of the EEPROM device 2 which has already been normally written, so that the rewriting prohibition process is executed on the written cell.

Next, the operation of the aging device 1 for the EEPROM having the above-described structure will be described to explain the aging method for the EEPROM, which is an embodiment of the present invention, with reference to FIGS. 2 and 3.

When carrying out the aging method of the EEPROM, a large number of EEPROM devices 2 as objects to be aged are detachably mounted on the aging board 11 through the respective sockets. The aging board 11 on which the EEPROM device group 2 is mounted has male connectors 13 and 1
4 is electrically connected to the female connectors 15 and 16. By this connection, the EEPROM devices 2 are connected to the testing unit 20 in parallel with each other.

When the testing unit 20 is started by a command from the CPU 30 after the EEPROM device 2 group is connected to the testing unit 20, the power source 21 supplies V
The pp voltage is set to a predetermined voltage value such as 12V, and the address is cleared. Further, the count of the retry counter 25 is cleared.

Next, the current number of times of the retry counter 25 is incremented by one.

Subsequently, a write command is set by the ALPG 23, and data is simultaneously written by the ALPG 23 to each cell at a predetermined address designated by the ALPG 23 for the plurality of EEPROM devices 2.

A preset very short time (eg 10
After the elapse of μS), the ALPG 23 sets a data write verify (confirmation) command for each of the cells designated in the EEPROM device 2.

A preset very short time (for example, 6 μ
S), the comparator 24 detects ALPG2
Expected value signal sequentially sent from 3 and multiple EEP
Each of the output signals sequentially sent from each of the inspection target cells of the ROM device 2 through the aging board 11 is compared.

When the output signal from one inspection target cell coincides with the expected value signal, the comparator 24 CE-controls the determination signal indicating that the signals of the present inspection target cell in the EEPROM device 2 coincide. To the circuit 27. The CE control circuit 27 controls to suppress the CE function for the matched inspection target cell, that is,
Execute the duplicate write protection process.

Here, when the output signal from the cell to be inspected of the EEPROM device 2 and the expected value signal match, the write operation expected for the cell currently designated in the EEPROM device 2 is normally executed. It means that it has been Therefore, it is not necessary to execute the write operation again for the inspection target cell of the EEPROM device 2 for which the write operation has been executed. Conversely, when the write operation is executed again, the EE
Since the number of writable times when the PROM device 2 is put into practical use is reduced, it is desirable to prohibit further write operations.

Therefore, in the present embodiment, the CE control circuit 27 executes the control for suppressing the CE function to rewrite the cell to be inspected at the present time when the write operation is executed. Is being prevented.

On the other hand, when the output signal from the current cell to be inspected in a certain EEPROM device 2 does not match the expected value signal, the comparator 24 determines that EEPROM
A determination signal indicating that the signals of the present inspection target cell in the ROM device 2 do not match is transmitted to the retry counter 25.

The retry counter 25 responds to the judgment signal from the comparator 24 to compare whether the present count value is smaller than the maximum retry value set in the retry register 26.

When the current count value is smaller than the maximum retry count value, the retry counter 25 sends a determination signal to that effect to the CPU 30. Based on the determination signal, the CPU 30 determines the retry counter 25, ALP
Control G23 and comparator 24. That is,
The loop 31 at the time of retry of the data write / verify shown in FIG. 2 is executed again.

At the time of this retry operation, in the current cell to be inspected in the EEPROM device 2 in which the write prohibition process has been executed, even if a data write operation is instructed, the actual writing of data is suppressed. Therefore, even if the data write command is repeated many times, it is possible to prevent the practical number of data write operations from being reduced.

Further, in the state where the data write command is issued again under the same condition, it is not necessary to change the write command or the verify command for each retry of the data write verify inspection, so that the testing time and testing cost can be reduced. Can be suppressed.

Even in this data write verify operation again, the same E as the previous mismatch is obtained.
When the output signal from the cell to be inspected in the EPROM device 2 again becomes inconsistent with the expected value signal, the comparator 24 retries the retry counter with a determination signal indicating that the same cell is inconsistent as the previous inconsistency. 25 again.

The retry counter 25 responds to the re-judgment signal from the comparator 24 to compare whether the present count value is smaller than the maximum retry value set in the retry register 26. At this time, it goes without saying that the count value of the retry counter 25 is counted up only once compared with the previous time.

When the current count value is smaller than the maximum retry count value, the retry counter 25 sends a determination signal to that effect to the CPU 30. Based on the determination signal, the CPU 30 determines the retry counter 25, ALP
Control G23 and comparator 24. That is,
The loop 31 at the time of retrying the data write / verify shown in FIG. 2 is executed again.

When the current count value becomes larger than the maximum retry count value after the above-described retry loop 31 is repeated many times, the retry counter 2
5 transmits a determination signal to that effect to the CPU 30. CPU
By controlling the defective device information latch circuit 28 on the basis of the determination signal, not only the cell under inspection in which writing has not been executed but also the entire EEPROM device 2 in which the cell is formed is defective. To certify. Then, the EEPROM device 2 is excluded from the subsequent data write verify inspection target. Then, along with this exclusion, the count of the retry counter 25 is cleared.

When the EEPROM device 2 having a cell for which the write operation has not been executed even after the maximum number of retries is retried by the retry loop 31 is excluded from the inspection object, the CPU 30 determines whether or not all the devices are defective. It That is, it is determined whether or not the exclusion has been executed in all the EEPROM devices 2.

If all devices are defective,
This means that the EEPROM device 2 to be inspected does not exist, so that the power supply 21 makes the Vpp voltage and the Vcc voltage equal by the path 34 shown in FIG. 2, and the EEPROM device 2 to be inspected this time. The data write verify check for the group is completed.

On the other hand, if all the devices are not defective, the EEPROM device 2 to be inspected remains, so that the inspection previously executed by the path 35 shown in FIG. 2 is the inspection for the cell of the final address. It is determined whether or not. If it is not the cell at the final address, the data write verify test is continuously executed on the next cell in the remaining EEPROM device group 2.

On the other hand, after the comparator 24 determines that the output signal from the cell to be inspected matches the expected value signal and the CE control circuit 27 executes the duplicate write inhibit control, the current inspected object is detected. An EEPR
If it is determined that the output signals of all the cells of the OM device match the expected value signals, the ALPG23
In, the cell at the next address in each EEPROM device 2 is designated as the next inspection target.

Then, it is verified whether or not the data is written in the designated cell to be inspected next. In other words, by designating the cell of the next address, the data write verify check is performed for a plurality of Es.
For the EPROM device 2, only one cell has been processed at the same time.

Then, a plurality of EEPROM devices 2
If the data write operation has not been executed for the cell at the next address in, the loop 32 shown in FIG. 2 causes the data write verify check operation to return to the time of the clear operation of the retry counter 25. Then, the above-described retry operation of the data write verify check is repeated.

On the other hand, when all the data write operations are executed for this inspection target cell group, when the verify judgment is made, the CE control circuit 27 suppresses the CE function for all the cell groups, that is, the data write operation. The ban is lifted at the same time.

When the CE control circuit 27 releases the inhibition of the CE function, it is determined whether or not the cell to be inspected at that time is the cell of the final address. When it is determined that the cell has the final address, the power supply 21 makes the Vpp voltage equal to the Vcc voltage, and the data write verify test is completed.

When it is determined that the cell is not the cell of the final address, the maximum number of retries is stored by the retry counter 25 by the loop 33 shown in FIG. Cleared. Further, the address is incremented by the ALPG 23.

Then, by the loop 33 shown in FIG. 2, the data write verify test operation is returned to the time of the clear operation of the retry counter 25. Then, the above-described data write verify inspection operation is repeated.

According to the above described embodiment, the following effects can be obtained. (1) Since the data write verify test can be executed simultaneously for a plurality of EEPROM devices, the workability of the data write verify test can be significantly improved.

(2) When the data write verify test is simultaneously performed on a plurality of EEPROM devices, the CE function is performed on the test target cell of the plurality of EEPROM devices, which has been verified that the data write was normally performed. By suppressing the data write verify check,
Even if the EPROM device is retried at the same time, it is possible to prevent the actual writing of data in the cell to be inspected with the CE function suppressed. It is possible to avoid reducing the practical number of data write operations in various EEPROM devices.

(3) When the data write verify test is simultaneously retried for a plurality of EEPROM devices, the data write verify test is retried under the same condition, so that the write condition and the verify condition are not changed for each retry. As a result, it is possible to suppress an increase in testing time and testing cost.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the semiconductor memory device to be inspected is not limited to the EEPROM, but may be an EPROM (Electror).
ically Programmable ROM. ROM that can be erased by irradiating ultraviolet rays. ) Etc.

In the above description, the case where the invention made by the present inventor is mainly applied to the aging technique which is the background field of application has been described. However, the present invention is not limited to this, and it is applicable to a wafer prober or an auto handler. It can be applied to all electrical characteristic tests such as a write verify test.

[0064]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

When the data write verify test is simultaneously performed on a plurality of semiconductor memory devices, the CE function is applied to the test target cell of the plurality of semiconductor memory devices, which has been verified that the data write is normally performed. By suppressing the data write verification test, even if the data write verification test is retried to the plurality of semiconductor memory devices at the same time, it is possible to prevent the actual writing of data in the test target cell in which the CE function is suppressed. Even if the data write verify test is retried many times, it is possible to avoid that the number of retries reduces the practical number of data write operations in a normal semiconductor memory device.

When the data write verify inspection is simultaneously retried for a plurality of semiconductor memory devices, the data write verify inspection is retried under the same condition, so that it is not necessary to change the write condition or the verify condition for each retry. Therefore, it is possible to suppress an increase in testing time and testing cost.

Since the data write verify test can be executed simultaneously for a plurality of semiconductor memory devices, the workability of the data write verify test can be greatly improved.

[Brief description of drawings]

FIG. 1 is a schematic view showing an aging device of an EEPROM which is an embodiment of the present invention.

FIG. 2 is a flowchart showing an aging method of an EEPROM which is an embodiment of the present invention.

FIG. 3 is a timing waveform diagram at the time of data writing and verification.

[Description of References] 1 ... Aging device for EEPROM (electrical characteristic inspection device for semiconductor memory device), 2 ... EEPROM device (semiconductor memory device), 10 ... Constant temperature bath, 11 ... Aging board, 12 ... Base, 13, 14 … Male connector, 15, 1
6 ... female connector, 20 ... testing part, 21 ... power supply,
22 ... Timing signal generator, 23 ... Algorithmic pattern generator (ALPG), 24 ... Comparator, 25 ... Retry counter, 26 ... Retry register, 27 ... Chip enable (CE) control circuit, 28 ... Bad device Information latch circuit, 29 ... Testing board, 30 ... Central processing unit (CPU),
31, 32 ... Flow loops, 33, 34, 35 ... Flow paths.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Keiji Tomita 3-3, Fujibashi 2-3, Ome-shi, Tokyo Within Hitachi Tokyo Electronics Co., Ltd. (72) Hideaki Mayuzumi 3-3 2 Fujibashi, Ome-shi, Tokyo Hitachi Inside Tokyo Electronics Co., Ltd.

Claims (3)

[Claims] 1. A method for inspecting electrical characteristics of a semiconductor memory device, wherein a data write verify test is performed on the semiconductor memory device, wherein a data write verify test is simultaneously performed on each cell of the plurality of semiconductor memory devices. After that, the data write inhibit process is performed on the test target cell that is verified that the data write is normally performed among the plurality of test target cells of the semiconductor memory device, and then the data write verify test is performed. A method for inspecting electrical characteristics of a semiconductor memory device, wherein the same cells of a plurality of semiconductor memory devices are simultaneously retried. 2. An electrical characteristic inspection device for a semiconductor memory device, wherein a data write verify test is performed on a semiconductor memory device, wherein a data write verify test is simultaneously performed on each cell of a plurality of semiconductor memory devices. And a means for executing a data write prohibition process on a cell to be inspected, which has been verified that data writing has been normally performed among a plurality of cells to be inspected in the semiconductor memory device, and a data write verify test. A means for simultaneously retrying the same cells of a plurality of semiconductor memory devices, respectively, and an electrical characteristic inspection device for a semiconductor memory device. 3. An electrical characteristic inspection device for a semiconductor memory device, wherein a data write verify test is executed on the semiconductor memory device, wherein: a power supply for simultaneously supplying power to the plurality of semiconductor memory devices; An algorithmic pattern generator that simultaneously performs a data write verify test on each cell of a semiconductor memory device, and its input end is connected to the output end of the algorithmic pattern generator. The expected value signal from the generator is compared with the output signal sent from each cell to be inspected, and if the output signal matches the expected value signal, it is judged as good, and the output signal is the expected value signal. If they are different, the comparator that determines that it is defective and its input end is connected to the output end of the comparator. It has been,
The current retry count is counted based on the judgment result sent from the comparator and the count value is held, and the count value and the set value set in the register are compared, and the count value is higher than the set value. It has a retry counter that stops the retry before it grows, and its output end is connected to each cell of multiple semiconductor memory devices at the same time, and its input end is connected to the output end of the comparator. In a semiconductor memory device, a chip enable control circuit is provided for executing a write inhibit process on a cell to be inspected that has already been normally written when retrying a data write verify inspection. Electrical characteristics inspection device.