200840023 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種快閃記憶體，尤指一種浮動閘極(floating gate)位於控制閘極(control gate)兩側之快閃記憶體。 【先前技術】 在現代化的資訊社會中，資訊的大量流通已成為日常生活的 一部份。為了方便資訊的管理，用來存取資訊的記憶裝置，也成 為為成產業發展的重點。尤其是快閃記憶體，其具 有低耗電、高速度、可讀寫、非揮發性（non_v〇latile)、不需機械 式動作等優點’已在各種記憶裝置中，佔有重要的一席之地。 一般而言，快閃記憶體係為一種非揮發性(n〇n-v〇latile)記憶 體，由於具有不因電源供應中斷而造成儲存資料遺失之特性，且 又具有重複寫入以及可被電抹除等優點，因此近年來被廣泛使用 在行動電話(mobile phone)、數位相機(digital camera)、遊戲機(video player)、個人數位助理(personal digital assistant，PDA)等電子產品 中。 但是，習知技術中的快閃記憶體為避免内部之接觸插塞 (contact plug)和周邊結構，如字元線(w〇rd line)等發生短路。所以， 接觸插基和子元線專周邊結構必須保持一定的適當距離，這使得 快閃記憶體的面積無法下降。可是，目前業界技術不_向微小 200840023 毛展所以細小非揮發性s己憶體的面積是現階段快閃記憶體技 術發展的重點，故如觸小轉發性記憶_面_為此領域之 重要課題。 【發明内容】 本發明係提供-種快閃記憶體單元㈣，以解決上述問題。 本發明係提供-種快閃記憶體單元，包含氧化層⑽e 〇娜位於基底上，—閘極結構位於_氧化層上方，—氧化·氮 化-氧化(oxide-nitride-oxide，ONO)層位於閘極結構兩側。1中，浮 動閘極位於間極結構兩側並與氧化-氮化-氧化層接壤，而側壁子 (啊㈣位於浮_極上方，以及掺籠位於該浮糊極的一側之 基底中。 本發明之快閃記憶聽構上的娜是具有兩個浮朗極位於 -控制閘極的兩側’而且控綱極頂部具有—定厚度介電層，以 及浮動間極的頂部具有側壁子，且整個結構外側被-介電^質的 襯墊層所覆蓋。在本發明製作浮_極時，可_蓋層和側壁子 自對準蝕财晶⑪叙硬料恤仏构，明 (—Μ Wmd〇W)。而當進行接觸孔時，^層 Gm，可作為餘刻停止層_轉使用。由於具導電 的汁動閘極和控_極上方又分別具有側壁子和蓋層，所以可達 到良好的介電效果會麵成綱滅後造雜路的情況。因 200840023 快閃記憶體中的接觸插塞和閘極結構之間所絲持的距離較 習知技術小，故本發明可有效降低記憶體面積。 【實施方式】 請參考第1至8圖，第1至8 _為本發縣閃記憶體之製 程示意圖。如第！圖所示，一基底區分為記憶區搬和周邊 區綱’而基底200内具有數個摻雜井⑽聊6，其中，基底· 係可為-石夕基底或者一石夕覆絕緣⑽c〇n 〇n insuiator綱基底。首 先，在基底200上方依序形成一介電層，例如是氧化層观、一導 ^ Μ列如是-多晶石夕層21〇和一氮切層(未顯示）。接著，進行 一黃光製程(lithography process)在主動區域聰，αα)方向 蝕刻出數個之後可形成淺溝隔離212的凹槽。再進行一離子佈植 (imPlantingprocess)，在凹槽外圍形成通道停止植入⑽邮 i_a_ 216。之後，沈積介電層在氮切層(未顯示)上並填滿淺 溝隔離212_槽，先進行—化學機械研磨製程⑽咖㈣ mechanical polishing)將介電層去除至露出氮化石夕層(未顯示），然 後，去除氮化石夕層，再進行-化學機械研磨製程直至多晶石夕層 21〇 ’以形成淺溝隔離212。接著，沈積一罩幕層，例如是^匕層 214在多晶矽層210上方。 請參考第2圖’進行-微影製程，利驗刻製程依序去除部 分氧化層2U、多晶石夕層別、部分淺溝隔離212以及氧化層通， 以形成開口 400。接著，可利用習知技術，形成一介電層，θ例如是 200840023 :氧化2、一氮化層依序形成在開σ彻、氧化層2i4上 ==乾_製程，以移除部份的氧化層、氮化層，而剩餘二， ;Γ=化-氮化層402在開σ.側壁上。之後再形成-: 2層，可卿料技術，實施_沉積餘或氧化製程形成—成較/ :化:404在乳化_氮化層4〇2表面上和開口 : 於開口 4_壁的氧化·氮化層術和氧化層_形化、= ‘xide’_開口伽底部= ^則作為間極氧化層撕。接下來，在氧化層⑽上 電層，例如是容曰si、，士 乃7導 程以形成多晶石夕口彻，並進行一化學機械研磨製 請參第：:：=之“來觀察之製程步驟。 蝴4的多B日縣Γ 進行一賴刻製程，使得經過回 ^ 曰$ 406和其外圍的氧化層214且有一古声#斑 :::餘的多晶—氧化層214二 緣層，之材質需和氧化層W需具有—較佳的_刻比。、 緣層行一化學機械研磨製程，去除部分第一絕 佳的，例如乾細3第一絕緣層603再進行一回餘刻製程，較 蓋層繼。 程’直到比周圍氧化層214來的低，以形成 200840023 _如第5圖所*，利用一習知技術，例如是濕钱刻製程，去除 氧化層214。然後，沈積一第二絕緣層605，例如是氮化石夕層、氮 氧石夕化物層...等並進行—乾_製程，以形成側壁子6G4圍繞在 多晶矽層406的周圍並位於多晶矽層21〇上方。 >如第6圖所示，利用側壁子6〇4和蓋層6〇2作為侧遮罩， 減自我對準钱刻(self align etch)，去除未被側壁子6〇4覆蓋之多 晶石夕^1〇。如第7圖所示，在整個基底200上形成-第三絕緣層， 例如疋氮化石夕層、氮氧石夕化物層…等作為襯墊層6〇8 ,需注意的 疋’襯塾層608的材質需和後續製程中形成的介電層802具有- 較佳的選擇蝕刻比。 經由以上製程，記憶區202所形成之多晶矽層4〇6係為快閃 記憶體之控制閘極，其上方具有蓋層6〇2，而其兩側的多晶石夕層 210則為洋動閘極，其上方則具有側壁子6〇4。在此，控制閘極及 浮動閘極的材質並不限定在多晶石夕一種材質，任一適合的閘極材 料，在製程條件許可下，皆可採用。 接下來，進行一離子佈植以形成摻雜區，在此實施例中因考 量離子佈植溫度，故先完成N型金氧半導體電晶體(N—type metal-oxide_semiconductor transistor，NMOS transistor)614 的源極/ 没極610後，再完成P型金氧半導體電晶體(P-type metal-oxide-semiconductor transistor，PMOS transistor)612 的源極/ 11 200840023 汲極610，其中兩個NMOS transistor 614中一個是高電壓NMOS transistor (high voltage NMOS transistor, HVN transistor)，另一個是 低電壓 NMOS transistor (low voltage NMOS transistor，LVN transistor) ; PMOStransistor612 亦同，其一為 HVPtransistor，另 一個則為 LVP transistor 〇 請參考第8圖，沈積一介電層，例如是硼磷矽玻璃(BPSG)層 802在基底200上，對其進行一化學機械研磨製程，以去除襯墊層 608上方的硼磷矽玻璃層8〇2。再沈積一介電層，例如是四乙氧基 矽烷(TE0S)層804在基底200上，接著，形成一多晶矽層(未圖示) 在四乙氧基矽烷層804上方，進行一微影製程，並以四乙氧基矽 烧層804上方的多晶矽層作為硬遮罩(hard mask)對四乙氧基矽烷 層804進行餘刻製程’以形成接觸淺溝。之後，再 進行一黃光姓刻，以蓋層602、側壁子604以及襯墊層608為蝕刻 遮罩’進行另一自動對準蝕刻，形成區域佈線(1〇calinterconnect) 開口 ’以擴大部分先前形成之接觸淺溝的寬度。之後，沈積一金 屬層’如：鎢金屬等，將其填入接觸淺溝和區域佈線開口中，並 以化學機械研磨製程磨至裸露出四乙氧基矽烷層8〇4，以形成接觸 插塞(contact plug)8〇0、導線 808。 請參考第9圖，第9圖係為第1至8圖製程所形成之快閃記 „ 憶體結構之俯視示意圖。複數條平行的淺溝隔離(shallow trench isolation，STI)212和複數條平行的多晶矽層4〇6構成的字元線 12 200840023 (word line)彼此垂直排列在快閃記憶體之記憶區202中。多晶石夕層 406的兩側外依序為氧化_氮化-氧化層4〇1、浮動閘極和其上方之 側壁子604，以及又稱共源極(comm〇ns〇urce)的源極(s〇urce)/没極 (drain)610。另外’有些接觸插塞(c〇ntact plug)81〇則位於源極/汲極 610上方，另外有接觸插塞8〇6位於多晶矽層4〇6上方。在第9 圖中，分別具有AA’、BB’、CC’三條切線，在第1〇圖中將詳細說 明每條剖線方向之橫剖圖結構。 在第10圖AA，方向之橫剖圖中，多晶矽層4〇6係作為快閃記 憶體單元的控制閘極，其兩側具有多晶矽層21〇作為浮動閘極， 而多晶矽層210的外側又具有源極/汲極61〇。多晶矽層4〇6和其 上方的蓋層602 (cap layer)構成閘極結構，而多晶矽層21〇上方具 有側壁子604，而多晶矽層406、蓋層602和多晶矽層210、側壁 子604之間具有0]^0層4〇1作介電層，且多晶矽層4〇6和基底 200之間具有閘極氧化層4〇5。襯墊層6〇8係覆蓋在蓋層6〇2、側 壁子604和浮動閘極21〇以及基底2〇〇上。 本實施例之多晶矽層210和基底200之間具有氧化層2〇8，而 ΟΝΟ層401之一側與氧化層2〇8接壤，另一側則與閘極氧化層4仍 襄另外在此貫施例中，快閃記憶體單元被石朋碟石夕玻璃層802 和四乙氧基矽烷層804所覆蓋。而接觸插塞81〇位於一多晶曰石夕層 406的一側和源極/汲極610電性連接。 13 200840023 在第10® BB，方向之橫剖圖中，多晶石夕層楊上方具有蓋層 602和襯墊層608，部分多晶石夕層概上方形成接觸插塞8〇6，^ 未形成接職塞806的襯㈣_上謂具有四乙氧基魏層 804 ’而部分四乙氧基石夕烧層8〇4具有導線簡。另外，第⑴圖中 cc’方向之多晶_ 21〇兩側的淺溝隔離212，以及多晶碎層加 上方具有氮切層6G2,而且另有婦層_位於蓋層6()2上方， 概墊層6〇8 _L方具有四乙氧基石夕烧層綱，其内具有數個導線獅。 本實施例之'_記憶體有兩個浮_極位於—控制閘極的兩 側’而且控制閘極頂部具有―轉度介電層，以及浮動閘極的頂 4具有側壁子’且整個結構外顺—絕緣介電性質的襯塾層所覆 盍。在製作浮動閘極時，可利用蓋層、側壁子作為自對準姓刻多 晶矽層之硬遮罩(hardmask)，以增大製程範缚㈣簡偷㈣。 由於”導電性貝的浮動雜和控侧極上方又分別具有側壁子、 蓋層和姆層可達職好的絕緣介電效果，_不會在形成接觸 插塞後造成短路。因此，娜咖中的接觸插塞和閘極結構之 間所需保持的距離較f知技術小’故本發明可有效降低記憶體面 積:例如在!6位元的快閃記憶體中約可下降ιι%的面積，而在幻 位70的快閃記憶體中約可下降6%的面積。 14 200840023 【圖式簡單說明】 ί:=圓係為本發明快柯記憶體之製程示意圖。 —回係為第1至s職程所形成之快閃記憶體結觀俯視示意圖 弟1〇 _第9圖之ΑΑ，、ΒΒ，、cc，三條切線之撗剖圖結構。 基底 記憶區 周邊區 摻雜井 氧化層 多晶碎層 淺溝隔離 通道停止植入區 開口 氧化-氮化-氧化層 氧化_氮化層 閘極氧化層 盒層 第一絕緣層 側壁子 弟—絕緣層 襯墊層 【主要元件符號說明】 200 202 204 206 208、214、404 210、406 212 216 400 401 402 405 602 603 604 605 608 15 200840023 610 源極/没極 612 P型金屬氧化電晶體 614 N型金屬氧化電晶體 802 硼磷矽玻璃層 804 四乙氧基矽烷層 806 、 810 接觸插塞 808 導線 16200840023 IX. Description of the Invention: [Technical Field] The present invention relates to a flash memory, and more particularly to a flash memory in which floating gates are located on both sides of a control gate. [Prior Art] In the modern information society, the massive circulation of information has become a part of everyday life. In order to facilitate the management of information, the memory device used to access information has also become the focus of the development of the industry. In particular, the flash memory has the advantages of low power consumption, high speed, readable and writable, non-volatile (non-v〇latile), no mechanical action, etc., and has occupied an important place in various memory devices. In general, the flash memory system is a non-volatile (n〇nv〇latile) memory, which has the characteristics of not being lost due to power supply interruption, and has repeated writing and can be erased by electricity. In recent years, it has been widely used in electronic products such as mobile phones, digital cameras, video players, and personal digital assistants (PDAs). However, the flash memory in the prior art avoids short-circuiting of internal contact plugs and peripheral structures such as word lines (w〇rd lines). Therefore, the contact interposer and the sub-line specific peripheral structure must be kept at an appropriate distance, which makes the area of the flash memory not fall. However, the current industry technology is not _ to the tiny 200840023 hair extension, so the area of small non-volatile suffixes is the focus of the development of flash memory technology at this stage, so it is important to touch the small forward memory _ surface _ Question. SUMMARY OF THE INVENTION The present invention provides a flash memory unit (4) to solve the above problems. The present invention provides a flash memory cell comprising an oxide layer (10) e on the substrate, a gate structure above the oxide layer, and an oxide-nitride-oxide (ONO) layer. Both sides of the gate structure. In the first embodiment, the floating gate is located on both sides of the interpole structure and borders the oxidized-nitrided-oxidized layer, and the sidewalls (ah (four) are located above the floating_pole, and the doped cage is located in the substrate on one side of the floating paste. The flash memory of the present invention has two floating poles on both sides of the control gate and the top of the control pole has a constant thickness dielectric layer, and the top of the floating pole has a side wall, and The outer side of the whole structure is covered by a dielectric layer of a dielectric layer. When the floating _ pole is fabricated in the present invention, the cover layer and the side wall can be self-aligned and etched into a solid material. Wmd〇W). When the contact hole is made, the layer Gm can be used as a residual stop layer. Since the conductive juice gate and the control electrode have a side wall and a cap layer respectively, A good dielectric effect can be achieved after the formation of a miscellaneous path. Since the distance between the contact plug and the gate structure in the flash memory of 200840023 is smaller than the prior art, the present invention can Effectively reduce the memory area. [Embodiment] Please refer to pictures 1 to 8, 1st to 8th - this is the hair Schematic diagram of the flash memory process. As shown in the figure!, a substrate is divided into a memory area and a peripheral area, and the substrate 200 has a plurality of doping wells (10), wherein the base layer can be - Shi Xi a substrate or a stellite insulating (10) c〇n 〇n insuiator substrate. First, a dielectric layer is sequentially formed over the substrate 200, for example, an oxide layer, a column, a polycrystalline layer, and a polycrystalline layer. A nitrogen nitride layer (not shown). Next, a lithography process is performed to etch a plurality of grooves in the active region Cong, αα) direction to form shallow trench isolation 212. An ion implantation process (imPlanting process) is performed to form a channel at the periphery of the groove to stop implanting (10) mail i_a_ 216. Thereafter, the dielectric layer is deposited on the nitrogen cut layer (not shown) and filled with the shallow trench isolation 212_slot, first performing a chemical mechanical polishing process (10) mechanical polishing process to remove the dielectric layer to expose the nitride layer ( Not shown), then, the nitride layer is removed, and a chemical mechanical polishing process is performed until the polycrystalline layer 21' to form shallow trench isolation 212. Next, a mask layer is deposited, such as a layer 214 over the polysilicon layer 210. Referring to Figure 2, the lithography process is performed to remove portions of the oxide layer 2U, the polycrystalline layer, the shallow trench isolation 212, and the oxide layer to form the opening 400. Then, a dielectric layer can be formed by using a conventional technique, for example, 200840023: oxidized 2, a nitrided layer is sequentially formed on the opening σ, the oxide layer 2i4 == dry _ process to remove part of The oxide layer, the nitride layer, and the remaining two, Γ=chemical-nitridation layer 402 are on the open σ. sidewall. Then form -: 2 layers, can be used in the material technology, the implementation of _ deposition or oxidation process formation - into / / : 404 on the surface of the emulsified - nitride layer 4 〇 2 and opening: oxidation of the opening 4_ wall · Nitriding layer and oxide layer _ shape, = 'xide' _ opening gamma bottom = ^ then as the inter-electrode oxide layer tear. Next, in the oxide layer (10), the electric layer, for example, the Rongsi si, Snei 7 lead to form polycrystalline stone, and a chemical mechanical polishing system, please refer to:::= The process steps of the butterfly 4 of the multi-B day county 进行 进行 刻 , , , , , 和 和 和 氧化 氧化 氧化 氧化 氧化 氧化 氧化 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 The edge layer, the material needs to have a better _ engraving ratio with the oxide layer W. The edge layer is subjected to a chemical mechanical polishing process to remove a portion of the first excellent, for example, the dry fine 3 first insulating layer 603 and then one The process of returning to the engraving process is continued until the cap layer is lower than that of the surrounding oxide layer 214 to form 200840023. As shown in FIG. 5, the oxide layer 214 is removed by a conventional technique such as a wet etching process. Then, a second insulating layer 605, such as a nitride layer, a oxynitride layer, etc., is deposited and subjected to a dry-process to form a sidewall spacer 6G4 surrounding the polysilicon layer 406 and located in the polysilicon layer. Above layer 21. > As shown in Fig. 6, using the side wall 6〇4 and the cover layer 6〇2 as side masks The self-aligned etch is removed to remove the polycrystalline stone that is not covered by the sidewalls 6〇4. As shown in Fig. 7, a third insulating layer is formed over the entire substrate 200, for example疋 nitride layer, oxynitride layer, etc. as the liner layer 6〇8, it should be noted that the material of the lining layer 608 needs to be formed with the dielectric layer 802 formed in the subsequent process - a preferred choice Etching ratio. Through the above process, the polysilicon layer 4〇6 formed by the memory region 202 is a control gate of the flash memory, and has a cap layer 6〇2 on the upper side, and a polycrystalline layer 210 on both sides thereof. The outer gate has a side wall 6〇4. Here, the material of the control gate and the floating gate is not limited to a material of polycrystalline stone, and any suitable gate material is in the process condition. Under the permission, it can be used. Next, an ion implantation is performed to form a doped region. In this embodiment, the ion implantation temperature is considered, so that the N-type metal-oxide semiconductor transistor is completed first (N-type metal-oxide_semiconductor) Transistor, NMOS transistor) 614 source / no pole 610, then complete P-type gold oxygen Source of the P-type metal-oxide-semiconductor transistor (PMOS transistor) 612 / 11 200840023 The drain 610, wherein one of the two NMOS transistors 614 is a high voltage NMOS transistor (HVN transistor) The other is a low voltage NMOS transistor (LVN transistor); the same is true for PMOStransistor612, one is HVPtransistor and the other is LVP transistor. Please refer to Figure 8 to deposit a dielectric layer, such as boron phosphorus. A beryllium glass (BPSG) layer 802 is applied to the substrate 200 by a chemical mechanical polishing process to remove the borophosphorus glass layer 8〇2 over the liner layer 608. A dielectric layer, such as a tetraethoxy decane (TEOS) layer 804, is deposited over the substrate 200, followed by a polysilicon layer (not shown) over the tetraethoxysilane layer 804 for a lithographic process. And the polyethoxy layer above the tetraethoxythoracic layer 804 is used as a hard mask to carry out a remnant process on the tetraethoxydecane layer 804 to form a contact shallow trench. Thereafter, a yellow ray is performed, and another automatic alignment etch is performed with the cap layer 602, the sidewall spacer 604, and the pad layer 608 as an etch mask to form a region wiring (1〇calinterconnect) opening to enlarge a portion of the previous The width of the contact shallow groove formed. Thereafter, a metal layer such as tungsten metal is deposited, which is filled into the contact shallow trench and the area wiring opening, and is ground by a chemical mechanical polishing process to expose the tetraethoxydecane layer 8〇4 to form a contact plug. Contact plug 8〇0, wire 808. Please refer to Figure 9, which is a top view of the flash structure formed by the processes of Figures 1 to 8. A plurality of parallel shallow trench isolation (STI) 212 and a plurality of parallel The word line 12 200840023 (word line) formed by the polysilicon layer 4〇6 is vertically arranged in the memory area 202 of the flash memory. The two sides of the polycrystalline layer 406 are sequentially oxidized-nitrided-oxidized layer. 4〇1, floating gate and sidewall 604 above it, and source (s〇urce)/drain 610, also known as common source (comm〇ns〇urce). Also 'some contact plugs (c〇ntact plug) 81〇 is located above the source/drain 610, and the contact plug 8〇6 is located above the polysilicon layer 4〇6. In the 9th figure, there are AA', BB', CC' respectively. Three tangent lines, the cross-sectional structure of each cross-sectional direction will be described in detail in Figure 1. In Figure 10A, the cross-sectional view of the polycrystalline germanium layer 4〇6 is used as the control of the flash memory unit. The gate has a polysilicon layer 21 on both sides as a floating gate, and the outside of the polysilicon layer 210 has a source/drain 61〇. The wafer layer 4〇6 and the cap layer 602 thereon constitute a gate structure, and the polysilicon layer 21 has a sidewall spacer 604 above it, and the polysilicon layer 406, the cap layer 602 and the polysilicon layer 210, and the sidewall spacer 604 There is a layer of 0 ^ 0 〇 1 as a dielectric layer, and a gate oxide layer 4 〇 5 between the polysilicon layer 4 〇 6 and the substrate 200. The lining layer 6 〇 8 is covered in the cap layer 6 〇 2 The sidewall 604 and the floating gate 21〇 and the substrate 2 are disposed. The polysilicon layer 210 and the substrate 200 of the embodiment have an oxide layer 2〇8, and one side of the germanium layer 401 is bordered by the oxide layer 2〇8. The other side is still with the gate oxide layer 4. In addition, in this embodiment, the flash memory cell is covered by the stone plate 802 and the tetraethoxy decane layer 804. The contact plug 81 The side of the polysilicon layer 406 is electrically connected to the source/drain 610. 13 200840023 In the cross-sectional view of the 10th BB, the polycrystalline stone layer has a cap layer 602 above it. And the lining layer 608, a portion of the polycrystalline slab layer forms a contact plug 8〇6, and the lining of the occupant 806 is not formed (4) _ the upper layer has a tetraethoxy Wei layer 804 And a portion of the tetraethoxy zephyr layer 8〇4 has a simple wire. In addition, the shallow groove isolation 212 on both sides of the polycrystalline _ 21〇 in the cc' direction in the figure (1), and the polycrystalline fracture layer plus the nitrogen cut on the upper side Layer 6G2, and another layer _ located above the cover layer 6 () 2, the cushion layer 6 〇 8 _L side has a tetraethoxy zebra layer, which has several wire lions. The memory has two floating _ poles located on both sides of the control gate 'and the top of the control gate has a "turning dielectric layer", and the top 4 of the floating gate has a side wall 'and the entire structure is externally-insulated dielectric The nature of the lining layer is covered. When making a floating gate, the cap layer and the sidewall can be used as a hard mask for self-aligned polysilicon layer to increase the process specification (4). Because "the floating impurities of the conductive shell and the upper side of the control side pole have the insulating dielectric effect of the sidewall, the cap layer and the m layer respectively, the _ does not cause a short circuit after forming the contact plug. Therefore, Naca The required distance between the contact plug and the gate structure is smaller than that of the known technology. Therefore, the present invention can effectively reduce the memory area: for example, in a flash memory of !6 bits, it can be reduced by about 3%. The area can be reduced by about 6% in the flash memory of the Phantom 70. 14 200840023 [Simple description of the drawing] ί:=Circle is a schematic diagram of the process of the invention. The flash memory formed by the 1 to s career is a top view of the schematic diagram of the 〇 第 第 第 第 第 第 第 第 第 第 第 第 第 第 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Polycrystalline shredded shallow trench isolation channel stops implant region opening oxidation-nitriding-oxidation layer oxidation_nitride layer gate oxide layer box layer first insulating layer sidewall children-insulation layer liner layer [main component symbol description] 200 202 204 206 208, 214, 404 210, 406 212 216 400 4 01 402 405 602 603 604 605 608 15 200840023 610 Source/No-pole 612 P-type metal oxide crystal 614 N-type metal oxide crystal 802 Boron phosphate glass layer 804 Tetraethoxy decane layer 806, 810 contact plug 808 Wire 16