TW200828817A - Analog to digital converting system - Google Patents

Abstract

A new Analog to Digital Converter (ADC) architecture using subranging successive approximation can reach high sampling rate, low power consumption and low complexity. It also can enhance the chip yield and area efficiency. Accordingly, the new proposed ADC is to combine the high sampling rate, low resolution flash converter with the low power consumption, low sampling rate successive approximation converter.

Description

200828817 r〇zyjuu49TW 22487twf.doc/n IX. INSTRUCTIONS: FIELD OF THE INVENTION The present invention relates to an analog-to-digital conversion system, and more particularly to a sub-range continuous approximation analog-to-digital conversion system. [Prior Art] Analog to digital converter (ADC) architectures such as flash ADC, pipeline (Pipelin DC, continuous approximation; Approximation, SA) ADC and bi-step (TW0-SteP ) ADC. These ADC architectures have their own range of applications. Although fast-flash ADCs are suitable for high-speed sampling rate applications, they consume a lot of power. The continuous approximation ADC has a lower sampling frequency, but its power consumption is low and its circuit complexity is low. ^ The characteristics of a pipelined ADC are between a flash aDC and a continuous approximation ADC', but a pipelined ADC requires a Multiplier Digital-to-Analog Converter (MDAC). The MDAC internally includes a Residue operational amplifier, which is a negative feedback frame. Therefore, the residual op amp will become the bottleneck of the pipeline ADC in high-speed sampling frequency applications. The dual P white ADC is further classified into a bit-cycled (Bit_Cycling) ADC and a sub-ranged (Subranging) ADC. The bit-cycle ADC also needs the remaining * to amplify, so there are similar problems. According to the current literature, the sub-range ADC can break through the bottleneck of the pipeline ADC and the bi-stage ADC with bit-cycle, achieving high-speed sampling frequency. Several conventional ADC systems will be introduced below. 5 200828817 rozs, 49TW 22487twf.doc/n The first conventional ADC system can be found in U.S. Patent No. 6,124,818. It uses pipeline technology, so its computing power is greatly increased. It uses a dual ADC architecture, and the internal coarse (c〇arse) ADc and fines use the SA-ADC architecture. Therefore, reducing the need for digital to analog converter (DAC) resolution has made DAc's circuit area smaller and adc's poor material conversion speed high. However, since the coarse ADC adopts the SA_ADC architecture, its Latency time is long and the sampling frequency is relatively slow. The first type of three-information ADC system can be found in U.S. Patent 5,973,632. "It is a technology that uses a two-stage ADC. Both the internal coarse ADC and the thin ADC use a flash architecture for data conversion. Due to &, the ADC's lean material conversion speed is increased. However, since the fine ADC adopts a flash architecture, the number of comparators is (2 jobs + 2 calls 2), MSBs and LSBs represent the most south effective byte and the least significant byte respectively, so the number of comparators is relatively large. This circuit has a high complexity, high power consumption and low effective area utilization. A second conventional ADC system can be found in U.S. Patent No. 5,567,534. V is a technology that uses a two-stage ADC. The internal coarse ADC uses a flash ADC architecture, while the thin ADC uses sa_ad to identify only two jobs, and the number is small. Therefore, the work is low and the area of the bracts is small. However, because it uses the adder (Editor (9)' will cause the DAC data conversion time is long, it is not suitable for high-speed conversion architecture. 'Because there is no sub-range technology, the MSBs from the coarse ADC must be f to the internal of the SA-ADC. DAC, so the area of the DAC is larger (since it includes more unit capacitance). The input capacitor is higher, so the ADC sampling frequency is slower under the same resolution of 200828817 rozy3uu49TW 22487twf.doc/n. The fourth conventional ADC system can be referred to the US patent uS52473〇i. Ming Mai Khao Tu 1, which shows the representative figure (picture!) of the US patent US52473〇1. This figure is not included, this bi-stage ADC mainly includes High bit comparator group ^2, 兀Sampling/Holding (Sample/H〇ld, S/H) Circuit Group 2, High Bit Coded State, Low Bit Comparator Group 4, Low Bit Sample/Hold Circuit Group $, • Low bit encoder 6, reference voltage generator 7, control signal generator 8, • analog switch Sm, and buffer 9. Γ High bit comparator group 1 includes a plurality of comparators 1-1 to lm. Group 1 compares the reference voltage with the input voltage vin. The circuit group 2 includes a plurality of sets of S/H circuits 2_丨~2_m, each S/Η circuit includes switches S2, S2丨 and a capacitor α. The high bit sample/hold circuit group 2 samples/holds the input voltage Vin and The result is sent to the high bit comparator group 1. The high bit encoder 3 encodes the comparison result of the high bit comparator group 成 into the high byte D 〇 H. Similarly, the low bit comparator group 4 includes a plurality of comparators '丨沁(7). j Low bit comparator group 4 compares reference voltages VL-1 to VL-n with input voltage

Vin. The low-order sample/hold circuit group 5 includes a plurality of sets of s/h circuits 5-1 to 5-n, and each S/Η includes switches S5 and S51 and a capacitor Ci. The low-order take-and-hold circuit group 5 samples/holds the input voltage Vin and sends the result to the low-order comparator group 4. The low bit coder compares the low bits - the result of the comparison of group 4 is encoded into the lower byte d 〇 L. The reference voltage generator 7 generates a high bit reference voltage VH 1 VH-m to compare n bits to group 1. In addition, the reference voltage produces crying 7 turns, Φδ2 and Huai 5 2 and low bit sampling /

200828817 P62950049TW 22487twf.doc/n 7 will generate a low bit reference voltage νι^~ν to the lower bit comparator group 4 according to the high byte DoH. The control number generator 8 generates control signals for the analog switch Sm and the clamp sample/hold circuit group holding circuit group 5, respectively. The analog switch Sm controls whether the input voltage Vin is turned on to the high bit sample/hold circuit group 2 and the low bit sample/hold circuit group 5. The fourth conventional ADC architecture combines a two-stage ADC with a sub-range ADC. Its data conversion speed is faster. However, the number of comparators is large, and therefore, the circuit has high complexity, high power complexity, low production yield, and low effective area utilization. A fifth conventional ADC system can be found in U.S. Patent No. 4,994,848. It uses the high-speed conversion features of the flash ADC to increase the conversion speed of the ADC. It uses an SA-ADC to improve the accuracy of the ADC. It combines the advantages of a fast-flash ADC with a SA-ADC to improve the overall performance of the ADC without the need for additional correction circuitry. However, because the residual amplifier needs to be used and the standby ADC is used at high-speed switching frequency, this amplifier will become the design bottleneck of the entire ADC system. SUMMARY OF THE INVENTION The present invention provides an analog-to-digital conversion system that converts an analog input signal into a digital output signal. The analog-to-digital conversion system includes a tracking and holding circuit for tracking and maintaining the tracked input signal; a coarse analog-to-digital converter that converts the output signal of the tracking and holding circuit according to a first reference voltage Into a first digit code, the first 8

L 200828817 ^62950049TW 22487twf.doc/n =:=:= group; -coding = (four) in the digit wheel _: most: ==,, = ΐ: ί:=!; ϊ bit code is encoded into -_ bit code; :: The tester, the reference voltage is generated by two:: Pressing the coarse analog to digital conversion _ digital code to produce a raw:;:= _ continuous approximation algorithm to turn; the signal into the second digital code. κ, the output of the hold circuit, such as the digital-to-digital conversion system further includes: a timing and hold circuit, the coarse analog-to-digital converter, the logarithm of the reference electrical generator, and the continuous approximation analogy when the analogy Input to the digital conversion system = the continuous approximation analog-to-digital converter includes: two out of the second digit code and a first; = ship digital to analog converter, according to out - the third 5 #u, the first The second reference voltage and the fourth digit code are converted according to the = voltage; the second sample/hold digit is analogized to the analog signal, the output signal of the fourth circuit, the second sac voltage and the digitizer The number is converted to a second analog voltage; with 9 200828817 F62y5UU49TW 22487twf.doc/n and a comparator, receiving the first _盥 second and analogizing the number of digits of the 11-bit analogy to - output signal to the continuous approximation The register is = the voltage 'generating', the round-off signal of the comparator is used to update, the complement of the fourth digit code and the digit code of the fourth digit code, the bracket: a preamplifier , receive the: 々 complement. The digits of the comparator packet are rounded up to the current nth sample/hold function Γ c, the output of the comparator =. 'Receiving the wheel of the preamplifier to cover the vivid temple, the input signal of the system is full difference according to 兮 _ 广, b voltage, a second digit to analog converter, out -; 2 2 pressure and The 2's complement of the fourth digit code, and the conversion and the tracking and holding circuit=transmission compare the first analog voltage to the second output: the letter === of the round-out temporary storage, the 2's complement generator The comparator is Zhao; updating the second digit code, the fourth digit code, and the 2's complement of the ί code. The comparator includes: the first pre-discharge transistor 1 and the first analog I first amplifier, receiving the tracking and holding circuit of the input 10 200828817 P62950049TW 22487twf.doc/ n output signal and the second analog mine M · a 筮 ^ x second preamplifier wheel ί ii metric force: the device, receiving the first and second preamplifier of the round: with m, receiving The first-and-third-out, and a latching unit are connected to the second to generate the ratio (4). The following is a detailed description of the embodiment of the Xijikou. c

Lj Each, two * two examples use a single-digit continuous performance approximation conversion algorithm. But this is the same as the ===== continuous approximation conversion algorithm Ϊ a four-bit data conversion, and the data conversion situation of the time-reading of the distribution of the traditional binary continuous approximation algorithm shown in Figure 2 of the synchronous timing , which has a charge recalculation element == applied binary (10) bit 贝 转换 转换 转换 由 由 由 由 由 粗 粗 粗 粗 粗 粗 粗 粗 粗 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 Data conversion for the least significant byte (ie MSB-2 and LSB). Since the coarse ADC uses a fast ADC architecture and has a very high data conversion speed, the time required to determine the MSBs can be less than 2*ΔΤ1. Since the fine aDC is only responsible for the conversion of the LSBs and the sub-range technique, the charge redistribution time is reduced by a factor of four, ie. In this way, the overall data • conversion speed can be significantly improved. [First Embodiment] Referring to Fig. 3', there is shown a circuit block diagram of an ADC system according to a first embodiment of the present invention. As shown in FIG. 3, the ADC system 30 includes a tracking and holding circuit (Track and Hold, T/H) 31, a coarse analog-to-digital converter (Coarse ADC) 32, and a coding and temporary storage unit (dec〇ding and Buffering u_33, reference voltage generator 34, SA_ADC 35, and timing control unit 36. In the tracking mode, the tracking and holding circuit 31 tracks the input signal. When the f mode is held, the tracking and holding circuit 31 maintains the tracked β. The U 乜 is input and transmitted to the circuit at the back end (ie, the coarse analog-to-digital converter 32, the SA-ADC 35, and the reference voltage generator 34). The coarse analog-to-digital conversion 32 receives the output signal of the tracking and holding circuit , The high-order data is converted to generate the digital code MSBs, and 'the digital code MSBs are passed to the encoding and temporary storage unit 33. The digital code MSBs has the most winter result Dout[nres-1 : 〇] (nres is the resolution) The most significant byte. The digital analog code 3 transferred from the coarse analog to digital converter 32 is, for example, Gray Code. The coarse analog-to-digital converter is available for 12 200828817 y, 49TW 22487twf.doc/n Using a flash ADC And it has a function of error correction. In the present embodiment, the architecture diagram of the coarse analog-to-digital converter 32 is not particularly limited as long as the above functions can be achieved. The encoding and temporary storage unit 33 stores MSBs and LSBs (which Generated by the SA-ADC 25) The encoding and temporary storage unit 33 can convert the MSBs (which are Gray codes) into 2MSBs (which is the n-code (1-〇f_n c〇de)), and transmit the 2MSBs to the reference. The voltage generator 34 is such that the reference voltage generator 34 is used to generate the reference voltage vb (the byte of VBrt, VBrb and .N is equal to the sum of the number of bits of the MSBs and the LSBs. When the SA-ADC 35 obtains the final digit code In LSBs, the encoding and temporary storage unit % can generate the final result dout[nres-i : 〇] according to the digital code MSBs and the digital code LSBs. Here, the number of bits of the digital code MSBs and LSBs is not necessarily the same. 34 generates a stable reference voltage source VARB) to the coarse analog-to-digital converter 32. The reference voltage generation state 34 generates a reference voltage VB to the sa_adc 35 based on the digital code (2 mSBs) transmitted from the encoding and temporary storage unit 33. When the input signal is a fully differential signal, the reference voltage is produced. ^34 even makes the common mode voltage (c〇mm〇n M〇de v〇ltage) of the output signal of the hybrid hold circuit 31 to ensure the accuracy of the reference voltage. S^V-ADC 35 Receive Tracking and Hold The output signal of the circuit 31 is subjected to the data conversion of the low bit by using the singular, (and), 1 approximation (SA): different method to generate the LSBs 2 and pass the LSBs to the coding and temporary storage unit. Mouth month again - people refer to Figure 2. The MSBs transferred from the coarse ADC are related to reference 13 200828817 P62950049TW 22487twf.doc/n Voltages VBRt and VBrb (supply SA-ADC). The relationship between the two is as follows. MSB ^ ' ~---- iYBRT^^B) 11 (VArt,VI) 10 "" -----------——. (VI,V2) 01 00 iYllVARB)

The difference between the two is fixed. #RT^ RE The sequence control unit 36 generates control signals to enable the units 31 to 35 to operate properly. The timing control unit 36 can control the units 31 to 35 in a synchronous or asynchronous day-to-day control mode. The timing control unit 36 receives the sampling signal and/or the clock signal transmitted from the outside. In particular, when the units 31 to 35 are controlled in a synchronous manner, an external clock signal is required. When the single 70 31 to 35 is controlled by the non-synchronization method, an external clock signal is not required. The timing control unit 36 is also responsible for communicating with the external interface. The principle of operation of Figure 3 will be explained below. It is assumed here that the resolution of the ADC of Figure 3 is 4 bits, and both MSBs and LSBs are 2 bits. Please refer to Figure 2 and Figure 3 together. :... Within eight-10, the coarse analog to digital converter 32 will convert the MSBs, assuming it is 01. Therefore, the reference voltage generator 34 generates a suitable reference voltage VB for the SA_ADC 35 in accordance with the MSBs. Next, within the first ΔT2, the SA-ADC 35 will convert the higher bits of the LSBs. In the second 14 200828817 F (D2y^uu49TW 22487twf.doc/n ΛΤ 2 'SA-ADC35 will convert the lower bits of the LSBs. Finally, the encoding and temporary storage unit 33 will combine the MSBs and the LSBs into the DOUT. The second embodiment of the ADC system is shown in Fig. 4, which shows a circuit block diagram of an ADC system according to a second embodiment of the present invention. As shown in Fig. 4, the ADC system 4 includes: Tracking and holding circuit 41, coarse analog-to-digital converter 42, encoding and temporary storage unit 43, reference voltage generator 44, SA-ADC 45, and timing control unit π 46. Timing control unit 46 can control the units in an asynchronous manner. 41~45 and its internal sub-circuit, so the timing control unit 牝 can not need external clock signal. Figure 4 is suitable when the input signal is fully differential input signal. SA-ADC 45 includes: 2's complement generator 451 A digital-to-analog converter (DAC) 452 and 453 with sample and hold functions, a comparator, and a continuous approximation register (SAR) 457. The comparator 454 includes: a set amplifier 455 and a latch unit 456. Comparator 454 At the same time, it has a deviation adjustment function U. Under the control of the digital code Code-I and Code-II (CodeJI is 2's complement of c〇deJ), the DACs 452 and 453 will be based on the output signal of the T/H circuit 41 and the reference voltages VBrb, VBrt, _. The analogy of the electrical house signals Vp and Vn. As for how the DAC 452 and 453 can be converted - the following figure and description - Hung amplification 455 amplification analog voltage signal Vp and. Latch suppression 456 latch preamplifier 455 The round-out signal is digitally rotated. The digital output signal of the request lock unit 456 is input to the continuous approximation device 15

Ο 200828817 P62950049TW 22487twf.doc/n 476 and 2's complement generator 451 Gentleman 靳 靳 仞 r r 在 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 Γ Γ Γ Γ Γ The architecture of the continuous approximation register 457 is not particularly limited herein. For example, it can be a combination of a shift register and a logic circuit. Referring to FIG. 5, a portion of the reference voltage generator 44 of FIG. 4 is shown for tracking a portion of the common mode voltage VCM-TH reference voltage generator 44 of the output signal of the T/Η circuit 41. • Resistor receives R52 'amplifier 51, current sources 52 and 53, and resistor string %. Resistor string 54 includes a plurality of resistors r connected in series. As shown in Figure 5, resistors R51 and R52 can be used to extract their common mode voltage VCM_TH from the output signal of the D/H circuit 4i. The common mode voltage VCM TH is input to the amplifier 51, and the other end of the amplifier 51 is connected to another common mode voltage vacm. The output signal of amplifier 51 can be used to control current source 52. The negative feedback mechanism established by elements 51-54 will cause the common mode voltage vacm to pursue the common mode voltage VCM_TH. Please refer to FIG. 6, which shows a schematic diagram of a digital-to-analog converter 452 (with sample/hold function). The structure of the digital-to-analog converter 453 is the same as that of the digital-to-analog converter 452, except that the control codes of b0 to b2 are different. As shown in Fig. 6, the digital-to-analog converter 452 includes switches 61 to 65' and capacitors 66 to 69. In this embodiment, the capacitance ratio of the capacitors 66 to 69 is 1: 1: 2: 4. When in reset mode, switch 61 is turned "on" and switches 62-65 are connected to common mode voltage VBCM. When in the sampling phase, the switch 61 will be turned on, and the switches 62 to 65 will switch to VO-TH, which is the output voltage of the T/H circuit 41, 200828,278, P62950049TW 22487twf.doc/n. When in the hold phase, switch 61 will fail and switch 62 will switch to VBrb. The switches 63 to 65 decide to switch to VBrb or VBRT based on the bits b0, Μ and b2, respectively. For example, when bit b0 is 0, switch 63 will switch to VBrb; otherwise, switch to VBRT. Bits b0 to b2 are LSBs. The voltage Vp can be expressed as follows··

Vp II VBcm - VO-TH+ Δ V-MSBs*( 1 /2*b2+1 /4*bl +1 /8*b0 )+VBrb f: (1) In the above formula (1), Δν-MSBs represents VBrt and The difference between VBrb. Please refer to FIG. 7, which shows an example of the architecture of FIG. 4 when determining 1^68. According to the continuous approximation algorithm, the preset values of Code_I and Code_II are both 1〇〇. During T1, the bit b2 is determined. It is assumed here that the determined bit b2 is 〇. The determined bit b2 is stored in the SAR 457 and the 2's complement generator 451, respectively, to update Code_I and Code_II to become 010 and 110 〇 ij respectively. During T2, the bit bl is determined. In Ding 3, it will determine the position bo. Similarly, the determined bits bl and bo will update Code_I and CodeJI as shown in FIG. After T3, the final value of the LSBs can be determined. • The architecture of Figure 4 is applicable, for example, to Ultra-Wide Band ('UWB) wireless communications. [Third Embodiment] Fig. 8' is a circuit block diagram showing an ADC system 17 200828817 P62950049TW 22487 twf.doc/n according to a third embodiment of the present invention. As shown in FIG. 8, the ADC system 80 includes a tracking and holding circuit 81, a coarse ADC 82, a code and temporary storage unit 83, a reference voltage generator 84, an SA-ADC 85, and a timing control unit 86. The timing control unit 86 can control the units 81-85 and its internal sub-circuits in a synchronous manner. The day-to-day control of the early element 86 requires an external clock signal and a sample signal. The units 81, 82, 83, 84 and 86 are identical or similar to those of the above-described embodiments and will not be repeated here. The SA-ADC 85 includes: a 2's complement generator 851, a DAC (with no sample/hold function) 852 and 853, a comparator 854, and a continuous approximation register 857. The comparator 854 includes preamplifiers 855a and 855b, adders 856a and 856b, and a latch unit 858. The comparator 854 also has a bias adjustment function. The connection relationship of the internal components of the SA-ADC 85 can be referred to FIG. 8, and will not be repeated here. Please refer to FIG. 9, which shows a schematic diagram of a digital to analog converter 852. The digital to analog converter 853 architecture is similar or identical to the digital to analog converter 852. As shown in Fig. 9, the digital-to-analog converter 852 includes switches 91 to 94, and capacitors 95 to 97. In this embodiment, the capacitance ratio of the capacitors 95 to 97 is 1:2:4. When in reset mode, switch 91 is turned "on" and switches 92-94 are connected to common mode voltage VBCM. When data is converted, switch 91 is opened and switches 92, 93 and 94 are determined to switch to VBRB or VBrT based on bits b, bl and b2. For example, when bit b0 is 〇, switch 83 switches to VBrb; otherwise 18 200828817 P62950U49TW 22487twf.doc/n switches to VBRT. Bits b0 to b2 are LSBs. As can be seen from the architecture of Figure 9, the voltage Vp can be expressed as ^:

Vp=z\V—MSBs*(l/2*b2+l/4*bl + l/8*bO)+VBRB (2) In the above embodiment, it is possible to reduce the power consumption of the ADC circuit and to know: Two characteristics such as conversion speed. The reason is that, in the case of the traditional two-stage ADC architecture, the demand for the coarse ADC comparator is (2 MSBS-i); and the demand for the fine ADC comparator is. However, in this embodiment, the demand for the internal comparator of the ADC is only a 2, so that the purpose of reducing circuit complexity and power consumption is achieved. In addition, since the demand for the comparator is reduced, the load capacitance of the tracking and holding circuit can be reduced. And ;==The resolution of the DAC inside the ADC is reduced, so the number of re-knifes can be shortened, and the ADC data conversion speed is improved. It is easy to reduce the equivalent capacitance of the wheel, so it can be used to achieve layout matching and better accuracy.

ScalmgPAC architecture (Figure 6 and Figure 9). -style (Charge

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[Simple diagram of the drawing J 19 200828817 ru, ^u. 49TW 22487twf.doc/n Figure shows a representative diagram of US Pat. No. 5,247,301. (4) ΐ 2 difficult traditional binary Lai approximation of the axis algorithm _ type - the schematic diagram of the continuous performance approximation algorithm. Into the box =. 3 shows the circuit of the ADC system of the ADC system according to the first embodiment of the present invention. Fig. 4 is a block diagram showing the second embodiment of the present invention.

Figure 5 shows how the reference voltage generator of Figure 4 traces the common mode voltage of the round-trip signal of the t/h path.

f 6 shows the digital ratio converter of Fig. 4 (not intended for sampling/holding function. Fig. 7 shows an example of the architecture of Fig. 4 when determining LSBs. Fig. 8 shows the power of the ADC system according to the third embodiment of the present invention. Block diagram Figure 9 shows a schematic diagram of Figure 8. Digital to analog converter (without sampling/holding function)

[Main component symbol description] 1: High bit comparator group 2: High bit sample/hold circuit group 3: High bit encoder 4: Low bit comparator group 5 Low bit sample/hold circuit group 6: Low bit encoder 7: Reference voltage generator 20 200828817 P62950049TW 22487twf.doc/n 8: Control signal generator 9: Buffer Sm: Analog switch 1- 1 to Ι-m: Comparator 2- 1 to 2-m · Sample/hold circuit S2, S21: switch

Ci: Capacitor 4- 1 to 4-n: Comparator 5- 1 to 5-n: Sample/hold circuit S5, S51: Switch 30: ADC system 31: Tracking and holding circuit 32: Rough analog-to-digital converter 33: Encoding and temporary storage unit 34: reference voltage generator 35 · Continuous Approximate Analog-to-Digital Converter (SA-ADC) 36: Timing Control Unit 40: ADC System 41: Tracking and Holding Circuit 42: Rough Analog-to-Digital Converter 43 : Code and Temporary Early Element 44: Reference Voltage Generator 45: Continuous Approximate Analog-to-Pixel Converter (SA-ADC) 46: Timing Control Unit 21 200828817 P62950049TW 22487twf.doc/n 451: 2's Complement Generator 452, 453: Digital to analog converter with sample and hold function 454 Comparator 455 Preamplifier 456 Latch unit 457 Continuous approximation register (SAR) R51~R52: Resistor 51: Amplifiers 52 and 53: Current source 54: Resistor String 61~65: Switch 66~69: Capacitor 80: ADC System 81: Tracking and Holding Circuit

82 ··Cold ADC 83: Encoding and temporary storage unit 84: Reference voltage generator 85: Continuous approximate analog-to-digital converter (SA-ADC) 86: Timing control unit 851: 2's complement generator 852 and 853 ·· Digital to analog converter (DAC) 854: comparators 855a and 855b: preamplifiers 856a and 856b · Adder 22 200828817 P62950049TW 22487twf.doc/n 857 : Continuous approximation register (SAR) 858: Latch unit 91 ~94: Switch 95~97: Capacitor 23

Claims (1)

200828817 rozyDuu49TW 22487twf.doc/n X. Patent application scope: 1.-face comparison digital conversion (4), the analogy turns into a digital output signal, and the analog-to-digital conversion system includes: "匕 conversion path, ^ίίϊ and partial (4) When the road is in the tracking mode, the tracking _ keeps the lightning = chasing (four) input signal 'in the hold mode, the tracking and tracking hold the input signal; y, road protection Γ - coarse analog logarithmic The converter, according to a first output == the output signal of the holding circuit is - the first number = the digit code has the most significant bit of the digital output signal ^. Haidi - code group code == temporary storage unit, Storing the first digit and the second digit μ first digit code is related to the digital output letter, the stone and the temporary storage unit, the first digit code is arranging the horse =^= the logarithmic bit: ί,: Generating the first reference voltage to the ic comparison digital converter of the coarse analog circuit to receive the Ct of the tracking and holding circuit: converting the tracking and holding power to the round signal by using a continuous approximation The second digit code. System, 2 more Ϊ 1 please patent scope The analog-to-digital conversion system of class 1 is _==t holding circuit, the coarse, buckle, side coding and temporary storage unit, the reference voltage generation 24 200828817 A —-49TW 22487twf.doc/n state and the continuous approximation Analog-to-digital converter. Green, 3 Gan patent range, the analogy of the digital conversion system described in item 1 drags the crying code, the code is Gray code, and the money is converted to a flash analogy. Digital converter. Γ , , , , , 二 it 围 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第The common mode voltage of the output signal of the circuit is maintained. The analogy of the digital conversion system, the charge, and the middle 5th second digit code described in Item 3 are nii codes. The analog-to-digital conversion system described in the item is a four-digit ΪΓ approximation register for outputting the second digit and a second === generating a complement of 2 of the fourth digit code; the tracking and maintaining The pair of τ converters of the circuit, according to the four-digit code, converts a skirt to a ^^" The test voltage is compared with the first and the first type of ink; the nine-digit digital-to-bulk converter, according to the four-digit mother's 2's complement two, the second reference power® and the first-comparator, receive the first- , analog voltage; and bit-to-analog converters have a number of injured sampling / holding function of the number of Fortune to generate - output signals to the connection of the ratio of electricity and the second analogy of the electrical private approximation of the temporary storage of the 2 Number 25 200828817 Fb2V^uu49TW 22487twf.doc/n The output signal of the comparator is used to update the complement of the second digit of the fourth digit code and the fourth digit code. 7. If the application is specifically described in the sixth handle, wherein the comparator comprises: a conversion 刖-刖 amplification ϋ 'receive the first-and the second with a sample/hold digital-to-analog converter output The first-class voltage is proportional to the voltage; and the 仏...the younger-class Γ the comparator receives the preamplifier - the center of the wheel produces the ratio, and the analog-to-digital conversion system is compared to the logarithm when the full differential signal is ' The continuous approximation class four-digit three-continuation approximation register 'for the output two-digit code 舆-second complement generator generates the complement of the fourth digit code. The flute number-to-analog conversion 11 Deriving a first analog voltage according to the second reference voltage, the code, and converting the second analog to the analog converter according to the second complement of the second reference voltage _ Converting - the second analog voltage; ^ a comparator 'comparing the first analog voltage with the chasing analog voltage and the chasing = ^ = generator, the rounding signal of the comparator is used for a more H digit code, The fine digit code and the fourth digit code of the 2 of the 26 200828817 rozyD〇u49T W 22487twf.doc/n Complement. 9. The analog-to-digital conversion system of claim 8, wherein the comparator comprises: "a first preamplifier that receives the input signal of the tracking and holding circuit and the first analog voltage; a second preamplifier that receives the signal of the tracking and holding circuit and the second analog voltage; Γ; a first adder that receives the first and second preamplifiers, the wheel and the first preamplifier a second adder of the amplifier, receiving the first output; and the comparing the first and second adders (4) generating a conversion system-------------- The analog-to-digital conversion system includes: a number; - 〇 ^ and keep Wei, track and keep the traced input signal, the conversion group according to the - reference voltage, the code and the temporary storage unit will; ^The least significant bit code of the phantom number; ", the human number code code stone Ma Cheng a third digit 27 200828817 ^ 〇 2y.uu49TW 22487twf.doc / n the digital bit pressure i two to produce the first, the reference voltage to the Rough analogy generation - second reference electricity house The ^ generator is further pressed according to the third digital mother, and the ίίίΓ ίίr is converted to the digital converter according to the second reference electrical algorithm to convert the chasing continuous approximation _ four-digit stone approximation register for Outputting the second digit to drink and - the first holding = the complement of the fourth digit code; the ^ vertical and the holding circuit is simple... according to the four recording code, converting - the first analogy is electromigration. The electric house and the first chasing ===== converter, according to the 2's complement of the four digit code, converting one or two corpses and the first comparator, receiving the first 盥 second taking two analog voltages; And outputting the converter to generate an output signal to the ^ digits to generate a H for the complement of the analog to 2, the comparator of the comparator and the digit stone, the fourth digit and the fourth The number ^^ is used to update the second U· as the complement of i, 42 of item H) of the patent application. a comparator, wherein the comparator comprises a preamplifier of a digital conversion system such as ^4, ^4, and the like, receiving the first analog electric castle outputted by the first and second ratio converters: sampling/holding digits pair ^ The second analog voltage of the younger brother; the output signal of the preamplifier is received by 28 200828817 F62^5U049TW 22487twf.doc/n and a latch unit. The output is generated to produce the ratio: a fine (4) logarithmic bit conversion system, a bitwise bit conversion, a hold circuit, the coarse gain, and the continuous approximation analog to digital converter. °海 reference electric dust generation 13. If applying for the system described in Item 1 (), where the first digit code is Gray code, and the ^ digital conversion converter is a flash analog to digital converter . _Comparative digits are transferred to 14. If the patent application scope is the first item generator, the pursuit of the butterfly == 统二如 ===: The analogy of the logarithm is converted into a number of numbers ^ the turn ^ system, a differential The class member than the input signal-two-switch system includes: a number; the input signal of the Weishen holding phase is a coarse analog-to-digital converter, and the rounding signal according to a first=3 holding circuit is a first number U 3 The most significant digit of the digitally rotated signal =; the brother-,, 'code and temporary storage unit' stores the first-digit code and the second digit 29 200828817 ϊΌζ^υυ49ΤΨ 22487twf.doc/n code, the first The binary code has a second reference voltage generated by the code and the temporary storage unit to generate the second reference voltage; and the second digit code is pressed by σ x °; the comparison digital converter '拫According to the second reference electric wheel holding circuit of the round: 2; near = method of the continuous analog analog-to-digital converter includes: brother-digit code 'quad-numbered stone tr approximation register for outputting The second digit code and the third digit of the third digit generate the fourth digit and the brother-digit pair analogy Converter: , 2 = number; the fourth four-touch code, converts a first analog voltage; the reference voltage and the first read (four) test voltage and the comparator - the parent converts the second analog power; and the output signal And the output signal of the voltage circuit of the tracking and holding circuit to generate the memory and the complement of the 2 ί = continuous approximation to temporarily add the second bit code and the second output signal for complementing number. / Digital U-number bite to drink the 2 Π. As described in the scope of claim 16 of the analog-to-digital conversion system 30 200828817 r〇z^juu49TW 22487twf.doc/n system, wherein the comparator includes a first before Locating an amplifier signal with the first analog voltage - a second preamplifier ^ 'receiving material (four) signal and the second analog voltage; receiving the round out of the rounding of the tracking circuit; the first adder receiving a second adder of the first and second preamplifiers, receiving the first 笙_out; and receiving the first and the third of the flash lock unit of the amp and the amp The second adder outputs the output signal of the comparator. a comparator, receiving - the output of the bit to analog converter to generate the second digit code. "Digital-number system, including the application of the patent-based model _ 16-like analog-to-digital conversion system, the meta-synchronization control signal to the tracking and maintaining electrical analogy analogy to the digital teleportation and the coding and temporary storage The unit is connected to, the, and/or the digit code is a Gray code; the coarse analog ratio is a converter; the first system, the heart test 2 ==== the common mode voltage of the output signal.