TW200812073A - Thin film fuse phase change cell with thermal isolation layer and manufacturing method - Google Patents

Abstract

A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member, An array of such memory cells is provided. The bridge comprises an active layer of memory material on the first having at least two solid phases and a blanket of thermal insulating material overlying the memory material having thermal conductivity less than that of an overlying electrically insulating layer.

Description

200812073 IX. Invention Description: [Related application materials] This case is related to the US continuation application filed on June 17, 2005. The application number of the application is 11/155,067, and the invention name is "THIN FILM". FUSE PHASE CHANGE RAM AND MANUFACTURING METHOD". Stomach [Partner of the Joint Research Contract] International Business Machinery Corporation New York Company, Wanghong International Co., Ltd. Taiwan Company and Infineon Technologies AG (Germany) are joint research PARTICIPANTS OF THE LICENSE FIELD OF THE INVENTION The present invention relates to high density memory elements using phase change memory materials, including chalcogenide based materials and other materials, and related to _ for manufacturing such components [Previous technique] 1 = Phase-based memory materials are widely used for reading and writing light. These materials include at least two solid phases, including such as a large part of the ill abomination And a substantially crystalline solid phase. It is used to read and write optical discs to switch between the two phases. And read the optical properties of the material after the phase change. Such phase change memory materials such as the squash and similar materials can be applied by applying the amplitude of 200812073. General and ancient non-曰 & ^ In the middle of the road (10)', the crystal phase can be easily changed. The characteristic is that its resistance is higher than the crystalline state. This resistor can be used as an indicator. This characteristic is used to form the field I material. Non-volatile memory circuit, etc., this circuit can be used for random access reading and writing. Electric Tower Temple /, this 攸 amorphous state to crystalline state one ^ ^ crystalline state to amorphous to Ding a total of 4 々 Also go to the ^ machine step to tie the current step, the next is called reset (10) called) - the general system is a high

The short-term high-current-density pulse of the social organization ii melts or destroys the phase-change material, which rapidly cools, and the structure of the phase change can be maintained in an amorphous state. Ideally, the reset of the phase change material from the crystalline state to the amorphous state should be as low as possible. To reduce the magnitude of the reset current required for resetting, it can be achieved by reducing the size of the phase change material component in the memory and reducing the contact area of the electrode with the phase change material, so that the phase change material can be The component applies a small stream of simple t currents to achieve a higher current density. One method of this domain is to create tiny holes in an integrated circuit structure and fill these tiny holes with a trace of programmable resistance material. The patents dedicated to such microscopic holes include: US Patent No. 5, No. 7,112, published on November 11, 1997, Multibit single Cell Memory Element Having Tapered Contact, inventor Ovshmky; 1998 8 US Patent No. 5,789,277, entitled "Method of Making Chalogenide [sic] Memory Device", inventor Zahorik et al., US Patent No. 6,150,253, published on November 21, 2000, "Controllable Ovonic Phase-Change"

Semiconductor Memory Device and Methods of Fabricating the Same,, the inventor is Doan et al. 200812073 The size of the second dimension is used to manufacture these devices, and to meet the production problems. When the strict process variables required by the company are met, the problems associated with the smaller phase-sized cells of Table 2 are caused by the thermal conductivity of the material of the ring J " In order to cause a phase change, the temperature of the phase change material in the active region must reach a phase change 1 threshold. However, the fabricated structure produced by the current through the phase change material is quickly conducted away. This conduction of heat from the phase change & material in the active region reduces the heating effect of the current and also interferes with the operation of the phase change material. Therefore, Xi shy can provide a memory cell structure that includes a small size and a low reset current, and a method for manufacturing such a structure that satisfies the strict process variable gauge when producing a large-sized memory device: Less is to provide a manufacturing process and structure that is compatible with manufacturing peripheral circuits on the same integrated circuit. SUMMARY OF THE INVENTION The present invention describes a phase change random access memory (PCRAM) element = which is suitable for use in a large size integrated circuit. The technique described herein, in addition to the first electrode, has a first electrode on the top side, a second electrode having a side, and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes, near the top side of the first electrode and the top side of the second electrode. A film guide bridges across the insulating member and defines an inter-electrode path between the first and second electrodes across the insulating member. The film bridge includes an active layer of phase change material and a layer of thermally isolating blanket material between the active layer and the underlying structure. The blanket material providing thermal insulation may comprise the same material as the phase change material of the active layer. The thermal insulation blanket material may comprise a 200812073 inclusion-composite structure having a -first isolation layer, and wherein the isolation layer is isolated from the main _ and the thermal insulation layer T has a path between the electrodes: =. It is defined across the width of the absolute. In order to explain the structure of the convenient road = the c-member. However, for the phase change memory, the ancient 1 ϋ fuse includes at least two solids (four) mesh = ς 化 ^; = 呆 丝 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The material is reversibly induced between the first electrode and the second electrode. Absolutely. The J is pressed against the blanket of thermal insulation material, wherein the thermal insulation material has a lower thermal conductivity than the electrically insulating material layer. The volume of the memory material having a text to phase k can be the thickness of the u-axis of the thickness of the piece), to form ^; = by the thickness (y-axis), and the bridge perpendicular to the path length in the bridge ^ The film is defined. In an embodiment, the width of the insulating member, and the thickness of the thin film memory material of the bridge are determined by the thickness of the film, and the guiding is limited by the second pattern process for forming the memory cell is not less than - the minimum feature Dimension F, this feature size F is:: lithography system made by the material layer of the embodiment (4) ^In the case of the patent, the width of the guide bridge is the photoresist pattern of the photoresist It is used to define a lithographic photoresist structure on the wafer, to cover the small feature size F, and to use the isotropic property to achieve a feature size smaller than F. The trimmed light ▲ is used to transfer the narrower pattern to the insulating material layer on the memory material. The other techniques can be used. (4) The body-cutting:: Therefore, it has a simple structure of phase change memory cells. can. Reset current and low energy consumption, and easy to manufacture. Hang from childhood 200812073 In the embodiment of the technique of the present invention, a "memory column" is provided. In this array, a plurality of electrode members and an insulating member ' located at the electrode gate are formed on an integrated circuit to form an electrode layer. = has an upper surface which in some embodiments of the invention is the surface of each cake. Corresponding to, across the insulating member, a plurality of film guides having a thermally insulating blanket between the pair of electrode members. From the J-pole in the electrode layer, through the thin film via of the upper surface of the electrode layer, to a current path of the electrode of the electrode layer, it is formed in a cell in the array. In the present invention, the electrical means under the electrode layer in the integrated circuit are conventionally used to form logic circuits and memory array circuits: for example, - complementary metal oxide semiconductor (CMGS) technology. Formed by the shaft, in addition, in one of the array embodiments described herein, the circuit above and the bridge array with a thermally insulating blanket are ^^: lines. One of the bit lines described in the electrode layer in the electrode layer is a memory cell: two =: cell ΓΠ: in the electric case, the corresponding number in the implementation of the complex i position i ^ / 极The bit lines can be arranged to share the contact with the _ neighboring memory cells in the -=: line along an array structure to form a method for making memory elements. The method includes an electro-shirt 1 on a substrate on which the front-end process generation circuit is completed. The pole and the insulating member===; the first electrode and the second armor are on the upper surface of the electrode layer, and the insulating member has a width between the first electrode and the second electrode And linked to the phase change memory cell structure described previously. The method also includes forming a memory material of a via bridge having a thermally insulating blanket for each phase of the memory cell to be formed on the upper surface of the electrode layer across the insulating member. The vial comprises a film of memory material having a first end and a second end and is in contact with the first and second electrodes at the first end. The bridge defines an inter-electrode path between the first electrode and the second electrode across the insulating member, the inter-electrode path having a path length of one of the first by the width of the insulating member. In an embodiment of the method, an access structure on the electrode layer is formed by forming a patterned conductive layer on the vial, and forming a conductive contact with the first electrode and the patterned layer. Between the layers. Other objects, advantages and the like of the present invention will be fully understood from the following description of the appended claims. [Embodiment] The film fuse phase change memory cells of the present invention, the array formed by the memory cells, and the method for producing the memory cells are described in detail with reference to Figures 1-16. 1 is a diagram showing a basic structure of a memory cell 1 (including a memory material vial 11 above the electrode layer, including a first electrode 12, a second electrode 13, and a first electrode 12; The insulating member 14 between the second electrodes 13. As shown, the first and second electrodes 12, 13 have upper surfaces 12a and 13a. Similarly, they also have an upper surface 14a. In this embodiment, The upper surfaces 12a, 13a, 14a of the structures in the electrode layer define a substantially planar upper surface of the J electrode layer. In other embodiments, the upper surfaces 12a, 13a, 14a are not in the same plane, such as The insulating member 14 may extend 200812073 to form an insulating wall between the electrodes. The memory material vial 11 includes an active layer 15 of memory material over the flat upper surface of the electrode layer such that the first electrode and the via 11 are The contact between the second electrode 13 and the viaduct 11 is achieved by the bottom side of the active layer 15 of the vial 11. The via 11 comprises a thermally insulating blanket comprising a barrier layer 16 and 17 thermal insulation material covering the active layer of the memory material 15 Above, the heat generated by the active layer 15 is confined to an active region of the memory cell. The barrier layer 16 comprises a material such as hafnium oxide or tantalum nitride, which may be provided between the active layer 15 and the layer 17. Electrical insulation between the barrier layer 16 can also serve as a diffusion barrier between the layer of thermal insulating material 17 and the active layer 15 of memory cells. In the embodiment shown, the blanket is only Covering the active layer 15. In other embodiments, the blanket may also cover the sides of the active layer 15. Further, the barrier layer 16 and the layer of thermal insulating material 17 may also comprise respective multilayer composite structures. Embodiments of the circuit can be contacted to the first electrode 12 and the second electrode 13 in a variety of configurations to control the operation of the memory cells such that they can be programmed to set the active layer 15 of the via 11 to one of the two solid phases The two solid phases can be reversibly implemented using a memory material. For example, using a chalcogenide-containing phase change memory material, the memory cell can be set to a relatively high resistance state, wherein the bridge is in the &gt At least in the current path One part is amorphous, and most of the guiding bridge in the current path is in a relatively low-resistance crystalline state. The active area in the active layer 15 is a phase change memory cell, and the material is induced. In the region shown in at least two solid phases, in the embodiment shown, the active region in the active layer 15 is substantially above the insulating member 14. It will be appreciated that this active region can be made very small. To reduce the magnitude of the current required to induce the phase change. 11 200812073 The length of the active region L "4 is called the channel dielectric" is between the 4th edge member 14 (defined by the thickness in the figure. This length L· It can be controlled by 4° /, the width of the edge wall 14 between the electrodes 13. (In the example of the control film cell embodiment, the length of the insulating wall 14 is defined.) In the example, we did not use thin

ί. 22: In the example, the thickness of the guide bridge is 峨50. In the example, the thickness of the guide bridge is less than or equal to m. It is 'guide bridge 5 degrees 4 can even be used such as atomic layer deposition technology: etc. = 2 depending on the application requirements, as long as this thickness allows the guide bridge to perform its purpose: At least two solid phases are reversibly induced by a voltage applied between the first and second electrodes. The V-bridge visibility W (z-axis) is also very small. In the preferred embodiment, the bridge width W is less than what should be earned. In some embodiments, the bridge width is below 40 nm. Examples of memory cells include a guide bridge 11 constructed of a phase change based memory material, which may include chalcogenide-based materials and other materials. The chalcogenide includes any of the following four elements - oxygen (redundant) stone 1 (S), stone (Se), and cerium (Te), forming part VI of the periodic table. Chalcogenides include the combination of a chalcogenin with a more positive element or a radical. The chalcogen compound alloy includes a combination of a hydrophobic compound with other substances such as a transition metal material. The rhodium compound alloy usually includes one or more elements selected from the sixth column of the periodic table, such as germanium (Ge) and tin (Sn). Typically, chalcogenide alloys include more than one of the following 200812073 elements: green strontium and silver (Ag). Many of the phase change gallium (Ga), indium (five), described in the technical file t, including the lower heart t-domain frequency has been traced / 碲, wrong / hoof, 锗 / recorded / 碲, minus gallium / 锑, indium / 锑, Indium/石西, Indium/Record/锗, Silver/Indium/Record/Lu, 锗Gallium/砸 、, tin/record/碲, binding/kick/锑/碲, 锗/锑/Selenium/碲, and 碲/ , / recorded / sulfur. In the family of tantalum/material alloys, a wide range of alloys can be tried. This is the following formula: TeaGeb.SW(a+b).

- The research of the most useful alloy system is that the average concentration of 4 contained in the deposited material is much lower than 7Q%, typically less than 6〇%, and the content of bismuth in the general type alloy. The range is from a minimum of 23% to a maximum of 58%, and the optimum is between 48% and 58%. The concentration of cerium is greater than about 5% and its average range in the material ranges from a minimum of 8% to a maximum of 30%, typically less than 5%. Optimally, the concentration range of lanthanum is between 8% and 40%. The main component remaining in this ingredient is hydrazine. The above percentages are atomic percentages, which is a total of 1 for all constituent elements. (Ovshinky 6112 patent, 〇1〇11) Special alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7. (Noboru Yamada 5 ^Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording 55, SPIE v. 31〇9 pp. 28-37 (1997)) More generally, transition metals such as chromium (Cr ), iron (pe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and mixtures or alloys thereof, may be combined with niobium / tantalum / niobium to form a phase change alloy including Has a programmable resistance property. A special example of a memory material that can be used, such as

The Ovshinsky ‘112 patent is described in Blocks 11-13, and examples are included in this series. The phase change alloy can be in the active channel region of the cell according to its position in the first structural state in which the material is in a generally amorphous state and is generally crystalline solid.

S 13 200812073 Switching between the second structural states of sadness. These alloys are at least separated. , tF about a "^ and heart 疋 #,, fruit amorphous" is used to refer to a relative weight unordered structure,

The second single crystal is more non-sequential, with a detectable characteristic such as a higher resistance value than the crystalline state. The term "crystalline" is used to refer to a structure that has a relative order of ruts, which is more ordered than the amorphous state, and therefore includes a resist that is detectable, such as a lower resistance than amorphous. value. Typically, the phase change material can be electrically switched to all detectable = identical states between the fully crystalline state and the fully amorphous state. Other materials that are affected by changes in amorphous and crystalline states include atomic order, free electron density, and activation energy. This material can be switched into a different solid state, or can be switched into a mixture of two or more solid yokes, providing the electrical properties of the gray-scale knife from the amorphous state to the crystalline state. May change. A phase k alloy can be switched from one phase to another by applying an electrical pulse. Previous observations indicate that a shorter, larger amplitude pulse tends to change the phase of the phase change material to a substantially amorphous state. A longer, longer pulse tends to change the phase of the phase change material to a substantial knot. The energy in the shorter, larger amplitude pulses is large enough to break the bond of the crystalline structure while being short enough to prevent the atoms from re-arranging into a crystalline state. In the absence of undue experimentation, an appropriate pulse-understanding curve that is particularly suitable for a particular phase change alloy can be determined. In the subsequent part of this article, this phase change material is referred to as GST, and we also need to understand that other types of phase change materials can be used. One of the materials described in this document for use in PCRAM is Ge2Sb2Te5. Other programmable memory materials that can be used in other embodiments of the invention include GST doped with N2, GexSby, or other materials that are converted by different crystalline states to determine electrical resistance; PrxCayMn03, PrSrMnO, ZrOx, TiOx, NiOx, WOx Doped SrTi03 or other material that utilizes electrical pulses to alter the resistance of the circuit; or other material that uses an electrical pulse to change the resistance state

TCNQ(7,7,8,8-tetracyanoquinodinietliane), PCBM (methanofullerene 6,6-phenyl C61 -butyric acid methyl ester), TCNQ_PCBM, Cu-TCNQ, Ag-TCNQ, C6 (rTCNQ, doped with other substances) The TCNQ, or any other polymeric material, includes a bistable or multi-stable resistance state controlled by an electrical pulse. The material of the layer of thermally insulating material may be the same material as the memory material, such as a cell GST in the embodiment. In other embodiments, the material 17 comprises polyvinylamine or other material having a lower thermal conductivity than the second electrical layer on the vial. Representative of the layer of thermal insulating material includes The following elements are combined: 矽, carbon, oxygen, fluorine, and 虱] are suitable as thermal insulation for thermal insulation cover, including carbon dioxide carbon dioxide cutting, polyamidamine, poly-, and fluorocarbon Polymer S15 is used as a material for thermal insulation coating, including fluorinated dioxyether / oxy oxane (10) Qing (4) (10) followed by polycycloolefin (P〇1yarylene pore car $ 矽 矽 矽 夕 夕 ( ( Mesoporous) bismuth oxide, more or more Wei, Porous poly-weimin and porous cycloolefin. The single layer of the second, Q, Q structure can provide thermal insulation and electrical insulation effects. In the structure of PCRAM cells, these cell lines form, etc., r 2 f 21 Above: for example, shallow trench dielectric (STI) (not listed. This save = structure) isolates the pair of memory cells to access the transistor 26 as a Λ in the -p county board 21, m Type terminal terminal. 1 夕, the same, the polar region, and the n-type terminal 25, 27 function as a dielectric filling word line 23, 24 is used as a gate for accessing the transistor. = crystal_gas above. This layer m includes a common source line 28 and a plug structure

15 200812073 Or other materials and combinations for the V i structure. The common source line 28 is a contact line: the second/second pair: a column in the array acts as a common source earth, and the earth, and port structures 29, 30 are respectively in contact with the drain terminals 25, 26. Filling Ϊ not), common source line 28, and plug structure 29, 3 〇 and the plate is flattened on the upper surface 'or suitable for use as a forming electrode layer,

The electrode layer 31 includes electrode members 32, 33, 34 which are separated from each other by an insulating member such as an insulating material t a, 5b, and the base member member is formed by a side wall process as described below. In the present embodiment =f, the base member can be thicker than the insulated gate (10) and the electrode assembly 2, the homopolar line 28 is isolated. For example, the base member may be between 80 and MOnm, and the insulating grid is much narrower than this, and the electric power between the source line 28 and the electrode member 33 must be reduced. In this embodiment, the insulating grid is called The electrode member is formed of a film dielectric material whose thickness on the surface of the electrode layer 31 is determined by the film thickness of the film. A composite memory guide 36a (e.g., GST) on the soil is placed over a blanket and includes a resist P early layer 36a and a layer of thermal insulating material 36c on one side of the electrode layer 31, spanning The first memory cell is formed by the edge wall 35a, and a thin film memory material guide 37 (for example, GST) is located above the %, which includes a resistive layer 37a and a thermal insulating material remaining 3^, 'On the other side above the electrode layer 31, a second memory cell is formed across the insulating gate 35b. A dielectric fill layer (not shown) is placed over the film viaduct. The dielectric fill layer comprises oxidized chopped, polyamidamine, nitride nitride, or other dielectric fill material. The thermal insulation material layer blanket 37c has a lower thermal conductivity than the filled dielectric layer of 16 200812073. The tungsten plug 38 contacts the electrode member 33 and includes a patterned conductive layer 40 of metal or other conductive material (including the bit lines in the array structure) over the dielectric fill layer and contacts the plug 38 to establish access to memory cells corresponding to the active layer 36a to the left of the film bridge and the active layer 37a to the right of the film bridge. Fig. 3 is a view showing the structure on the semiconductor substrate 21 in Fig. 2, which is presented in a layout manner. Thus, the arrangement of word lines 23, 24 is substantially parallel to common source line 28, arranged along a common source line in a memory cell array. The plugs 29, 30 are in contact with the terminals of the access transistors in the semiconductor substrate and the bottom sides of the electrode members 32, 34, respectively. The thin film memory material guides 36, 37 are located above the electrode members 32, 33, '34, and the insulated gates 35a, 35b separate the electrode members. The plug 38 is in contact with the electrode member 33 located between the bridges 35 and 37, and the bottom side of the metal bit line 41 (transparent in Fig. 3) below the patterned conductive layer 40. Metal bit line 42 (non-transparent) is also shown in Figure 3 to emphasize the array layout of this structure. In operation, the access to the memory cells corresponding to the via 36 is achieved by applying a control signal to the word line 23 by φ, and the word line 23 connects the common source line 28 via the terminal 25, the plug 29, And the electrode member 32 is coupled to the film guide 36. Electrode member 33 is coupled to a bit line in the patterned conductive layer via contact plug 38. Similarly, access to memory cells corresponding to the via 37 is achieved by applying a control signal to the word line 24. It will be appreciated that a variety of different materials can be used in the structures of Figures 2 and 3. For example, copper metallization can be used. Other types of metallization such as aluminum, titanium nitride, and tungsten-containing materials can also be used. At the same time, non-metallic conductive materials such as doped polysilicon can also be used. In the case of the embodiment used in the embodiment of the invention, the electrode may be a material or a nitride button. Or 遝 white aluminum titanium or aluminum nitride tantalum, or may include more than one (four), and from top, = (^, 铱 (Ir), 镧 (La), nickel (10), and Shu 35a, 35b may be dioxane An alloy composed of an alloy, an insulating gate between electrodes, a low dielectric constant, a nitride nitride, an oxide, or the like selected from the group of twisted mussels or an inter-electrode insulating layer may include one and carbon. ^素: Shi Xi, Titanium, Ming, New Zealand, Nitrogen, Oxygen, and the brother of the 4 map system - 3 pictures made by inserting, and:, recall the schematic diagram of the array 'which can refer to the 2nd and 2nd Therefore, the reference numerals in Fig. 4 correspond to the column structure in which the H cells are used in the same manner as the common source lines 28 and A_ shown in Fig. 4. In the description of the figure, on the Y-axis, the Y in the upper parallel block 45 decodes the cry and the i is on the x-axis. Therefore, on line 23, 24. In the square broadcast 4,, and the two sub-line drivers, the coupling Connected to the character, the handle is connected to the bit buffer, the X decoder and a set of sense amplifiers, crystal 50, 51 52. The common source line 28 is coupled to the access electrical connection to the word line 2^/ Take ^曰, ° access The gate of the crystal 5 存取 access transistor 5 2 is connected to 5 ^, and the surface is connected to the word line 2 4 . 2 pole _ to the word line 2 ^ 23, moving to the electrode member 32 to connect the bridge 36^: a 汲 5 〇 汲 转接 转接 转接 。 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 34 The electrode is connected to the electrode assembly member 34_the wire element/connected to the electrode member 34. The piece 34 is in the position of the bit read 41, and the same position is convenient to illustrate, and the electrode structure M is set up. It can be understood that

&lt;S 18 200812073 In other embodiments, different accessor transistors 52 and cell bridges may use different electrode members. cell. As can be seen, the farmer's = bit line 42 is coupled to the corresponding memory, and the column is along the line of the "shame line 28" by the two columns of memory cells. arrangement. Similarly, the electrode members 34 are arranged along the X axis. The cells are shared, and the line 5 in the array is the root block diagram. The simplified circuit of the integrated circuit of the integrated circuit of the embodiment of the present invention is a memory cell memory array 60 which is consumed by a thin film protector 61 to a plurality of semiconductor substrates. - Column decoding is arranged for each column. - Wry, green 62, and along these traces in the memory array 6 沿着 along the trace to a plurality of bit lines 64, the multi-gate memory run in array 6 = = = = And used as a slave sense amplifier and 列ί;, column decoder 61. The middle of the block is the decoder 63. The bit ^ = structure is lightly connected to the column decoder 61 via the bus bar 67. At block 6, row 65 is provided to row decoder 63 to U f I to be coupled to the input/output port on row decoding crying substrate 75, or "7; 1 Μ, His internal or external data source 'passes the data input structure via data entry line ki to block 66. In the illustrated embodiment, the body circuit includes other circuits 74, such as a general purpose processor or a specific purpose application circuit, Or an integrated module for system single-chip (8) function supported by a thin film fuse phase change memory cell array. The data is transmitted from the sense amplifier in block 66 to the integrated circuit via the data output line 72. 75 wheel input/output ports, or other data objects transmitted to or within the integrated circuit 75. 19 200812073 In this embodiment, a controller of the state machine 69 is used to control the application of the bias voltage to supply the voltage 68, For example, reading, programming, erasing, erasing confirmation and stylizing confirmation voltage, etc. This controller can use a conventional purpose-specific logic circuit. In an alternative embodiment, the controller includes a general purpose. The processor can be applied to the same integrated circuit that performs a computer program to control the operation of the component. In still another embodiment, the controller uses a specific purpose logic circuit and a general purpose Combination of destination processors. Figures 6-16 show the process of a structure and a double-embedded electrode structure. In a double-embedded structure, a dielectric layer is formed in a two-level (ie, double-layer) pattern, wherein The first level pattern defines the trenches of the wires, and the second level pattern defines the via holes connecting the underlying structures. A single metal deposition step can be used to simultaneously form the wires and fill the via holes connecting the underlying structures to form conductive connections. The vias and trenches can be defined using a two-stage lithography step. The trench is typically etched to a first depth, and the via is etched to a second depth to form a via opening that connects the underlying structure. After the via holes and trenches are etched, a deposition step can be used to simultaneously fill the vias and trenches with metal or other conductive species. After filling, the trenches are deposited. The excess material is removed by a chemical mechanical polishing process, a flat, double-inserted structure filled with conductive material! This is completed. Figure 6 shows a process diagram of a double-embedded structure, an electrically insulating material layer 651, Typically, a dielectric layer is formed over the front-end process structure and is formed as a subsequent dual damascene structure. The front-end process is used to form a standard CMOS device. In the illustrated embodiment, it corresponds to the second The figure shows the word line, the source line, and the access transistor in the column. In FIG. 6, the source line 106 covers the doped region 103 in the semiconductor substrate, wherein the doped region 103 Corresponding to the first access transistor 20 200812073 ^ 左侧 on the left side of the figure and the source terminal of the second access transistor on the right side in the figure. In this example, the source line 106 extends to the structure 99 Upper surface. In other real =11 ' this source line does not extend completely to the surface. - The doped region 104 is the drain of the first access transistor. Containing a polycrystalline stone 107: the sub-twist line serves as the gate of the first access transistor. A dielectric layer (not shown) 109 is located above the polycrystalline stone 〇1〇7. A plug 11 is connected, and thus the region 1 () 4 is doped, and a conductive path is provided to the structure, and the surface, t, is connected to a memory cell electrode in a manner to be described later. The alignment area (10) is used as the second terminal of the access transistor. A word line including a polycrystalline stone line (1) is used as a gate of the second access transistor. - The plug 112 is in contact with the doped region and provides a conductive path to the upper surface of the structure 99 and is connected to the -memory cell electrode in a manner to be described later. An electrically insulating material layer 651 is formed over the front stage process structure as shown. The double damascene process includes a -first patterned photoresist layer 652 overlying ^ 651 as shown in FIG. This first patterned photoresist layer (6) defines regions 651, 654 and 655 of layer 651 that are etched into trenches, which correspond to the electrode members in the dual-embedded electrode structure. Using the patterned photoresist layer 652 as a mask, the layer 651 is silver-engraved to not fully penetrate the 6M depth to form (4) 656, 657, and 658, as shown in FIG. Thereafter, as shown in FIG. 9 = No, a second patterned photoresist layer 659 is formed over the layer 651. The second patterned photoresist layer 659 "exits the electrode members of the plugs (10), 112 = 660, 661. Using patterned photoresist layer 659 to make = or layer 65i is fully penetrated to contact with plugs 11 , 112 = 2 degrees to form more 662, 663 in trench regions 656, 657 and 658, such as This is shown in Figure 1. The finished double trench layer 651 is then filled with metal, such as _ is copper 21 200812073, gold, with suitable adhesion and barrier layers known to those skilled in the art. A layer 664 is formed as shown in Fig. 11. As shown in Fig. 12, a chemical-mechanical polishing or other similar technique is used to remove a portion of the metal layer 664 up to the dielectric layer 651 to form a double Electrode layers of electrodes 665, 666 and 667 are embedded. The electrodes 665 and 6667 are in contact with the plugs 11A, 112 and the electrode structure 666 is isolated from the source line 1 〇 6. In the next step, as shown in Fig. As shown, a layer of memory material 668a, a barrier layer 668b, and a thermal insulating layer 668c are formed in the embedded layer. Above the dielectric φ layer 651, referred to herein as the electrode layer of this element. A patterned photoresist layer ′ including masks 670 and 671 as shown in Fig. 14 is then formed over layer 668c. The covers 670 and 671 first exit the position of the bridge of memory material in the memory cell. Thereafter, a step is performed to remove portions of layers 669 and 668 that are not covered by masks 670 and 671, retaining a previously described inclusion of one Memory bridges 672 and 673 are formed by a composite structure of a memory material active layer, a barrier layer and a thermal insulating layer. The active layer of the bridge 672 extends from the electrode structure 665 to the electrode structure 666 through an insulating member 674. The width of the insulating member 674 is such that the length of the inter-electrode path of the memory material bridge 672 is expanded. The active layer of the bridge 673 extends from the electrode structure 667 to the electrode structure 666 through an insulating member 675. The width of the insulating member 675 The length of the electrode 辋 path of the memory material bridge 673 is expanded. As shown in Fig. 16, after the memory bridges 672 and 673 are defined, a dielectric filling layer (not shown) is formed and Flattened. Then, the via window is Engraved in a dielectric fill layer filled into electrode member 666. These vias are filled with a plug such as tungsten to form a conductive plug 676. A metal layer is then patterned to define bit line 677, which is embedded with the plug Contact, and arranged along the rows of memory cell pairs as shown in Figure 16. This dielectric filled material may not have a barrier layer with good thermal insulation. Therefore, 22 200812073 is used for memory bridge 672 and The thermal insulating material of 673 has a lower thermal conductivity than the dielectric filling material underneath. Figure 2 shows the final structure resulting from the process of the dual-insertion electrode structure, and the dielectric material removed from the electrode layer 651 of Fig. 16. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The application was filed on June 17, 2005 (attorney file number) VIXIC1621-1), the application series is a reference for this case, and this technology can be easily extended to the composite bridge structure described here in this bridge. A very narrow active layer is formed. Most of the phase change memory cell species known to the applicant are formed by forming a micropore and filling in phase change memory cells, followed by formation of top and bottom electrodes of the phase change material. This tiny hole junction ^ reduces the stylized current. The invention reduces the stylized current without micro holes, so that better process control can be achieved. In addition, there is no top electrode to avoid potential damage to the phase change material. The process of the H-bit process, the electrode layer structure on the functional circuit structure or the memory and function circuit on the single-chip is easy to support the system on chip (S0C) element* chip, for example, The advantages of the embodiment P of the invention result in a phase change of the vial on the electrically filled layer, rather than the fact that the viaduct is born on the junction, thus providing better reliability. Use, = between the poles ^ ^ used in the reset and the reduction of the cells described here, including the two substrates, and the dielectric layer on the electrode, across the dielectric phase, the bottom ▲ The electrode and the dielectric system are formed on the front-end process guide bridge. The current in 200812073 is limited to a small volume, allowing high current density and the resulting local heating effect, while requiring only a small reset current to - and a lower reset power consumption. Although the present invention has been described with reference to the preferred embodiments, it is understood that the invention is not limited by the detailed description. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, the structures and methods of the present invention, all of which are substantially identical to the components of the present invention and which achieve substantially the same results as the present invention, do not depart from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents. Any patent application or printed text mentioned in the foregoing is a reference for this article. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an embodiment of a phase change memory element film guide. Figure 2 is a perspective view showing a set of phase change memory elements having an access circuit under the φ one electrode layer and a bit line above the electrode layer. Figure 3 is a schematic plan view showing the structure in Figure 2. Figure 4 shows a memory array containing one phase change memory element. Figure 5 is a block diagram of an integrated circuit component including a thin film fuse phase change memory array and other circuits. Figure 6 is a first step cross-sectional view of a double damascene process for forming a memory element electrode layer. Figure 7 is a second step cross-sectional view of a double damascene process for forming a memory element electrode layer. 24 200812073

Figure 8 is a cross-sectional view showing a third step of forming a memory element electrode. Fig. 9 is a cross-sectional view of a fourth step for forming an electrode layer of a memory element. Fig. 10 is a fifth step sectional view of the electrode cone for forming a memory element. They are also defeated and lighted. Figure 11 is a six-step cross-sectional view of a six-step process for forming an electrode layer of a memory element. Melon light is shown in Fig. 12 as a seventh step sectional view of a cone for forming an electrode layer of a memory element. Also entertaining, Figure 13 is a cross-sectional view of an eighth step used to form. Figure 14 is a cross-sectional view of a ninth step for forming. Figure 15 is a cross-sectional view of a tenth step for forming. Figure 16 is a cross-sectional view of an eleventh step formed. Double-embedded process memory element electrode layer of the process memory element electrode layer double-embedded process memory element electrode layer double-embedded process memory element electrode layer double damascene process [main component symbol description] 1 memory cell 11 memory Chip guide 12 first electrode 12a, 13a, 14a upper surface 13 second electrode 14 insulating member 15 active layer 25 200812073

16 barrier layer 17 thermal insulating material layer 21 semiconductor substrate 23, 24 word line 25, 27 n-type terminal drain 26, 28 common source line 29, 30 plug structure 31 electrode layer 32, 33, 34 electrode member 35a, 35b insulated gates 36a, 37a memory material 36b, 37b barrier layer 36c, 37c thermal insulation material layer 38 tungsten plug 40 conductive layer 41, 42 bit line 45 Υ decoder and word line driver 46 X decoder and a sense of Amplifier 50 to 53 Access to Transistor 60 Memory Array | 61 Column Decoder 62 Word Line 63 Line Decoder 64 Bit Line 65, 67 Bus 68 Supply Voltage 69 Bias Arrangement State Machine 26 200812073 71 72 74 75 99 103~105 106 107,111 110~112 651 652 653,654,655 656,657,658 659 660,661 662,663 664 666,667 668a 668b 668c 670,671 672,672 674,675 676 677 Data input line data output line Other circuit integrated circuit structure Doped area source line polycrystalline seconds plug electrical insulation Material layer first patterned photoresist layer trench shallow trench second patterned photoresist layer embedding position deep trench metal layer electrode structure memory Material Barrier Layer, Thermal Insulation Material Layer Curtain Guide Bridge Insulation Member Conductive Plug Position Bit 27

Claims (1)

200812073 X. Patent application scope 1. A memory element, comprising: a first electrode having an upper surface; a second electrode having an upper surface; and an insulating member located at the first electrode and the second electrode The insulating member has a thickness between the first electrode and the second electrode adjacent to the upper surface of the first electrode and the upper surface of the second electrode; a guiding bridge spanning the insulating member, The viaduct has a first side 10 and a second side, and the first side contacts the upper surface of the first and second electrodes, and defines an inter-electrode path across the insulating member Between the first electrode and the second electrode, the inter-electrode path has a first path length from the width of the insulating member, wherein the guiding bridge comprises an active layer of a memory material on the first side, which has at least two a solid phase, and a blanket of thermal insulation overlying the memory material; and a layer of electrically insulating material over the blanket of thermal insulation, wherein the blanket of thermal insulation has a lower thermal conductivity Layer of electrically insulating material. The element of claim 1, wherein the electrically insulating material layer comprises sulphur dioxide. The component of claim 1, wherein the insulating member has a thickness of about 50 nm or less, and the active layer of the memory material comprises a film having a thickness of about 50 nm or the following. 4. The component of claim 1, wherein the insulating member has a thickness of about 20 nm or less, and the active layer of the memory material comprises a film having a thickness of about 20 nm or less. . The element of claim 1, wherein the active layer of the memory material comprises a film having a thickness of about 10 nm or less. 6. The element of claim 1, wherein the blanket comprises an electrically insulating material barrier layer between the active layer of the memory material and the thermal insulation material blanket. 7. The element of claim 1, wherein the blanket comprises a diffusion barrier layer between the active layer of the memory material and the thermal insulation blanket. 8. The element of claim 1, wherein the thermally insulating material comprises a chalcogenide. 9. The component of claim 1, wherein the thermally insulating material comprises polyamidamine. 10. The element of claim 1 wherein the at least two solid phase comprises a generally amorphous phase and a generally crystalline phase. 11. The component of claim 1, wherein the thickness of the insulating member is less than a minimum lithographic feature size used to form a lithography process of the component. 12. The component of claim 1, wherein the active layer of the memory material has a thickness between the first side and the second side, wherein the system is 29 200812073. The minimum lithography feature of the memory material One inch smaller than the one used to form one of the lithography processes of the element. The element described in the scope of the patent application includes a composition formed of ruthenium, osmium, and iridium. [1] The element according to Item 1, wherein the memory material comprises two or more compositions selected from the group consisting of: (Mi), Sb (Sb), and Te (Te). , indium (in), titanium (f), gallium (Ga), secret (Bi), tin (Sn), copper (Cu), palladium (Pd), lead (pb), silver (octal, sulfur (s), and Gold (Au) 〇15·- a memory element comprising: a substrate; an electrode layer on the substrate, the electrode layer comprising an electrode pair array having a first electrode having an upper surface and a second electrode having an upper surface a surface and an insulating member between the first electrode and the second electrode; an array of vias spanning the insulating members of the respective electrode pairs, the vias having respective first sides and a second Side, and the first side contacts the upper surface of the first and second electrodes with the respective electrodes, wherein the bridge, each of the active layers comprising a memory material on the first side, has at least two a solid phase, and a blanket of thermal insulation overlying the memory material; a layer of electrically insulating material over the array of vias, The thermal insulating material has a thermal conductivity lower than the electrically insulating material layer; and the bit line is over the electrically insulating material layer, and the via in the electrically insulating material layer contacts the bridge in the via array 30. The device of claim 15, wherein the insulating member has a thickness of about 50 nm or less, and the active layer of the memory material comprises a film having a thickness of about The component of claim 15, wherein the insulating member has a thickness of about 20 nm or less, and the active layer of the memory material comprises a film having a thickness of The object of claim 15, wherein the active layer of the memory material comprises a film having a thickness of about 10 nm or less. The component of claim 15, wherein the blanket comprises an electrically insulating material barrier layer between the active layer of the memory material and the thermal insulation blanket. The The device includes a diffusion barrier layer between the active layer of the memory material and the blanket of thermal insulation material. The component of claim 15, wherein the thermal insulation material comprises a chalcogenide. The component of claim 15, wherein the thermal insulating material comprises polyamidamine. 23. The component of claim 15, wherein the at least two solid 31 200812073 phase comprises a normal An amorphous phase and a generally crystalline phase. The component of claim 15 wherein the thickness of the insulating member is less than a minimum lithographic feature used to form a lithography process of the component. size. The component of claim 15, wherein the active layer of the memory material has a thickness between the first side and the second side, which is less than a lithography process for forming the component. A minimum lithographic feature size of the object of claim 15, wherein the memory material comprises a composition formed from enamel, recorded, and brick. The component of claim 15, wherein the memory material comprises two or more compositions selected from the group consisting of germanium (Ge), germanium (Sb), and germanium (Te). , indium (In), titanium (Ti), gallium (Ga), surface (Bi), _ tin (Sn), copper (Cu), p (Pd), erbium (Pb), silver (Ag), sulfur (S And a method for manufacturing a memory element, comprising: forming an electrode layer, the electrode layer comprising a first electrode having an upper surface, a second electrode having an upper surface and a An insulating member is disposed on an upper surface of the electrode layer between the first electrode and the second electrode, the insulating member extends to form an insulating wall on the upper surface of the electrode layer, and the insulating member has the a width between the electrode and the second electrode at the upper surface; 32 200812073, forming a memory material of a via bridge over the upper surface of the electrode layer of the insulating member, the bridge has a memory An active layer of material is in contact with the first-second electrode, and a thermal insulating blanket is over the active layer, and the guide The bridge defines an inter-electrode path between the first electrode and the second electrode across the insulating member, the inter-electrode path having a path length of a first one of the width of the insulating member, wherein the memory material has at least a second solid phase; and forming a layer of dielectric material over the via, wherein the thermally insulating blanket Φ comprises a thermally insulating material having a lower thermal conductivity than the dielectric material. The method of claim 28, wherein the insulating member has a thickness of about 50 nm or less, and the active layer of the memory material comprises a film having a thickness of about 50 nm or less. . 30. The method of claim 28, wherein the insulating member has a thickness of about 20 nm or less, and the active layer of the memory material comprises a film having a thickness of about 20 nm or less. . The method of claim 28, wherein the forming a bridge comprises forming a patch having a thickness of about 10 nm or less. 32. The method of claim 28, wherein forming an electrode layer comprises defining first and second electrodes of a plurality of pairs, and the isolating member separates one of the plurality of pairs from the other of the plurality of pairs a pair. 33. The method of claim 28, wherein the forming a viaduct comprises: 33 200812073 forming a memory material layer over the upper surface of the electrode layer; &quot; forming a layer of thermal insulating material thereon Above the memory material layer; &gt; The memory material layer and the layer of thermal insulation material are patterned to define the via bridge. The method of claim 28, wherein the forming the first and second electrodes comprises a double damascene process. 34