200810036 九、發明說明： 【發明所屬之技術領域】 本發明係有關於積體電路堆疊構造，特別係有關於 一種多封膠體共用基板之積體電路堆疊構造。 【先前技術】200810036 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit stack structure, and more particularly to an integrated circuit stack structure of a multi-package common substrate. [Prior Art]
在以往的積體電路封裝構造中，在一個別的基板上 形成有一封膠體，以密封保護積體電路晶片。多個積 體電路封裝構造會縱向堆疊，以減少接合至印刷電略 板之表面覆蓋面積（footprint)。 本國專利公告第55S153號「可堆疊式半導體封较 結構」揭示一種可堆疊式積體電路封裝構造，在封膠 體之頂面設有一頂封裝基板，並以一軟性電路板兩側 連接該頂封裝基板與一形成有封膠體之底封裝基板 在上方的頂封裝基板可供3D堆疊另一積體電路封裝In the conventional integrated circuit package structure, a single colloid is formed on one of the other substrates to seal and protect the integrated circuit wafer. A plurality of integrated circuit package configurations are stacked longitudinally to reduce the surface footprint of the bond pads. National Patent Publication No. 55S153 "Stackable Semiconductor Package Comparative Structure" discloses a stackable integrated circuit package structure having a top package substrate on the top surface of the sealant and connected to the top package by a flexible circuit board The top package substrate on the substrate and the bottom package substrate on which the encapsulant is formed is available for 3D stacking in another integrated circuit package
構造。在此一習知架構中，使用了大量的封裝基板，X 導致封裝成本的提高。 尽國專 「五丁 7賤褥坡 揭示一種積體電路封裝之堆疊構造，複數個積體、J 封裝構造各包含有一基板與一晶片並 路 休露的曰 片背面，雨兩晶片背面相對並以一接合膠黏钟 曰曰 晶片背面比較小面積且光滑’容易有位移與魏著由於 的問題。此外，每一積體電路封裝構造亦是採=不佳 基板’再以軟性電路板側向連接，壤 個別 守双程中兩 組裝步驟增多。 而要的 5 200810036 【發明内容】 本發明之主要目的係在於提供一種多封膠體共用 基板之積體電路堆疊構造，將多個積體電路封裴構造 整合在一可撓性基板並可堆疊固定，有效運用該可撓 性基板之封膠面積，以降低製造成本並縮小表面覆蓋=structure. In this conventional architecture, a large number of package substrates are used, and X leads to an increase in packaging cost. The "King Ding 7" slope reveals a stacked structure of an integrated circuit package, and a plurality of integrated body and J package structures each include a substrate and a wafer on the back side of the wafer, and the back sides of the rain are opposite to each other. With a bonding adhesive clock, the back side of the wafer is relatively small and smooth, and it is easy to have displacement and Wei. Therefore, each integrated circuit package structure is also a poor substrate and then a flexible circuit board. In the connection, the two assembly steps are increased in the individual two-way two-way process. The main purpose of the present invention is to provide an integrated circuit stack structure of a multi-package common substrate, and to seal a plurality of integrated circuits. The crucible structure is integrated on a flexible substrate and can be stacked and fixed, and the sealing area of the flexible substrate is effectively utilized to reduce manufacturing cost and reduce surface coverage.
本發明之次一目的係在於提供一種多封膠體共用 基板之積體電路堆疊構造，具有增進封膠體之黏著面 積、防止黏著材料溢膠之功效。 本發明之另一目的係在於提供一種多封膠體共用 基板之積體電路堆疊構造，$中一封膠體係具有：易 膠孔，不需要在壓模之後另施以其它不必要的蝕 』或每射鑽孔步驟，而避免對該積體電 件造成損害。 1構w之兀 方窣夾眘月的目的及解決其技術問題是採用以下技術 積體雷政現的。本發明揭示一種多封膠體共用基板之 =電路堆4構造’主要包含—可撓性基板一第一封膠 #膠體以及—黏著材料。該可撓性基板係具有一 上表面鱼一 ΊΓ ^ ^ ~ 。“第一封膠體係形成於該可撓性基板之 上表面並密封有—隻—曰 ^ ^ . 第一 Μ片。該第二封膠體其係形成於該可 挽性基板之上矣& # h i 极之上表面並密封有—第二晶片，其 在該第一封膠體盥訪楚-+ 』挽性基板 以第一封膠體之間的區段係 使該第二封膠體折暴力兮哲 ^ 斜 乂 封膠體之上方。該黏著材料係 黏者在折受後之兮^ , 亥第—封膠體之頂面與該第一封膠體之頂 6 200810036 面在另f施例中’該第二封膠體可折疊在該第一封膠體 之側面此外，複數個容膠穴或容膠槽係可形成在該第一封 膠體之頂面、側面或是該第二封膠體之頂面。 本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 在則述的夕封膠體共用基板之積體電路堆疊構造 中’該第-封膠體之頂面係形成有複數個容膠穴。A second object of the present invention is to provide an integrated circuit stack structure of a multi-sealant-composite substrate, which has the effects of improving the adhesive area of the sealant and preventing the adhesive material from overflowing. Another object of the present invention is to provide an integrated circuit stack structure of a multi-sealant common substrate, wherein the one-glue system has an easy-to-glue hole, and does not need to apply other unnecessary etching after the stamper or Each shot is drilled to avoid damage to the integrated electrical components. The structure of the 构 w 兀 兀 兀 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎 慎The invention discloses a multi-package common substrate. The circuit stack 4 structure ′ mainly comprises a flexible substrate, a first sealant #colloid and an adhesive material. The flexible substrate has an upper surface fish ^ ^ ^ ~ . The first encapsulation system is formed on the upper surface of the flexible substrate and sealed with a first cymbal. The second encapsulant is formed on the susceptibility substrate. # hi The upper surface of the pole is sealed with a second wafer, and the second encapsulant is violently entangled in the first encapsulant of the first encapsulant Zhe ^ 乂 乂 乂 乂 。 。 。 。 。 。 。 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该The second encapsulant can be folded on the side of the first encapsulant. In addition, a plurality of adhesive cavities or adhesive cavities can be formed on the top surface, the side surface of the first encapsulant or the top surface of the second encapsulant. The object of the present invention and the technical problems thereof can be further achieved by the following technical measures. In the integrated circuit stack structure of the oc-latent gel common substrate, the top surface of the first sealing body is formed with a plurality of adhesive materials. hole.
在刖述的夕封膠體共用基板之積體電路堆疊構造 中，該些容膠穴係由複數壓模針點（multiple ㈣所形 成的原生孔。 在别述的夕封膠體共用基板之積體電路堆疊造 中’另包含有複數個外接端子，其係設置於該可撓性且基板之 該下表面。 在前述的多封膠體共用基板之積體電路堆疊構造 中，該些外接端子係對準於該第一封膠體之下方。 在前述的多封膠體共用基板之積體電路堆疊構造 中，該些外接端子係包含銲球。 1 在前1的多封膠體共用基板之積體電路堆疊構造 中，該黏著材料係為非導電性液態黏膠。 【實施方式】 不—種多封膠體 圖係為該積體電 為該積體電路堆 在本發明之第一具體實施例中，揭 共用基板之積體電路堆疊構造，第1 路堆疊構造之戴面示意圖，第2圖係 疊構造在未摺疊狀態之截面示意圖。 7 200810036 如第1及2圖所示，一種積體電路堆疊構造1〇〇主 要包含一可撓性基板110、一第一封膠體12〇、一第二封膠 體1 3 0以及一黏著材料i 4〇。該可撓性基板丨丨〇係具有一上 表面111與下表面112，該第一封膠體120與該第二封勝 體1 3 0係共用該可撓性基板丨1 〇，即是複數個積體電路封裝 構造共用同一基板。此外，在封膠體堆疊之後不會增加該積 體電路堆疊構造1〇〇在對外表面接合時的表面覆蓋面 積（footprint)。 該第一封膠體120係形成於該可撓性基板11〇之上表面 111並密封有一第一晶片150。在本實施例中，利用複數個 第一銲線152電性連接該第一晶片150之複數個銲墊15ι至 該可棱性基板11 0。 該第一封膠體120之頂面121係形成有複數個容膠穴 122，以容納該黏著材料14〇並增加對該黏著材料14〇之黏 著面積。如第3圖所示，在本實施例中，該些容膠穴122可 進一步區分為在該第一晶片150上方的中央孔與在第一封膠 體1 20之周邊孔。較佳地，該些容膠穴i 22係由複數壓模針 點3 0(multiple mold pin)所形成的原生孔（如第4A圖所示）， 可快速形成該些容膠穴122，不需要在壓模之後另施以其它 不必要的姓刻或雷射鑽孔步驟’而避免對該積體電路堆疊 構造100之可撓性基板110等其它元件的損害。 該第二封膠體13 0係形成於該可撓性基板11 〇之上表面 111並密封有一第二晶片160,在本實施例中，利用複數個 第二銲線1 62電性連接該第二晶片1 60之複數個銲墊！ 6丨至 8 200810036 該可撓性基板110。該第二晶片160係可該第一晶片15〇可 為相同的積體電路晶片。其中，如第1圖所示，該可挽性基 板110在該第一封膠體120與該第二封膠體130之間的區段 係為可彎折並具有互連線路（圖未繪出），以使該第二封膠體 130折疊在該第一封膠體12〇之上方，以減少表面覆蓋面 積。 如第1圖所示，該黏著材料140係黏著在折疊後之該第 二封膠體130之頂面131與該第一封膠體12〇之頂面121， 以機械式固定該第二封膠體130，使該第二封膠體13〇不會 滑移鬆脫。通常該黏著材料14〇係可選用非導電性液態黏 膠’例如環氧熱固樹脂。 此外，該積體電路堆疊構造100可另包含有複數個外接 端子170，其係設置於該可撓性基板11〇之該下表面“2。 在本實施例中，該些外接端子丨70係對準於該第一封膠體 120之下方，以供對外表面接合。該些外接端子17〇係可包 含銲球（solder ball)。 因此，在上述之積體電路堆疊構造10〇中，其係整合至 少兩個封裴構造，其封膠體120與130係可共用同一個可撓 性基板no。當黏著材料140黏接兩封膠體12〇與13〇之後， 其整體表面覆蓋面積（即表面接合一印刷電路板之後，該積 體電路堆疊構造100所佔據的面積）約略等同一個封裝構造 的表面覆蓋面積。此外，在本實施例中，該第一封膠體12〇 之谷膠八122係具有增進黏著面積，防止黏著材料14〇溢膠 之功效。 9 200810036 第4A至4D圖係繪示該積體電路堆疊構造1〇〇在形 成該第一封膠體120之過程中之局部截面示意圖。首 先’如第4A圖所示，在壓模步驟中，該可撓性基板丨丨〇係 爽合在一上模具10與一下模具2()之間。在該上模具之In the integrated circuit stack structure of the occlusion sealing body common substrate, the capacitor holes are formed by a plurality of primary mold holes (multiple (four) formed by the original holes. The circuit stack is further configured to include a plurality of external terminals disposed on the flexible and lower surface of the substrate. In the integrated circuit stack structure of the multi-package common substrate, the external terminals are paired In the integrated circuit stack structure of the multi-colloid shared substrate, the external terminals comprise solder balls. 1 The integrated circuit stack of the first multi-package common substrate In the structure, the adhesive material is a non-conductive liquid adhesive. [Embodiment] The non-multi-colloidal pattern is the integrated circuit, and the integrated circuit is stacked in the first embodiment of the present invention. The integrated circuit stacking structure of the common substrate, the schematic diagram of the wearing structure of the first way stacking structure, and the cross-sectional view of the tied structure in the unfolded state of Fig. 2 7 200810036 As shown in Figs. 1 and 2, an integrated circuit stacking The first substrate comprises a flexible substrate 110, a first encapsulant 12, a second encapsulant 130, and an adhesive material i4. The flexible substrate has an upper surface. 111 and the lower surface 112, the first encapsulant 120 and the second enclosing body 1300 share the flexible substrate 〇1 〇, that is, a plurality of integrated circuit package structures share the same substrate. After the colloid stacking, the surface footprint of the integrated circuit stack structure 1 when the outer surface is bonded is not increased. The first encapsulant 120 is formed on the upper surface 111 of the flexible substrate 11 and sealed. There is a first wafer 150. In this embodiment, a plurality of first pads 150 are electrically connected to the plurality of pads 15 of the first wafer 150 to the prismatic substrate 110. The first encapsulant 120 The top surface 121 is formed with a plurality of adhesive cavities 122 for accommodating the adhesive material 14〇 and increasing the adhesion area of the adhesive material 14〇. As shown in FIG. 3, in the embodiment, the adhesive cavities are formed. 122 can be further divided into a central hole above the first wafer 150 and Preferably, the adhesive cavities i 22 are primary holes formed by a plurality of multiple mold pins (as shown in FIG. 4A). The adhesive pockets 122 can be formed quickly, without the need for other unnecessary surname or laser drilling steps after the stamping, and avoiding the flexible substrate 110 of the integrated circuit stack structure 100, etc. The second encapsulant 130 is formed on the upper surface 111 of the flexible substrate 11 and is sealed with a second wafer 160. In the embodiment, a plurality of second bonding wires 1 62 are electrically used. Connect a plurality of pads of the second wafer 1 60! 6丨至 8 200810036 The flexible substrate 110. The second wafer 160 can be the same integrated circuit wafer. Wherein, as shown in FIG. 1 , the section between the first encapsulant 120 and the second encapsulant 130 of the flexible substrate 110 is bendable and has interconnection lines (not shown). So that the second encapsulant 130 is folded over the first encapsulant 12〇 to reduce the surface coverage area. As shown in FIG. 1 , the adhesive material 140 is adhered to the top surface 131 of the second encapsulant 130 and the top surface 121 of the first encapsulant 12 , to mechanically fix the second encapsulant 130 . So that the second sealant 13〇 does not slip and loosen. Usually, the adhesive material 14 is optionally made of a non-conductive liquid adhesive such as an epoxy thermosetting resin. In addition, the integrated circuit stack structure 100 may further include a plurality of external terminals 170 disposed on the lower surface “2” of the flexible substrate 11 . In the embodiment, the external terminals 丨 70 are Aligned under the first encapsulant 120 for external surface bonding. The external terminals 17 may include solder balls. Therefore, in the above-mentioned integrated circuit stack structure 10, Integrating at least two sealing structures, the sealing bodies 120 and 130 can share the same flexible substrate no. When the adhesive material 140 is bonded to the two sealing bodies 12〇 and 13〇, the overall surface coverage area (ie, surface bonding) After a printed circuit board, the area occupied by the integrated circuit stack structure 100 is approximately equal to the surface coverage area of a package structure. Further, in the present embodiment, the first sealant 12 has a gluten-eighth 122 series. The adhesion area is improved to prevent the adhesive material from overflowing. 9 200810036 The 4A to 4D drawings show a partial cross-sectional view of the integrated circuit stack structure 1 in the process of forming the first encapsulant 120. First 'as shown in Figure 4A, in a stamper step, the flexible substrate Shushu engaged in a square-based cool the mold 10 and the lower mold 2 between the () in the upper mold
模穴内設有複數個壓模針點3〇，以在壓模步驟中同時形成上 述之容膠穴122。如第4B圖所示，在壓模步驟之後，當該 第一封膠體120形成之際，該第一封膠體12〇之頂面便形成 有複數個容膠穴122。此外，在本實施例中，該第一封膠體 120係密封在該可撓性基板11〇上之第一晶片15〇與該些第 銲線152。通常上述之第二封膠體13〇係與該第一封膠體 120同時形成（圖未繪出）。如第4C圖所示，可利用植球或/ 及銲料回銲技術將該些外接端子m設置在該可撓性基板 110之該下表® Π2。該些外接料17〇係可對準於該第一 封膠體i20之下方。之後，如第4D圖所示，以點 -點膠針頭4。提供該黏著材料14〇,將該黏著材料;4〇线 在該第一封膠體12 0之頂面12 1，可填入$小 』具入至少一部分之該些 容膠穴122内，例如在該第一晶片15〇 工万之中央孔。最後， 折疊該可撓性基板1 1 〇，使該第-私舰μ t 史哀第一封膠體13〇之頂面131可 黏接至該黏著材料140，即可組製成如第 路堆疊構造1〇〇。 帛1圖所不之積體電 請參閱第5及6圖，在本發明之第：具體實施例中 一種多封膠體共用基板之積體電路堆叠構造200係主要 包含一可撓性基板210、一第一封膠體22〇、至，一’、要 膠體230以及一黏著材料24。。在本實施例中至：：第二封 仕第一封滕 10 200810036 膠 體220之側面（例如是兩侧或是四側邊）各黏接有一第二封 體 230 〇 該可撓性基板210係具有一上表面211與一下表面212。 其中，該可撓性基板210之上表面211係被該第一封膠體22〇 與該些第二封膠體230所共用。 該第一封膠體220係形成於該可撓性基板2ι〇之上表面 211並密封有-第—晶片250。並且，該些第二封膠體㈣ 亦形成於該可撓性基板21〇之上表面211並密封有一第二晶 片260其中，該可撓性基板21〇在該第一封膠體與該 第二封膠體23G之間的區段係為可彎折。此外，該第一封膠 體220另密封複數個第—銲線252，其係電性連接該第一晶 片250之複數個銲塾251至該可撓性基板加；該第二封膠 體230另&封複數個第二銲線262，其係電性連接該第二晶 片260之複數個銲墊261至該可撓性基板21〇。 再如第5圖所示，該些第二封膠體23〇係可折疊在該第 一封膠體22〇之側面222。該黏著材料㈣係黏著在折疊後 之該些第二封膠體230之頂面231與該第-封膠體220之側 故該二第一封膠體230被該黏著材料24〇所機械固 定至該第-封膝體22〇。在本實施例中，該積體電路堆疊 構造2〇0另包含有-散熱片·，其係設置於該第一封膠體 2 2 〇之頂面2 2 1，用以;隹私备并以 曰進政熱並增加可供該些第二封膠體 2 3 0黏貼的部位。 較佳地，如第6圖所示，該第—封膠體22〇之侧面⑵ 係形成有複數個第一容膠穴223或容膠槽或者可在該第二 200810036 封膠體230之頂面231形成 ^ ^ 有複數個第二容膠穴232或容膠 槽’以增加該黏著材料240之黏荽 0之黏耆面積與黏著強度，並可減 輕該黏者材料240之溢膠程度。 該積體電路堆疊構造2〇〇 乃』巴3有複數個外接端子 270,其係設置於該可撓^ ^ 双1下表面212。該些外 接端子270係對準於該第一封膠體22〇之下方。 — 以上所述’僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然'本發明已以較佳實 施例揭露如上’然而並非用以限定本發明，任何熟悉 本項技術者’在不脫離本發明之技術範圍0，所作的 任何簡單修改、等效性變化與修飾，均仍屬於本發明 的技術範圍内。 【圖式簡單說明】 第1圖：依據本發明之第一具體實施例，一種多封膠 體共用基板之積體電路堆疊構造之截面示意A plurality of stamper pins 3 are provided in the cavity to simultaneously form the above-mentioned adhesive cavities 122 in the stamping step. As shown in Fig. 4B, after the stamping step, when the first colloid 120 is formed, a plurality of cavities 122 are formed on the top surface of the first encapsulant 12. In addition, in the embodiment, the first encapsulant 120 seals the first wafer 15A and the first bonding wires 152 on the flexible substrate 11A. Usually, the second encapsulant 13 described above is formed simultaneously with the first encapsulant 120 (not shown). As shown in Fig. 4C, the external terminals m can be placed on the lower surface of the flexible substrate 110, Π2, using a ball or/and solder reflow technique. The outer materials 17 can be aligned below the first encapsulant i20. Thereafter, as shown in Fig. 4D, the needle 4 is dispensed with a dot. Providing the adhesive material 14〇, the adhesive material; the 4 turns of the top seal 12 of the first sealant 120 can be filled into the at least a portion of the adhesive cavities 122, for example The first wafer 15 is completed in the center hole. Finally, the flexible substrate 1 1 折叠 is folded, so that the top surface 131 of the first private seal 第一 第一 first sealing body 13 可 can be adhered to the adhesive material 140, and can be assembled as a first way stack Construct 1〇〇. Referring to FIGS. 5 and 6 , in the first embodiment of the present invention, an integrated circuit stack structure 200 of a multi-package common substrate mainly includes a flexible substrate 210 , A first encapsulant 22, a, a ', a colloid 230, and an adhesive material 24. . In the present embodiment, the second sealing body 230 is bonded to the side of the colloid 220 (for example, the two sides or the four sides). The flexible substrate 210 is attached to each other. There is an upper surface 211 and a lower surface 212. The upper surface 211 of the flexible substrate 210 is shared by the first encapsulant 22 〇 and the second encapsulants 230. The first encapsulant 220 is formed on the upper surface 211 of the flexible substrate 2 ι and is sealed with a - wafer 250. Moreover, the second encapsulant (4) is also formed on the upper surface 211 of the flexible substrate 21 and is sealed with a second wafer 260. The flexible substrate 21 is disposed on the first encapsulant and the second seal. The section between the colloids 23G is bendable. In addition, the first encapsulant 220 is further sealed with a plurality of first bonding wires 252 electrically connected to the plurality of bonding pads 251 of the first wafer 250 to the flexible substrate; the second encapsulant 230 is additionally & And sealing a plurality of second bonding wires 262 electrically connected to the plurality of pads 261 of the second wafer 260 to the flexible substrate 21A. As shown in Fig. 5, the second sealant 23 can be folded over the side 222 of the first gel 22'. The adhesive material (4) is adhered to the top surface 231 of the second sealing body 230 and the side of the first sealing body 220, so that the two first sealing bodies 230 are mechanically fixed to the first sealing body 230 by the adhesive material 24 - Close the knee body 22〇. In this embodiment, the integrated circuit stack structure 2〇0 further includes a heat sink, which is disposed on the top surface of the first sealant 2 2 2 2 2 1; Into the political heat and increase the parts that can be attached to the second sealant. Preferably, as shown in FIG. 6, the side surface (2) of the first sealant 22 is formed with a plurality of first adhesive pockets 223 or adhesive tanks or may be on the top surface 231 of the second 200810036 sealant 230. Forming a plurality of second adhesive pockets 232 or adhesive tanks to increase the adhesive area and adhesion strength of the adhesive material 240, and to reduce the degree of gelation of the adhesive material 240. The integrated circuit stack structure 2 has a plurality of external terminals 270 disposed on the flexible surface 211. The external terminals 270 are aligned below the first encapsulant 22〇. The above description is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way, although the invention has been disclosed in the above preferred embodiments, but is not intended to limit the invention. Any simple modifications, equivalent changes, and modifications made by the skilled artisan without departing from the technical scope of the present invention are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a stacking structure of an integrated circuit of a multi-sealant-composite substrate according to a first embodiment of the present invention.
圖0 第2圖：依據本發明之第一具體實施例，該積體電路 堆疊構造在未摺疊狀態之截面示意圖。 第3圖：依據本發明之第一具體實施例，該積體電路 堆疊構造之其中一封膠體之俯視示意圖。 第4A至4D圖：依據本發明之第一具體實施例，該積 體電路堆疊構造在其封膠體形成過程中之爲 部截面示意圖。 第5圖：依據本發明之第二具體實施例，另一種多封 12 200810036 膠體共 用基板之積 體電路堆疊構造之截面 意圖。 第6 圖：依據本 .發明 之第二 具體實施例， 該積體電 堆疊構 造在未摺疊狀態之截面示 意 圖。 【主 要元件符號說明】 10 上模具 20 下模具 30 壓 模針點 40 點膠針頭 100 積體電路堆 疊構造 110 可撓性基板 111 上表面 112 下 表面 120 第一封膠體 121 頂面 122 容 膠穴 130 第二封膠體 131 頂面 140 黏著材料 150 第一晶片 151 銲墊 152 第 一銲線 160 第二晶片 161 銲墊 162 第 二銲線 170 外接端子 200 積體電路堆 疊構造 210 可撓性基板 211 上表面 212 下 表面 220 第一封膠體 221 頂面 222 側 面 223 第一容膠穴 230 第二封膠體 231 頂面 232 第 二容膠穴 240 黏著材料 250 第一晶片 251 銲塾 252 第 一鲜線 260 第二晶片 261 銲墊 262 第 二銲線 270 外接端子 280 散熱片 13Fig. 0 Fig. 2 is a schematic cross-sectional view showing the stacked circuit structure in an unfolded state in accordance with a first embodiment of the present invention. Figure 3 is a top plan view of a colloid of the integrated circuit stack structure in accordance with a first embodiment of the present invention. 4A to 4D are views showing a cross-sectional view of the integrated circuit stack structure in the process of forming the sealant in accordance with the first embodiment of the present invention. Figure 5 is a cross-sectional view of an integrated circuit stack structure of another multi-package 12 200810036 colloidal conjugate substrate in accordance with a second embodiment of the present invention. Figure 6 is a cross-sectional view of the integrated electrical stack constructed in an unfolded state in accordance with a second embodiment of the present invention. [Main component symbol description] 10 Upper mold 20 Lower mold 30 Presser pin point 40 Dispensing needle 100 Integrated circuit stack structure 110 Flexible substrate 111 Upper surface 112 Lower surface 120 First gel 121 Top surface 122 Capacient hole 130 second encapsulant 131 top surface 140 adhesive material 150 first wafer 151 pad 152 first bonding wire 160 second wafer 161 pad 162 second bonding wire 170 external terminal 200 integrated circuit stack structure 210 flexible substrate 211 Upper surface 212 lower surface 220 first gel 221 top surface 222 side 223 first glue pocket 230 second seal 231 top surface 232 second glue pocket 240 adhesive material 250 first wafer 251 solder 252 first fresh line 260 second wafer 261 pad 262 second wire 270 external terminal 280 heat sink 13