200819997 九、發明說明： 【相關申請案資料] 本案主張於6/2/2006所申請之美國臨時申請案第 60/803,782號與7/6/2〇〇6所申請之美國臨時申^ 60/806,704 號優先權。 。 【發明所屬之技術領域】 治本發明係有關於序列周邊介面(SPI)匯流排，特別是關於 2 :多杈匯流排上許多腳位上同一方向進行資料傳輸的 傳輸速度的方法及裝置。 【先前技術】 本發明係相關於序列周邊介面(SPI)匯流排，其具有一次 ;„位:乂及一資料輸入腳位。例如序列周邊介；“ 較傳統上具有一優點，即序列周邊介面具有-的連接式。此外’隨著時脈速度日益增加，平行介面 點也變得越來越不重要。然而，在速度與簡 八重要的應用中，仍是希望能繼續使用標準的序列周邊 D匯流排，而同時又能增加其傳輸速度。 【發明内容】 驗之—目的在練供—種積體電路，其财在積體電 腳二傳=八匯流排。™^ 兮Ffe# 作槟式此腳位包含一第一資料通訊腳位以在 ‘、甬::、一曰又，吼、—第二貧料通訊腳位以在該匯流排上進 之ίΤ3二^#選擇腳位以指示在該積體電路與另—積體電路 之間疋否正在進行軌、以及—時_卩姻叫紐流排上提 200819997 供時脈。此選擇性操作模式，包含一第一模式，在其中該第一 資料通訊腳位與該第二資料通訊腳位係以相反方向'在^積體 電路與另一積體電路之間進行通訊，以及_第二模式，=▲中 該第一資料通訊腳位與該第二資料通訊腳位係以同方^在 該積體電路與另一積體電路之間進行通訊。因為此通訊係選擇 性地發生，此操作模式包含至少第一及第二操作模弋'在許多 實施例中，在至少操作模式之一(例如第—操'作模或第1 操作模式）此資料通訊腳位係以自該積體電路至另一 路’及/或自另一積體電路至該積體電路的方向進行資料通笊。 在某些實施例中，此匯流排使用多餘週期以補、另一精 延遲。在某些實施例中’此匯流排係根據-序列周邊 積體t同的實施例巾’此積體電路是—主频電路或是一僕 片、登ΐίΐ主—積H路的實施例中，複數個腳位包括複數個晶 卜擇腳位’母-柄數個晶片選擇腳 與一個別賴频電路之狀紅在騎㈣。^積體電路 主積實施例中’該晶片選擇腳位指示在該 主積體电路與該僕積體電路之間是否正在進行通訊。 些實施例中’更包含—記憶體於此積體電路中。 ，明之另-目的在於提供—種在—積體電路與另 -电路之間進行資料傳輸的方法，包含下形驟·· 、 政夕時脈職提供喊給在該频電路與另—積體電 路之間傳輸資料的-匯流排。 刀娜電 路夕，t晶片選擇信號以指示在該積體電路與另一積體電 路之間是否正在進行資料傳輸。 ⑽電 少包地=复f賴式之—傳輸該資料，該複數個模式至 as 式及-第二模式；其中在該第—模式中_第_ 200819997 腳位與一第二貢料傳輸腳位係以相反方向在兮 tiir積體電路之間進行傳輪；且在該第二模式麗 腳位與該第二資料傳輸腳位係以相同方向在；ί〜 電路與另一積體電路之間進行傳輸。 /積體 其他的貫施例則在之後描述。 料傳又:含目的在於提供-種在積盤電路之間進行資 電狀給在—純電軸另~積趙 積體，^之以:^^二傳：不在該積體電路與另- 次粗3iiTf地在至少包含—第—模式及―第二模式之-傳於 J:次：值袁’其中在該第一模式中-第-資料傳輸腳位與： 路之間進仃傳輸；且在該第二模式中該 ， 位係以相同方向在該積體電路與^一積= 周邊侧在讀贿，㈣祕祕錄據-序列 【實施方式】 ΝΤ>Τ、第1圖為一具有主與僕積體電路實施例的序列周邊介面 (SPI)組態示意圖。 _此序列周邊介面（SPI)匯流排是一序列介面，具有以下的 ΐί、/、序列時脈(SCK);主資料輸出或僕資料輸入(MDO/SI); 夕資料輪入或僕資料輸出（MDI/SO);以及晶片選擇(cs#)。許 夕序列周邊介面(SPI)的實施例具有兩個組態位元，時脈極性 200819997 (CPOL)及時脈相位(CPHA)。因為序列時脈(SCK)承載一分離的 時脈信號，其是做為此序朋邊介面(spi)#料的時脈 f 2_是—_步介面，即其不會將時脈信號包 含於資料流本身之中。 時脈極性(CPOL)決定此位移時脈閒置 (〇>〇㈣或是高準轉P0L=1)。時脈相位(CPHA)決定資= 哪-個時脈雜被师❹(CPHA=G時，謂SI資料在 邊緣被位移ϋ{，而CPHA=1時，MQ/SI #料在场邊 人。因為每—位元具有兩個狀態，如此可以允許四個不 四個時脈極性與相位設定中的兩個 )的子木，且其疋序列周邊介面（SPI)的一實施 5具，下之固定的日_亟性與相位:SI(資料位移進5 在^序列時脈的上升邊緣被拾鎖，且s〇(資料位移 降邊緣被改變。序列時脈總是在低準位假如並沒有 争古邊介面(SPI)的—實施例修改SI和so腳位以進杆 =速存取的操作。並不再將輸人81腳位僅 : i=:r=同λ?輸入或在： 且自主元件腳位同時皆作為輸入腳位 so腳付而抖。而在資料/狀態輸出相位時，SI釦 so腳位兩者同時皆作為輪出腳位且傳送資料至了 SI和 此SI和so腳位可以被用作為輸入及輸出腳位之用，:此 200819997 #σ SI/SI01 ° 入 的效率與傳統僅使用輸入SI腳位作為指令/ 有效二腳位作為資料级_相較，其具 電路L1 列周邊介面㈣組態’其具有-主積體 電路件UG電性連接至三健積體電路元件、1〇1和 102此主元件no的晶片選擇腳位為c·、c撕和^隨， 接i各別儒元件100、101和102的晶片選擇腳 1 *牛110的序列時脈(SCK)腳位電性連接至僕元 件、101和102的序列時脈(SCK)腳位。此主元件110的 M_腳位電性連接至僕元件刚、1〇1和1〇2的丄〇〇 = 主70件11G #MSI0()腳位電性連接至僕元件觸、 101和102的謂101腳位。在此組態下，此主積體電路元件 的和msio1腳位以及此備積體電路元件的·1〇= SO/SKM腳位為雙向輸入/輸出腳位。在指令輸入相位時， MSIOO和MSI01腳位作為主元件輸出腳位而此si/s·和 S0/SI01腳位係作為特定僕元件的輸人。相反地，在 相位時，此漏〇〇和S〇/SI〇1腳位係作為特錢元件的輸出 腳位，而MSIOO和MSI01腳位作為主元件輸入。 第2圖為一序列周邊介面(spi)積體電路的一讀取時脈示 意圖，其具有許多多餘週期以補償僕積體電路的延遲。 —在厂兀、件選擇信號(CS#)於一下降邊緣發出之後，一 8位 兀指令被傳运且由SI腳位接收以致能此兩個輸人/輸出腳位進 行相同方向的輸人輸出操作。此位址在序列時脈(SCK)的上升/ 下降邊緣被栓鎖，且位址資料在每一次序列時脈(SCK)的上升/ 下降邊緣位移兩個位元，在兩個輸入/輸出腳位，即·1〇0 200819997 和S0/SI01間交錯進行。此位址的第一和第二位元由此主元件 的MSIOO和MSI01腳位傳送，而由此僕元件的SI/SI〇〇和 S0/SI01腳位同時接收。因此，位址位元經由SI/SIOO和 S0/SI01腳位一次傳遞2個位元。位址位元持續地被傳送與接 收直到24位元位址傳送被完成為止。根據序列時脈(sck)的頻 率，某些特定數目Ν=〇、〇·5、卜ι·5、2、2.5等的多餘週期可 以在位址的最後一位元與輸出資料的第一位元之間被插入。此 多餘週期被用於僕元件的内部運作。例如在一 4位元的多餘週 期被插入之後，此資料開始於此多餘週期結束之後在序列時脈 (sck)的上升/下降邊緣位移出來。此資料每一次由SI/SI〇〇和 S0/SI01腳位位移出2位元。此一位元組的資料僅需4個時脈 上升/下降邊緣就可以被位移出。此2位元輸出係利用此序列 周邊介面(SPI)匯流排兩個腳位所產生的高效率資料輸出之優 點。與一較簡單的序列周邊介面(SPI)介面比較，此序列周邊介 =(sn)介^面具有兩倍資料輸出效能以及較短的位址位元輸入 蚪間。一南效能介面增加了系統存取時間效率以及在僕元 作等待時改善了整體系統表現。 立第3圖為一序列周邊介面(SPI)積體電路的一讀取時脈示 ，圖，其具有較第2圖更多的多餘週期以補償僕積體電路的 長延遲。 圖:顯示一具有8位元假時脈週期之資料傳輸。需要較大 f目的多餘週期以配合僕元件的内部運作，例如當僕元件的内 f運作較慢時，或是當此序列時脈(SCK)的頻率高於利 作的序列時脈(SCK)時，例如第2圖中所顯示的四 舰^週期。多餘職的數目躲決於相時脈(SCK)的 y用例實施例中，相異於8個位元的多餘週期被使 例如&過8個位元或是少於8個位元。 10 200819997 第4圖為一序列周邊介面(si>i)積體電路的一操作模式流 程圖，其係使用單一腳位(應加上即當成丨位元執盥 相符)來傳輸資料。 圚甲 在步驟402 ’晶片選擇信號(CS#)為低準位。在步驟404， 與此使用單一序列周邊介面(SPI)腳位來傳輸資料相關的讀取 指令程式碼被送出。在步驟406，此24位元位址被送至二 一腳位來傳輸資料。在步驟408，等待一 8位元多餘週期。在 步驟410，資料被儲存於此單一腳位傳輸資料所指定的位址。 在步驟412，晶片選擇信號(CS#)變為高準位，此改變 於步驟410中發生。 近 第5圖為一序列周邊介面(spi)積體電路的一操作模式流 程圖、，、其係使用多重腳位來傳輸資料，且一定數目的多餘以= 於傳送位址之後和資料被儲存於此位址之前被插入。 在步驟502，晶片選擇信號(CS#)為低準位。在步驟5〇4， 與此使用兩個序列周邊介面（SPI)腳位來傳輸資料相關的讀取 指令程式碼被送出。在步驟5〇6，此24位元位址被交錯送至 此兩個腳位來傳輸資料。在步驟5〇8，等待一 8位元多餘週期。 在步驟51G，資料被儲存於此兩個腳位傳輸資料所指定的位 址。在步驟512,晶片選擇信號(cs#)變為高準位，此改變可以 隨時於步驟510中發生。 士第6圖為一序列周邊介面(SPI)積體電路的一傳送資料之 時脈示意圖，其係使用多重腳位以及兩倍速(DDR)傳送資料。 不論是自主積體電路傳送至僕積體電路的位址，以及由此 位址所儲存之回傳資料自僕積體電路回傳至主積體電路，兩者 皆以兩倍速(DDR)傳輸。在兩個方向上，兩個腳位被用來交錯 200819997 傳輸資料，因此增加了傳輸速度。在另一實施例中，係使 一腳位而不是兩個腳位來傳輸資料。 第7圖為一序列周邊介面(SPI)積體電路的一傳送資料 =不意圖，其錢用多重職以及僅在域之間的一個方向 上利用兩倍速(DDR)傳送資料。 自主積體電路傳送域積體電路的位址並沒有以兩 fDR)傳輸。而由此位址所儲存之資料自僕顏電路回傳至主 Π，’則是以兩倍速(DDR)傳輸。在兩個方向上，兩個腳 Γ來!?傳輸資料’因此增加了傳輸速度。在另—實施例 中，係使用單一腳位而不是兩個腳位來傳輸資料。 士第8圖為一序列周邊介面(SPI)積體電路的一傳送資料之 日^脈不意@，其係使用多重腳位以及僅在主僕之間的—個方向 利用兩倍速(DDR)傳送資料，特別是與第7圖相反的方向。 自主積體電路傳送至僕積體電路的位址係以兩倍速(ddr) 傳輸。而由此位址所儲存之資料自僕積體電路回傳至主積體電 路則不疋以兩倍速(DDR)傳輸。在兩個方向上，兩個腳位被 用來交錯傳輸資料，因此增加了傳輸速度。在另一實施例中， 係使用單一腳位而不是兩個腳位來傳輸資料。 第9圖為根據本發明之一實施例的包含一非揮發記憶陣 列之序列周邊介面(SPI)積體電路的範例方塊示意圖。 此積體電路950包括在一半導體基板上使用電荷捕捉結 構=彳軍發記憶胞，例如浮動閘極、電荷捕捉或是電阻元件(如 相I:化)所構成的一記憶陣列9⑻。此記憶胞陣列9⑻可以是單 獨的記憶胞、交錯形成陣列或是在多重陣列中交錯。一列解碼 12 200819997 $ 90】_接於在該記憶陣列9〇时成列排列的複數個字 =2^仃解碼器·係祕至在該記憶陣列__成行 Ϊ=ίί=4。在匯流排9〇5上提供位址到行解碼請 歹J解馬益901。在區塊906 f感測放大器盥資 通過資料匯流排9〇7喻接至該行解碼器9Q、m:= 該積體電路㈣上的輸人/輸出槔Ϊ 卩或外部㈣源提供細彳區塊906 的貝科輸入結構。在區塊906中通過該資料輪出綠 感測放大器提供資料至積體電路9 幹 < = 供資料至在積體電路950内部或外部之出^或提 :控制偏厂陶供應電二 列周邊介面_傳輸腳γ㈣及/或平付錯使用此兩個序 揭露=日m解$考^^上之該較佳實施例與例示而 而為非用:限; 成各種的修飾與結合，而該些化飾^^^而吕’可輕易地達 與及下列申請專利範圍所限^的i圍、;口/洛於本發明之精神 【圖式簡單說明】 第1 積體電路的mr序列周邊介面卿)組 態’其具有主及僕 示 意圖介面(spi)積體電路的-讀取時脈 有才〜餘週期以補償僕積體電路的延遲。 第3圖為為-序列周邊介面(SPI)積體電路的—讀取時脈 13 200819997 積體電路的 二意圖’其具有較第2圖更多的多餘職以補 較長延遲。 、 第4圖為一序列周邊介面 體 程圖，其係使用單一腳位來傳輸資料。路的&作拉式流 第5圖為一序列周邊介面(处^積體電路 程圖，其係使用多重腳位來傳輸資料。路的&作拉式流 日丰rr第立6闽圖為一序列周邊介面(SPI)積體電路的一傳送資料之 、不思圖’其係使用乡重腳位以及兩倍速(DDR)傳送資料。 時脈ί咅7pTi=列周邊介面_積體電路的一傳送資料之 圖，其係使用多重腳位以及僅在主僕之間的—個方向 上利用兩倍速(DDR)傳送資料。 日士Hr第立8圖為一序列周邊介面(SPI)積體電路的一傳送資料之 ^=不意圖，其係使用多重腳位以及僅在主僕之間的一個方向 •用兩倍速(DDR)傳送資料，特別是與第7圖相反的方向。 第9圖為根據本發明之一實施例的包含一非揮發記憔陣 ，之序列周邊介面(SPI)積體電路的範例方塊示意圖 ， 【主要元件符號說明】 主積體電路 僕積體電路 晶片選擇 序列時脈 主資料輸入 110 100、1〇1、102 csa200819997 IX. Invention Description: [Related application materials] This case claims the US provisional application 60/803,782 and 7/6/2〇〇6 applied for in US Provisional Application No. 6/2/2006. Priority 806,704. . [Technical Field] The present invention relates to a sequence peripheral interface (SPI) bus, and more particularly to a method and apparatus for transmitting data in the same direction on a plurality of pins on a plurality of bus bars. [Prior Art] The present invention relates to a Sequence Peripheral Interface (SPI) bus, which has one time; „ bits: 乂 and a data input pin. For example, a sequence peripheral; “more traditionally has an advantage, that is, a sequence peripheral interface Connection with -. In addition, as the speed of the clock increases, the parallel interface becomes less and less important. However, in applications where speed and simplicity are important, it is still desirable to continue to use the standard sequence peripheral D bus, while at the same time increasing its transmission speed. [Summary of the Invention] The test--the purpose is to train and supply the integrated circuit, and its wealth is in the integrated circuit of the second pass = eight bus. TM^ 兮Ffe# For the Penang style, this pin contains a first data communication pin to be in the ', 甬::, 曰, 吼, 第二, second poor communication pin to enter the bus. Two ^ # select the pin to indicate whether the ongoing circuit between the integrated circuit and the other integrated circuit, and - when the 纽 叫 纽 纽 纽 纽 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 The selective operation mode includes a first mode in which the first data communication pin and the second data communication pin are in opposite directions to communicate between the integrated circuit and another integrated circuit. And the second mode, in the ▲, the first data communication pin and the second data communication pin are in the same way to communicate between the integrated circuit and another integrated circuit. Since this communication occurs selectively, the mode of operation includes at least first and second modes of operation 'in many embodiments, in at least one of the modes of operation (eg, the first mode or the first mode of operation) The data communication pin is communicated in the direction from the integrated circuit to the other path 'and/or from another integrated circuit to the integrated circuit. In some embodiments, this bus uses redundant cycles to compensate for another fine delay. In some embodiments, the bus line is based on the same embodiment of the sequence-integrated body t. The integrated circuit is in the embodiment of the main frequency circuit or the servant chip, the ΐ ΐ ΐ main-product H channel. The plurality of pins include a plurality of crystals, the selection of the feet, the number of the mother-handle, and the selection of the chip and the shape of a different frequency circuit (four). The integrated circuit in the main product embodiment 'the wafer selection pin indicates whether communication is in progress between the main integrated circuit and the supercharger circuit. In some embodiments, the memory is further included in the integrated circuit. And the purpose of the other is to provide a method for data transmission between the integrated circuit and the other circuit, including the lower form, and the political and ceremonial service provides shouting to the frequency circuit and the other. The data-bus is transmitted between the circuits. At the knife circuit, the t chip selects a signal to indicate whether data transfer is in progress between the integrated circuit and another integrated circuit. (10) electric less packet = complex 赖 — - transmission of the data, the plurality of modes to as and - second mode; wherein in the first mode _ _ 200819997 pin and a second tribute transfer pin The bit is carried in the opposite direction between the 兮tiir integrated circuits; and the second mode is in the same direction as the second data transfer pin; ί~ circuit and another integrated circuit Transfer between. /Integrations Other embodiments are described later. The material is transmitted again: the purpose is to provide - the kind of power supply between the circuit of the accumulation plate to give - the pure electric axis and the other product, the product is: ^^2: not in the integrated circuit and another - coarse 3iiTf is at least included in the -first mode and the second mode - passed in J: times: value Yuan' where in the first mode - the - data transmission pin and: the road between the transmission; In the second mode, the bit is in the same direction in the integrated circuit and the peripheral side is reading the bribe, (4) the secret record-sequence [embodiment] ΝΤ > Τ, the first picture is a master and Schematic diagram of the sequence peripheral interface (SPI) configuration of the embodiment of the servant circuit. _This sequence peripheral interface (SPI) bus is a sequence interface with the following ΐί, /, sequence clock (SCK); main data output or servant data input (MDO/SI); eve data round or servant data output (MDI/SO); and wafer selection (cs#). The embodiment of the Xuzhou Sequence Peripheral Interface (SPI) has two configuration bits, clock polarity 200819997 (CPOL) Time Lapse Phase (CPHA). Because the sequence clock (SCK) carries a separate clock signal, it is the clock of the sequence interface (spi) that is the _step interface, that is, it does not include the clock signal. In the data stream itself. The clock polarity (CPOL) determines whether the displacement clock is idle (〇 > 〇 (4) or high-precision P0L = 1). The clock phase (CPHA) determines the cost = which clock is misunderstood (when CPHA=G, the SI data is shifted at the edge ϋ{, and when CPHA=1, MQ/SI # is on the side of the field. Because Each bit has two states, so that four of the four clock polarity and phase settings can be allowed, and the implementation of the subsequence interface (SPI) is fixed. Day_亟 and phase: SI (data shift into 5 is picked up at the rising edge of the sequence clock, and s〇 (the data shifting edge is changed. The sequence clock is always at the low level if there is no contention The Ancient Edge Interface (SPI) - the embodiment modifies the SI and so feet to enter the bar = speed access operation. It will no longer enter the 81 pin: i =: r = same as λ? input or in: and At the same time, the autonomous component pin is used as the input pin sock. While in the data/status output phase, both the SI pin and the pin are both used as the pin and transmit the data to the SI and this SI and so. Pins can be used as input and output pins: this 200819997 #σ SI/SI01 ° efficiency and traditional use only input SI pin as command / effective two feet As a data level _, it has a circuit L1 column peripheral interface (4) configuration 'the wafer selection with the main body circuit component UG electrically connected to the three health integrated circuit components, 1 〇 1 and 102 this main component no The pin position is c·, c tear and ^, and the chip selection pin 1 of the respective Confucian elements 100, 101 and 102 is connected to the slave clock element (SCK) pin electrically connected to the servant element, 101 and 102. Sequence clock (SCK) pin. The M_ pin of this main component 110 is electrically connected to the servant element, 〇1 and 1〇2 主= main 70 piece 11G #MSI0() pin position The connection to the servant element, 101 and 102 is the 101 pin. In this configuration, the sum of the main circuit circuit component and the msio1 pin and the 1⁄2 = SO/SKM pin of the spare circuit component It is a bidirectional input/output pin. When the input phase is commanded, the MSIOO and MSI01 pins are used as the main component output pins, and the si/s· and S0/SI01 pins are the inputs of the specific servant components. Conversely, In phase, the drain and S〇/SI〇1 pins are used as the output pins of the special money component, while the MSIOO and MSI01 pins are input as the main components. Figure 2 shows a sequence of peripheral interfaces (spi A read clock diagram of the integrated circuit having a plurality of redundant periods to compensate for the delay of the servo circuit. - After the factory, the component selection signal (CS#) is issued at a falling edge, an 8-bit command Being transmitted and received by the SI pin to enable the two input/output pins to perform the same direction of the input output operation. This address is latched at the rising/falling edge of the sequence clock (SCK), and the bit is latched. The address data is shifted by two bits at the rising/falling edge of each sequence clock (SCK), interleaved between two input/output pins, ie, 1〇0 200819997 and S0/SI01. The first and second bits of this address are transmitted by the MSUMO and MSI01 pins of the master element, and thus the SI/SI and S0/SI01 pins of the slave are simultaneously received. Therefore, the address bit transfers 2 bits at a time via the SI/SIOO and S0/SI01 pins. The address bits are continuously transmitted and received until the 24-bit address transfer is completed. According to the frequency of the sequence clock (sck), some specific numbers of Ν=〇, 〇·5, 卜·5, 2, 2.5, etc. can be in the last bit of the address and the first bit of the output data. The meta is inserted between. This extra cycle is used for the internal operation of the servant component. For example, after a 4-bit redundant period is inserted, the data begins to shift out at the rising/falling edge of the sequence clock (sck) after the end of the excess period. This data is shifted by 2 bits each time by the SI/SI〇〇 and S0/SI01 pins. This one-tuple data can be displaced by only 4 clock rise/fall edges. This 2-bit output utilizes the advantages of high-efficiency data output from the two peripherals of this sequence of peripheral interface (SPI) busses. Compared with a simpler Serial Peripheral Interface (SPI) interface, this sequence has a double data output performance and a shorter address bit input. The One-South Performance Interface increases system access time efficiency and improves overall system performance while waiting for the servant. Figure 3 is a read clock diagram of a sequence of peripheral interface (SPI) integrated circuits, which has more redundant periods than Figure 2 to compensate for the long delay of the servo circuit. Figure: shows a data transfer with an 8-bit false clock cycle. A large period of f-purpose is required to match the internal operation of the servant element, for example, when the internal f of the servant element is slower, or when the frequency of the sequence clock (SCK) is higher than the sequence clock (SCK) of the benefit. For example, the four ship ^ cycle shown in Figure 2 is used. The number of redundant jobs is hidden from the y use case of the phase clock (SCK). In the embodiment, the excess period different from 8 bits is, for example, & 8 bits or less than 8 bits. 10 200819997 Figure 4 is an operational mode flow diagram of a sequence of peripheral interfaces (si>i) integrated circuits that use a single pin (which should be added as a bit) to transmit data. The armor at step 402' wafer select signal (CS#) is at a low level. At step 404, the read command code associated with the transfer of the data using the single sequence peripheral interface (SPI) pin is sent. At step 406, the 24-bit address is sent to the second bit to transfer the data. At step 408, an 8-bit redundant period is awaited. At step 410, the data is stored in the address specified by the single pin transmission data. At step 412, the wafer select signal (CS#) becomes a high level, which changes to occur in step 410. Figure 5 is a flow chart of an operation mode of a sequence of peripheral interface (spi) integrated circuits, which uses multiple pins to transmit data, and a certain number of extras are used after the transmission address and the data is stored. Inserted before this address. At step 502, the wafer select signal (CS#) is at a low level. In step 5〇4, the code-related read instruction code is transmitted using the two sequence peripheral interface (SPI) pins. In step 5〇6, the 24-bit address is interleaved to the two pins to transfer the data. In step 5〇8, wait for an 8-bit redundant period. At step 51G, the data is stored in the address specified by the two pin transmission data. At step 512, the wafer select signal (cs#) becomes a high level and this change can occur at any time in step 510. Figure 6 is a clock diagram of a sequence of peripheral interface (SPI) integrated circuits that uses multiple pins and double speed (DDR) to transmit data. Regardless of the address transmitted by the autonomous integrated circuit to the servo circuit, and the backhaul data stored by the address is returned from the servant circuit to the main integrated circuit, both are transmitted at twice speed (DDR). . In both directions, two pins are used to interleave 200819997 to transfer data, thus increasing the transmission speed. In another embodiment, a pin is used instead of two to transmit data. Figure 7 is a transmission of a sequence of peripheral interface (SPI) integrated circuits = not intended, the money is used to transmit data in multiple directions and in only one direction between domains using double speed (DDR). The address of the autonomous integrated circuit transmission domain integrated circuit is not transmitted in two fDR). The data stored in this address is transmitted back to the host from the servant circuit, and is transmitted at twice the speed (DDR). In both directions, two feet come! The data is transmitted, thus increasing the transmission speed. In another embodiment, a single pin is used instead of two to transmit data. Figure 8 shows the transmission of data in a sequence of peripheral interface (SPI) integrated circuits. It uses multiple pins and uses double speed (DDR) transmission only in the direction between the master and the servant. Information, especially in the opposite direction to Figure 7. The address transmitted by the autonomous integrated circuit to the servo circuit is transmitted at twice the speed (ddr). The data stored in this address is transmitted back to the main integrated circuit from the servant circuit and transmitted at twice the speed (DDR). In both directions, two pins are used to interleave data, thus increasing the transmission speed. In another embodiment, a single pin is used instead of two to transmit data. Figure 9 is a block diagram showing an example of a sequential peripheral interface (SPI) integrated circuit including a non-volatile memory array in accordance with an embodiment of the present invention. The integrated circuit 950 includes a memory array 9 (8) formed on a semiconductor substrate using a charge trapping structure, such as a floating gate, a charge trap, or a resistive element (e.g., phase I). The memory cell array 9(8) can be a separate memory cell, interleaved into an array or interleaved in a multiple array. A column of decoding 12 200819997 $ 90] _ connected to a plurality of words arranged in a column at the time of the memory array = 2 ^ 仃 decoder · system secret to the memory array __ line Ϊ = ίί = 4. Provide address-to-row decoding on bus 9〇5. 歹J Jie Ma 901. In block 906, the sense amplifier is supplied to the decoder 9Q, m:= the input/output 槔Ϊ or the external (four) source on the integrated circuit (4) through the data bus 9〇7. Block 906's Beca input structure. In block 906, the green sense amplifier is provided by the data wheel to provide data to the integrated circuit 9 to dry <= supply data to the inside or outside of the integrated circuit 950. Peripheral interface _ transmission foot γ (four) and / or flat payment error using the two sequence disclosure = day m solution $ test ^ ^ on the preferred embodiment and illustration and not use: limit; into various modifications and combinations, And the embossing ^^^ and Lu' can easily reach the following range of the patent application scope; the mouth / Luo in the spirit of the invention [simple description of the figure] mr of the first integrated circuit The sequence peripheral interface is configured to 'have the main and servant schematic interface (spi) integrated circuit - read the clock to have a ~ residual period to compensate the delay of the servo circuit. Figure 3 is a read-sequence of the serial-sequence interface (SPI) integrated circuit. 13 200819997 The second intention of the integrated circuit is that it has more redundant jobs than the second one to compensate for the longer delay. Figure 4 is a sequence of peripheral interface diagrams that use a single pin to transmit data. Figure 5 of the road & pull-type flow is a sequence of peripheral interfaces (integrated power path diagram, which uses multiple feet to transmit data. Road & pull-type flow Rifeng rr first set 6 The picture shows a transmission of data in a sequence of peripheral interface (SPI) integrated circuits. It does not reflect the picture. It uses the township weight and double speed (DDR) to transmit data. Clock 咅7pTi=column peripheral interface_integrated A diagram of a transmitted data of a circuit that uses multiple feet and transmits data in double direction (DDR) only in the direction between the master and the servant. The Japanese Hr Dili 8 is a sequence of peripheral interfaces (SPI). The transmission data of the integrated circuit is not intended to use multiple pins and only one direction between the master and the servant. • Transmit data with double speed (DDR), especially in the opposite direction to Figure 7. 9 is a block diagram showing an example of a sequence peripheral interface (SPI) integrated circuit including a nonvolatile matrix, according to an embodiment of the present invention, [main element symbol description] main product circuit processor circuit chip selection Sequence clock master data input 110 100, 1〇1, 102 csa
SCKSCK
MSI 14 200819997 si so 10 900 901 902 903 904 905 907 906 908 909 911 915 950 僕資料輸入 僕資料輸出 輸入及輸出腳位 非揮發記憶陣列 列解碼器 字元線 行解碼器 位元線 匯流排 資料匯流排 感應放大器/貨料輸入結構 偏壓安排供應電壓 偏壓安排狀態機器 資料輸入線 資料輸出線 積體電路 15MSI 14 200819997 si so 10 900 901 902 903 904 905 907 906 908 909 911 915 950 servant data input servant data output input and output pin nonvolatile memory array column decoder word line line decoder bit line bus data sink Row sense amplifier / material input structure bias arrangement supply voltage bias arrangement state machine data input line data output line integrated circuit 15