200818927 九、發明說明： 【發明所屬之技術領域】 發明領域 本發明總的涉及顯示設備的領域，具體地，涉及用、 5在單個集成電路片上集成多個視頻功能的方法和系統。、 具體地，本發明涉及用於3D Y/c梳狀濾波器和交織〜 變換器的單片集成的方法和系統。 λ進 【先前击迴 發明背景 10 傳統的電視監視器通常呈現具有快速的視頻場的序列 的形式的視頻圖像，以高的頻率改變，建立運動的圖像， 電視攝像機和其他的視頻源通常不產生全幀圖像，而是這 樣的視頻源典型地以每秒60個這樣的場的速率（在交織t 統中），產生包含每個全幀圖像的約一半的行的場。另一個 15場包含視頻數據的另外的行。換句話說，一個場包含奇數 的行乂及下{固场包含偶數的行。因此，每個視頻的場可 被標識為“奇，’場或“偶，，場。 在通常的交織系統中，視頻場序列在奇場與偶場之間 父替。接收場序列的傳統的電視監視器順序地重現每個視 2〇頻場。每個視頻場僅僅以一半掃描線被顯示在電視屏幕 上例如，首先奇場通過使用奇數掃描線被顯示，然後， 偶场通過使用偶數場線被顯示，料。電視機從左上方到 右上方掃描屏幕的光柵，產生第-掃描線。然後把光柵返 回到屏幕的左邊緣到比原先位置稍微下面的位置。然而， 5 200818927 光柵返回到的位置並不緊接在第一掃描線 致广旬，而是允 然後 以及這樣地 但通常允 有足夠的空間來容納另一個場的交織的掃缺 光栅掃描到屏幕的右邊緣，產生第二掃描線，、二 繼續進行到屏幕的底部邊緣。 在掃描線之間的距離是監視器尺寸的函數，BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to the field of display devices, and more particularly to a method and system for integrating multiple video functions on a single integrated circuit chip. In particular, the present invention relates to a method and system for monolithic integration of a 3D Y/c comb filter and an interleaving-transformer. λ入[ Previously hit back to the background of the invention 10 Traditional TV monitors typically present video images in the form of sequences with fast video fields, changing at high frequencies, creating motion images, television cameras and other video sources usually Instead of producing a full frame image, such a video source typically produces a field containing about half of the lines of each full frame image at a rate of 60 such fields per second (in interlaced t). The other 15 fields contain additional lines of video data. In other words, a field contains odd rows and the next {solid field contains even rows. Thus, the field of each video can be identified as "odd," field or "even," field. In a typical interleaving system, the video field sequence is replaced by a parent field between the odd field and the even field. A conventional television monitor that receives the field sequence sequentially reproduces each of the video fields. Each video field is displayed on the television screen with only half of the scan lines. For example, the odd field is first displayed by using odd scan lines, and then the even field is displayed by using even field lines. The television scans the raster of the screen from the upper left to the upper right to generate a first scan line. The raster is then returned to the left edge of the screen to a position slightly below the original position. However, 5 200818927 The position at which the grating returns is not immediately adjacent to the first scan line, but allows the scan of the interlaced scan raster to the screen and then, but generally allows sufficient space to accommodate the other field. The right edge produces a second scan line, and the second continues to the bottom edge of the screen. The distance between the scan lines is a function of the size of the monitor.
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:在完成第-場後畫出插人的掃描__個 描線）。在掃描每個掃描線後光柵以不可看 、 ▼ 的左邊緣，是回掃或水平恢復階段，它比起可看= 二 =得快得多。在這_下，可以產== (f占優勢的美國視_格式），完成單個視頻 在母個％中顯不該幢的一半。 -旦達到屏幕的底部邊緣，光栅就在“垂直消隱間 』間，不可看見地返回到左上角原先的位置。水平和 :直消隱間隔階段是快速的和不可看見的。>於傳統的電 、種交織掃描方法是㈣直恢復速率，垂直分辨率， 與有限的帶寬之間的適當的折衷。 2〇間六而由傳統的1^系統使用的、用於在奇幢與偶候之 β、父替的方法’都知道具有各種缺點，諸如行閃烤，行 嘴動，點螺動，有限的水平分辨率，閃爍的偽彩色:、和大 ^的閃爍。各種各樣的技術被開發，諸如3D梳狀渡波， 漸進變換’和場速率上變換到雙倍場速率輪出，克 艮傳統的TV信號的這些缺點。然而，犯梳狀渡波器和交 200818927 織—漸進變換器（“IPC”）需要幾個場的存儲器。 θ八在通常的現有技術解決方案中，3 D梳狀滤波器和I p C =開的、集成電路芯片。因此，需要兩個分開的存儲器 麩（】如，DRAM) ’ 30梳狀濾波器和IPC每個一個芯片。 5 =而1用用於每個這些^件的分開的存儲㈣片，導致 冋的=統成本。而且，由於分開的元件數目增加，安裝它 要的物理空間也增加。因此，現有技術系統具有不 希差的高的製造成本和與它們有關的大的形式因子。 【聲明内容】 10 發明概要 所以’需要-種在單個1C芯片上集成3D Y/c梳狀滤波 2和交織-冑進變換器（或場速率上變換器）的方法和系統 結構，這樣，它們可共享單個幀緩存器（存儲器），因此減小 結構的形式因子和製造成本。 15 另外，進一步需要一種用於單片集成3D Y/C梳狀濾波 态和父織-漸進變換器的方法和系統，它可以提供與當前 存在的夕芯片解決方案相同的或更好的性能，而同時具有 小的形式因子和降低的製造成本。 按照本發明，提供了一種用於單片集成3D Y/C梳狀濾 2〇波器和交織-漸進變換器的方法和系統，它基本上消除或 減少與現有技術的、用於提供Y/c梳狀濾波和交織-漸進變 換的多芯片方法和系統有關的缺點和問題。 更具體地，本發明的一個實施例提供了單片集成結 構，結構包括用於接收和處理視頻信號的集成電路芯片， 7 200818927 其中集成⑽片包括梳狀據波器，交織一漸進變換哭， 和用於視頻信號與它的處理⑽件的通信的多個數據通 道。結構還可包㈣緩存器，用於存儲從視頻信號處理的 一個或多_ ’其中_存器可通信地連接到集成電路忠 5片。集成電路怒片還可包括存儲器控制器，用於協調從械 狀慮波器和從IPC_緩存器的讀和寫請求。替換地，存儲 器控制器可以是與集成電路芯片分開的元件，它可通信地 連接到集成電路怒片和幅緩存器。多個數據通道還可包括 在集成電路芯片内和在集成電路芯片外的、用於傳送信號 10到集成電路芯片的出腳和連接頭。 用於在單個1C芯片上集成3D Y/c梳狀濾波器和交織— 漸進全換為的方法和系統結構的技術優點在於，它們可共 享單個幢緩存器，因此減小結構的形式因子和製造成本。 用於單片集成3D Y/C梳狀濾波器和交織-漸進變換器 15 的方法和系統的另一個技術優點在於，它們可以提供與當 前存在的多芯片解決方案相同的或更好的性能，而同時具 有小的形式因子和降低的製造成本。 圖式簡單說明 當結合附圖參考以下的說明時，可以更全面地理解本 20 發明及其優點，其中相同的參考數字表示相同的特性，以 及其中： 第1圖是提供梳狀濾波、交織-漸進變換和幀緩存的現 有技術多芯片結構的方框圖。 第2圖是本發明的單片集成系統的實施例的簡化方框圖。 200818927 【實方式】 較佳實施例之詳細說明 圖上顯示本發明的優選實施例，所使用的相同的數字 是指各個圖上的相同的和相應的部件。 5 本發明包括在單個芯片上集成3D Y/C梳狀濾波器和交 織-漸進變換器（或替換地，場速率上變換器）的電路結構的 各種實施例’這樣，它們可共享單個幀緩存器。本發明的 實施例因此提供更緊凑的形式因子的優點，它在電路板上 佔用較少的空間’以及提供降低的製造成本，而不用相對 10於現有技術方法和系統折衷性能。不像現有技術解決方案 需要多個分開的芯片塊那樣；本發明只需要單個幀緩存器 芯片，可通信地連接到集成3D Y/C梳狀濾波器和IPC的單個 芯片。 第1圖是包括兩個分開的IC芯片60和65的現有技術多 15芯片結構10的方框圖。1C芯片60包括用於執行γ/c分離的 3D梳狀濾波器20,和存儲器控制器3〇。1(：：芯片65包括交織— 漸進變換器25和第二存儲器控制器3〇。替換地，交織—漸 進變換器25可替代地包括場速率上變換器。交織—漸進變 換器作為輸出信號提供同時積累的圖像信息，然後逐行地 2〇或順序地輸出，而不是以交織的方式輸出。結果是在單個 快速的快η過程中獲取的、具有全垂直和水平分辨率的非 交織的圖像。 結構10也可包括㈣存器i5。如第！圖所示，現有技術 結構10需要用於每個集成電路芯片6〇和65的一個幢緩存器 9 200818927 Μ。賴她5存儲視頻嶋貞，以便由扣梳狀滤波器2〇 和IPC 25處S存儲|g控制器3〇(每個悄緩存器—健制器） 協調在3D梳狀據波器2〇和賴存器15之間以及在㈣25和 賴存器15之間的讀/寫請求。幢緩存器啊以是對於本領 5域技術人員已知的，何適#的存儲器媒體，諸如dram。 而且，中貞缓存器15可以包括不同的尺寸的幅緩存器，取決 於特定的應用。幢緩存器15還可包括多個存儲器芯片，滿 足特定的應用的存儲器需要。 3D梳狀濾波器20取復合視頻信號5〇作為輸入。復合視 W頻信號50可以是NTSC信號，PAU言號，或對於本領域技術 人員已知的任何其他的這樣的信號。刪以持國家電視標 準委員會’以及規定具有每秒60個半幀的（交織的）恢復速率 的復合視頻信號。每個幀包含525行，以及可包含16百萬不 同的顏色。信號50也可以是用於高清晰度電視的信號，它 15比起基於1^1^(：：標準的當前的電視標準，可以提供好得多的 分辨率。PAL支持相位交替行，歐洲的占優勢的電視標準。 雖然NTSC以每秒60個半幀傳遞525行的分辨率，但PAL以 每秒50個半幀傳遞625行。這些技術條件在技術上是熟知 的。 20 3D梳狀濾波器2〇接收復合視頻信號50，以及把復合視 頻^號50分離成它的分量信號(如下面討論的）。有不同的類 型的梳狀濾波器，以及它們在性能上是非常不同的。為了 本專利申請，說明將集中在3D梳狀濾波器技術上。 復合視頻信號50包括發光度（亮度）信號和色度（彩色） 200818927 信號。在視頻術語中，它們常常分別被稱為Y和c信號。c 信號是兩個其他的中間信號（諸如在YIQ信號中的I和Q信 號，以及在YcbCr信號中的Cb和Cr信號）的專門的調製的組 合。這些附加的色度信號是從視頻攝像機的原先的紅、綠 5 和藍（“RGB”）輸出產生的。每個彩色空間模型（例如， YIQ，YCbCr，和YUV)使用亮度值來表示基本的黑和白圖 像信息。每個模型也使用兩個色度值來描繪彩色信息，雖 然它們每個在如何規定色度值方面是不同的。不同的彩色 空間模型和它們的運行對於本領域技術人員是熟知的。視 10 頻處理設備，諸如電視監視器，必須採用Y/C分離的某個形 式’從復合視頻信號(例如，復合視頻信號50)中恢復γ和c 信號信息。: Draw a scan of the inserted __ after the completion of the first field. After scanning each scan line, the raster is invisible, the left edge of ▼, is the retrace or horizontal recovery phase, which is much faster than the visible = two =. Under this _, you can produce == (f dominant US _ format), complete a single video in the parent % is not half of the building. Once the bottom edge of the screen is reached, the raster is in the "vertical blanking interval" and returns invisibly to the original position in the upper left corner. Horizontal sum: the straight blanking interval phase is fast and invisible. The electrical and interlaced scanning method is a suitable compromise between (4) direct recovery rate, vertical resolution, and limited bandwidth. 2 〇 而 而 由 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统 传统The method of β and parental replacement is known to have various disadvantages such as line flashing, mouth movement, point screwing, limited horizontal resolution, flashing pseudo color:, and large ^ flicker. Various techniques Developed, such as 3D comb-like wave, progressive transform' and field rate up-conversion to double field rate turn-off, these disadvantages of traditional TV signals. However, the comb-like waver and the 200818927 weaving-progressive converter ("IPC") requires several fields of memory. θ8 In a typical prior art solution, a 3 D comb filter and an I p C = open, integrated circuit chip. Therefore, two separate memory braces are required (], for example, DRAM) '30 comb filter and IPC each one chip. 5 = and 1 with separate storage (four) for each of these pieces, resulting in a 冋 = system cost. Moreover, due to the increased number of separate components, install it The physical space required is also increased. Therefore, the prior art systems have high manufacturing costs and large form factors associated with them. [Declaration] 10 Summary of Invention So 'required--integrating 3D on a single 1C chip Method and system architecture for Y/c comb filtering 2 and interleaving-inverting converters (or field rate upconverters) such that they can share a single frame buffer (memory), thus reducing the form factor and manufacturing of the structure Cost. 15 In addition, there is a further need for a method and system for monolithically integrating 3D Y/C comb filter states and parent-pig-forward converters that can provide the same or better results than currently existing chip solutions. Performance, while having a small form factor and reduced manufacturing cost. According to the present invention, a method for monolithically integrating a 3D Y/C comb filter 2 chopper and an interleaving-progressive converter is provided A system that substantially eliminates or reduces the disadvantages and problems associated with prior art multi-chip methods and systems for providing Y/c comb filtering and interleaving-incremental transformation. More specifically, one embodiment of the present invention provides A monolithic integrated structure comprising an integrated circuit chip for receiving and processing video signals, 7 200818927 wherein the integrated (10) slice comprises a comb-like data tract, interleaved with a progressive transform crying, and used for video signals and its processing (10) pieces Multiple data channels for communication. The structure may also include (four) buffers for storing one or more of the video signal processing _ 'where the memory is communicably connected to the integrated circuit loyalty 5. The integrated circuit anger may also A memory controller is included for coordinating read and write requests from the mechanical filter and from the IPC_buffer. Alternatively, the memory controller can be a separate component from the integrated circuit chip that is communicatively coupled to the integrated circuit rake and amplitude buffer. The plurality of data channels can also include pins and connectors for transmitting signals 10 to the integrated circuit chips within the integrated circuit chip and outside of the integrated circuit chip. The technical advantage of a method and system architecture for integrating 3D Y/c comb filters and interleaving-asymptotically all-in-one on a single 1C chip is that they can share a single building buffer, thus reducing the form factor and manufacturing of the structure cost. Another technical advantage of the methods and systems for monolithically integrating 3D Y/C comb filters and interleaved-forward converters 15 is that they can provide the same or better performance than currently existing multi-chip solutions. At the same time, it has a small form factor and reduced manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS The present invention and its advantages will be more fully understood from the following description taken in conjunction with the accompanying drawings in which <RTIgt; A block diagram of a prior art multi-chip architecture for progressive transform and frame buffering. Figure 2 is a simplified block diagram of an embodiment of the monolithic integrated system of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) The preferred embodiments of the present invention are shown in the drawings, and the same numerals are used to refer to the same and corresponding parts in the various figures. 5 The present invention includes various embodiments of a circuit structure that integrates a 3D Y/C comb filter and an interleaved-forward converter (or alternatively, a field rate upconverter) on a single chip, such that they share a single frame buffer Device. Embodiments of the present invention thus provide the advantage of a more compact form factor that occupies less space on the board' and provides reduced manufacturing cost without compromising performance relative to prior art methods and systems. Unlike prior art solutions requiring multiple separate chips; the present invention requires only a single frame buffer chip that is communicatively coupled to a single chip that integrates a 3D Y/C comb filter and IPC. Figure 1 is a block diagram of a prior art multi-15 chip structure 10 including two separate IC chips 60 and 65. The 1C chip 60 includes a 3D comb filter 20 for performing γ/c separation, and a memory controller 3A. 1 (:: chip 65 includes interleaving - progressive converter 25 and second memory controller 3 〇. Alternatively, interleaving - progressive converter 25 may alternatively include a field rate upconverter. Interleaving - progressive converter is provided as an output signal The image information accumulated at the same time is then outputted line by line or sequentially, rather than in an interleaved manner. The result is a non-interlaced with full vertical and horizontal resolution acquired in a single fast fast η process. The structure 10 may also include (4) a memory i5. As shown in the figure!, the prior art structure 10 requires a building buffer 9 200818927 for each integrated circuit chip 6 〇 and 65.嶋贞, so that the button comb filter 2〇 and the IPC 25 at the S store |g controller 3〇 (each sneak buffer-health) are coordinated in the 3D comb filter 2〇 and the keeper 15 Read/write requests between and between (4) 25 and the memory device 15. The building buffer is known to those skilled in the art of the field 5, He Shi #'s memory media, such as dram. Moreover, the median buffer 15 can include different sizes of the amplitude buffer Depending on the particular application, the building buffer 15 may also include a plurality of memory chips to meet the memory needs of a particular application. The 3D comb filter 20 takes the composite video signal 5〇 as an input. The composite video W-frequency signal 50 may be NTSC. Signal, PAU number, or any other such signal known to those skilled in the art. Deleted by the National Television Standards Committee' and a composite video signal with an (interleaved) recovery rate of 60 fields per second. Each frame contains 525 lines and can contain 16 million different colors. Signal 50 can also be a signal for high definition television, which is 15 compared to the current TV standard based on 1^1^(:: standard Can provide much better resolution. PAL supports phase alternate lines, Europe's dominant TV standard. Although NTSC delivers 525 lines of resolution at 60 frames per second, PAL is delivered at 50 frames per second. Line 625. These technical conditions are well known in the art. 20 3D comb filter 2 〇 receives composite video signal 50, and separates composite video ^ 50 into its component signals (as discussed below) There are different types of comb filters, and they are very different in performance. For the purposes of this patent application, the description will focus on the 3D comb filter technique. The composite video signal 50 includes a luminosity (brightness) signal and Chromaticity (color) 200818927 Signals. In video terminology, they are often referred to as Y and C signals, respectively. The c signal is two other intermediate signals (such as the I and Q signals in the YIQ signal, and in the YcbCr signal). A combination of specialized modulations of the Cb and Cr signals. These additional chrominance signals are generated from the video's original red, green 5, and blue ("RGB") outputs. Each color space model (eg, YIQ) , YCbCr, and YUV) use luminance values to represent basic black and white image information. Each model also uses two chrominance values to depict color information, although each differs in how the chromaticity values are specified. Different color space models and their operation are well known to those skilled in the art. Depending on the frequency processing device, such as a television monitor, the gamma and c signal information must be recovered from the composite video signal (e.g., composite video signal 50) in some form of Y/C separation.
現在回到第1圖，3D梳狀濾波器20可以是正如技術上已 知的、3D運動自適應Y/C分離濾波器。3D梳狀濾波器20因 15 此可以處理從接連的視頻幀取得的相同的掃描線（幀間的 梳狀濾波），與場内梳狀濾波相反，它涉及處理單個視頻場 内接連的掃描線。來自兩個接連的幀的相同的掃描線被饋 送到3D梳狀濾波器内的基本數字行梳狀濾波器。如果圖像 在帕之間在同一個位置上是靜止的，則幀間梳狀濾波器可 20以完美地分離Y*C信息。如果在幀之間有圖像運動或彩色 改變’則在接連的幀中的相應的行將具有不同的γ/C内容。 在這樣的情形下，幀内梳狀濾波器產生錯誤信號信息。所 以，3D Y/C分離濾波器必須是運動自適應的，以及僅僅在 不存在運動時選擇幀内梳狀濾波。所以，3D運動自適應Y/C 11 200818927 分離梳狀濾波諸在地關對靜止圖像進行接近完美的 γ/c分離。 70 ' 3D梳狀遽波器20把分離的信號轉發到以片65 内的IPC 25。頓-漸進變換㈣取得交織的丫和匚信號， 5以及把它們變換成漸進的（也稱為非交織的或順序的）信號 75，它被輸出到顯示器。漸進信號乃與漸進掃描有關，漸 進掃描是在顯示器上以與交織信號相同的方式畫出圖像掃 描線的-種方法，但代替把視頻幢分離成兩個場，一個包 含奇數號的掃描線以及另一個包含偶數掃描線，完全的核 10在一個過程中從底部掃描到底部。IPC 25因此把交織的信 號變換成非交織的信號，它可以以漸進的顯示被輸出，而 沒有假像。從IPC 25輸出的漸進信號75可以是對於顯示監 視器的適當的格式(諸如NTSC或PAL)的信號。 第2圖是本發明的用於在單個芯片上集成3〇 y/c梳狀 15濾波斋和IpC塊的方法和系統的實施例的方框圖。第2圖的 結構100包括單個集成電路芯片11〇和幀緩存器8〇。集成電 路芯片110包括3D梳狀濾波器2〇(它可以是運動自適應γ/c 分離梳狀濾波器或本領域技術人員已知的其他梳狀濾波 器），IPC 25和共享的存儲器控制器7〇。ipc 25可以是運動 20和邊緣自適應交織-漸進變換器。替換地，IPC 25可以代 之以包括場速率上變換器。 3D梳狀濾波器20和IPC 25結構1〇〇都由共享的存儲器 控制器70提供服務。共享的存儲器控制器70可以協調來自 3D Y/C梳狀濾波器20和IPC25的讀和寫請求，以使得幀緩存 12 200818927 盗8〇能夠被二者使用。共享的存儲器控制器7〇可以是 私路〜片110的集成的元件，或它可以是分離的元件，可通 信地連接到集成電路芯片_喝緩存器8〇。幢缓存器8〇可 以是對於特定的應用所需要的、任意尺寸的親存器，以 及y以包括-個或多個⑽施芯片，或可以是本領域技術 人員已知的任何其他存儲器器件。 第2圖的單個芯片結構還可包括（雖然在第2圖 上未示 出）按本領域技術人員已知的方式，在單個集成電路芯片的 1〇兀件之間和/或在外部元件之間的出聊和連接頭 。出腳和連Returning now to Figure 1, the 3D comb filter 20 can be a 3D motion adaptive Y/C separation filter as is known in the art. The 3D comb filter 20 can handle the same scan lines (comb filtering between frames) taken from successive video frames, as opposed to intra-field comb filtering, which involves processing successive scan lines within a single video field. The same scan line from two consecutive frames is fed to the basic digital line comb filter in the 3D comb filter. If the image is stationary at the same position between the cells, the inter-frame comb filter 20 can perfectly separate the Y*C information. If there is image motion or color change between frames, then the corresponding lines in successive frames will have different gamma/C content. In such a case, the intra comb filter generates error signal information. Therefore, the 3D Y/C separation filter must be motion adaptive and only select intra comb filtering when there is no motion. Therefore, the 3D motion adaptive Y/C 11 200818927 split comb filter performs near-perfect γ/c separation on the still image. The 70' 3D comb chopper 20 forwards the separated signal to the IPC 25 in the slice 65. The ton-forward transform (4) takes the interleaved 丫 and 匚 signals, 5 and transforms them into progressive (also called non-interlaced or sequential) signals 75, which are output to the display. Progressive signals are related to progressive scanning, which is a method of drawing an image scan line on the display in the same way as an interlaced signal, but instead of separating the video block into two fields, an odd-numbered scan line And the other contains an even scan line, and the complete core 10 is scanned from the bottom to the bottom in one process. The IPC 25 thus transforms the interleaved signal into a non-interlaced signal which can be output in a progressive display without artifacts. The progressive signal 75 output from the IPC 25 may be a signal for a suitable format (such as NTSC or PAL) for the display monitor. Figure 2 is a block diagram of an embodiment of the method and system of the present invention for integrating a 3 〇 y / c comb 15 filter and IpC block on a single chip. The structure 100 of Figure 2 includes a single integrated circuit chip 11 and a frame buffer 8A. Integrated circuit chip 110 includes a 3D comb filter 2 (which may be a motion adaptive gamma/c split comb filter or other comb filter known to those skilled in the art), IPC 25 and a shared memory controller 7〇. Ipc 25 can be motion 20 and edge adaptive interleaving-progressive converters. Alternatively, IPC 25 may instead include a field rate upconverter. Both the 3D comb filter 20 and the IPC 25 structure 1 are served by a shared memory controller 70. The shared memory controller 70 can coordinate read and write requests from the 3D Y/C comb filter 20 and IPC 25 to enable the frame buffer 12 200818927 to be used by both. The shared memory controller 7 can be an integrated component of the private path to slice 110, or it can be a separate component that can be communicatively coupled to the integrated circuit chip _ drink buffer 8 〇. The building buffer 8 can be any size of the memory required for a particular application, and y can include one or more (10) chips, or can be any other memory device known to those skilled in the art. The single chip structure of Fig. 2 may also include (although not shown in Fig. 2) between one component of a single integrated circuit chip and/or external components in a manner known to those skilled in the art. Talk and connect. Out foot and even
妾頭可按特疋的應用所需要地被配置。梳狀濾、波器2〇， 多知第1圖描述的，取復合視頻信號50作為輸入。由3D k狀濾、波H2G被轉發到IPC 25的¥和。信號在第2圖上未顯 示出。 15 本發明的實施例可包括如第2圖所示的系統，以及也可 15包括用於共享在梳狀濾波器20和〇^ 25之間的單個幀缓存 态80的方法。方法可包括在集成電路芯片ιι〇上町通信地連 接，用於接收和處理視頻信號，諸如復合視頻信號50，3D k狀濾波器20，IPC 25，以及_個或多個數據通道，用於 視頻信號和它的處理的分量的通信。方法還可包拮把幀缓 2〇存器80可通信地連接到集成電路芯片11()。 本發明的方法和系統的實施例提供減小的形式因子和 減】、的製造成本的優點’而同時保持性能可以與當前的現 有的解決方案相比較的或更好的。減小的形式因子（滅小的 尺寸）可以允許引用本發明的實施例的設備的尺寸要求上 13 200818927 的減小。同樣地，本發明的實施例可以提供與現有技術的 一重幀緩存為需求有關的成本的節省。 本發明的方法和系統的實施例可包括這樣的實施例， 其中魏存器80包括一個以上的可供使用的存儲器器件， 5可通信地連接到用於3D梳狀濾波器20和IPC 25的存儲器控 制器70。在這樣的實施例中，存儲器控制器％可控制(調停) 從3D梳狀濾波器2〇和從lpc 25到幀緩存器8〇的讀/寫請 求以便確疋對於給定的讀/寫請求接入那個存儲器器件。 在多存儲器器件鴨緩存器8〇實施例中，存儲器控制器顺 1〇可控㈣緩存器80的那個存儲器器]牛由3D梳狀據波器斯口 IPC 25接入。這樣，存儲器控制器7〇可以路由來自3^梳狀 濾波器20和IPC 25的請求，以使得速度和效率最大化。 幀緩存器80可以具有對於應用所需要的任何存儲器尺 寸，但典型地對於3D運動自適應γ/c分離，幀緩存器8〇必 15須具有對於以由實施本發明的應用所使用的格式保持從視 頻信號50處理的至少兩個視頻幀所足夠的尺寸。幀緩存器 80被使用來存儲視頻幀，用於平均和運動檢測。例如，對 於NTSC格式，一個幀約為720,480像素。對於72〇,48〇像素 的NTSC幀，幀緩存器80必須包括四個丨兆字節乘以16比特 20 DRAM芯片來存儲64比特的幀。替換地，可以使用兩個“匕 字節乘以32比特芯片。然而，這些存儲器需求在技術上是 熟知的，以及可以不用過度的實驗而被實施。對於幀緩存 器80的尺寸需求因此可以容易地對於特定的應用被確定。 本發明的方法和系統的實施例可以作為高清晰度 200818927 r事」或渐進的掃插電視的視頻處理系統的一部分被實 本i明的方法和系統的實施例可以作為具有 IPC變換器和31)栌妝 、 , 爪狀慮波器的任何顯示系統的視頻處理糸 統的一部分被實施。 5 雖然本發明在這裡是參照說明性實施例被詳細地描述The hoe can be configured as needed for the application. Comb filter, wave 2 〇, as described in the first figure, take the composite video signal 50 as input. It is forwarded to the ¥ and IPC 25 by the 3D k-shaped filter and the wave H2G. The signal is not shown on Figure 2. Embodiments of the invention may include a system as shown in Fig. 2, and may also include a method for sharing a single frame buffer 80 between comb filters 20 and 2525. The method can include communicatively connecting at an integrated circuit chip 〇 , for receiving and processing video signals, such as composite video signal 50, 3D k-like filter 20, IPC 25, and _ or more data channels for video The communication of the signal and its processed components. The method can also provide for the frame buffer 80 to be communicatively coupled to the integrated circuit chip 11(). Embodiments of the method and system of the present invention provide the advantages of reduced form factor and manufacturing cost while maintaining performance while being comparable or better than current existing solutions. The reduced form factor (too small size) may allow for a reduction in the size requirements of the apparatus referenced to embodiments of the present invention on 13 200818927. As such, embodiments of the present invention can provide cost savings associated with prior art one-frame buffering. Embodiments of the method and system of the present invention may include embodiments in which the cache 80 includes more than one memory device available for use, 5 communicatively coupled to memory control for the 3D comb filter 20 and IPC 25. 70. In such an embodiment, the memory controller % can control (mediate) read/write requests from the 3D comb filter 2 〇 and from the lpc 25 to the frame buffer 8 以便 to confirm the request for a given read/write. Access that memory device. In the multi-memory device duck buffer 8 embodiment, the memory controller is compliant with the memory of the (4) buffer 80. The cow is accessed by the 3D comb-like data port IPC 25. Thus, the memory controller 7 can route requests from the 3 comb filter 20 and the IPC 25 to maximize speed and efficiency. Frame buffer 80 may have any memory size required for the application, but typically for 3D motion adaptive gamma/c separation, frame buffer 8 must have a format maintained for use by the application embodying the present invention. At least two video frames processed from video signal 50 are of sufficient size. Frame buffer 80 is used to store video frames for averaging and motion detection. For example, for the NTSC format, one frame is approximately 720,480 pixels. For a 72 〇, 48 〇 pixel NTSC frame, frame buffer 80 must include four megabytes by 16 bits of 20 DRAM chips to store 64 bit frames. Alternatively, two "匕 bytes can be used multiplied by a 32-bit chip. However, these memory requirements are well known in the art and can be implemented without undue experimentation. The size requirements for the frame buffer 80 can therefore be easily The method is determined for a particular application. Embodiments of the method and system of the present invention can be implemented as part of a high definition 200818927 r or a progressive video processing system for sweeping television. An example can be implemented as part of a video processing system for any display system having an IPC transducer and 31) makeup, claw-shaped filter. 5 Although the invention is described in detail herein with reference to illustrative embodiments
的應田看到，說明僅僅是作為例子的，以及不打算把它 作為限制的意義。所以，還應當看到，本發明的實施例的 細即的多個改變和本發明的附加實施例對於號參照本說明 的本頊域技術人員將是顯而易見的，或可能由他們作出 10的。所有這樣的改變和附加實施例打算屬於如下面申請專 利範圍主張的、本發明的精神和真王的範圍内。 【圖式簡琴^ 明】 苐1圖是提供梳狀濾波、交織-漸進變換和幀緩存的現 有技術多芯片結構的方框圖。 15 第2圖是本發明的單片集成系統的實施例的簡化方框 圖。 【主要元件符號說明】 60，片 75…漸進信號 110…雜成電路芯片 15，80…浪緩存器 20…3D梳狀濾波器 25…交織·漸進變換器 30，70···存儲器控制器 50…復合視頻信號 15Ying Tian sees that the description is only an example and that it is not intended to be a limiting meaning. Therefore, it should be understood that the various modifications of the embodiments of the invention and the embodiments of the invention may be All such changes and additional embodiments are intended to be within the scope of the spirit and scope of the invention as claimed. [Picture] The 苐1 diagram is a block diagram of a prior art multi-chip architecture that provides comb filtering, interleaving-incremental transformation, and frame buffering. 15 Figure 2 is a simplified block diagram of an embodiment of the monolithic integrated system of the present invention. [Description of main component symbols] 60, slice 75... progressive signal 110... hybrid circuit chip 15, 80... wave buffer 20... 3D comb filter 25... interleaved/incremental converter 30, 70... memory controller 50 ...composite video signal 15