JPH11136592A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor which can omit a memory of large capacity even while performing the satisfactory processing of both image and caption signals and can inexpensively consist of a single LSI without increasing the substrate area. SOLUTION: This image processor is provided with a signal extraction means 118 which extracts in real time the image signals and their corresponding caption signals from the input video signals VC including those image and caption signals, a video signal processing means 119 which sets the magnification of the extracted image signals, a caption signal storage means 110 which stores the extracted caption signals, and a caption signal control means which puts the caption signals read out of the means 110 into the image signals processed toy the means 119 and outputs the display video signals VO to a display device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus applicable to a popular type of vertically enlarged display apparatus in which a screen is enlarged by vertical deflection processing.

[0002]

2. Description of the Related Art For example, when an image based on a video signal having an aspect ratio of 4: 3 of the current television system is displayed as it is on a wide display screen having an aspect ratio of 16: 9, the image has a distorted and distorted shape. For this reason,
Prior to display, it is necessary to convert an image signal having an aspect ratio of 4: 3 into an aspect ratio corresponding to a screen having an aspect ratio of 16: 9.

[0003] An image display system for switching the enlargement ratio of a video signal is described in Japanese Patent Application Laid-Open No. 4-192694. In the image display system described in this publication, a video signal having an aspect ratio of 4: 3 of the current television system is temporarily stored in a memory, and the number of scanning lines of an effective screen is detected from the video signal read from the memory. Further, an enlargement magnification is calculated from the number of scanning lines,
The conversion of the number of scanning lines is controlled based on the calculated enlargement magnification to convert the aspect ratio.

In the conventional image display system described in the above publication, for example, when a video signal includes a caption signal in addition to an image signal, the caption may be enlarged together with the image, protrude from the screen, and may not be displayed. In order to solve such inconveniences, the input video signal is temporarily stored in a memory, the subtitle signal and the image signal are temporarily separated from the input video signal, and the enlargement ratio of the image signal is changed. There is an image processing device that inserts a caption signal again into an image signal and outputs the image signal.

[0005]

In the above-mentioned conventional image processing apparatus, after an input video signal including an image signal and a subtitle signal is stored in a memory, the image signal processing and the subtitle signal are separated and processed separately. A screen frame memory or the like having a large storage capacity is required. For this reason, for example, it has been difficult to meet the demand for miniaturizing the image processing apparatus by configuring the image processing apparatus from one LSI (large-scale integrated circuit).

SUMMARY OF THE INVENTION In view of the above, the present invention realizes a low-cost LSI without performing a large-capacity memory without increasing the substrate area, while sufficiently performing signal processing on image signals and subtitle signals. It is an object to provide a possible image processing device.

[0007]

In order to achieve the above object, an image processing apparatus according to the present invention converts an input video signal including an image signal and a subtitle signal into an image signal and a subtitle signal corresponding to the image signal in real time. Signal extraction means for extracting with
An image signal processing unit for setting an enlargement ratio of the extracted image signal; a subtitle signal storage unit for storing the extracted subtitle signal; and an image signal processed by the image signal processing unit, wherein the subtitle signal storage unit Insert the read subtitle signal,
Subtitle signal control means for outputting to the display device as a display video signal.

According to the image processing apparatus of the present invention, an image signal extracted in real time from an input video signal and a subtitle signal corresponding to the image signal are processed, and the image signal and the video signal are subjected to subtitle signal control. It can be output as a display video signal by means. Therefore, a caption can be inserted and displayed at an appropriate position with respect to the separately enlarged image, so that a problem that the caption protrudes from the screen and is not displayed can be avoided. In addition, since the caption signal storage means can be composed of a memory having a small storage capacity enough to store the caption signal, the area of the substrate does not increase. Therefore, it is possible to configure the image processing apparatus from one small and inexpensive LSI.

Here, the subtitle signal control means may include a subtitle position control means for separating a horizontal synchronizing signal and a vertical synchronizing signal from the input video signal and specifying a subtitle writing position from the horizontal synchronizing signal and the vertical synchronizing signal. preferable. In this case, it is possible to specify the caption writing area by the control means having a simple circuit configuration.

[0010] More preferably, the caption signal control means includes caption compression means for displaying the caption based on the caption signal in a state where the caption is compressed in the horizontal direction of the screen of the display device. In this case, the image and the compressed subtitle can be viewed at the same time, and the area of the screen hidden by the subtitle is reduced, so that the screen is easy to see.

It is preferable that the subtitle signal control means has a function of inserting character data indicating the presence of subtitle display into an image signal and outputting it. In this case, by seeing the character displayed on the screen, for example, the presence of subtitles can be recognized, so that subtitles can be displayed as required by a predetermined operation.

Preferably, the subtitle signal control means stores the character data of the symbol character to be inserted into the image signal.
M. In this case, character data can be easily changed only by replacing the ROM.

[0013] The subtitle signal control means displays the screen of the display device,
It is also a preferable embodiment to include a cursor display unit for displaying a cursor indicating a subtitle writing range. In this case, the cursor can be conveniently used as an index at the time of setting which part of the caption signal is to be written in the memory and where the caption is displayed on the image.

[0014]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention. The image processing apparatus includes a clamp circuit 102, an image signal extraction circuit 118, a screen enlargement ratio setting circuit 119, a synchronization separation circuit 103, a horizontal synchronization clock generation circuit 104, and a write control HD counter 1.
05, a read control HD counter 106, an interlace correction circuit 107, a read horizontal compression circuit 108, a read horizontal position control circuit 109, a RAM 110, a subtitle signal quantization circuit 111, a subtitle signal insertion circuit 112, and a system control circuit 113.

The clamp circuit 102 has a function of fixing the amplitude tip or pedestal level of the synchronization signal of the input video signal VI from the video signal input terminal 101 to a constant DC voltage level, and outputting the input video signal VC. The input video signal VI (VC) includes an image signal and a caption signal. FIG. 2 is a time chart showing the relationship between the clamp level and each slice level.

FIG. 2A shows the sync separation slice level used in the sync separation circuit 103 and the subtitle signal for the input video signal VC whose sync signal tip level is fixed to a constant DC level by the clamp circuit 102. Quantization circuit 11
1 shows the relationship with the subtitle signal detection level LT used in FIG. FIG. 2B shows a sync signal separated from the input video signal VC by a sync signal slice level, and FIG. 2C shows a caption signal (character signal) detected from the input video signal VC by a caption signal detection level LT. Is shown. FIG. 2D shows the relationship between the caption signal insertion level LI used in the caption signal insertion circuit 112 and the synchronous leading edge clamp level. The caption signal insertion level LI and the caption signal detection level LT are both set by the system control circuit 113.

The image signal extracting circuit 118 constitutes a signal extracting means for extracting an image signal from an input video signal VC including an image signal and a caption signal in real time based on a control signal from the system control circuit 113. The screen enlargement ratio setting circuit 119 is for setting the enlargement ratio of the image signal extracted by the image signal extraction circuit 118. Is calculated, and the conversion ratio of the number of scanning lines is controlled based on the calculated magnification ratio to convert the aspect ratio.

The synchronization separation circuit 103 receives the input video signal VC
And outputs a horizontal synchronizing signal HD and a vertical synchronizing signal VD. The horizontal synchronization signal HD serves as a reference signal for the horizontal synchronization clock generation circuit 104. The vertical synchronizing signal VD and the horizontal synchronizing signal HD become count operation signals when input to the write control HD counter 105 and read control HD counter 106, and determine the field of the video signal when input to the interlace correction circuit 107. Signal.

The horizontal synchronizing clock generation circuit 104 generates a horizontal synchronizing signal HD (fck) synchronized with the horizontal synchronizing signal HD, and an integral multiple of this horizontal synchronizing signal HD (2 in this embodiment).
The clock signal 2fck having a frequency of 2) is output. this is,
This is because, in addition to using fck as the read clock signal, horizontal compression of the caption signal is also possible. The horizontal synchronization clock generation circuit 104 also outputs a write clock signal to the RAM 110. The write clock signal can be generated as a signal having a frequency different from fck by a phase lock loop described later.

FIG. 3 shows a horizontal synchronization clock generation circuit 104.
FIG. 3 is a block diagram showing an example of the configuration of FIG. The horizontal synchronization clock generation circuit 104 includes a phase comparison / previous value holding circuit 40,
An integrating circuit 41, a voltage controlled oscillator 42, and a frequency divider 43;
Phase lock loop (Phase Lock Loop)
Loop: PLL) generates clock signals 2fck and fck synchronized with the horizontal synchronization signal HD. Clock signal 2fc
The frequency of k is the product of the frequency f _HD of the horizontal synchronization signal HD and the frequency dividers 43 and 45. Here, the clock signal is NT
For an SC signal or the like, a clock (burst lock) synchronized with a color burst may be used. However, when a signal including jitter (time-axis fluctuation) such as a reproduction signal of a home VTR is also input, the horizontal fluctuation due to the jitter is conspicuous and the subtitles are difficult to see. It is desirable to use a synchronized clock (line lock).

The write control HD counter 105 receives the horizontal synchronization signal HD and the vertical synchronization signal VD, is reset by the vertical synchronization signal VD, and counts the horizontal synchronization signal HD. The counter 105 further includes the system control circuit 1
13 and input the position setting data PW0 and PW1 respectively, and change the vertical write start pulse WVS and the horizontal write start pulse WHS to RA.
M110, and outputs the subtitle writing position cursor signal WE to the subtitle signal insertion circuit 112. The writing position cursor signal WE indicates the position at which the writing of the subtitle signal is started, and is inserted into the video signal during the operation of setting the subtitle writing position by the system control circuit 113.

FIG. 4 is a time chart showing signals processed by the write control HD counter 105. In the same figure
(a) is an input video signal including an image signal and a subtitle signal, (b)
Indicates a vertical synchronizing signal VD, and (c) indicates a horizontal synchronizing signal HD.
The write control HD counter 105 inputs the vertical synchronizing signal VD and the horizontal synchronizing signal HD of (b) and (c) to the input video signal of (a), and thereby, A vertical writing start pulse WVS, a horizontal writing start pulse WHS, and a subtitle writing position cursor signal WE are respectively generated.

The vertical write start pulse WVS of 4 (d) specifies the upper end of the pulse amplitude of the caption signal to be written, and the output timing is set by the position setting data PW0. The horizontal write start pulse WHS in FIG. 9E designates the left end of the screen of each line (scanning line) of the subtitle signal to be written. The output timing is set by the position setting data PW0, and the stop timing is set by the position setting data PW0. Set by the setting data PW1. The subtitle writing position cursor signal WE of FIG.
Is output during the writing period of the caption signal,
It is not necessary to output the sync signal even during the output period,
The output line corresponds to the line from which the horizontal write start pulse WHS is output.

The read control HD counter 106 inputs the horizontal synchronizing signal HD, the vertical synchronizing signal VD, and the count correction signal HS from the interlace correction circuit 107, respectively.
It is reset by the vertical synchronizing signal VD and counts the horizontal synchronizing signal HD. The read control HD counter 106 further receives the position setting data PR from the system control circuit 113.
0, PR1 is input, and read start pulse RV is read into RAM 110.
S: Output a horizontal read control pulse RHD to the read horizontal position control circuit 109, and output a read position cursor signal RE to the caption signal insertion circuit 112. The read position cursor signal RE indicates a subtitle insertion position.
It is inserted into the video signal during the operation of setting the subtitle reading position by the system control circuit 113. In addition, the read control HD counter 106 outputs the read control pulse RHD and the read position cursor signal RE with a delay of one line, and prevents a decrease in vertical resolution due to the reverse of the field of writing and reading of the subtitle signal.

FIG. 5 is a time chart showing signals processed by the read control HD counter 106. In the same figure
(a) shows an input video signal, (b) shows a vertical synchronizing signal VD, and (c) shows a horizontal synchronizing signal HD. Read control HD counter 106
(D), (e) and (f) are shown by inputting the vertical synchronizing signal VD and the horizontal synchronizing signal HD of (b) and (c) to the input video signal of (a). Vertical read start pulse RVS, horizontal read control pulse RHD, and read position cursor signal R
Generate E respectively.

The vertical read start pulse RVS shown in FIG. 5D specifies the position (upper end) of the subtitle signal to be read on the screen, and the output timing is determined by the system control circuit 11.
3 is set by the position setting data PR0. The horizontal read control pulse RHD in FIG. 3E specifies the left end of the screen of each line (scanning line) of the caption signal to be read. The output timing is set by the position setting data PR0, and the stop timing is set by the position setting data. Set by PR1. The read position cursor signal RE shown in FIG. 11 (f) is output during the reading period of the subtitle signal, but need not be output in the synchronization signal portion during the output period, and its output line is the horizontal read control pulse RHD. Corresponds to the line on which is output. Figure (g)
Indicates a subtitle signal to be read from the RAM 110 and to be inserted into the image signal in a relative position (time) relationship with each signal shown in (d), (e), and (f).

Interlaced scanning is performed on a video signal such as NTSC. Therefore, in the image processing apparatus of the present invention, when reading a subtitle signal in the field next to the written field, it is necessary to perform correction so that the vertical relationship with the scanning line of another field adjacent to the current scanning line is not reversed. There is. The interlace correction circuit 107 performs this correction, receives the horizontal synchronization signal HD and the vertical synchronization signal VD, determines the field of the video signal, and determines whether the current video signal is in an odd field when reading the subtitle signal. In some cases, a count correction signal HS is output to the read control HD counter 106.

FIG. 6 is a schematic diagram for explaining the correction by the interlace correction circuit 107 by oblique lines composed of dots 1 to 9. FIG. 9A shows a state where the dots 1 to 9 are normally located in the odd field and the even field, respectively, and the dots 1, 3, 5, 7, and 9 are located on the scanning lines of the odd field. In addition, dots 2, 4, 6, and 8 are located on the scanning lines of the even-numbered fields. FIG.
This shows a state in which read data is inserted into the video of the next field without performing the interlace correction. Dots 1, 3, 5, 7, and 9 are inserted into even fields, and dots 2, 4, 6, and 8 are displayed. Inserted in odd field.
As a result, a diagonal line that should be as shown in FIG.
Since the images are displayed in a state where they are alternately shifted left and right, the vertical resolution is reduced. FIG. 11C shows a state in which read data has been inserted into the video of the next field after the interlace correction has been performed.
3, 5, 7, and 9 are inserted into the even-numbered fields, and the read data of dots 2, 4, 6, and 8 move from the white circle position to the black circle position. Thereby, the oblique line is correctly displayed.

For example, R for two fields, which is twice the current value, is used.
If the AM is used and the writing is performed while reading in the same field, the above-mentioned correction becomes unnecessary, but in that case, the memory size increases and the price increases. In the image processing apparatus of the present embodiment, this can be solved by the correction by the interlace correction circuit 107. In this image processing apparatus, in addition to the correction at the time of reading, the correction at the time of writing, or only the writing of the even field
The same correction can be performed by the correction that delays the line.

The read horizontal compression circuit 108 receives the clock signals 2fck and fck from the horizontal synchronization clock generation circuit 104, receives the horizontal compression switch signal HC from the system control circuit 113, and sends the read horizontal position control circuit 109 and the RAM 110 to the RAM 110. Outputs read clock signal RCK.
If the read clock signal RCK is set to the same frequency as the write clock signal, the subtitle signal can be displayed in the same size as when writing, and if the frequency is doubled, the subtitle signal is compressed in half in the horizontal direction of the screen. Can be displayed.

The read horizontal position control circuit 109 receives the horizontal read control pulse RHD from the read control HD counter 106, reads the read clock signal RCK from the horizontal compressing circuit 108, and sets the delay time set value PH to the system control circuit 113. And outputs a horizontal read start pulse RHS to the RAM 110.

FIG. 7 is a block diagram showing a configuration example of the read horizontal position control circuit 109 and the read horizontal compression circuit 108. In the figure, 46 is a horizontal position control counter, 47
Is a signal switching unit. For example, when a horizontal read control pulse RHD is input to the read horizontal position control circuit 109,
The horizontal read control pulse RHD is delayed by the delay time set value PH by the horizontal position control counter 46 using the read clock signal RCK as a clock, and is output as a horizontal read start pulse RHS. On the other hand, in the readout horizontal compression circuit 108, the signal switching unit 47 is switched by the horizontal compression switching signal HC, and selects one of the clock signals 2fck and fck and outputs it as the read clock signal RCK.

The RAM 110 receives the write data WD as a subtitle signal from the subtitle signal quantization circuit 111, inputs fck as a write clock signal from the horizontal synchronization clock generation circuit 104, and outputs a vertical write start pulse WVS and a horizontal write start pulse. WHS write control HD counter 105
Enter from. The RAM 110 further inputs the read clock signal RCK from the horizontal compression circuit 108, inputs the vertical read start pulse RVS from the read control HD counter 106, inputs the horizontal read start pulse RHS from the read horizontal position control circuit 109, and reads The data RD is output to the caption signal insertion circuit 112.

FIG. 8 is a block diagram showing an example of the configuration of the RAM 110. The RAM 110 includes a memory cell 50, an input buffer 51, a write address controller 52, a read address controller 53, and an output buffer 55.
Is provided. The memory cell 50 is composed of 1 bit, n columns, and m rows (that is, 1 bit × n columns × m rows). Each row corresponds to one scanning line, and the column corresponds to the number of data samples in one line period. Corresponding. Therefore, when the memory cell 50 is used, data of one bit and n samples per line can be written or read for a maximum of m lines.

In the RAM 110, when reading the subtitle signal, the write data WD is input to the input buffer 51,
Further, when the vertical write start pulse WVS is input to the write address controller 52, the row address of the controller 52 is initialized to 1. Next, when the horizontal write start pulse WHS is input to the write address controller 52, the column address of the controller 52 is initialized to 1 and the data is clocked in the column direction of the memory cell 50.
Written in synchronization with fck. When the data is written up to n columns, the data writing stops, and the address holds the value at that time. Next, when the horizontal write start pulse WHS is input again to the write address controller 52, the row address advances by one, the column address returns to 1, and the data on the second row is synchronized with the clock signal fck in the column direction of the memory cell 50. Written. In this way, the caption signal is written with the head data of the line aligned with the head of each line.

On the other hand, when reading the subtitle signal, the read address controller 53 sends a vertical read start pulse.
When RVS is input, the row address of the controller 53 is initialized to 1. Further, when the horizontal read start pulse RHS is input, the column address is initialized to 1, and data is read in the column direction of the memory cell 50 in synchronization with the read clock signal RCK. When the data is read up to n columns, the reading stops, and the address holds the value at that time. Next, when the horizontal read start pulse RHS is input again to the read address controller 53, the row address advances by 1, the column address returns to 1, and the memory cell 5
In the column direction of 0, data for two rows is read out in synchronization with the read clock signal RCK. The read data is output from output buffer 55 as read data RD.

A subtitle signal quantization circuit 111 extracts a subtitle signal corresponding to the image signal extracted by the image signal extraction circuit 118 from the input video signal VC in real time based on a control signal from the system control circuit 113. It constitutes an extracting means. The subtitle signal quantization circuit 111 receives the clamped input video signal VC from the clamp circuit 102 and outputs the subtitle signal detection level LT to the system control circuit 11.
3, the fck as the sampling clock signal is input from the horizontal synchronization clock generation circuit 104, and the write data WD as the subtitle detection output (subtitle signal) is input to the RAM 110.
Output to The write data WD is 1-bit data obtained by quantizing a level higher than the caption signal detection level LT into “1” and a lower level into “0”.

The caption signal insertion circuit 112 inputs an image signal (video signal) that has been subjected to predetermined processing via the clamp circuit 102, the image signal extraction circuit 118, and the screen magnification setting circuit 119, and outputs a caption signal insertion level. LI and display switching signal SD are input from system control circuit 113, and read data RD is input from RAM 110. The caption signal insertion circuit 112 further includes a caption writing position cursor signal WE.
Is input from the write control HD counter 105, the read position cursor signal RE is input from the read control HD counter 106, and the display video signal (caption signal processing output) VO is output to the video signal output terminal 114.

FIGS. 9 and 10 are block diagrams showing examples of the configuration of a caption signal insertion circuit. The caption signal insertion circuit 112a in FIG. 9 is of a caption signal switching and insertion type, and includes a low-pass filter 56, a switching unit 57, and a switching unit 59. The low-pass filter 56 removes a high-frequency component that is higher than the signal band generated by inserting the caption signal. The switching unit 57 selects one of the read data RD, the subtitle writing position cursor signal WE, and the read position cursor signal RE according to the input display switching signal. The switching section 59 selects one of the image signal (video signal VC) and the caption signal insertion level LI according to the signal selected by the switching section 57. In the caption signal insertion circuit 112 having such a configuration, the cursor can be displayed on the screen in a white-white band.

The subtitle signal insertion circuit 112b of FIG. 10 is of the subtitle signal addition and insertion type, and includes a switching unit 60, an adder 61 and an amplitude limiter in addition to the low-pass filter 56 and the switching unit 57 similar to those in FIG. 62. The switching unit 60 selects one of the 0 level and the subtitle signal insertion level LI according to the signal selected by the switching unit 57. The adder 61 adds the signal selected by the switching unit 60 and the image signal (video signal VC), and adds the signal to the amplitude limiter 62.
Output to When the video signal VC exceeds the white level due to the addition in the adder 61, the amplitude limiter 62 clips the signal so as not to exceed the white level.

The subtitle signal insertion circuit 112a inserts the read data RD, the subtitle write position cursor signal WE, and the read position cursor signal RE into the image signal (video signal VC). However, the caption signal insertion circuit 112b converts the read data RD and the cursor signals WE and RE into RGB data.
Since it can be inserted into each of the R, G, B signals of the conversion, it can be displayed on the screen in color. In the subtitle signal insertion circuit 112b having such a configuration, the background video can be displayed by appropriately selecting the subtitle signal insertion level LI.

The system control circuit 113 includes an interface with an external switch, a controller, and the like, and has a function of outputting the above-described control signals, setting data, and the like. That is, the system control circuit 113 sends a subtitle moving processing operation (ON / OFF), a subtitle writing position setting operation (ON / OFF), and a subtitle reading position setting operation (ON / OFF) from a system microcontroller or the like inside the television receiver. ,
A subtitle signal detection level, a subtitle signal superimposition level, and the like are input, and necessary information is supplied to each constituent circuit.

FIG. 11 is a schematic diagram showing a general case where video and subtitles are displayed on the screen of a television receiver.
(a) shows an example in which a video signal of the NTSC system or the like having a video of a Vista size is directly displayed on a screen 65 of a normal television receiver. An image portion is located at the center of the screen 65, and subtitles are inserted below the image portion. FIG. 7B shows a state in which only the image in FIG. 7A is enlarged and displayed on the entire area of the screen 65. In this case, since the image is displayed enlarged in the center of the screen 65, the subtitle displayed below the image portion in (a) disappears from the screen 65.

Here, according to the image processing apparatus of the present invention, the following display can be made. FIG. 12 is a schematic diagram showing display contents by the image processing apparatus. In FIG.
The subtitle shown in FIG. 11A is directly moved and inserted into the display portion of the image of FIG. 11B enlarged and displayed on the entire area of the screen 65. In this display example, the enlarged video and subtitles can be viewed simultaneously. In FIG. 12B,
In the image of FIG. 11B enlarged and displayed on the entire area of the screen 65,
The subtitle shown in FIG. 11A is inserted in a state where it is compressed in the horizontal direction of the screen. Also in this display example, the enlarged image and the compressed subtitle can be viewed at the same time, and the area of the screen hidden by the subtitle is half that of the case of FIG.

FIG. 12C shows the same image compressed in the horizontal direction of the screen.
It shows an insertable position when the subtitle of (b) is inserted into the screen 65. The insertable positions include, for example, a total of four positions, that is, a left portion and a right portion in the upper and lower positions of the screen 65, and can be inserted into any easily visible position according to the content.

FIG. 13 is a schematic diagram showing another display state by the image processing apparatus. FIG. 11A shows a screen 65 of FIG. 11A displaying an original Vista-sized image with subtitles.
Is inserted at the bottom of the box to display the subtitle writing range. In FIG. 13B, a cursor is inserted at a substantially central portion of the screen 65 to display a subtitle writing range. The setting range of subtitle writing is indicated by the position and width of the cursor.
As described above, the method of inserting the cursor on the screen 65 is conveniently used as an index when setting which part of the subtitle signal is to be written in the memory and where the subtitle is to be displayed with respect to the image.

FIG. 14 is a block diagram when the image processing apparatus according to the first embodiment of the present invention is functionally represented. The image processing apparatus includes an image signal extraction unit corresponding to the image signal extraction circuit 118, an image signal processing unit corresponding to the screen magnification setting circuit 119, and a subtitle signal extraction unit corresponding to the clamp circuit 102 and the subtitle signal quantization circuit 111. Means and RA
A subtitle signal storage unit corresponding to M110 and a subtitle signal writing control unit corresponding to the synchronization separation circuit 103, the horizontal synchronization clock generation circuit 104, and the writing control HD counter 105 are provided. The image processing apparatus further includes a subtitle signal read control unit corresponding to the read control HD counter 106 and the read horizontal position control circuit 109, and a subtitle signal insertion circuit 11
2, a subtitle signal insertion unit that inserts a subtitle signal read from a subtitle signal storage unit into a designated area of an image signal and outputs the same to a display device, and a system control unit that corresponds to the system control circuit 113.

In the image processing apparatus, the image signal extracting means includes:
An image signal is extracted in real time from the input video signal VC based on a control signal from the system control unit, and the image signal processing unit sets and outputs an enlargement ratio of the image signal extracted by the image signal extraction unit.

On the other hand, the subtitle signal extracting means outputs the same input video signal VC as the image signal extracted by the image signal extracting means.
Then, after the sync signal or the pedestal level is clamped to a certain level, it is compared with the caption signal detection level set by the system control means. As a result, sampling is performed using a clock signal having the same frequency as the clock signal for writing to the caption signal storage unit, with the large one being “1” and the small one “0”. That is, the subtitle signal is extracted in real time. When the frequency of the input video signal VC includes a frequency that is 1/2 or more of the sampling frequency, the band is limited so that the frequency of the input video signal VC becomes 1/2 or less before or after the clamp.

The caption signal writing control means (caption position control means) controls the input video signal VC
From the horizontal synchronizing signal HD and the vertical synchronizing signal VD. The horizontal synchronizing signal HD and the vertical synchronizing signal VD are input to a write control HD counter 105 that specifies a subtitle write position. The write control HD counter 105 has data relating to a write start position and a write end position set by the system control means. When the write control position reaches the write start position, a write start pulse WVS which is a write control signal to the caption signal storage means is provided. , WHS and subtitle writing position cursor signal W
E is output. Next, when the writing end position is reached,
The output of these write control signals is stopped. The subtitle signal writing control means includes a horizontal synchronization clock generation circuit 10.
At 4, the write clock signal fsc to the subtitle signal storage means is generated by the PLL using the horizontal synchronization signal HD as a reference signal.

The subtitle signal storage means is a RAM 110 composed of 1 bit × the number of samples per line × the number of subtitle symbol storage lines. The upper limit of the number of subtitle signal storage lines is determined by the number of subtitle signal storage lines of the RAM 110. . The caption signal storage means writes and holds the signal from the caption signal extraction means by the caption signal writing control means, and reads the held signal based on the control of the caption signal reading control means.

The subtitle signal read control means receives the horizontal synchronizing signal HD and the vertical synchronizing signal VD from the subtitle signal writing control means.
And inputs it to a subtitle read position designation counter corresponding to the read control HD counter 106. The read position designation counter has data relating to the read start position and the read end position set by the system control means. When the subtitle read position designation counter reaches the read start position, a vertical read start pulse RVS and a horizontal read start pulse RH as read control signals to the subtitle signal storage means are provided.
S, a read control pulse RHD, and a read position cursor signal RE are output. Further, when reaching the read end position, the output of each signal RVS, RHS, RHD, RE is stopped.

The subtitle signal read control means inputs the write clock signal fsc and the clock signal 2fsc having a frequency twice that of the write clock signal fsc from the horizontal synchronization clock generation circuit 104 of the subtitle signal write control means, and outputs the read clock signal RCK.
Is generated and supplied to the caption signal storage means.

The caption signal insertion means changes the caption signal insertion level set by the system control means from the image signal processing means for one period of the data read from the caption signal storage means by the caption signal read control means. Is inserted or added to the image signal. In the image processing apparatus according to the first embodiment of the present invention, the caption signal is inserted into the image signal as a whole and displayed on the screen 65.

Next, a description will be given of a second embodiment of the image processing apparatus according to the present invention. FIG. 15 is a block diagram showing the configuration of the present embodiment. In the figure, elements having the same functions as those of the image processing apparatus shown in FIG. 1 are denoted by the same reference numerals.

The image processing apparatus according to the present embodiment has a symbol / character display function in addition to a subtitle display function similar to the image processing apparatus according to the first embodiment. That is, the image processing apparatus according to the present embodiment includes a ROM 115 for generating character data.
And a symbol / character code writing control circuit 116 and a writing data selection circuit 117, and a character corresponding to the caption is displayed on the screen instead of the caption display.

The symbol / character writing control circuit 116 is a RAM
For writing the symbol character code in 110
A signal CD of information such as a symbol character code and an arrangement is received from the system control circuit 113, and is synchronized with the clock signal fck and the horizontal synchronization signal HD and the vertical synchronization signal VD inputted from the synchronization separation circuit 103, and the inputted arrangement. Outputs the symbol character code according to the information.

The write data selection circuit 117 includes a subtitle signal quantization circuit 111 and a subtitle character code write control circuit 11.
6 is selected and the write data W to the RAM 110 is selected.
D is output. The write data selection circuit 117 is switched by the switching signal WDS from the system control circuit 113, selects one of the output of the subtitle signal quantization circuit 111 and the output of the symbol / character code write control circuit 116, and selects the RAM.
Output to 110. The character data ROM 115 is
The read data RD is input from the RAM 110 as a symbol character code, and character data corresponding to the symbol character code is output to the caption signal insertion circuit 112.

Here, only operations different from those of the image processing apparatus of the first embodiment will be described. That is, in the image processing apparatus according to the present embodiment, the write data selection circuit 117 determines whether one of the caption signal passed through the caption signal quantization circuit 111 and the symbol / character code from the symbol / character writing control circuit 116 is controlled by the system control. The selection is made in accordance with the switching signal WDS from the circuit 113, and is output to the RAM 110 and stored. Thereby, the caption signal insertion circuit 112 displays the caption on the screen based on the read data RD input from the RAM 110 in the same manner as in the first embodiment, or displays the character data corresponding to the read data RD on the character data ROM 115.
And displays the corresponding character on the screen.

The manner in which a character is displayed on the screen 65 will be described with reference to FIG. That is, in the present image processing apparatus, a symbol character code corresponding to a character for displaying information such as a screen size and the presence or absence of a caption is written in a RAM 110 for storing a caption signal, and the symbol character code is read out and stored in data RD. Output to the ROM 115. At this time, the caption signal insertion circuit 112 converts the character data corresponding to the symbol character code into the character data R
It reads from the OM 115 and displays a character “with subtitles” at the lower right of the screen 65, for example.

As described above, according to the present image processing apparatus, after the image signal and the caption signal extracted in real time from the input video signal VI (VC) are individually processed, the both are combined as the display video signal VO. Output, or
Character data in place of a caption signal can be inserted into an image signal and output as a display video signal VO. Therefore, the viewer can recognize the presence of the caption by looking at the “captioned” character displayed on the screen 65. For example, when viewing a foreign movie, subtitles can be displayed on the screen 65 as necessary by a predetermined operation. Further, it is also possible to display a character using only a symbol instead of a character character such as “with subtitles”. The caption signal insertion means, caption position control means,
The caption compression means, the character data ROM, and the cursor display means constitute a caption signal control means.

FIG. 17 is a block diagram showing a display device as a comparative example of the first and second embodiments. This display device is an example of a vertical enlargement display device that performs vertical enlargement (vertical deflection processing) of an image and performs aspect ratio conversion without performing digital signal processing. The vertical enlarged display device is YC
A separation color demodulation circuit 25, an RGB conversion circuit 26, a drive circuit 27, a display device 29 such as a CRT, a synchronization separation circuit 30,
A deflection circuit 31 and a vertical deflection control circuit 32 are provided.

In the vertical enlargement display device, the image is vertically enlarged by increasing the vertical deflection in the enlarged portion of the image on the display device 29 such as a CRT without performing digital signal processing. That is, when the video signal is input to the YC separation color demodulation circuit 25 and the synchronization separation circuit 30, RGB
The video signal is converted to an RGB display system by the conversion circuit 26, and this signal is transmitted to the display device 29 via the drive circuit 27.
Is output to On the other hand, the video signal input to the sync separation circuit 30 is output to the display device 31 via the vertical deflection control circuit 32 and the deflection circuit 31. Therefore, in a vertically enlarged display device, for example, when there is a caption displayed on the screen in a foreign image or the like, only the area including the image and the caption is vertically enlarged to display the entire screen, and the caption is displayed on the image. It cannot be moved and displayed.

FIG. 18 is a block diagram showing a display device as a comparative example of the first and second embodiments. This display device is configured as a vertically enlarged display device having a function of converting an aspect ratio by digital signal processing.
The vertical enlargement display device includes an AD conversion circuit 11, a YC separation color demodulation circuit 12, a caption signal processing circuit 13, and a scanning line interpolation circuit 1.
5, a vertical enlargement circuit 16, a DA conversion circuit 17, an RGB conversion circuit 19, a drive circuit 20, a display device 21 such as a display, a sync separation circuit 22, and a deflection circuit 23.

In the above vertically enlarged display device, the following operation is performed.
The video portion is enlarged and displayed to fill the screen with respect to the video signal such as the Vista size, and the subtitle signal is moved and inserted into the video signal to be displayed on the display device 21. That is, if the video signal is A
When input to the D conversion circuit 11 and the synchronization separation circuit 22,
The AD conversion circuit 11 converts the whole video signal into a digital signal, the YC separation color demodulation circuit 12 separates the luminance signal Y and the color signal C and performs color demodulation, and the subtitle signal processing circuit 13
Writes the subtitle portion to an image memory (not shown). Next, the scanning line interpolation circuit 15 returns the scanning line of the captured video signal to the scanning line on the front surface of the screen in order to read the subtitle signal from the image memory at a predetermined insertion timing and add it to the video signal. Further, the vertical enlargement circuit 16 enlarges the vertical direction so that the image portion is displayed on the entire screen, and the DA conversion circuit 1
7 converts the input signal from the vertical enlargement circuit 16 into an analog signal, and the RGB conversion circuit 19 converts the analog signal from the DA conversion circuit 17 into an RGB display system. The conversion signal from the RGB conversion circuit is supplied to the display device 21 via the drive circuit 20.
Are output to the display device 21 via the sync separation circuit 22 and the deflection circuit 23, and an image including subtitles is displayed on the display device 21.

In the vertical enlargement display device, a subtitle signal once separated from an input video signal can be reinserted into a video signal to display characters on a screen, but digital signal processing using an image memory is required. This digital signal processing over the entire video signal increases the precision and flexibility of the signal processing, but also increases the number of components, increases the board area, etc., and leads to an increase in cost. Therefore, it is difficult to mount an effective subtitle signal processing circuit on a vertical enlargement display device by a vertical deflection process of a popular type that occupies a large number of products.

In contrast to the comparative example, the image processing apparatuses of the first and second embodiments have the following effects. That is, in a television receiver, for example, an image portion near the center, such as Vista-size video software (see FIG. 11A)
When a video signal including a subtitle portion and a subtitle portion outside the subtitle portion is input and only the image portion is displayed on the entire screen, displaying the subtitle lost from the screen 65 in the image portion is performed by a field memory, A / D, or A single integrated circuit can be used without using a large-scale circuit using a D / A converter or the like. Therefore, it is possible to provide a subtitle signal processing circuit which can be sufficiently used for a television receiver which performs a vertical enlargement display by a vertical deflection process of a popular type which occupies a large number of products.

Although the present invention has been described based on the preferred embodiment, the image processing apparatus of the present invention is not limited to the configuration of the above-described embodiment, but rather the configuration of the above-described embodiment. An image processing device in which various modifications and changes have been made is also included in the scope of the present invention.

[0069]

As described above, according to the image processing apparatus of the present invention, a memory having a large storage capacity is not required while sufficiently processing an image signal and a caption signal. One L without inviting
It is possible to construct the system at low cost from SI.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a time chart showing a relationship between a clamp level and each slice level, wherein (a) shows a relationship between a sync separation slice level and a caption signal detection level, and (b) shows a synchronization separated by a sync signal slice level. (C) shows the detected caption signal, and (d) shows the relationship between the caption signal insertion level and the synchronization front clamp level.

FIG. 3 is a block diagram illustrating a configuration example of a horizontal synchronization clock generation circuit.

FIG. 4 is a time chart showing signals processed by a write control HD counter, where (a) is an input video signal, (b) is a vertical synchronization signal, (c) is a horizontal synchronization signal, and (d) is a vertical synchronization signal. A write start pulse, (e) shows a horizontal write start pulse, and (f) shows a subtitle write position cursor signal.

5A and 5B are time charts showing signals processed by a read control HD counter, wherein FIG. 5A is an input video signal, FIG. 5B is a vertical synchronization signal, FIG. 5C is a horizontal synchronization signal, and FIG. A read start pulse, (e) indicates a horizontal read control pulse, (f) indicates a read position cursor signal, and (g) indicates a caption signal to be inserted into an image signal.

6A and 6B are schematic diagrams for explaining interlace correction by oblique lines using a plurality of dots, where FIG. 6A illustrates a state where each dot is at a normal position, and FIG. 6B illustrates a case where interlace correction is not performed. State (c) shows a state in which interlace correction has been performed.

FIG. 7 is a block diagram illustrating a configuration example of a read horizontal position control circuit and a read horizontal compression circuit.

FIG. 8 is a block diagram illustrating a configuration example of a RAM.

FIG. 9 is a block diagram illustrating a configuration example of a caption signal insertion circuit.

FIG. 10 is a block diagram illustrating a configuration example of a caption signal insertion circuit.

11A and 11B are schematic diagrams showing a general case where a video and subtitles are displayed on a screen, wherein FIG. 11A is an example in which a video is displayed as it is on a screen, and FIG. 11B is an enlarged view of only the video in FIG. An example of the display is shown.

12A and 12B are schematic diagrams illustrating display contents by the image processing apparatus, in which FIG. 12A illustrates an example in which subtitles are directly inserted into an enlarged display image, and FIG. 12B illustrates a case in which subtitles are compressed and inserted into an enlarged display image. For example, (c) shows a position where a caption compressed in the horizontal direction of the screen can be inserted.

13A and 13B are schematic diagrams illustrating another display state of the image processing apparatus, wherein FIG. 13A illustrates an example in which a cursor is inserted at a lower portion of a screen, and FIG. 13B illustrates an example in which a cursor is inserted at a substantially central portion of the screen. Show.

FIG. 14 is a block diagram when the image processing apparatus according to the first embodiment is functionally represented;

FIG. 15 is a block diagram illustrating a configuration of an image processing apparatus according to a second embodiment of the present invention.

FIG. 16 is a schematic diagram illustrating display contents of the image processing apparatus according to the second embodiment.

FIG. 17 is a block diagram showing a display device as a comparative example of the first and second embodiments.

FIG. 18 is a block diagram showing a display device as a comparative example of the first and second embodiments.

[Explanation of symbols]

 Reference Signs List 103 Synchronization separation circuit 104 Horizontal synchronization clock generation circuit 105 Write control HD counter 108 Readout horizontal compression circuit 110 RAM 111 Caption signal quantization circuit 112 Caption signal insertion circuit 115 Character data ROM 116 Symbol character code writing control circuit 118 Image signal extraction circuit 119 Screen magnification setting circuit

Claims (6)

[Claims] An image signal and a subtitle signal corresponding to the image signal are extracted in real time from an input video signal including the image signal and the subtitle signal, and an image for setting a magnification of the extracted image signal. A signal processing unit; a subtitle signal storage unit that stores the extracted subtitle signal; and a subtitle signal read from the subtitle signal storage unit inserted into the image signal processed by the image signal processing unit. And a caption signal control means for outputting to a display device. 2. The apparatus according to claim 1, wherein the subtitle signal control unit includes a subtitle position control unit that separates a horizontal synchronization signal and a vertical synchronization signal from an input video signal and specifies a subtitle writing position from the horizontal synchronization signal and the vertical synchronization signal. The image processing apparatus according to claim 1, wherein: 3. The image processing device according to claim 1, wherein the subtitle signal control unit includes a subtitle compression unit that displays a subtitle based on the subtitle signal in a state where the subtitle is compressed in a horizontal direction of the screen of the display device. apparatus. 4. The image processing apparatus according to claim 1, wherein the subtitle signal control unit has a function of inserting character data indicating presence of subtitle display into an image signal and outputting the image data. . 5. The image processing apparatus according to claim 4, wherein said subtitle signal control means includes a ROM for storing character data of a symbol character to be inserted into an image signal. 6. The apparatus according to claim 1, wherein the subtitle signal control unit includes a cursor display unit that displays a cursor indicating a subtitle writing range on a screen of a display device. The image processing apparatus according to any one of the preceding claims.