TW200816373A - Circuit component and process for forming the same - Google Patents

Abstract

The present invention provides a thick metal trace or plane over a passivation layer connect multiple internal circuits in a same semiconductor IC chip, sending electrical stimulus from one of the internal circuits to other of the internal circuits or distributing a power or ground voltage to the internal circuits.

Description

200816373

JVLbUA uo-ui^TWB Nine, the invention relates to: [Technical Field] The present invention relates to a circuit component, and more particularly to a metal formed by a protective layer on an integrated circuit (1C) wafer A line or plane transmits signals from a chip built-in circuit (〇n_chip drcuit) unit to other circuit units, or a structure in which a power supply voltage or a ground reference voltage is transmitted to other circuit units and methods thereof. [Prior Art] Many of today's electronic components are required to operate at a high speed and/or low power consumption. In addition, today's electronic systems, modules or circuit boards (circuitb〇ard) contain many different types of wafers, such as the central processing unit Pressing Units 'CPUs', digital signal processors (Digitai signal processors 'DSPs), analog wafers Al〇g chip), dynamic random access memory (DRAMs), static random access memory (SRAMs) s flash memory theory, etc. The mother U is manufactured using an unsuitable type and/or a different generation of integrated circuit process technology. For example, 'in today's notebook-type personal electrician--C〇mi theory', the central processing unit may be the 65-nano (four) technology of the amount-news to manufacture 'the power supply voltage is 12 volts (v), analog wafer system Manufactured using a 0.25 micron (/zm) integrated circuit process technology, the power supply voltage is μ volts. The accessor core is manufactured using a 9 〇 nanometer integrated circuit process technology. The voltage is! • 5 volts, while the flash memory chip is fabricated using a 〇·18 micron touch, and its voltage should be volts. As a result of a single 5 200816373

ivucAjh υυ-υι j rWB system has a variety of supply voltages, so that a built-in (〇n_chip) voltage regulator, voltage converter or a circuit containing voltage regulation and voltage transformation is required. Designs, such as DRAM chips, require a chip built-in transformer to convert 3.3 volts to 1.5 volts' while flash memory chips require a chip built-in transformer to convert 3.3 volts to 2 volts. 5 volts. Among them, the chip built-in voltage regulator, transformer or circuit design with voltage regulation and voltage transformation provides a stable voltage to different positions on the same wafer through the built-in power/ground bus of the chip. Semiconductor component. In addition, if a voltage regulator, a transformer, or a circuit with voltage regulation and voltage transformation is built into a chip, a low-resistance power/ground reference voltage line is added, in addition to minimizing energy consumption, the load can also be reduced. The noise caused by the fluctuation of capacitance and resistance. In U.S. Patent No. 6,495,442, a post_passivation structure on the top of a wafer is disclosed. The back-sheath structure on the integrated circuit protection layer is used as a global, power, ground reference or signal distribution network. The power/ground reference voltage is from an external (wafer external) power supply. An embossing process for forming a post-passivation interconnection structure on a protective layer of an integrated circuit is disclosed in U.S. Patent No. 6,649,509, which can be used as a power supply, a ground reference voltage, A comprehensive distribution of the clock or signal. SUMMARY OF THE INVENTION One object of the present invention is to pass through a metal line on a protective layer or 6 200816373

The plane 'transmits the circuit built-in circuit cells under the protective layer to signals a number of components or circuit elements on the same chip (IC chip). SUMMARY OF THE INVENTION The object of the present invention is to enable a built-in voltage regulator on the underside of the protective layer to transfer power to a plurality of components or circuit elements on the same wafer through metal lines or planes on the protective layer. The object of the present invention is to pass through the gold secret path or plane on the protective layer, so that the wafer under the protective layer can be transferred to a plurality of components or circuit units on the power supply. The object of the present invention is to reduce the enthalpy loss of the transporting member due to the parasitic effect (4) of the reduction of the kiss. ^Inventive-purpose, the power loss transmitted to digital components or circuit units caused by parasitic effects on the falling side. The purpose of the metal is to transmit electricity to a component or circuit unit through the opening of the protective layer and the circuit surface of the circuit formed on the protective layer. The purpose of the invention is to transmit another signal, power supply, or ground reference voltage to another internal circuit or internal component through a metal line or plane on the protective layer. From at least two purposes, through the metal lines or planes on the protective layer, the signal, power supply, or ground reference voltage transmission coffee that is distributed to the interior 70 will be cleared in the future. (4) ♦ Light to static discharge or toughness Circuit. 200816373

MliCiAUO-Ul^TWB The present invention is directed to a gold-viewing or plane that transmits a bribe, power, or ground reference output from at least an internal circuit or internal component to at least another-(four) Circuit or (4) components without the need for external (wafer external) circuitry. SUMMARY OF THE INVENTION The object of the present invention is to transmit signals generated by internal circuits or internal components to an external circuit through a singular metal structure gamma-mesh structure under the lamella and a metal line or plane on the protective layer. The object of the present invention is to distribute a signal, power supply, or ground reference voltage output from at least an internal circuit or internal component to at least a further internal circuit or internal component through a Jinlin Road or plane on the service layer. Moreover, the contact structures on the protective layer are respectively connected to the circuit and the external circuit. The object of the present invention is to distribute an external power supply helper circuit and a power supply and ground reference voltage to the external power supply through the metal lines or planes on the protective layer. A ^ For the purposes of the present invention, the line tree includes - a metal line or plane on the protective layer 'and can be distributed over the metal line or plane - depending on the voltage and/or current of the detail circuit. According to the present invention, the line component includes a metal line or plane on the tilt layer, and the metal line or plane can distribute the signal, power, or ground reference voltage output from at least the internal circuit or internal component to at least ―Two other circuits or internal components. 200816373

ν/υ-υ 1J TWB In accordance with the purpose of the present invention, a 'line component includes a metal line or plane on a protective layer that can direct a signal, power supply, or ground reference from at least one internal circuit or internal component. The voltage output is divided into at least - another internal circuit or internal component ' and uses a contact structure on the protective layer to connect a wafer to the external circuit to the external circuit. For the purposes of the present invention, the line component comprises - a metal line or a plane on the protective layer - the side of the metal line or plane is distributed - the external power supply to the internal circuit and - the power supply and ground of the contact structure to the external power supply Reference voltage 0 [Embodiment] The circuit component of the present invention includes a wafer (m_ threat c read (8), chip (chip) or package unit, etc. Poor one embodiment: connecting a voltage regulator or a transformer Over-paeeivation power/ground reference voltage bus. Please refer to Figures 1B to lc, 2B to 2c, and 3B to 3D, respectively. A first embodiment of the present invention, wherein FIG. 1B and FIG. 1C show a simplified circuit diagram, which is connected by a Jinlin road or plane 81 on the protective layer 5 and/or a surface line or plane 82.虔If (voltage reguiator) or transformer (v〇〗 tage c〇nverter) 4i and internal circuit 2〇 (including 2 卜 22, 23, called 'and use this metal line or plane 81 and / or metal line or plane 82 Distribution - stability (four) or bribe 41 output Voltage and / or ground Cloth >. 2B ® test voltage of FIG. 2C, respectively, and the second presents a first and second 200 816 373 FIG.

JVUiUA UO-U13 fWB 1C diagram of the circuit is not a schematic view. Figures 3B and 3c are schematic cross-sectional views of the circuits shown in the second and third figures. In addition, the coffee column and the younger brother, the protective layer 5 is indicated by a broken line, the line or plane on the protective layer 5 is represented by a "thick line", and the line formed under the protective layer 5 is, Come, and in this embodiment of the silk method (four) shame (four). In the actual package, the power supply is transmitted from the U-turn or the transformer to the Jinlin Road or plane above the protective layer to several components on the integrated circuit 'IC. (circuit). The metal line or plane 'power source deposited on the protective layer can be transferred to a smart component or circuit unit in low impurity conditions. This kind of adjustment voltage and the metal line above the protective layer or the design of the surface transmission voltage can be accurately controlled to the internal circuit and accurately controlled at the - voltage level. In addition, the output voltage of the voltage regulator is between the positive and negative 10% of the target county in the voltage regulator (that is, the voltage difference between the voltage value and the slave target voltage value). It is better to set the target voltage value to be less than 10%) and to set between the positive and negative 5% of the target voltage, wherein the set target voltage of the regulator is, for example, 〇5 volts to Between 1 volts or between 0.5 volts and 5 volts. Therefore, in this way, the input node can be prevented from being subjected to a voltage surge generated by an external power supply or a large voltage fluctuation, so that the circuit performance can be improved by such a design. However, in some applications, because the chip needs to be different from the voltage supplied by an external power supply, 200816373

LviiiUA υο-υ l d FWB Therefore, in addition to the voltage regulator, a voltage transformer is used to convert the voltage supplied from the external power supply into the voltage inside the wafer. The transformer can convert an input voltage into an "output voltage," and the wheel voltage is different from the wheel voltage, and the difference between the input voltage "output % voltage divided by the fine voltage is greater than ·, where the wheel voltage is The type that is between 1 volt and volt volt or between 5 volts and 5 volts may be - the step-down transformer is a booster transformer. Figure 1A, Figure 2A and Figure 3A It is a schematic diagram showing how a conventional voltage regulator or transformer 41 is connected to an internal circuit 2 (including 21, 22, 23, and 24), a top view and a cross-sectional view. This prior art utilizes a protective layer 5 The lower fine-line metal structures 619, 6191, and 61 (including 618, 6ln, 6121, and 6141, which in turn include 6121a, 6121b, and 6121e) are used to connect the voltage regulator or transformer 41 to the external supply power input voltage Vdd, output. A voltage Vcc and a transfer voltage Vcc to the internal circuit 20 (including 21, 22, 23, and 24). However, the thin-line metal structure 61 under the protective layer 5 and fabricated using the wafer process and material cannot be easily provided thick. Metal layer (eg 5 microns thick) The metal layer) is either a thick dielectric layer (for example, a dielectric layer with a thickness of 5 μm). In addition, the high unit length resistance of the thin line metal layer and the high unit length capacitance cause a voltage drop in the power supply (IR v〇ltage dr〇 p), noise, signal distortion, propagati〇n time delay, high power consum|rti〇n, and high heat generation 〇11 200816373

MiiUA υο-υ 13 TWB 20 'where the fine-line metal structure 611 to the internal circuit 21; through the fine-line metal structure 612a and the thin-line metal structure 612b to the internal circuit 22; through the fine-line metal structure 612a and the thin-line metal structure 61 The internal circuit 23, and through the fine line metal structure 614 to the internal circuit 24. Referring to Fig. 4, it is a circuit diagram of the first embodiment of the present invention. In this embodiment, the regulator or transformer 41 receives the voltage double of the external supply power supply via the protective layer opening and the fine line metal structure 619, and outputs the voltage w to the internal circuit 2G (including 21, 22, 23 and 24). The voltage v(2) of the voltage regulator or voltage regulator 41 at the node P is sent to the voltage nodes Tp, Up, Vp, 矸 of the internal circuit 2, 22, 23, 24 through the following means, which is first through the thin line. The road metal structure 619 passes upward through the protective layer opening 519'' of the protective layer 5 and then passes through the metal line or plane & on the protective layer 5, and the county passes through the protective layer openings 511, 512, 514, and then passes through Fine-line metal structure 61, (including 6U, 612, 614, wherein 612 includes sin, (10), called internal circuit, internal circuit 20 (including 21, 22, 23, 24) is at least one MOS micro-transistor (MOS transistor), and the thin-line metal structure described above is a gold-oxide semi-transistor connected to the internal circuit 20 (including 21, 22, 23, 24), such as a source connected to the MOS transistor (source) And the MOS transistor can be a "Channel width / Channel length" ratio between 〇·〗 至5 or an N-type gold oxide between 0.2 and 2. Semi-transistor _ 〇 8 transistQ] r), or "channel width / channel length" ratio between 〇 · 2 to Between 1〇 or between 〇·4 to 12 200816373

-P-type gold oxide semi-transistor between MliUAUb-Ul^rWB 4 (pM〇st Cong (4). In addition, the m flowing through the metal line or plane 81 is between 5G microamperes to 2 milliamperes or between Between 100 microamperes and 1 milliamperes. Therefore, the structure shown in Fig. 1B uses a metal line or plane 81 as the source line or plane, and because the metal lines or planes on the protective layer 5 are thick. Metal conductors, while thick metal conductors have the advantage of low resistance, so the pressure drop generated by the large salt > metal lines or plane 81 (4) 丨 Qing & Gp), and the supply voltage provided by the metal line or plane 81 can be stabilized. . In FIGS. 1B to 1C, 2B to 2C, and 3B to 3D, the 'internal circuit 20 includes an internal circuit 2, an internal circuit 22, an internal circuit 23, and an internal circuit 24, wherein the internal circuit 22, 24 is for the inverse or gate _ to (four), while the inner P private road 23 is the reverse and the gate q^and period pull), and each of the inverse or gate and the opposite gate has an input node Ul, Wi, Vi, an output node Uo, Wo, Vo, a voltage VCC power supply node UP, Wp, Vp and a ground reference voltage Vss ground node Us, Ws, Vs, and the internal circuit 21 has an input node xi, an output node X 〇, a voltage Vcc power supply node Tp and a ground reference voltage Vss are grounded to point ^. Therefore, the internal circuit (including 21, 22, 23 and 24) usually 'has a signal point (8) to n〇de), the power node (4) wer n〇(je) and grounding node (glOUndn〇de). However, the internal circuit 20 (including 21, 22, 23, and 24) can also be any type of integrated circuit, and the contents of this part will be combined. The description of the internal circuit 20 (including 21, 22, 23, and 24) is described in the series after reading the ls picture; another related to the inner 13 200816373

Some of the application examples of the ivicu/1 uo-uuTWB circuit 21 will be described in the 5C to 5R drawings in the subsequent 5C to 5j. Please refer to FIG. 2B and FIG. 3B at the same time, which are respectively a schematic plan view and a cross-sectional view of the first embodiment of the present invention. In FIG. 3B, the fine-line metal structures 611, 612 '614, 619, 619 may be formed by a thin-line metal layer 6 〇 and an opening 3 〇; filled with a plug 60, the way of which is, for example, _ A slightly aligned stacking pattern is formed, that is, between the upper and lower openings 3〇, which are substantially aligned, and the upper and lower fine line metal layers 6G are substantially aligned, and the upper and lower conductive plugs 6〇, It is also generally understood that the metal layer (9) is separated by a dielectric layer 3 (e.g., tantalum oxide), and the description of the fine line metal structure is also applicable to all embodiments of the present invention. In FIG. 2B, the metal line or plane 81 on the protective layer 5 may be a single layer of patterned metal layer (eg, patterned metal layer 8 of FIG. 3b) or a plurality of patterned metal layers (not shown), and When the metal line or plane 81 is a multi-layer patterned metal layer, the patterned metal layers are separated by a polymer layer, and the polymer layer may be a polypimide (PI) or a phenyl ring. Benzocydobutene (BCB), parylene, epoxy-based material such as epoxy resin or ph〇t〇epoxy supplied by Sotec Microsystems, Renens, Switzerland SU-8, an elastomer (elastomer) such as silicone. In addition, the metal line or plane 81 includes an adhesion/barrier/seed layer and a thick metal layer. For example, in FIG. 3B, the patterned metal layer m includes an adhesion/barrier/ Seed layer, 200816373

MiiUA UO-Ul^ fWB and - thick metal layer 8m. A detailed description of the method for forming metal lines or plane illusions and the metal lines or planes 81 is illustrated in the following series, series 16, series 17, series 18, and series 19. The other 'fine line metal structure 612 includes a fine line metal structure coffee, a fine line metal structure (four) and a fine line metal structure 612e, which is used as a regional power (1〇cal P〇(4), and a metal line or Plane 81 is used as a global power distribution and is connected to fine-wire metal structures (including, for example, 612, 614) and fine-line metal structures 619. Please also refer to As shown in Fig. 2B and Fig. 3B, the external power supply is supplied with a voltage vdd at the contact pad, and after passing through a protective layer opening 519 and a thin line metal structure (10), input to the voltage regulator n or the transformer. 41, wherein the thin-line metal structure 619 includes a metal pad (shock) pad at the topmost layer of the thin-line metal layer 60. The cough penetrates the metal pad 619 from the protective layer opening 519 to connect the contact pad 8 (10). Inventively, the top polymer layer 99 covers the metal line solution surface 81. The top polymer layer 99 may be a pro-imine, a silk ring, a xylene, or an epoxy material (for example, Wei or phGtoep() xy su_8 ), the fine materials are as fine as stone, as shown in Figure 3B. The patterned metal layer 811 covers a top polymer layer 99. Alternatively, a polymer layer may be selectively added between the layer 5 and the metal line or plane 81. The polymer layer may be polyimine. Phenylcyclobutene, parylene, %oxy material (such as epoxy resin or ph〇t〇ep〇xy su_8), elastic material (such as linaloic acid), for example, as shown in the figure, in the protective layer 5 with patterned metal layer attached 15 200816373

Ivino/\ υο-υ id fWB is added a polymer layer 95, wherein the polymer layer is opened π 9519, 9519, 95n, Ml2 95U is not aligned with the protective layer openings 5i9, 5i9 in the protective layer 5, For example, in 512 514, the size of the bottom of the opening of the polymer layer may be smaller than the size of the opening of the lower layer, and the interface of the polymer layer covering the opening of the protective layer is, for example, in the third drawing. The dimensions of the opening side of the polymer layer, the state of the state 9, and the bottom are respectively smaller than the dimensions of the lower protective layer openings 519, 519, and the polymer layer 95 covers the partial protective layer openings 519, 519, and the exposed metal joints. Art 619〇, 6190', and additional protective layer openings 519, 519, the size is between 2 〇 micron and excitation micron, and the polymer layer σ 9519, 9519, the size is 2 〇 micron to 1 〇 Between microns; however, in some designs, the size of the opening of the polymer layer may also be greater than the size of the opening of the underlying protective layer, and the opening of the polymer layer exposes all portions of the opening of the protective layer, such as polymerization. Dimensions of the layer openings 9511, 9512, 9514 Is larger than the size of the lower protective layer openings 511, 512, 514, respectively, and the polymer layer openings 9511, 9512, 9514 respectively expose all portions exposed by the protective layer openings 511, 512, 514, in addition to the protective layer opening 511, The dimensions of 512, 514 are between 10 microns and 50 microns, while the polymer layer openings 9511, 9512, 9514 are between 20 microns and 1 micron. The above description is also applicable to all embodiments of the invention. Alternatively, the metal line or planar phantom used to distribute the stabilizing or switching voltage Vcc may be a single layer patterned metal layer (such as the patterned metal layer hi shown in FIG. 3B). Multilayer patterning between each metal layer 200816373

IVU30/\ 1J TWB metal layer ' M multilayer _ metal layer can penetrate the opening between the polymer layers to connect the different layers of the metal layer. Then, please refer to Figure 1A, Figure 5 and Figure 3A. The system is a related art. As shown in the figure, the external power supply provides the required input voltage in the following manner. 'The system is: using the protective layer to open: the exposed metal pad receives the voltage Vdd from the external supply input and then goes down through the fine line metal structure 619, and finally the voltage is input to the regulator or transformer 41. Continuing, the voltage regulator or transformer 41 is brought to the internal circuit 21, 22, 23, 24 via a thin line metal junction _ (including 618, 6m, 6121, 6141). There is a significant energy loss (ene_ss) and a slower speed (the disadvantage of _ her ~. In the Guagua, 2B, 3B and 3D, the ground reference voltmeter is not VSS 'but The circuit, layout and structure are not described in detail. At present, the same time, the MiCmc diagram and the 3C riding, respectively, are used to separate the metal lines or planes above the protective layer (the x and the ground reference voltage W structure). Circuit diagram, top view and cross-section diagram, in addition to the regulator or transformer 11 41 and internal power (4) (including 2b 22, 23, 24): the reference ^ pressure in addition to the internal circuit 2〇 The structure and connection method of the ground reference voltage Vss are the same as the above-mentioned voltage 17 200816373, except that the points Ts, Us, Vs, Ws, and Rs are connected to the same ground reference voltage node.

Mj^ua υο-υ l d TWB

Vcc is similar. In FIGS. 1C, 2C, and 3C, the ground node Es receiving the ground reference voltage Vss is connected to the voltage regulator via the protective layer opening 529 of the protective layer 5 and the thin line metal structure 629 under the protective layer 5 The ground node Rs' of the facer 41 and the metal line (2), 622 (including 622a, 622b) through the metal line or plane 82 (patterned metal layer milk in FIG. 3C), protective layer openings 521, 522, 524 , 622c), 624 are connected to the internal circuits 21, 22, 23, % of the ground nodes Ts, Us, Vs, Ws. Referring now to FIG. 3C, the two layers of patterned metal layer 812 are used as a power/ground reference voltage structure above the side shield layer, wherein the patterned metal layer of the underlying layer is a metal line or plane 82. For distribution of a ground: test = pressure Vss route, bus bar or plane, and the top layer of patterned metal layer is committed to the metal line or plane 81, 甩 as the distribution - voltage Vcc line, bus or plane. In addition, in FIG. 3C, the number 821 is used to represent a patterned metal layer as a ground reference voltage, wherein the number 1 to the right of the number 821 represents the first metal layer, and the number 2 in the middle of the horse 821 represents the ground. The number on the left side of the number milk indicates that the metal above the abundance layer (10) is on the back (10) coffee (four). Similarly, rgri | Qiao, 810 is used to represent the patterned metal layer as the power source, where the number 812, the number 2 of the side represents the second metal layer, and the digital work in the middle of the number (10) represents the electric power (' The number on the left of the number (4) indicates that the metal above the protective layer is - followed by: - the layer 98 is separated from the two patterned metal layers 821 and 812, and the top of the top layer / layer 991 is on the top of the ugly metal layer 8 丨 2 Plant complex, layer, 200816373

MliUA uo-unTWB may be a polyhedamine, a phenyl ring, a second coat, a Wei (4) (e.g., epoxy or photoepoxy SU-8), or an elastomer (e.g., anthrone). Alternatively, a polymer layer 97 (X: not shown) may be selectively formed between the protective layer 5 and the bottommost end of the patterned metal layer 821, and the polymer layer 97 may be polyimide, benzene. A cyclobutene, a poly-p-methyl, an epoxy-based material (for example, an epoxy resin or a coffee), and an elastic material (for example, a sulphonone). The materials and pastes of the polymer layers 97, 98, and 99 in Fig. 3C are the same as those in Figs. 3B and 3D, and the related description will be described in the subsequent Fig. 15 series. In addition, the patterned metal layer 821 for distributing the ground reference voltage Vss in FIG. 3C is connected to the inside of the protective layer through the opening of the protective layer, M2, 524, S29, and the thin-line metal structure 62, 622, 624, and 629. The ground node Ts, Us, Vs, Ws of the circuit 2, 22, 23, 24 and the ground node Rs of the voltage regulator or transformer 41, and the patterned metal layer 812 for distributing the voltage Vcc is through the polymer Wire), thin wire metal structure (not shown) connected to internal circuits 21, 22 under the protective layer, power supply nodes Tp, Up, Vp, Wp and voltage regulator Or the power node of the transformer 41 (not shown). The current flowing through the metal line or the plane, a, is between 5 〇 microamperes to 2 milliamperes or between just microamperes to mA amps. In some financial applications, metal lines or planes 81 may be used to transmit data or signals (such as digital signal signals) in addition to electrical meters. Where, the metal line surface 82 can be used in addition to the grounding design, metal lines or plane 82 (10) lines or planes can be used 19 200816373

Ivmo/\ υο-υ i d TWB transmits data or signals (such as digital signals or analog signals). There are many other types of structures above the protective layer, which are summarized as follows: (1) In the application of high performance circuits or high percision analog circuits, the patterned metal layer 812 and the patterned metal layer A patterned metal layer (not shown) for transmitting a signal (such as a digital signal or an analog signal) may be added between the 821, and a polymer layer is formed below and above the patterned metal layer (in the figure) (not shown), the patterned metal layer is separated from the patterned metal layer 812 and the patterned metal layer 821; (2) in the application of high current or high percision circuits, patterned metal A patterned metal layer (not shown) for distributing a ground reference voltage may be added over the layer 812, and a polymer layer is formed between the patterned metal layer and the patterned metal layer 812, and a A top polymer layer covers the patterned metal layer. In other words, the patterned metal layer 812 is intermediate the patterned metal layer 821 and the patterned metal layer, thereby forming a vss structure over the protective layer 5; (3) if necessary, further in the above (2) Above the added patterned metal layer, another patterned metal layer (not shown) for distributing a power source is formed, and between the patterned metal layer and the patterned metal layer 812 added in the above (2) Forming a polymer layer, forming another polymer layer between the patterned metal layer added in the above (2) and another patterned metal layer, and a top polymer layer covering the other patterned metal layer, This results in a power/ground reference voltage structure of vss/ycc/yss/ycc (stacked from bottom to top). For high current circuits, high precision grab analog circuits, high speed circuits, low power circuits, power 20 200816373

The MliCiA U6-UnfWB source management (powermanagement) circuit and high-performance circuits provide a stable power supply. Referring to Fig. 4, an example of a voltage regulator or transformer 41 shown in Figs. 2D, 2C, and 3B to 3D is shown. This example circuit is a transformer with both voltage regulation and voltage transformation functions, and is commonly used in the "Semiconductor Memories: A handbook of Design, Mamifketure" by J.H. Wiley & Sons. The design of the modern dynamic random access memory 1 and the Kando Access Memory (DRAM) described in the book "and Application". As shown in Fig. 4, through the voltage regulation and voltage transformation function of the transformer, the voltage vdd of the external power supply input can be converted into an output voltage Vcc, and the difference between the output voltage Vcc and a set target voltage VccO is divided by The percentage of the target voltage Vcc〇 is set to be less than 1%, and less than 5% is preferred. As described in the "Prior Art," more modern integrated circuit chips need to convert the voltage supplied by the external (system, board, module or circuit card) supply to the voltage by means of a built-in transformer on the chip. The voltage required for the wafer. In addition, 'some wafers, such as a DRAM chip, require twice or three times the voltage on the same wafer, for example, the peripheral control circuit uses 3.3 volts () and Z [ The memory cell (mem〇r^ cell) in the array area of the body unit uses 1.5 volts. In the figure 4, the transformer includes two circuit blocks, which are reference voltage generators. Generator) 410 and current mirror circuit 21 200816373

Υο-υ i d TWB (current mirror drcuit) 410'. The reference voltage generator 41 产 can generate a reference voltage VR in the node R to avoid being affected by the voltage fluctuation of the external power supply voltage of the node 41 ". In addition, the external power supply voltage is also the input supply voltage of the reference voltage generator 410 (hlputsupply v〇ltage). The reference voltage generator 410 includes two voltage dividers, one comprising three P-type MOS transistors 41 〇 1, 41 〇 3, 41 〇 5 connected together, and the other is Two P-type MOS transistors 41 〇 2, 41 〇 4 are connected together. Continuing, the reference voltage Vr can be regulated by the connection of the drain of the P-type MOS transistor 4103 to the gate of the p-type MOS transistor 4104. Therefore, when the external power supply voltage Vdd fluctuates, the voltage of the node 上升 rises, resulting in a lower degree of opening of the p-type MOS transistor 4104, which in turn causes the reference voltage Vr to drop. Similarly, when the external power supply voltage Vdd falls, the reference voltage Vr rises. So far, the above has explained the adjustment characteristics of the reference voltage generator 410. The reference voltage produces 11-pass output for use as a current mirror circuit, and the reference voltage _, for an integrated circuit chip, the current mirror circuit 410 can output a stable power and/or a large power w 6 force, and by avoiding the direct high current path from the external power supply voltage to the ground tea test voltage Vss, the current mirror circuit can also eliminate huge power consumption or waste. In addition, through the p-type MOS transistor; and the pole is connected to the gate of the P-type MOS transistor 4106, and the output voltage section is connected to the reference voltage mirror (referenCe-V〇ltage mi^^) p Type MOS semi-electrode shed, Wei mirror circuit, can regulate the output voltage *, let the output 22 200816373

The voltage Vcc of MliCjAU6-Ul^TWB is controlled at a specified voltage. In addition, the conductance transistor 4112 is a small P-type MOS transistor, and its gate is connected to the ground reference voltage Vss, so the electrically conductive crystal 4112 is always on; and the electrically conductive crystal 4111 is It is a large p-type MOS transistor, and its gate is controlled by a signal Φ. When the internal circuit is in the active cycle, the electrically conductive crystal 4111 is turned on, and the p-type MOS is half-electric. The current path formed by the crystal "(9) and the sized metal oxide semi-transistor 4107 and the current path formed by the p-type MOS transistor 4110 and the N-type MOS transistor 4108 have a fast response (fast response) In addition, the opening of the electrically conductive crystal 4111 can be an internal circuit (for example, internal circuits 21, 22, 23 in FIGS. 1B to 1C, 2B to 2C, 3B to 3D, 24) The instantaneous transient instability of the output voltage Vcc caused by the large transient current demand is minimized. When the internal circuit is in the idle cycle, the transistor 4111 is turned off to avoid power. Consumption Consumption) a method of connecting an over-the-air interconnection of an internal circuit. The content disclosed in the prior patents by the patentee of the present invention, for example, U.S. Patent No. 6,657,310 No. 6,495,442, the thick metal conductor of the present invention (or a metal line or plane above the protective layer) can be used to distribute the signal, voltage or ground reference voltage. Additionally, the "protective layer" used above is used in the present invention ( The word oveivpassivation)" is the patentee of the present invention in the prior patent, Example 23 200816373

Mi^uA υο-υ 13IWB, as in US Patent No. 6,495,442, the term "post-passivation" is used, and the metal line or plane above the "protective layer" is used as a solid axis. (4) Lan Miseng. In this case, the thick metal conductor (or the money line or plane above the layer) can be used to transfer the miscellaneous or domain from the -th-inner (four) way to the (four) point (Qutput nQd_ to the first -||5 circuit An input node (lnput n〇de) designed to connect the two (10) switches of the phase (eg, over the wire) to her group (such as poor material, bit 兀 or 1fl address) A bundle of metal lines, for example, for connecting 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, 256-bit, 512-bit between a processor unit and a memory unit on the same wafer Yuan or 1024-bit data (or address) metal lines 'usually these metal lines are called bus bars ((4), this bus bar, such as the word used in the - note button (sud d) bus bar NZ (4) The bus bar. In addition, since the present invention provides a thick metal conductor (or a metal line or plane above the protective layer) over the protective layer to connect a plurality of internal circuits, and the thick metal conductor can be away from the semiconductor component, when the signal passes through the thick This signal can be reduced when the metal conductor (or the metal line or plane above the protective layer) The case of a square semiconductor component 'or 疋 can reduce the situation where the lower semiconductor component interferes with this signal, so that this signal has a side integrity. However, in the financial operation, the thick metal conductor (or protective layer) above the protective layer The upper metal line or plane) is only connected to the I circuit of the internal circuit and is not connected to an external circuit. It is also not connected to an external circuit. In addition, the present invention 24 200816373

ΜϋϋΑ 06-0151WB The thick metal conductor above the protective layer (or the metal line or plane above the protective layer) is designed differently than the conventional pad redistribution design. In addition, because the thick metal conductor (or the metal, the line or the plane above the protective layer) has the advantage of low resistance and the resulting parasitie capacitance is not low, the enthalpy will not be violently attenuated, so that the present invention _ is often suitable for high speed, low power, high current or low voltage applications. In most cases, the present invention does not require an additional amplifier, driver/receiver or signal repeater to help maintain signal integrity. However, in some cases, an internal driver (intemaldr (4), internal reception is required. IKinternal receiver), interface device or internal tri-state buffer from tri-statebufifer) 'to transmit signals over long distances' and internal drivers, internal receivers, internal 4=sorrow buffers ☆ or signal relays all include smaller size than the chip Circuit MOS transistor (MOS transist), as for the internal circuit, internal drive H, internal receive H, internal tri-state buffer, and the size of the gold-oxide semi-transistor of the external circuit of the die, It will be described and compared in detail in the following contents. Referring now to Figures 5B, 6B and 7B, a second embodiment of the present invention is disclosed. Figure SB shows a simplified The schematic diagram of the circuit, which is based on the Jinguan Road or Ping (4) Qian Lai layer on the Wei Wei 5, the fine line of the genus. The structure of the 63 碰 心 奶 卜 卜 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接=, 23^24). In Figure 5B, 'internal circuit 21 has an input node phantom, P point X 〇 and sends a signal through the output node, and this signal can be a secret word (four) object _ road metal Structure 敝, 632a, 632b, 632^ 25 200816373

The IVJLtSUA UO-U1DIWB 634 is transmitted to the input nodes u, vi, Wi of the internal circuits 22, 23, 24, and the internal circuit 21 can be a logic gate (such as a reverse gate). (NAND) gate, or (0R), and (AND) gate, or an internal buffer (such as inverters, internal drivers, or internal tristates shown in Figures 5C, 5D, and 5E) Buffering). Figure 6B shows a top plan view of the circuit shown in Figure 5B. Fig. 7B shows a schematic cross-sectional view of the circuit shown in Fig. 5B. Further, in the first and sixth objects, the line or plane formed on the protective layer 5 is "thick line," and the line structure formed under the protective layer 5 is "thin line," To represent. In the present invention, the internal driver for driving the metal wiring above the protective layer is the same as the in-wafer driver driver described in U.S. Patent No. (6) (the prior patent of the present patentee). Through the metal line or plane 83 on the protective layer $, the protective layer opening μ2 in the protective layer 5, 5%, and the fine line metal structure 63 632a, 632b, 632c, 634 under the protective layer 5, three internal logic circuits ( The internal circuits 22, 24 are inverted or gated, and the internal circuit Μ is and the gate can receive the data or signal transmitted by the internal 4 circuit 2ι. Since the metal line or plane 83 above the protective layer has low resistance and can produce low parasitic capacitance characteristics, the voltage amplitude (v〇itage swing) between the points Ui, Vi, and Wi between Vdd and Vss is very high. Small attenuation and noise. In addition, in the present embodiment, the metal line or the flat line does not need to be connected to any external circuit that will be used to connect to an external private path in the subsequent U (4), such as electrostatic discharge (4) (7) protection circuit, crystal # External drive, chip external receiver or chip external buffer circuit (such as wafer tristate buffer 26 200816373

Μϋϋ Α υο-υ 13 f WB circuit]) Therefore, this embodiment can improve speed and reduce power consumption. The same circuit is shown in FIG. 5A, FIG. 6A and FIG. 7A, which is a related art of the present embodiment. As shown in the figure, the internal circuit 21 located under the protective layer 5 is a thin-line metal. The structure 631 638, 6321a, 632ib is connected to an internal circuit 22 (e.g., a reverse or gate), is connected to an internal circuit 23 (e.g., a reverse) through the thin line metal structures 6311, 638, 6321a, and 6321c, and through the thin line. The road metal structures 6311, 638, 6341 are connected to other internal circuits 24 (e.g., a reverse or gate). Therefore, it is conventional to transfer the data output from the internal circuit 21 to the other internal circuits 22 23, 24 depending on the fine line metal structures (10), 0311, 632, and 6341 located under the protective layer 5. However, conventional designs can cause signal degradation, performance degradation, high power consumption, and high heat generation. Then, please refer to FIG. 5B and FIG. 6B simultaneously, which establishes a metal line or plane 83 on the protective layer 5, and replaces the fifth and eighth figures with a metal line or plane 83 located on the protective layer 5. The thin-line metal structure (10) in the first team diagram connects the internal D 23 24 by metal lines or planes 83. As shown in Fig. qing: - the signal is outputted by an output node of the internal circuit 21 (usually an internal circuit) The transmission is then transmitted through the thin-line metal structure 631 under the protective layer $, the protective layer opening 1 of the protective layer 5, and the metal line or plane 83' on the protective layer 5, followed by (1) the protective layer opening through the protective layer 5, and The underlying "wire metal structure 634" is finally passed down to the internal circuit 24 (for example, a reverse _ - wheel 峨 峨 is often the internal circuit 24 - MOS half transistor 27 200816373

Ivuiu a υο-υ id TWB gate, such as the gate of a gold oxide semi-transistor of the reverse or gate; (2) the protective layer opening 532 through the protective layer 5 and the fine-line gold structure under the protective layer 5 632 (including 632a, 632b, 632c), and finally to the internal circuit 22 (such as a reverse or gate) and the internal circuit 23 (such as a reverse gate) - the input node (usually the internal circuit 22 and the internal circuit 23 respectively) The gate of a MOS transistor is, for example, the gate of a reverse thyristor and a gate of a MOS transistor. Therefore, in summary, an output node of the internal circuit 21 (usually the recording of the internal circuit 21 and the recording of the semi-transistor) is connected to the lower layer-line metal structure 631, and then passes through the protective layer of the protective layer 5. The metal line or plane 83' on the opening connection protective layer 5 is finally passed through the protective layer opening of the protective layer 5, and the fine line gold structures 632, 634 under the protective layer 5 are connected, and further with the domain circuits 22, 23, 24 The input node (usually the internal circuit 22, 23, the gate of one of the MOS transistors) is connected. Wherein, the internal circuit 2, 22, 23, 24 includes a reverse thyristor, a sluice gate, and - and the squadron - and the internal circuit 2, 22, 23, 24 are composed of at least one MOS The composition, that is, the inverse or gate, or gate, and the closed or opposite gate to ^ is composed of a gold-oxygen semi-transistor, and the gold-oxygen semiconductor is, for example, the size (channel width_passivity ratio) N-type oxy-halide transistors between or between i and 5, or size (channel width divided by channel length ratio) between 〇.2 and 1G_ between Q 4 and 4 _ a p-type gold ^ semi-transistor 'level through the Jinlin Road remarks 83 current, such as between 50 micro-female, (μΑ) to 2 hairy female, or between the micro-ampere to 1 mAh 28 200816373

ΜϋυΑ υο-unTWB between the training. Continuing, please refer to both FIG. 7B and FIG. 7C, which are two embodiments of the pen path structure shown in FIG. 5B, as shown in the two figures, the metal line or plane 83 above the protective layer 5. It may be a single layer patterned metal layer (such as the single layer patterned metal layer 831 shown in FIG. 7B), or a multilayer patterned metal layer with a polymer layer between each adjacent patterned metal layer. For example, two layers of patterned metal layer 831 (including 831a and 831b) and 832 shown in FIG. 7C have a polymer layer 98 between the two patterned metal layers 831 and 832. Alternatively, the metal line or plane 83 above the protective layer 5 may cover a top polymer layer 99 (as shown in FIG. 7B, a top polymer layer 99 overlies the metal layer 831; as shown in FIG. 7C, a top end The polymer layer 99 is overlying the patterned metal layer 832), and the top polymer layer 99 does not have openings to expose the metal lines or planes 83, so the metal lines or planes 83 above the protective layer 5 (eg, the patterned metal layer 831 or The patterned metal layer 832) cannot be connected to an external circuit. In other words, in this embodiment, the metal lines or planes 83 (e.g., patterned gold, phylogenetic layer 831, or patterned metal layer 832) are not provided with contact pads for connecting external circuitry, in Figure 7B. The numbers of the patterned metal layer 831 are each represented by: "8, which represents the metal above the protective layer, "3" represents a signal line, and the shoulder, which represents the first-gold system above the protective layer. In Fig. 7C, the numbers of the patterned metal layer 832 are each representative. · "8" represents the metal above the protective layer, "3" represents the signal line, and "2" represents the upper layer of the protective layer (4) Metal 29 200816373

丄vuc^/\ υυ-υ 丄 j fWB layer. In addition, the patterned metal layer 831 on the protective layer 5 includes an adhesion/barrier/seed layer 8311 and a thick metal layer 8312, and optionally a polymer layer 95 is formed on the protective layer. 5 and the bottom layer of the patterned metal layer 831, as shown in Fig. 7D. Similarly, in FIG. 7C, the patterned metal layers 831a, 831b, 832 on the protective layer 5 include an adhesion/barrier/seed layer 8311a, 83nb, 8321 and a thick metal layer 8312a, 8312b, 8322, and also A polymer layer 95 can be selectively formed between the protective layer 5 and the patterned metal layer 831 (including 831a, 831b). The Fig. 7C is similar to Fig. 7B except that the structure above the protective layer includes two patterned metal layers 831 and 832. In FIG. 7C, the two patterned metal layers 831 (including 831a, 831b) and the patterned metal layer 832 are substituted for the single patterned metal layer 831 of FIG. 7B and separated by a polymer layer 98. The metal layer 831 and the patterned metal layer 832 are patterned. In addition, in terms of signal transmission, a signal is output from an output node of the internal circuit 21 (usually a MOSFET of the internal circuit 21), and then transmitted through the thin-line metal structure 631 under the protective layer 5, and is protected. A protective layer opening 531 in layer 5 and a patterned metal layer 831b' above protective layer 5 are then (1) in the first path: upward through polymer polymer layer 9831 in polymer layer 98, through patterned metal layer 832 Passing through a polymer layer opening 9834, passing through the patterned metal layer 83la, passing through a protective layer opening 534 of the protective layer 5, passing through the thin line metal structure 634 under the protective layer 5, and finally passing down to the internal circuit 24 ( An input node such as an inverse or gate (usually internal circuit 24 ~ 200816373

MJiCiA U6-U1MWB gate of a gold-oxide semi-transistor, such as the anti-gate or the gate of a gold-oxide semi-transistor); (7) in the second path: a protective layer opening through the protective layer 5 The thin line metal structure 632 under the protective layer 5 is finally transferred to an input node of the internal circuit 22 (eg, an anti-gate) and an internal circuit 23 (eg, an anti-gate) (usually one of the internal circuit 22 and the internal circuit 23, respectively). The gate of the MOS transistor is, for example, the gate of a reverse thyristor and a gate of a MOS transistor. The part of the metal circuit or the plane, the polymer layer and the internal circuit above the protective layer of the embodiment of the present invention will be followed by the series of the 15th, the 3rd, the 17th, and the 18th series. The details are shown in the 19th series. In addition, in FIGS. 5B, 6B, 7B, 7C, and 7D, the metal lines or planes 83 (including 831 and/or 832) are not connected to the wafers for connecting an external circuit. The external circuit is connected so that no significant voltage drop or signal attenuation occurs on the metal line or plane 83. In addition, the size of a MOS transistor of the present invention can be defined as the ratio of the channel width (channel Wldth) divided by the channel length, or precisely the ratio of the effective channel width divided by the effective channel length. This definition applies to all embodiments of the invention. Now, please refer to FIG. 5C to FIG. 5E at the same time, which exposes the internal circuit 21 as an example of an internal buffer, wherein the internal buffer is composed of a metal oxide semi-transistor (MOS). a transistor, such as a channel width/channel length ratio between 3 and 60 or between 5 31 200816373

MiiUA UO-U1M - p-type MOS micro-transistor between WB and 20 (pm) (pm), or channel width/channel length ratio between U and 3G or between 25 and iq An N-type MOS transistor, and the current flowing through the metal line or plane 83 is between 500 microamps to 1 amp milliamperes or between microamps to 2 milliamperes. between. The 5C indicates the reverse 211, which is used as the internal circuit 21 of the 5b, 6B, 7B, 7C, and 7D. In the first application, the size of the N-type MOS transistor and the p-type MOS transistor 21〇2 can be compared with the use of the slab circuit for the semi-electric crystal, so in the inverter 211 The size of the N-type MOS transistor 21〇1 is between 〇1 and 5 and is preferably between 0.2 and 2, and the size of the p-type MOS transistor 2 is Between G.2 money, and between 4 and 4 are preferred. In addition, the current output from the reverse phase H 211 and passing through the metal line or plane 83 above the protective layer 5 is between 5 〇 micro. The range between ampere (μΑ) and 2 mA, and preferably in the range between 100 microamps to 1 milliamperes. In the second application, the inverter 211 needs to output a larger one. Driving current (driwcurrent), for example, when the internal circuits 22, 23, 24 require a heavy load, or when the internal circuits 22 23 24 are separated from the internal circuit 21 by more than 1 mm or 3 mm and require a long distance When the metal line is connected, the inverter 211 needs to output a large driving current. In addition, the current from the output of the inverter 2 is higher than that of the general internal power. Road, and current 'for example 1 mA (!!^) or 5 mA, ranging from 5 〇〇 microamperes (μΑ) to 10 mA, and between 700 μA to 2 mA Between 32 200816373

Ivmu/\ υο-υ ι j TWB is better. Therefore, in the second detail, the size of the inverter type 211 MOS semi-transistor is between 1.5 and 30, and the cost is between 25 and 10. The size of the P-type MOS transistor 21 〇 2 is in the range of 3 to 60, and preferably in the range of 5 to 20. The details of the size of the MOS transistor for the (-) internal circuit or the circuit for driving the (4) negative-axis circuit will be described in detail in the subsequent figure. ^ ▲ In addition, in Figure 5C, the metal line or plane 83 above the non-polar system of the N-type oxy-oxygen semi-transistor fiber and the protective layer 5 (as shown in Figure 5b, Figure 6B, Figure 1, Figure 7C) Connected to the 7D), and the P-type MOS transistor 2102 has a metal line or plane above the protective layer 5 as the sb, 狃, 7B, 7C _ Figure 7D shows) connection. In the application of the large 4 knife 'because of the metal line or plane above the protective layer and the small impedance, the multiple internal circuits formed by the smaller metal oxide semi-transistors pass through the metal lines on the protective layer. Connection, wherein the facial circuit includes a size (channel width divided by channel length ratio) between Gih or between Μ to 2, a Ν-type MOS transistor, or a size (channel width divided by The ratio of the length of the channel is between 0.2 and 10 or between one and four (4) gold crystals. In addition, on some Lang, when the internal circuit ^, Μ, !: or t is internal When the circuit 22, the object part electric pen meter or 3 pen meters and need a long distance connection metal line, it needs a larger 33 200816373

Drive current of MECiA06-0I5TWB. Therefore, 'in the case of high load, __ internal drive is required from temai drive) or an internal buffer (intemai bugfer) 〇 5D and 5E are revealed as internal driver 212 or internal tristate buffer 213 The internal circuit 2 uses the internal driver 212 or the internal tristate buffer 213 to drive the metal line or plane 83 on the protective layer 5 as shown in the first diagram, the fourth diagram, the 7th Bffi, and the 7th to 7th. And other examples of internal circuits ^, 23, 24. The circuits shown in FIGS. 5D and 5E are (1) internal driver 212 or internal tristate buffer, 213 not connected to an external circuit; and (7) internal driver m or internal tristate buffer, 213 gold oxide half transistor The size is smaller than the size of the MOS transistor of the wafer-external driver or the wafer tri-state buffer, and the others are similar to the chip-out circuit (〇ff_chip drcuit) described in the back sheet 11A and the lie sheet, respectively. The internal driver 212 in Fig. 5D is an example of an intra_chip driver described in the U.S. Patent No. 20040089951. The internal tristate buffer 213 provides the drive capability and swkch capability of the amplified signal, and the internal tristate buffer H 213 is particularly useful for the protection layer of the riding or address bus. The metal line or plane transmission - memory crystal #巾's - #料喊 or - address signal. In the 5D figure, the size of the N-type MOS transistor 21〇3 is between 15 and 3 ,, and preferably between 2.5 and 10, and the p-type MOS transistor The size of 2104 is between 3 and 60, and between 5 and 2 is preferred. 34 200816373

The IVlHU/\UO-U1D fWB additionally reds the current of the metal line or plane 83 on the layer 5 and the internal driver commits the output node X. The current output (usually the female of the metal-semiconductor element) is in the range of microamperes to 1G milliamperes, and is preferably in the range of between ampere and 2 milliamperes. In addition, in FIG. 5D, the internal driving pirate 212 can drive a signal outputted by the output node ,, and after passing through the metal line or plane 83 above the protective layer 5, it is transmitted to the input circuit of the internal circuit. Vi, Wi' but not transmitted to - external circuit. In Figure 5E, the size of the N-type MOS transistor is between 1 $ and : = between 2.5 and 1 ,, and the size of the p-type MOS transistor 2108 is Between 3, 'Asian 7 丨 between 5 and 20 is better than the second t Shield 5 above the gold riding flat * 83 like (10) three-state slow = = the node X ° wheeled current system Microamperes to 丨 at 5°°. mAh is good. Another Asian heart to microamperes to 2 mAh _ range is more than _ XoZ brother 5E figure 'internal tristate buffer 213 can drive from the output illusion, pass and above the Congxian County 5 Jinlin Road or plane is , two =:, 23, 24 —,” 23, 2=^2a α requires a high load, or when the internal circuit 22, the connection is ^ ^ distance is greater than 1 mm or 3 milliseconds and requires a long distance out node When f is in the 'internal drive 212 and the internal tristate buffer, the output is required to output a large drive current. 35 200816373

One of the important applications of the MliUAUO-Ul^rWB metal line or plane above the protective layer is a memory cell (mem〇ry cdl) and an internal circuit (such as a logic circuit) spaced apart by a distance from a memory chip. Referring to FIG. 5F, it is revealed how a memory cell is connected to the internal circuit D, 23 as a logic circuit by using a metal line or plane 83 on the protective layer 5 and a thin line metal under the protective layer 5. 24 (Fig. 5B, Fig. 6B, Fig. 7B, Fig. 7C, and Fig. 7D). Wherein, the logic circuit includes, for example, a -re-gate, - or a gate, a gate or a reverse and a closed, and the internal circuits I 23, 24 may be at least composed of a gold-oxygen semiconductor, and the above-mentioned thin wires The metal structure of the circuit is a gold-oxide semi-electrode connected to the internal circuits 22, 23, 24, for example, a source connected to a MOS transistor, a bungee (four) or a closed-pole ((4). The transistor may be a -N type MOS transistor having a channel width/channel length ratio between 〇1 and 5 or between 0.2 and 2, or a channel width/channel length ratio between G.2 and -p-type MOS transistors between 1 或 or between 4·4 and 4', and the current flowing through the metal line or plane 83 is, for example, between % microamperes to 2 amps or Between 1 〇〇 microamperes and 丨 milliamperes. In this case, the metal lines on the protective layer 5 or the flat & 83 are used as a data bus, such as a bit line (5) (four) bus or A reverse bit line (M lme) bus bar. In the design of a memory array $J (mem〇ty navigator) and logic circuit, can be in the protective layer 5 Forming parallel lines of 4, 8, m from, 128, 256, 512, 1024, 2048, or 4096 metal lines or planes 83 as data busses for memory chips, and benefiting these metal lines or planar illusions 36 200816373

Ινΐϋ〇/\ υο-υ l d TWB The data signal between the memory unit and the logic circuit. The metal line or plane 83 above the protective layer 5 is particularly suitable for transmission over a wide bit (for example, a transmission of 64, 128, 256, 512, 1024 bit widths.) When transmitting a signal between a memory unit and a logic circuit, the metal line or plane 83 above the protective layer 5 can be used as an address bus in addition to the above-mentioned data bus. The signal transmitted by the metal line or plane 83 on the protective layer 5 also includes a clock (d〇ck) signal. The 5F is a static random access memory unit 215. An example of a memory unit, but the memory unit in this embodiment may also be another memory unit, such as a dynamic random access memory (DRAM) unit, and an erasable programmable read-only body (EPROM). Unit, electronically erasable read-only memory (EEpR〇M) unit, flash memory (Flash) unit, read-only memory (R〇M) unit, and magnetic random access memory (MRAM) unit This static random access memory unit 21 5 includes six MOS semi-transistors, which are two driven N-type MOS transistors 2115, 2117, two load 1 > type MOS transistors 2116, 2118, and two word lines - control (word-line-control) N-type MOS transistors 2119, 2120. In addition, in a memory chip, a memory array can be formed by repeating the SRAM cell 215. When static random access When the memory unit 215 is in the read state, the SRAM cell 215 outputs complementary data, such as bit (secret) data and inverted bit (secret) poor material, and respectively passes through the N-type MOS transistor. 2119 and N-type MOS semi-transistor 2120 pass the complementary data to the bit (secret) line and reverse 37 200816373

Μϋ〇Α υο-υ ι d TWB bit two) line, then bit 〇) data and reverse bit (clear) data transfer through row selection (CS) transistors 2122, 2123 and then input to a sense A sense amplifier 214. Then, the bit line of the memory cell is connected to the gate of the N-type MOS transistor 2113 in the sense amplifier 214, thereby controlling the opening or closing of the N-type MOS transistor 2113 of the sense amplifier 214. When the N-type MOS transistor 2113 of the sense amplifier 214 is turned on, the sense amplifier 214 can initially amplify the inverted bit 〇 data to have a better waveform or a better voltage level, and output the same The amplified inverted bit (^) data is initially caused to the internal tristate buffer 213. In FIG. 5F, a differential amplifier is used as an example of the sense amplifier 214. The differential amplifier includes four transistors, including two N-type MOS transistors 2111, 2113. And two P-type MOS transistors 2112, 2114, wherein the differential amplifier uses the N-type MOS transistor 2121 to isolate the differential amplifier and the ground reference voltage Vss, and controls the differential by one line selection signal Amplifier to avoid power consumption. When the SRAM cell 215 is not in the read state, that is, when both the word line and the bit line connected to the SRAM cell are not selected, the N-type metal oxide half-electric day The Japanese body 2121 is closed. The reverse bit (product) output from the gate of the N-type MOS transistor 2113 of the sense amplifier 214 is transferred to an internal driver, internal buffer or internal tristate buffer 213 (as shown in Figure 5F). The input node Xi. In addition, the control signal (5), $ is output from - read (four) enable, road (not shown) and uses this control signal to control the opening or closing of the internal tristate buffer 213. In the 5F®, the internal tristate buffer 213 is 38 200816373

Iviiiu/\ υο-υ 13 TWB output node X〇 outputs more amplified bit data through the metal line or plane 83 on the protective layer 5 to the internal circuits 22, 23, 24 (eg, the first map, the sixth map, the first 7B, 7C and 7D). Therefore, in summary, as described above, the static access memory unit 215 is protected by the sense amplifier 214, the internal three-state stimuli, the fine-line metal structure 63 under the protective layer 5, and the protection layer 5 The metal openings or planes 83 on the protective layer 5, the protective layer openings 532, 534 in the protective layer $, and the fine-line metal structures 632, 634 are connected to the internal circuits 22, 23, 24 of the same wafer 2, such as 5B, 6B, 7B, 7C, and 7D. The internal circuit 21 is here an internal tristate buffer 213, but the internal circuit 21 can also be the internal driver 212 (as shown in the figure) or other internal circuits, such as the inverse or gate ^OR (four), the opposite And the guide gate, and the gate (AND gate), _ (〇R _), adder (adder), multiplexed cry __), duplexer, called, multiplication, ah Ling complementary metal: semiconductor, A bipolar-complementary MOS or a bipolar circuit, and when the internal circuit knives are internal drivers, the internal circuit is at least composed of a MOS transistor and the MOS transistor includes Channel width / channel length ratio between 3 and 6G or between 5 and 2G riding - p-type MOS semi-transistor ' or the width / channel length ratio between ls to 3 或 or between h -N-type gold-oxide semi-transistor to between 10 and the current flowing through the metal line or plane 83 is between 500 microamps to 1 milliamperes or between microamperes to 2 milliamperes. In addition, when the internal circuit 21 is the other internal circuit described above: 39 200816373

MJbUA υο-unfWB This internal path 21 includes at least an N-type MOS transistor with a channel width/channel length ratio between 〇1 and 5 or between 0.2 and 2, or a channel width/channel length A p-type MOS transistor having a ratio between 〇·2 and 10 or between 44 and 4, and the current flowing through the metal line or plane 83 is between 5 〇 microamperes to 2 Between milliamperes or between 100 microamperes and 1 ampere. Referring to FIG. 5G, the reverse bit (product) data outputted by the sense amplifier 214 will pass through a pass circuit 216 before reaching the output node of the internal circuit 21. Circuit 21 is pass circuit 216. This pass

Circuit 216 can be a simple MOS transistor, such as N-type MOS transistor 2124, and is controlled by a read signal. In this design, a static random access memory cell 215 is transmitted through the sense amplifier 214, through the circuit 216, the germanium line metal structure 63 under the protective layer 5, the protective layer opening 531 in the protective layer 5, and the protective layer 5 The upper metal line or plane 83, the protective layer openings 532, 534 in the protective layer 5, and the thin line metal structures 632, 634 under the protective layer 5 are connected to the internal circuits 22, 23, 24' as shown in Fig. 6B , Figure 7B, Figure 7C and Figure 7D. As shown in Figure 5H, the inverted bit (1) data output by the sense amplifier 214 will pass through a latch circuit 217 ' before reaching the output node of the internal circuit 21 The internal circuit 21 is the flash circuit 217. The path 217 can be a static random access memory unit for temporarily transmitting the data of the sense amplifier 214 before the logic circuit (such as the internal circuits 22, 23, 24). Storage 200816373

Ϊ́νΐϋ^/\ UO-U1J TWB Stores the data of the amplified 214 output (that is, the data is latched). Alternatively, the N-type MOS transistors 2129, 2130 can be controlled by a read signal. In this design, a static random access memory cell 215 is transmitted through the sense amplifier 214, the latch circuit 217, the thin line metal structure 63L under the protective layer 5, the protective layer opening 53W in the protective layer 5, and the protective layer 5 The upper metal line or plane 83, the protective layer openings 532, 534 in the protective layer 5, and the thin line metal structures 632, 634 are connected to the internal circuits 22, 23, 24, as shown in Fig. 5B, Fig. 6B, Fig. 7B, 7C and the claw diagram show 0. However, the pass circuit 216 of the 5Gth diagram or the latch circuit 217 of the 5Hth diagram does not provide a large drive capability. In order to drive the internal circuit 22, 23, 24' requiring high load or the bit (5) of the output of the reverse bit (_) data or the latch circuit 217 outputted by the circuit 216 for long distance transmission to the internal circuits 22, 23 24, an internal driver mentioned in the above may be added at an output node of the circuit (as shown in FIG. 51) or an output node of the flash lock circuit (as shown in FIG. 5J) to utilize the internal driver 212. The data output through the circuit 216 and output to the bit (5) data or the flash lock circuit 2 port is amplified. Referring to Figure 5, except that the internal circuit 21 receives signals from the internal circuit 24 (here, the -reverse or gate), rather than driving the internal circuit 24, the remaining circuit design is similar to that of Figure 5. The internal circuit 24 (here, a reverse or gate) 疋 passes through the thin-line metal structure 634 under the protective layer 5, the protective layer opening 534' in the protective layer 5, the gold-plated line or the planar illusion on the protective layer 5. Protection in protective layer 5 200816373

The MEGA 06-015TWB layer opening 531' and the thin line metal structure 631 under the protective layer 5 transmit a signal or data sent from the output node Wo to the wheel node % of the internal circuit 21 (through the internal circuit 21) One of the gates of the gold-milk semi-transistor), and the internal circuit is here a reverse or gate) also passes through the thin-line metal structure 634 under the protective layer 5, the protective layer opening 534' in the protective layer 5, a metal line or a plane on the protective layer 5, a protective layer opening 532 in the protective layer 5, and a thin line metal structure 632a', 632b under the protective layer 5, and a path 22 sent from the output node Wo (here The input node u is an inverse or gate). Furthermore, the internal circuit 24 (here, a reverse or gate) also passes through the thin-line metal structure 634' under the protective layer 5, the protective layer opening 534 in the protective layer 5, the metal on the protective layer $ or The plane 83, the protective layer opening in the protective layer 5 is light, and the thin line metal structures 632a, 632c under the protective layer 5 transmit the signals or data sent by the output node w to the internal circuit 23 (here - Inverse gate % of the input node. Wherein, the fine-line metal structures 634, 631 may be formed by metal lines and planes, and in this example, the thin-line metal structures 634, 631 are made of conductive plugs and metal pads and thin lines in the dielectric layer. The metal layers are formed, for example, in an approximately aligned stack. f Some of the accumulated occupational shots, guides the handle of the crane (4) or iron ^^ (damascene copper) 〇 21,22 ^ ^ χ., ^

Ui, Vi receive the signal, and at the output node χ〇, , (5), % output the signal to the internal circuit of the basin. In addition, the internal circuit 21 may be an internal receiver 212 (as shown in FIG. 5L) and an internal tristate buffer 213 (if the field indicated in the measurement is other 42 200816373

Ινΐϋ〇/\ υο-υ ι j TWB internal circuits, such as reverse or gate (N〇R gate), reverse gate (AND), or gate (〇R gate), operational amplifier (〇 Perati〇nal fat sentence, adder, multiplexer, duplexer, multiplier, analog/digital converter (A/D c〇nverter), digital/analog conversion (D/AConverter), a complementary metal oxide semiconductor, a bi-carrier complementary MOS or a bipolar drcuit, and when the internal circuit 21 is an internal receiving junction 212', the internal circuit 21 is at least a gold-oxygen semi-transistor comprising a channel width/channel length ratio between 3 and 6 或 or between 5 and 汾 - P-type MOS (s) or channel An N-type MOS transistor having a width/June ratio between 1. 5 and 30 or between 2.5 and 1 G, and the current flowing through the metal line or plane 83 is between 5 〇. 〇 microamperes to (7) milliamps or between 700 microamps to 2 milliamps; in addition, when the internal circuit?! In the circuit, the internal path 21 includes at least a channel width/channel length ratio between 0.1 and 5 or between 〇·2 and 2, an N-type MOS transistor or a channel width/channel length ratio. a Ρ-type MOS transistor between α 2 and 1 G or between 4 4 and 4, and the current flowing through the metal line or plane 83 is between 50 μA and 2 mA or It is between ι 〇〇 microamperes and 1 milliamperes. In addition, the internal circuit 21 also includes a static random access memory unit (SRAMcdl), a dynamic random access memory unit (DRAMcell), and a non- Volatile memory cell (non-volatile _〇ry cdl), flash memory memoty cell, erasable programmable read-only memory unit (EpR〇M(2)u) 43 200816373

MJtiUAU6-Ul^TWB read-only memory unit (R〇M eell), magnetic random access memory (disarmed RAM MRAM) unit or sense amplifier (sense). In addition, the input node of the internal circuit 21 is a gate of a MOS transistor. Please refer to the internal receiver 212 shown in the figure, which can receive the signal via the metal line or plane % on the protection layer 5 and output a signal from the output node Xo to other internal circuits, but the signal is not output. To - external circuit. Referring to FIG. 5M, the internal three-way buffer commits a signal through a metal line or plane 83 on the protective layer 5, and outputs a signal from the output node Xo to other internal circuits, but does not The signal is output to an external circuit. In the 5th L picture, the N-type oxy-oxide semi-transistor is fine, and the size is between i 5 and 3 ' 'and is preferably between 2.5 and 2. The w-type MOS transistor 2 is given. The size of the input is between 3 and 6G, and between 5 and 2 (), in addition to the metal line or plane 83 above the protective layer 5 and the input current receiving _, the input node Xi current system The range between the microamperes and the milliamperes is preferably between 700 microamperes and 2 amps. In addition, the input node edge of the internal receiver can accept the internal circuit 24 to the φ-ϋ line via the road or plane 83, and the 4th wheel_point bird output-signal sub-reception-continuation sacrifice, (4) = Figure, Figure 7C and Day 7D. In the 5th to 5th pictures of Lechuan, the two sisters, Fu Jie, will reveal the design of the internal circuit 24 (logic gate, rounded-out data to memory-memory unit memory. I. 44 200816373

Ινΐϋ〇/\ υο-υ ι d TWB See the fifth and fifth figures, the internal circuit 21 can be an internal three-state buffer 213'. The internal tristate buffer 213 has the function of amplifying the data and the switch, and the control nickname office and the office output are from a reading circuit (not shown), and the control signal is used to control the internal tristate. The buffer 213 is turned on or off. In addition, through the metal line or plane 83 on the protective layer 5, one bit (four) data can be transferred to the input node Xi of the internal tristate buffer 213, and when an amplified reverse bit two) is poor For a supply voltage, the amplified reverse bit (should) data is from the p-type MOS transistor 2110, output to the reverse bit protection) line, and when an amplified reverse bit is two) the data is For the ground reference voltage, the amplified reverse bit (6) data is output from the n-type MOS transistor to the inverted bit (four) line. The output node χ〇, the output amplified reverse bit (8) data can be transferred to the SRAM cell 215 via the row select transistor 2122 controlled by a row select (cs) signal and via the N-type MOS transistor 2119. . Please also refer to FIG. 5K and FIG. 5N. The internal circuit 24 (here, a reverse or gate) is through a thin-line metal structure, 4, a protective layer opening 534, and a metal above the protective layer 5. A line or plane 83, a protective layer 531 thin line metal structure 631' and an internal tristate buffer 213 transfer the material to a static random access memory unit 2 in a memory array. Referring to FIG. 50, the bit readout output from the internal circuit 24 (here, a reverse or gate) is passed through the pass-through circuit 216, and then connected to the bit line of the SRAM. The human static random access memory unit 215 is written by row selection. Among them, the internal circuit 21 in the 5K diagram is a pass-through 45 200816373

JVLbLrA U0-UJ3 fWB circuit 216', and this through circuit 216, can be a simple gold oxide semi-transistor, such as N1 gold oxide solar cell 2124 ', and by a write signal (write such as Zhanhua Ming 3〗) Household control. In this design t (please refer to both FIG. 5K and FIG. 5), a data output by the internal circuit 24 (here, -reverse or inter-) is outputted through the following means - The SRAM cell 215+: passes from a thin-line metal structure 634 up through a protective layer opening 534, through a metal line or plane 83 on the protective layer $, and passes down through a protective layer opening 531. , a fine-line metal structure (8), a pass circuit 216, and then connected to the bit line of the SRAM cell array, and then write the human smart_access memory unit 215 through the lion transistor . " 言月 see the SP picture shown in the 'the system is similar to the first crime map, the input bit can be temporarily stored or locked in a flash lock circuit claw before writing to the static random access memory unit. . Another 'N-type gold oxide semi-transistor help, coffee, used as a writer's control. In the discriminating towel (please refer to the first figure and the figure ==), the output of the internal circuit 24 (here, a reverse or gate) output node w〇 is written by the following means - static The mining machine stores the mosquito memory in the single body from the thin metal structure 634, and goes up through the protective layer opening, and a metal line or plane 83' on the protective layer 5 goes down through a protective layer. A fine line metal structure 631, a flash lock circuit is added, and is connected to the bit line of the access memory unit array, and then enters the static random access memory unit 215 through the row selection transistor. 46 200816373

MJbUAUO-UI^TWB However, the pass circuit 216 of Fig. 50, or the flash lock circuit 2 of Fig. 5P, may not provide sufficient sensitivity to detect weak signals at the input node. In order to restore the weak data signal, an internal receiver 212 can be added, either at the input through circuit 216 (as shown in Figure 5Q) or at the input of _ circuit ^ (eg 5R) Figure shows). Another important application of the connection line above the protective layer is the transmission of accurate analog signals. The resistance and capacitance per unit length characteristic of the metal line or plane above the protective layer provides a digital analog analog signal with low signal distortion. Referring to the % diagram, it is revealed that the metal line or plane 83 on the ugly layer 5 is connected to an analog-like analog design. The signals transmitted by the internal circuits 21, 22, 23, 24 are analog-mode circdts, metal lines or planes 83 are digital analog analog signals and the internal circuits 21, 22, 23, 24 are output/received. In addition to the analog-to-digital analog analog signal, the design of the 5S picture is similar to that of the 5th picture: In the 5S picture, an output node of the internal circuit 21 is connected to the fine line metal structure 631 'and then protected upwards The layer opening 531 of the layer 5 is connected to the metal line or plane 83 on the protective layer $, and then the thin line metal structure 632 is connected through the protective layer openings 532, S34 (including gamma, _, _, 634, and finally fine line metal is used). , 632 (including 632a, 632b, 632c), 634 connected to the internal circuit 22, 23, 24 - input node w, w, s, where the internal circuit 2 as an analog circuit 22 22, 23, 24 The system includes a P-type gold oxide semi-transistor and an N-type gold oxide semi-electric crystal 47.

JVLE\J/\ uo-u 丄]rWB body, NOR gate, NAND gate, AND gate ^ -icffl(ORgate) ^ (sense amplifier) &gt ; Operational Amplifier, a class of analog/digital converters (_(;〇1^1^), a digital/analog converter (D/A Converter), a pulse reconstruction circuit (pUise reshaping circuit), A switched-capacitor filter, a RC filter, or other types of analog circuits. For other related parts, please refer to Figure 5B, which will not be described in detail here. Referring to FIG. 5T, an example in which the internal circuit 21 in FIG. 5S is an operational amplifier 218 and the output node γ0 is connected to the gold trace or plane 83 on the protective layer 5 is disclosed. The amps are designed according to a complementary metal-oxide-semiconductor (CMOS) technology. Please refer to the CM〇s Digital Circuif and Differential Analog Signals issued by Prentice-Hall in 1987. Input to two >fg|N type MOS transistors 2125, 2127 and two P-type MOS transistors 2126 2128 formed a differential circuit (female than the 'CirCUit) 219 input node you and Zhazhong, where the input node Y1+ and Yi_ are connected to P-type MOS semi-transistor 2126 and P-type oxidized half The gate of the transistor is welcoming. The differential circuit 219 is connected to the N-type MOS transistor in the output of the N-type MOS transistor 2127 and the p-type MOS transistor 2128. a gate and a capacitor on the first electrode of the capacitor 2133. One round of the node is connected to the second electrode of the capacitor H 2133, the N-type semi-transistor 2135 secret and the p-type MOS semi-transistor 2136 Therefore, the signal at the output node γ〇 can be 48 200816373

The ivuiu/\uo-uidTWB is controlled by the degree of opening of the N-type MOS transistor 2135, wherein the n-type MOS transistor 2135 is also controlled by the output of the differential circuit 219. The power node P of the differential circuit 219 is connected to the drain of the P-type MOS transistor 2132, wherein the differential circuit 219 is a P-type MOS transistor and a p-type MOS transistor. 2128 is mixed with the power supply (four) p. In addition, the voltage level of the p-type MOS transistor 2 like the interface is controlled by the resistor 2134. Further, the signal output from the differential circuit 219 can be amplified by the capacitor (10). Capacitor 2133 is often used in the design of an analog circuit, and is usually a metal-oxygen half-capacitor (M〇sc-shaped (four) or 曰曰 曰曰 夕 对 对 晶 晶 夕 夕 夕 ( ( (p〇ly_t〇_ P〇ly capacit〇r) is formed, wherein the gold semi-capacitor _ makes the twin (four) pole (pQly gate__sm_ as the two electrodes of the capacitor 2133, and the polycrystalline pair of polycrystalline capacitors uses a eve of the meteorite Poly silicon and a second polycrystal are used as the two electrodes of the capacitor 2133. The resistor is also often used on an analog circuit, and is usually doped with an impurity in the shi shi substrate (impurity-doped Diffilsi〇n area), for example, n well, p well, N+ diffusion, P+ diffusion, and/or heterogeneous f doping (10) (4) 叩 ~ ~ silicon). Poor example · The complete structure of the present invention. Silk County is said to be fine metal (the technique of hiding or flattening above the layer can provide additional wafers. 4. The material of the thick metal conductor above the protective layer (or the metal line or plane above the protective layer) includes gold, Copper, silver, 姥, 姥, Ming, 胄 _ 'There are miscellaneous (10) handles, the village is other 49 200 816 373

IVLiiUA uo-uidTWB touch structure. Use a variety of different types of contact structures, such as solder bumps (10) 1 (1 sink bump), solder pads, solder balls, gold bumps (Au bomp), gold pads ( Gold pad), palladium pad (1> (1 Qiu (1), aluminum pad (8 1 1 (1) or wire bonding pad), the wafer can be easily used to connect with external circuits by different methods In Figures 5B, 5K, 5S, 7B, 7C, and 7D, the metal lines or planes above the protective layer are used to transmit signals output or input from internal circuits, and internal The circuit is not connected to an external circuit. However, a b-chip must be connected to an external circuit and transmitted to an external circuit. Next, please refer to Figures 8B to 8F, 9B to 9D, and 10B. Figure 1 to Figure 1 shows a complete structure of the present invention, and as a third embodiment of the present invention. Figs. 8B to 8F, 9B to 9 and Figures MB through 101 illustrate how the signals generated by the internal circuitry pass through the metal lines or planes above the protective layer and under the protective layer. The thin-line metal structure is transferred to the external circuit, or the signal generated by the external circuit is transmitted to the internal circuit through the metal line or plane above the protective layer and the thin-line metal structure under the protective layer. 8B to 8F, 9B to 9D and 1D to 2D are respectively a circuit structure, a top view and a cross-sectional view of the present embodiment, which are an internal wafer design in which an internal circuit is connected to an external circuit to reveal the use of the fine line metal of the present invention. The structure and the complete structure of the metal above the protective layer. In addition, the internal circuits 2〇 (including 21'22, 23, 24) described in Figures 5b to 5T, 6B and 7B to 7D are also The internal circuit suitable for use in this embodiment includes 21, ^, 200816373

Ivmu/γ uo-uoTWB 23 - 24) In the present embodiment, the signal of the internal structure 200 is transmitted to an external circuit (not shown) through an off-chip structure 400, such as the 8th figure. The signals shown in the external circuit (not shown) are transmitted to the internal structure 200 through the 接fr_chip structure, as shown in FIG. 8C. The metal line or plane 83r above the protective layer 5 can be used as a reconfigured line of a fine-wire metal structure (wheel input/output) pad (for example, the metal pad 6390 in FIG. 10B), in other words, a thin line. The metal structure (input/output) pads are repositioned to a different location of the pads using a reconfigured line (eg, contact pads 831 in Figure 10B) and then utilize a wire or bump on the pad. Connected to an external circuit, so the position of the pad is different from the (input/output) pad position of the thin-line metal structure, as viewed in a top perspective view, for example, in Figure 10B, viewed from a top perspective view, contact The position of the pad 831 is different from the position of the metal pad 6390. Further, the thickness of the reconfigured line for forming the contact pad 831 is greater than 1.5 microns. Alternatively, the metal lines or planes 83r on the protective layer 5 may be formed simultaneously with the metal lines or planes 83 on the protective layer 5. The current flowing through the metal line or plane 83 is between 50 microamps and 10 milliamps. The contact pads 8310 exposed by the polymer openings 9939 located in one of the top polymer layers 99 can be connected to an external circuit using wire bonding or other bonding methods as described in the subsequent series of Figure 15. In addition, for flip chip assembly (flip_chip aSSembly), Tape Automated Bonding (TAB) or others as follows 15 51 200816373

The bonding method described in the JVLtiUA Ub-unfWB diagram series can selectively form a contact structure 89 on the contact pad and in the polylayer opening. As for the formation of the contact structure, the financial method and its detailed description will also be followed. Figure 15 _ paid. The flip pad can be connected to the external circuit 40 of the wafer. Thus, in conjunction with the above description, the wafer is externally structured. It includes a die attaching circuit 4, a metal bond, a contact structure 89 (selective), and a reconfiguration line 8 above the protective layer. The wafer external circuit 40 includes a -chip external input/output circuit as a wafer external circuit 42 and at least - Electrostatic Discharge (ESD) as a wafer external circuit 43. The external circuit 43 includes two electrostatic discharge protection circuits. In the above, the chip external input/wheeling circuit may be a chip external driver, a chip external receiver or a chip external buffer (for example, a wafer tristate buffer), and the related content is respectively 2 11A, ι1Β, nc, and nE are condensed; in addition, the ESD protection circuit can be composed of two reverse biased diodes (the _31, 4332). As shown in Fig. 11F, the size of the recording half-crystal in the external input/round-out circuit of the wafer and the size of the gold-oxygen semiconductor in the internal circuit will be described in the series of the 15th figure. Figure 8A, 9A Figure and Figure 10A are the design structure of the conventional wafer. As shown in the figure, all the circuits (including the internal circuit 2, 22, 23, 24 and the external power of the wafer) are smashed through the fine-wire metal structure (10). Including $ milk a, 6321b, c) 6341, 6391 are connected to each other, but there is no use protection 52 200816373

The metal line or plane above the MbUA 06-015TWB layer connects all circuits, knowing that the position of the external connection pads is reconfigured using a reconfigured metal line above the protective layer only when the contact structure is tin-lead. Please also refer to Figure 9B and Figure 1B for the circuit shown in Figure _. Also take a look at the unintentional and cross-sectional schematic. An internal circuit is connected to the contact pad or contact structure 89 through the path described below, and the signal generated by the internal circuit 21 is transmitted to an external circuit: the internal circuit first passes through a thin line metal structure 63i and passes upwards. a protective layer opening 531 continues through a single layer (such as the patterned metal layer in the figure) or a plurality of metal lines or flat (four), and then passes through the protective layer opening 539, and the fine line metal structure 639, The turn-in node connected to the die-out circuit 42 is further connected to the signal contact of the chip-connected circuit 42 as the electrostatic discharge protection circuit through the fine-wire metal structure 69, and then goes up. A thin metal structure _ and a protective layer opening 539' are finally connected to the contact 831 〇 or the contact structure 89 via a metal line or plane 83r as a reconfiguration line above the protective layer. In addition, the method of connecting the external circuit 42 to the external circuit 43 of the wafer may also be achieved by using a metal circuit or a plane above the protective layer to achieve both the metal line and the plane above the protective layer. Replace the fine line metal structure 69. Referring to Fig. 10C, it is disclosed that the metal wiring or plane 83 has a patterned metal layer 8S 832 similar to that shown in Fig. 7c. In addition, Fig. 10E and Fig. 10E are added between the protective layer 5 and the bottommost end of the patterned gold layer 831 53 200816373

丄υυ-υ 丄 jTWB A polymer layer 95, the others are similar to the 1GB chart and the 1GC chart, respectively. Referring to the indications, the original metal interface 6390 can be reconfigured to the contact pad on the protective layer 5 by using the metal line or plane 83r as a reconfigured line. Use the reconfiguration line to reconfigure the input/output pads, especially in stacked package flash memory, dynamic random access memory or SRAM chips, and add the disgusting machine to access the input/round of the memory chip.塾通当县 is roughly designed in the middle of the line, on the line, _ law is in the material. However, by reconfiguring the central interface to the crystal (10) with a metal trace or plane 83r as a reconfigured line, the crystallographic body can be used for wire bonding in a job (e.g., stacked package). Please refer to both the ship map and the 1GG figure, which are specific examples of the contact joints 10 having a wire bond. In the figure of the second and the first leg, a static random access memory unit is used to connect the memory unit to the input node in the internal circuit 21, and the internal circuit U and the memory are related. The method in which the body unit is connected to the internal circuit has been described in the figures to 5J, respectively. First, as shown in Figure 1, F, a static random access memory cell, a flash (four) single-chip random access memory cell connected to the outer 4 circuit is via (1) sense amplifier; (2) internal buffer , pass circuit, flash lock circuit, pass circuit oil drive or _ circuit and internal drive; (3) fine line metal structure 6311; (4) fine line metal structure 638; (5) via thin line metal structure hidden, connected to - the input node of the external circuit of the wafer; (6) via 54 200816373

MECiA 06-015TWB is connected to the fine-wire metal structure by the output node of the external circuit 42 of the chip, and is connected to the electrical circuit by the metal structure 69 of the circuit, and is connected to the external circuit (7)-protective layer opening 539; (8) As one of the reconfiguration lines, all of the lines or planes 83r, (9) are exposed through the contact opening of a polymer layer; and (10) a line of wire 89 is contacted through the contact coffee. = part circuit. Then, as shown in the figure, a static random access L-body single TG, a lyon unit or a random access (4) unit is connected to an external circuit via: (1) a sense amplifier; (2) ) internal tristate buffer, pass circuit, interrogation circuit, pass circuit and internal driver or glock circuit and internal driver, (3) fine line metal structure 631; (4) upward through the protective layer opening; (3) polymer layer opening 9531; (6) patterned metal layer 831; (7) passes through the polymer layer opening 9539, (8) protective layer opening 539, (9) through the fine line metal structure 639, ^ is connected to an input node of the wafer external circuit 42; (10) connecting the thin-line metal structure (4)' via the output node of the wafer-external circuit 42 and connecting to the wafer-external circuit 43 as the ESD protection circuit through the thin-line metal structure 69; (11) Protective layer opening 539, (12) Polymer layer opening 9539; (13) through a gold lip line or plane 83r as a reconfigured line; (14) through a contact pad 8310 exposed by a polymer layer opening 9939; and (15) through contact Pad 8310 A conductor wire connected to an external circuit. Further, a polymer layer may be formed below or above the metal line or plane 83r as a reconfiguration line, for example, in Fig. 10G, the metal line or plane 83r 55 200816373

The iVA^^u〇-uuTWB is formed into a layer 95, and a metal layer or a plane 8 is formed with a top layer and a layer. In addition, the metal line or plane pole as a reconfigured line can be made by thickness! .5 micron micro-weight __ between 2 microns and 1 〇 micro ^ is preferred - gold layer formation (formed by electroplating or no electricity), or by thickness 71 to 2 microns A steel layer is formed between the micrometers (preferably between 3 micrometers and micrometers) (formed by electroplating). Wherein, the top of the copper layer has a nickel layer (having a thickness between 0.5 micrometers and 5 micrometers) and one of the gold and domain nails is assembled (figure, 'genus layer C, thickness) 〇. 〇 5 micrometers to 5 Between microns). A single wire is bonded to the surface of the gold, handle or ruthenium layer on the contact pad 8310. When the signal is transmitted to an external circuit or component, some of the external circuits of the chip need to (1) drive the external circuit or component that is required to carry a large current and load; (2) detect the signal containing the noise from the external circuit or component. (noisy signal); and (3) protect internal circuitry from damage caused by surge signals from external circuits or components. Referring to FIG. 11A, FIG. 19 and FIG. 11E and FIG. 5G, the wafer external driver 421, the chip external driver 422 and the internal tristate buffer are respectively exposed as the chip external circuit 42. example. In Fig. 11A, it is a two-stage cascade of one of the wafer-connected external drivers 421. In order to drive an external circuit (package, other wafer or component, etc.) that requires a heavy load, the wafer-external driver 421 is designed to generate a large current. Alternatively, the wafer external driver can be formed using a complementary metal oxide semiconductor series driver. This series drive cry may include a number of inverters. The output current of a chip connected to the external driver is with the stage 56 200816373

MliUA UO-UnTWB number and the transistor size (W/L, the ratio of the width of the MOS transistor to the channel length), more precisely the effective channel width of the MOS transistor. Proportional to the ratio of the effective channel length). In FIG. 11A, the first stage 421 of the external driver 421 is an inverter formed by an N-type MOS transistor 42〇1 and a p-type MOS transistor 42〇2. And the size of the N-type MOS transistor 42〇1 and the p-type MOS transistor 42〇2 is larger than the size of the internal circuit (such as the first embodiment, the second embodiment, the third embodiment, and the subsequent fourth The dimensions of the internal circuits 21, 22, 23, 24 of the embodiment). In addition, the first stage 421 of the external driver 421 receives a signal from the internal circuit 21, 22, 23, 24 at the input node F. In addition, the second stage 421" of the wafer external driver 421 is also an inverter formed by a larger size n-type MOS transistor 4203 and a P-type MOS transistor 4204. The wafer is externally driven. The 421 provides a driving current ranging from 5 milliamperes (_) to 5 amps (amperes, A), and ranges from 1 mA to mp amps. Preferably, in order to achieve the target output drive current, the size of the n-type MOS transistor 4203 of the second stage 421 (which is the output stage of the external driver 421) is between 2 〇 and 2 〇, the range between 〇〇〇, and the range between 3 〇 to 300 is preferred. In addition, because the driving current of a p-type MOS transistor is about an N-type oxy-half The drive current of the transistor is half. Therefore, the size of the p-type MOS transistor 4204 of the first stage 421" (in other words, the output stage of the external driver 421) is between 4 〇 and 4 〇, 〇 Between the 〇〇, and 57 200816373

MliUA UO-Ul^TWB is preferred; the range between 60 and 600 is preferred. However, for a power chip or a power management chip, the drive current must be larger, for example (1) amps or 2G amps, and the drive current is between mA and 50 amps. The range between amps and the range between 500 mA and 5 amps. Therefore, the size of the N-type MOS transistor of the power chip or the power management chip is between 2, 〇〇〇 to 2 (8), and the range between 〇〇〇 and 2,000 To 20, the range between 〇〇〇 is preferred, while the size of p-type MOS transistors is between 4,000 and 4 (10), the range between 〇〇〇, and 1 to 4,000 to 40,000 The range between the two is preferred. In addition, referring to the ud diagram, the wafer-external driver 421 can connect a plurality of inverters in parallel in the second stage 421" so that the driver of the second stage 421" can provide the size (the ratio of the channel width divided by the channel length) A larger N-type MOS transistor and a P-type MOS transistor, so that the external driver 421 can provide a larger driving current, wherein in the driver of the second stage 421, multiple anti-transistors The n-type MOS transistor of the transistor is connected to the gate of the p-type MOS transistor, and the N-type MOS transistor of the plurality of inverters and the Pole phase of the P-type MOS transistor Join. 8E, 9C, and 10H are respectively a circuit diagram, a top view, and a cross-sectional view of the circuit design of the 11D drawing of the embodiment. Referring to FIG. 11G, the external driver 421 can also form a cascade driver by connecting a plurality of inverters in the first stage 421, and then through the step-by-step size reversal. The phase device is used to enable the external driver 421 to amplify the signal step by step, wherein the n-type gold oxide of the inverter of the latter stage is 200816373

The size of MliUA UO-UOTWB semi-transistor and P-type gold oxide semi-electrical reduction (the ratio of the pass-through degree divided by the channel length) is larger than that of the previous-stage inverter N-type MOS semi-transistor and p-type gold. The size of the oxygen half turtle asteroid (the ratio of the channel width divided by the length of the channel), the preferred magnification is the natural index (e, natural exponent) magnification, and the connection mode is the N-type gold of the inverter of the previous stage. The xenon of the oxygen semi-transistor and the p-type MOS transistor is connected to the N-type MOS transistor of the reverse-phase H of the back-stage and the P-type MOS transistor. 8F, 9D, and ι〇Ι are circuit diagrams, top views, and cross-sectional views, respectively, of the circuit design of the application of the embodiment. Referring to FIG. 11B, it is a two-stage series-connected external receiver 422. The external receiver 422 can receive signals from an external circuit (not shown) and output signals to internal circuits. Input node. The first stage 422 of the external receiver 422, (close to the external circuit) is an inverter formed by an N-type MOS transistor 4205 and a P-type MOS transistor 42A, and The N-type MOS transistor 4205 and the P-type MOS transistor 42〇6 have dimensions designed to detect external signals containing noise. The first stage 422 of the external receiver 422 receives a signal from an external circuit or component containing noise at point E (which may be a signal from another chip). The second stage 422 of the wafer external receiver 422, which is also an inverter, is formed by a larger size N-type MOS transistor 4207 and a P-type MOS transistor 4208. The second stage 422 of the chip receiver 422 is used to restore the integrity of the external signal containing the noise to the internal circuitry. Please refer to FIG. 11C, which is a wafer tristate buffer as a wafer. 59 200816373

The uo-uidTWB is connected to the If-example of the external drive, and the chip tristate buffer outputs the signal to a bus and then to multiple logic gates. The wafer tristate buffer in the f llc diagram can be considered as a gated inverter. When the enabling signa (four) is high level (the watt is low level), the chip tristate buffer transmits the signal from the internal circuit to the external circuit, and when the signal 仏 is at the low level, the internal circuit is The external circuit is cut off. In this case, the wafer tristate buffer is used to drive the external data bus. The other is the N-type MOS transistor used as the wafer external driver. The range of 42〇9 size and p-type MOS transistor 4210 dimensions is described in Figure UA and will be further described in the series of Figure 15. See Figure 11E for the wafer-three The state buffer is used as an example of a chip receiver. When the signal is high level (the tile is low level), the chip's binary buffer allows the signal from the external circuit to be transmitted to the internal circuit. When the signal is at a low level, the internal circuit is disconnected from the external circuit. In this case, the 'chip two secret device receives the signal from the external data bus at node E. The other is related to the chip tristate buffer. Chip outside The range of the size of the N-type oxy-oxygen semiconductor 42 〇 9 and the P-type MOS half-crystal side of the receiver is described in Figure 11B and will be further illustrated in the series of Figure 15. The above example is for Complementary metal oxide semiconductor level signal (CM〇s level signal). If the external signal is a transistor-transistor logic (tmnsistor-tmnsistoi· logic ' TTL) level, a CM〇s/TTL buffer is required. 200816373

MliUA Ub-U13fWB, if the external signal is emitter-coupled logie (ECL) level, a CMOS/ECL interface buffer is required. An inverter of one or more poles can be added between the internal circuit and the wafer tristate buffer. Referring to Fig. 11F, there is further shown an example in which a wafer receiving external receptacle 422 has a wafer receiving external receptor 43 as an electrostatic discharge preventing circuit. In this example, the wafer external circuit 43 as an electrostatic discharge protection circuit includes two reverse-biased diodes 433, 4332. The bottom reverse bias diode 4331 can be reverse biased between the external input voltage (voltage at point E) and the ground reference voltage V%, while the top reverse bias diode 4332 can be externally input with voltage and The power supply voltage Vdd is reverse biased. When the external input voltage from the external circuit is charged to the power supply voltage, the current will be discharged to the top of the reverse-collector diode 4332. When the external input voltage is lower than the ground reference voltage Vss, the current will be discharged. After the bottom end of the reverse biased diode gamma. Therefore, the input voltage of the internal circuit will be maintained between the power supply voltage and the ground reference voltage VSS' and the semiconductor device in the external receiver or the internal circuit 20 will be protected from static electricity. damage. A structure. In the case of the cage - the external power supply is via the telescope - the internal circuit 20 (including 21, 22, but in this case, the need for profit - electrostatic discharge protection 61 200816373

Ινιχ^α/^ υ〇-υ ι j TWB circuit 44 to the external supply of electricity to generate electricity / Lai her current (four). First, please refer to Fig. 12A, which is a related art of the present embodiment. In Fig. 12A, an external voltage Vdd is input through a protective layer opening 549, and the fine metal structure 618, 6m, 6121 (including 6121a, 6121b, 6121c), 6141 located under the protective layer 5 is distributed to A power supply node Tp, Up, Vp, Wp of the internal circuits 21, 22, 23, 24. The power supply node Dp of an ESD protection circuit 44 is coupled to the thin line metal structure 618 via a thin line metal structure 6491. Fig. 13 and Fig. 14 are a schematic plan view and a cross-sectional view corresponding to Fig. 12 and Fig. 8. 12B to 12C, 13B to 13C, and 14B to 14D are respectively a schematic view of the circuit structure, a top view and a cross-sectional view of the fourth embodiment of the present invention, as shown in the figure. As shown, an ESD protection circuit 44 is connected in parallel with the internal circuits 21, 22, 23, 24 through metal lines or planes 81 and/or metal lines or planes 82 on the protective layer 5, wherein the internal circuits 21, 22, 23, 24 such as a reverse gate (n〇r gate), an inverse gate, an AND gate, or a gate (〇R gate), an operational amplifier (〇perati〇nal amplifier), an adder, Multiplexer (muitipiexer), duplexer, multiplier, analog/digital converter (a/d converter), digital/analog converter (D/AConverter), complementary metal oxide semiconductor, Bi-carrier complementary MOS, bipolar circuit, SRAM cell, dynamic random access memory cell (dramcell), non-volatile memory 62 200816373

MJiUA 06-01 ^TWB non-volatile memory cell, flash memory cell print ash mem〇ry cell), can eliminate programmable read-only memory cell (EPR〇M cell), read-only memory ROM cell, magnetic random access memory (magnetic unit or sense amplifier). The internal circuit 2i, 22, 23, 24 is at least a channel width / channel length ratio of up to 5 An N-type MOS semi-transistor 08 coffee (4) between 〇.2 and 2, or a channel width/channel length ratio between 0.2 and 10 or between 〇·4 and 4 A p-type MOS transistor is formed, and the current flowing through the metal line or the plane 8 82 is, for example, between 50 microamperes and 2 milliamperes or between the brain and the daughter. The electrical circuit or the planes 81, 82 are formed on the metal lines or planes 81, 82 by a wire, for example, and are electrically connected to an external power source. Further, the electrostatic discharge protection circuit 44 is, for example, a Reverse-biased diode 4333 'As shown in the 帛 layout, it has an electric Contact and a grounding contact. In addition, in the first implementation series shown in the first picture series, the second picture series and the third picture series, the village increases the electrostatic discharge _, and parallels the voltage regulator or transformer 41 and the internal Circuits 21, 22, 23, 24. In the first sinker map and the first map, the "electrostatic discharge protection circuit 44 and the internal circuit 20 (including 21, 22, 23, 24) include - the power supply node (four) ^ off) and a ground node, wherein the external electrical input node is via a metal line or plane S1 on the protective layer 5, a protective layer of the protective layer $m 514, and a fine-line metal structure under the protective layer 5, 6i2 (including save, money, 63 200816373

Υο_υ 1 :>TWB 612c), 614, connected to a power supply node of the internal circuits 21, 22, 23, 24, Tp, Up, Vp, Wp, thereby distributing the external voltage Vdd to the internal circuit 2 Power nodes Tp, Up, Vp, Wp of 22, 23, and 24. In addition, the node Ep is also connected to a power supply node Dp of an electrostatic discharge protection circuit 44 via a metal line or plane 81 on the protective layer 5, a protective layer opening 5 of the protective layer 5, and a thin line metal structure 649 under the protective layer 5. . Fig. 14B is a schematic cross-sectional view corresponding to Fig. 12B. In the i4B diagram, the gold alloy 811 as a metal wiring or plane 81 includes an adhesion/barrier/seed layer 8111 and a thick metal layer 8112. The uc diagram also discloses a connection of a ground reference voltage Vss in addition to the connection of the external voltage salt as shown in Fig. 12B. In FIGS. 12C and 13C, the node Eg input to the ground reference voltage Vss is via the metal line or plane 82 on the protective layer 5, the protective layer opening 52 of the protective layer 5, 522, 524, and the thin line under the protective layer 5. The road metal structures 621, 622 (including, 622b, 622c), 624 are connected to the ground nodes Ts, Us, Vs, Ws of the internal circuits 2, 22, 23, 24. Further, the node island is also connected to the ground node Dg of the electrostatic discharge protection circuit 44 via the metal 82 on the protective layer $, the protective layer opening 保护 of the protective layer 5, and the fine line metal structure (10)' under the protective layer 5. The figure is a schematic cross-sectional view corresponding to the 12th C. The i4c figure reveals that there are two 瞧t jinlang above the protective layer, the towel _ jin 618 is used for the ground reference voltage Vss connection, and the patterned metal layer M2 is 甩 甩 64 200816373

Ivuc.o/1 uo-u l d TWB source Vdd connection. The patterned metal layer 821 includes an adhesion/barrier/seed layer 8211 and a thick metal layer 8212, and the patterned metal layer 812 includes an adhesion/barrier/seed layer 8121 and a thick metal layer 8122. Fig. 14D is similar to Fig. 14B except that a polymer layer 95 is formed between the protective layer 5 and the bottommost end of the patterned metal layer 811 which is a metal line or plane 81. Please refer to Fig. 12D, which is similar to Fig. 12C. The difference is that the 12C is only the ESD protection circuit 44, and the 12D is the ESD protection circuit 44, 45' The protection circuit 45 is, for example, a reverse bias diode. In the brother 12D diagram, the ESD protection circuits 44, 45 and the internal circuit 2 (including 2, 22, 23, 24) each include a - power node and a ground node, and an external voltage Vdd is via the metal on the protective layer 5. The line or plane 81, the protective layer openings 511, 512, 514 of the protective layer 5 and the thin line metal structures 61 612 & 612b, 612c, 614 under the protective layer 5 are input to the internal circuits 21, 22, 23, 24 A power supply node Tp, Up, Vp, Wp further distributes the external voltage vdd to the internal circuit to the power supply nodes Tp, up, γρ, 梆 of i 22, 23, 24. In addition, the external voltage is also input to the ESD protection circuit through the metal line on the protective layer 5 or the protective layer openings 549, 559 of the protective layer 5 and the fine-line metal structures 649, 659 under the protective layer 5. - Power nodes Dp, Dp, . In addition, a ground reference voltage Vss is via a metal line or a flat layer on the protective layer 5, protective layer openings 521, 522, 524 of the protective layer 5, and a thin line metal structure 62 under the protective layer 5, 622b , 622c, 624 are input to a ground node 65 of the internal circuits 21, 22, 23, 24 200816373

MliUA uo-unTWB

Ts, Us, Vs, Ws. In addition, the ground reference voltage Vss is also connected to the electrostatic discharge protection circuit 44 via the metal 82 on the protective layer 5, the protective layer openings 549 of the protective layer 5, 559, and the thin-line metal structures 649', 659' under the protective layer 5. , a ground node Dg, Dg, of the shirt. The other related content of this embodiment is the same as that of the first embodiment, the second embodiment, and the third embodiment, and will be in the following series of 15th, 16th, 3rd, and 18th series. This is described in further detail in the series of Figure 19. Furthermore, the reconfiguration line described in the third embodiment can also be applied to the first embodiment and the fourth embodiment of the present invention, that is, in the first embodiment and the fourth embodiment, for receiving an external voltage. Contact pads of Vdd or ground reference voltage Vss (for example, contact pads 8110, 8120 in FIGS. 3B to 3D, contact pads 811〇, 812〇 in FIGS. 14B to 14D) may also be utilized. The reconfiguration line is repositioned to a different location of the contact pads, such that the contact pad locations at the different locations and the metal pads of the thin line metal structure (eg, metal pads 6190, 6290 in Figures 3B through 3) The metal contacts 6490, 6490 in Figures 14B through 14D are positioned differently and then connected to an external circuit using a wire or bump on the contact pads located at the different locations.

In all of the embodiments (the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment) of the present invention, the main feature of the 〇ver_passivation structure is a thick patterned metal layer. (thickness between 2 microns and 200 microns) and thick 66 200816373

1VLDO/1UO-U1J TWB dielectric layer (thickness from 2 microns to micron). The Fig. 15 series and the i6th series of knives show an emb〇ssing process and a double embossing (such as _mbossing). It can be used to make the pattern above the protective layer in all embodiments of the present invention. Metal layer and dielectric layer. In these two processes (the b-th series and the second-order series), the polymer material (10) mer _ ri is used as a dielectric layer, and is formed on each patterned metal layer between each patterned metal layer. And/or under each patterned metal layer. Further, the series of <15> and Fig. 16 are based on the 1st GE diagram in the third embodiment, and use this as an example to illustrate the method in which all the embodiments of the present invention are laid out on the green layer of the f-layer. The methods described below are applicable to all embodiments of the present invention with their associated description. The process of forming the structure above the protective layer begins after the IC wafcr process is completed. Referring to Figure 15A, it is revealed that a starting material is formed as a structure above the protective layer. As shown in the figure, the process of forming the structure above the fourth layer is started in a conventional semiconductor manufacturing plant. (IC fab) is fabricated on a V-integrated circuit wafer 10, the wafer 10 includes: (1) a substrate 1 The substrate 1 is usually a silicon substrate, and the stone substrate can be It is an intrinsic germanium substrate, a p-type germanium substrate or an n-type germanium substrate. For high performance wafers, a germanium (SiGe) or a silicon-on-insulator (Silicon-OiHnsulator ’ SOI) substrate is used. Wherein, the ruthenium substrate comprises an epitaxial layer on the surface of the ruthenium substrate, and the ruthenium substrate on the other insulation layer comprises 67 200816373

MEGA 06-015TWB An insulating layer (preferably yttria) is placed on a substrate and a germanium or germanium epitaxial layer is formed on the insulating layer. (b) device layer 2 The component layer 2 usually comprises at least one semiconductor component (semiconductor deviee), and the component layer 2 is in the surface of the substrate 1 and/or on the surface. The semiconductor component may be a MOS transistor 2', such as an NMOS transistor (n-channel MOS transistor) or a p-channel MOS transistor (PMOS transistor), The MOS transistor 2' includes a source 201, a drain 202 and a gate 203, and the gate 203 is usually a poly silicon, a polycrystalline tungsten (tungsten polycide), a tungsten silicide, a titanium silicide, a cobalt silicide or a salicide gate. Alternatively, the semiconductor component may be a bipolar transistor ( Bipolar transistor, Diffused MOS (DM0S), Lateral Diffused MOS (LDM0S), Charged-Coupled Device (CCD), Complementary Gold-Oxide Semiconductor ( CMOS) a sensing element, a photo-sensitive diode, a resistive element (formed by a polysilicon layer or a diffusion region in a germanium substrate). Various semiconductor circuits can be used to form various circuits, such as complementary metal oxides. Semiconductor (CMOS) circuit, N-type MOS circuit, P-type MOS circuit, bi-carrier complementary metal-oxide-semiconductor (BiCMOS) circuit, complementary metal-oxide-semiconductor sensor circuit, diffusion metal oxide half Guide 68 200816373

丄VJLDer/i UO-U13 TWB body power supply circuit, laterally diffused metal oxide semiconductor circuit, etc. In addition, component layer 2 also includes internal circuitry 20 (including 21, 22, 23, 24). In all embodiments, voltage regulator or transformer 41 is in the first embodiment, and the wafer is connected to external circuitry 4 (including 42, 43 In the third embodiment, and the electrostatic discharge protection circuit 44 is in the fourth embodiment. (3) Fine-line scheme 6 This fine-line structure 6 includes a plurality of fine-line metal layers (j^ne_iine metai layer) 60, a plurality of fine-line dielectric layers (fme_line dielectric layers), and a plurality of thin lines. The conductive via plug 60 in the opening 30 ′ of the dielectric layer 30 〇 the other thin metal structure 63 includes the fine wiring metal layer 6 〇 and the conductive plug 60 ′ and the fine line metal structure 63 is in the present invention. Included in the first embodiment; (2) fine line metal structures 611, 612 (including 612a, 612b, and 612c), 614, 619, 619, 621, 622 (including 622a, 622b, and 622c), 624, 629; Thin line metal structures 631, 632 (including 632a, 632b, and 632c), 634 in the second embodiment; (3) fine line metal structures 631, 632 (including 632a, 632b, and 632c), 634, 639, 639' Third embodiment; (4) fine line metal structures 611, 612 (including 612a, 612b, and 612c), 614, 649, 659, 62 622 (including 622a, 622b, and 622c), 624, 649, and 659, Fourth embodiment. The fine line metal layer 60 may be an inscription layer or a copper layer, or more specifically, an aluminum layer formed by sputtering or a copper layer formed in a damascene manner. Therefore, the fine-line metal layer 60 may be: (1) all of the fine-line metal layers 6 are aluminum layers; (2) all of the thin-line metal layers 60 are copper layers; and (3) the bottom layer of fine-line metal layers 6〇为69 200816373

MbCiAU6-U15rWB ^ g and the top fine metal layer 6 is a copper layer; or (4) the bottom fine metal layer 6 is a copper layer, and the top fine metal layer 60 is a layer. In addition, each ^^^^ 60 0.05 2 , ^ is preferably between 0.2 μm and i μm thick, and the other thin metal layer 6 is a line, then the lateral design standard (width) The system is between % nanometers (__me(4) to 15 micrometers, and preferably between 2 nanometers and 2 micrometers. In the above, the aluminum layer is usually deposited by physical vapor deposition. ^丨(3)iv叩 sink

The method of Deposition 'PVD) is formed, for example, by sputtering, and then deposited through a thickness ranging from α1 μm to 4 μm (preferably between 〇·3 μm and 2 μm). A photoresist layer is patterned for this layer, and then it is here! The lu layer is made with wet etching or a dry etching. The preferred way is to dry plasma. (usually contains fluorine plasma). Another adhesive/barrier layer may be selectively formed under the aluminum layer, wherein the adhesion/resistance P early layer may be titanium, titanium tungsten alloy, titanium nitride or the like. A composite layer; and an anti-reflective layer (for example, titanium nitride) may be selectively formed on the aluminum layer. In addition, the opening 30 can be selectively filled with a chemical vapor deposition vap〇r^叩(10), (CVD), and then a tungsten metal layer, followed by mechanical mechanical polishing of the tungsten metal layer to form a metal. The plug 60, in addition to the above, the copper layer is usually formed by means of electroplating and damascene process, which is described as follows: (1) depositing a copper diffusion barrier layer (for example, 200816373)

Gossip ο-υ ld rWB oxynitride layer or nitride layer with a thickness between 0. 05 micrometers and 0. 25 micrometers); (2) using plasma enhanced CVD (PECVD), A fine-line dielectric layer 30' having a thickness between 〇丨 microns and 2.5 microns is deposited by spin-on coating or high-density plasma CVD (HDPCVD). Wherein the thin-line dielectric layer 3 is preferably a thickness between 0.3 μm and L 5 μm; and (3) using a photoresist layer having a thickness between 0 μm and 4 μm. Patterning the fine-line dielectric layer 3〇, wherein the thickness of the photoresist layer is preferably between 0.3 μm and 2 μm, and then exposing and developing the photoresist layer to form a plurality of openings in the photoresist layer And/or a plurality of trenches to remove the photoresist layer; (4) depositing an adhesion/barrier layer and a seed layer by sputtering or chemical vapor deposition. Wherein, the adhesion/barrier layer comprises a button, a nitride button, a titanium nitride, a titanium or a titanium tungsten alloy, or a composite layer formed of the above materials. In addition, the seed layer is usually a copper layer, and the copper layer may be made by splashing copper metal, chemical vapor deposition of copper metal, or first by chemical vapor deposition - copper metal, and then splashing money - copper metal Forming a method; (5) a copper layer having an electric ore thickness between 0. 05 micrometers and 2 micrometers on the seed layer, wherein the copper layer having a thickness of between about 2 micrometers and 1 micrometer is electroplated. Preferably, (6) removing the copper layer, the seed layer, and the adhesion/barrier layer not in the opening or trench of the thin-line layer 30 by grinding (preferably CMP) wafers until exposed Out of the fine line dielectric layer 30 under the adhesion/barrier layer. After undergoing chemical mechanical research 200816373

JVLbLrA UO-U13 TWB as a metal conductor (line or plane) or conductive plug 60, (connecting two adjacent thin-line metal layers 60), another 'may also use - double-edged dGuble_damaseene) process; A conductive plug 60 is formed simultaneously with a chemical mechanical polishing, and to a line or metal plane. Two micro-views (10) 〇切驰 叩 (4) process and two electroplating processes are applicable to the dual damascene process. The dual damascene process adds more steps to deposit and pattern another dielectric layer between the step (3) of patterning the dielectric layer in the single damascene process and the step (4) of depositing the metal layer. The filament t-layer 30 is formed by chemical vapor deposition, electro-chemical vapor deposition, thermal plasma chemical vapor deposition or spin coating (Spin_〇n). Fine line; the material of the layer 10 includes silic〇n 〇xide, siiic〇n nitride, siiicon oxynitride, and plasma-assisted chemical vapor deposition. Tetraethoxydecane (PECVD TEOS), spin-on glass (SOG, yttrium oxide or yttrium oxide), Fluorinated Silicate Glass (FSG) or a low dielectric constant (low-K) material For example, black diamond film (BlackDiamond, which is a product of Applied 4 Materials, company translated as Applied Materials), ULK CORAL (product of Novellus) or SiLK (IBM) low dielectric constant dielectric material. Oxidized oxide formed by plasma-assisted chemical vapor deposition, tetraethoxy decane formed by plasma-assisted chemical vapor deposition, or oxide formed by high-density plasma having a Between 3.5 and 4.5 Dielectric constant K; fluorocarbon glass formed by plasma-assisted chemical vapor deposition or fluorocarbon glass formed by high-density plasma having an electrical constant value between 3.0 and 3.5, and a low-k dielectric material Then there is between L5 and 3.5 200816373

Ivir, u/\ uo-υ i d The dielectric constant value of TWB. Low dielectric constant dielectric materials, such as black diamond films, are porous and include hydrogen, carbon, helium and oxygen in the formula HwCxSiy〇z. The thin circuit dielectric layer 30 typically comprises an inorganic material to achieve a severity greater than 2 microns. The thickness of each thin-line dielectric layer 3〇 is between 微米 5 μm and 2 μm. In addition, the opening 3 in the thin wiring dielectric layer 30 is formed by etching the patterned photoresist layer by wet etching or dry etching, wherein the preferred etching method is dry etching. The dry type includes fluorine plasma (f[uorine plasma>. (4) protective layer 5) The protective layer 5 plays a very important role in the present invention. The protective layer 5 is in the integrated circuit industry. As an important component, such as 〇 〇 由 由 S , , , , , L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L The needle is defined as the hiding layer and deposited on the entire upper surface of the wafer. The protective layer 5 is an insulating and protective layer that prevents mechanical and chemical damage during assembly and packaging. In addition to the scratches, the protective layer 5 can also prevent moving ions (such as sodium ions and transition metals), such as gold and copper penetrating into the lower side. In addition, the protective layer 5 can also protect the underlying components and connection lines (fine line metal structure and fine-line dielectric layer) from moisture intrusion. The protective layer 5 usually includes a Silicium nitride layer and/or one Sleeper oxide (silicon oxynitride) layer, and the thickness is between 2 and 15 micrometers square of 73,200,816,373

Between MliCiAtKHmTWB and a thickness of between 33 μm and ι·〇 micron is preferred. Other materials used in the protective layer 5 are oxides of cerium oxide, plasma-enhanced tetraethyl orthosilicate 'PETEOS, which are formed by plasma-assisted chemical vapor deposition. , Shishixi Glass (10) 〇Sph〇siii gamma giass, PSG), borax silicate glass (BPSG), oxide formed by high density plasma (HDP). Next, some examples of the protective layer 5 composed of a composite layer will be described. The order from the bottom to the top is: (1) the thickness is between 〇1 μm and 1 μm (preferably, the thickness is between 〇·3 μm to 〇·7 microns between oxides/thickness between 〇·25 μm and ι·2 μm (preferably between 〇·35 μm and 1 μm) The protective layer 5 of the type is usually covered on a metal connecting line formed of aluminum, wherein the metal connecting line formed of aluminum usually comprises a process of sputtering aluminum and etching aluminum; (2) the thickness is between 0·05 micrometers and 〇· Nitrogen oxides/thickness of 35 microns (preferably between 〇·1 μm and 0.2 μm) from 0.2 μm to 12 μm (preferably between (U μm and 〇·2 μm) The oxide/thickness of the oxide/thickness from 〇·2 μm to ι·2 μm (preferably between 〇·3 μm and 〇·5 μm) is between 〇·2 μm and ΐ·2 An oxide of micron (preferably between 3·3 μm and 〇.6 μm). This type of protective layer 5 is usually covered with a metal formed of copper. The connection line, wherein the metal connection line formed by copper generally comprises electroplating, chemical mechanical polishing and damascene process. In addition, the oxide layer in the above two examples may be yttrium oxide and plasma formed by plasma-assisted chemical vapor deposition. Reinforced tetraethyl orthosilicate (plasma_enhanced tetraethy ortliosilicate, 200816373

Oo_u 丄 j rWB PETEOS) oxide, _ sorghum plasma formed oxide. The above is applicable to all of the embodiments (first embodiment, second embodiment, third embodiment, and fourth embodiment) of the present invention. The protective layer opening 50 is formed by wet etching or dry etching, wherein dry etching is preferred. In the present invention, the protective layer opening 5〇 includes: (1) protective layer openings 511, 512, 514, 519, 519, 52, 522, 524, and 529 in the first embodiment; (2) protective layer opening 531 , 532 and 534 in the second embodiment; (3) protective layer openings 53 532, 534, 539 and 539, in the third embodiment; (4) protective layer openings 511, 512, 514, 549, 52 522, 524, 549, 559, and 559' are in the fourth embodiment. In addition, the size of the protective layer opening 5〇 is between 〇1 μm and 200 μm, and preferably between 1 μm and 1 μm or between 5 μm and 30 μm, and the protective layer is further provided. The shape of the opening 5〇 may be a circle, a square, a rectangle or a polygon, so the size of the protective layer opening 5〇 refers to the diameter of the circle, the length of the side of the square, the longest diagonal of the polygon, or the width of the rectangle. Dimensions, in which the length of the rectangle is between 丨micrometers to i.m. and preferably between 5 micrometers and 200 micrometers. For internal circuits, the size of the protective layer openings 53 532, 534 is between 微米"micron and 1" micron' and is preferably between 0.3 micrometers and 30 micrometers. Protective layer openings 519, 519, 529 of the transformer or transformer 41 or protective layer openings 539, 539' for the external circuit of the wafer, 43 or for the electrostatic discharge protection circuit 44, 549, 549, 559, 559 In terms of size, the size of the opening is large, and its range is 75 200716373

MliUAU6-Ui3rWB is between 1 micrometer and 150 micrometers, and it is better to bribe between 5 micrometers and 1 micrometer. In addition, the protective layer opening 5 〇 exposes the metal layer of the uppermost layer of the thin wiring metal layer 6 ( (metal _ for electrically connecting the circuit or plane above the protective layer. A wafer 10 ' such as a silicon wafer , manufactured using different generations of integrated circuit process technology, such as i micron, 〇.8 micron, Μ micron, 〇 5 micron, 0.35 micron, 0.25 micron, 0.18 micron, 〇 25 micron, 〇 13 micron, nano (four) , 65 nm, 45 nm, 35 nm, 25 nm technology, and the generation of these integrated circuit process technology is a gold oxide semi-transistor 2, the length of the idle length ^ length) or effective channel length candle丨length) to define. The size of the other wafer is, for example, 5 忖, 6 pairs, 8 pairs, 12 忖 or 18 pairs. Wafers are fabricated using a lithography process that includes coating (eg, exposure (4), (10), (4), and developing photoresist. The photoresist used to make the wafer has a thickness of 0.1. The microwire is between 0.4 microns and is exposed to the photoresist by a five-times (5 χ) stepper (Cliner (four) or scanner). The multiple of the towel, step optometry refers to when the beam is from the reticle ( Usually when it is projected onto a wafer, the pattern on the reticle is reduced on the wafer, and five times (5X) means that the pattern ratio on the reticle is the ratio of the pattern on the wafer. Five times. Using a scanner in the advanced generation of integrated circuit process technology, the pass f is reduced by four times (4X) to improve the resolution. The beam wavelength used by the stepper or scanner is 436 nm (g_line), 365 nm (i-line), 248 nm (deep ultraviolet light, 0 call, 193 nm 76 200816373

1V1GU/V uo-u 1D fWB or 13.5 nm (very short UV, EUV). In addition, the high-index turbidity ex immersion lithography technology can also be used to complete the fine line characteristics of the wafer. In addition, 'wafer ίο is made in a deanroom with class 1 or better (eg grade ^). Class 1 无 clean room allows the number of large dust particles per cubic inch of suction It is: no more than one dust particle containing greater than or equal to i micron, no more than 1G ash containing more than 0.5 micron, and no more than 3 (g) of gypsum greater than or equal to G.3 micron. , containing no or equal to 〇2 micro-weight ash, no more than 75, dust particles containing 妓 scale in Q1, no more than 35G' and the level of 丨 clean room allows the maximum number of dust particles per cubic inch Is: dust particles containing no more than or equal to G5 micron, no more than ι, containing more than or equal to G. 3 microns, no more than 3, no more than or equal to 0.2 micron, no more than 7 dust particles, containing No more than 35 dust particles larger than or equal to 〇ι microns. Please refer to Figure 15B. When using copper as the fine-line metal layer 6〇, a metal cap 66 (including 66, 669) is required. And 669,) to protect the copper from the protective layer opening 50 The pad (eGpperpad) protects the copper bond from oxidation and damage, and can be used as a wire bond for subsequent wafers. The metal top layer 66 includes an aluminum layer, a gold layer, and a titanium layer. (10) a layer, a titanium-tungsten alloy layer, a button (Ta) layer, a nitride button (TaN) layer or a nickel layer, wherein when the metal top layer 66 is an aluminum layer, then the copper pad and the metal top layer A barrier iayer is formed between 66, and the barrier layer comprises titanium, titanium tungsten alloy, gasification 77 200816373

IVUiUA uo-u 1 d fWB = choose = gold:::: In this embodiment, please refer to the 15C to 15K riding instructions, which are disclosed in the figure as shown in Figure 弟 or 弟 (9) The process step of fabricating the upper structure of the protective layer (__PaSSivatiGnseheme) 8 on the wafer 1G, the process step of forming a two-layer metal layer over the protective layer, and the two-metal layer connecting the internal circuit and connecting the wafer . However, the axis only reveals that there are two layers of patterned metal layer above the protective layer, but it can also be formed in the same or similar way as described in the conditional figure, forming a layer above the protective layer. The layer, the three-layer patterned metal layer, the four-layer metallization layer or more layers of the chemically-coated metal layer. In addition, the contents described below are applicable to all embodiments of the present invention. First, as shown in Fig. 15K, a structure 8 above a protective layer is formed on a ##^Kstarting material), and the starting material is one half of the wafer 10 (such as the 15th or 15th image). Shown). In addition, the structure 8 above the protective layer includes a patterned metal layer 8〇 and a polymer layer (or insulating layer) 9〇, wherein the patterned metal layer 8〇 includes one layer, two layers, three layers, four layers or more. a multi-layered metal layer, and the patterned metal layer 80 can be, for example, except that the topmost patterned metal layer is a gold layer, and the rest are copper layers and their adhesion/barrier layers (eg, chromium or titanium-bismuth alloy). All embodiments of the present invention are exemplified by the patterning of the metal layer 80 comprising a tuft or two layers of patterned metal layers, including: 78 200816373

MECiA U6-U1MWB (a) patterned metal layer 801, including (1) 811 and 821 in the first embodiment; (2) 831 (including 831a, 831b) in the second embodiment; (3) 83r, 831 (including 831a, 831b) in the third embodiment; and (4) 811 and 821 in the fourth embodiment. (ii) patterned metal layer 802, including (1) 812 in the first embodiment; (2) 832 in the second embodiment; (3) 832 (including 832a, 832b) in the third embodiment; (4) 812 In the fourth embodiment. In addition, the material of the patterned metal layer 80 includes gold, silver, copper, palladium, platinum, rhodium, iridium, and nickel, and the patterned metal layer 80 constituting the metal wiring or the plane is generally a composite layer of 4 stacked by metal. In FIG. 15K, both the patterned metal layer 801 and the patterned metal layer 802 are a composite layer, wherein the bottom layer of the composite layer is an adhesion/barrier/seed layer 8011, 8021, The system includes: (1) 8111, 8121 and 8211 in the first embodiment; (2) 8311, 8311a, 8311b and 8321 in the second embodiment; (3) 831 831 la, 831 lb, 8321a and 8321b In the third embodiment; and (4) 8111, 8211 and 8121 are in the fourth embodiment; in addition, the top layer of the composite layer is a thick metal layer 8012, 8022, which includes: (1) 8112, 8122 and 8212 In the first embodiment; (2) 8312, 8312a, 8312b, and 8322 are in the second embodiment; (3) 8312, 8312a, 8312b, 8322a, and 8322b are in the third embodiment; and (4) 8112, 8212 And 8122 are in the fourth embodiment. In the above, the adhesion/barrier/seed layer 8011, 8021 includes an adhesion/barrier layer (not shown) and a seed layer (not shown) on the adhesion/barrier layer. The material of the adhesion/barrier layer may be titanium, tungsten, cobalt, nickel, titanium nitride, 79 200816373

Ivu^vj^ υο-υ l jTWB Titanium-niobium alloy, ruthenium, chromium, copper, chrome-copper alloy, group, tantalum nitride, alloy formed by the above materials or composite layer composed of the above materials. $, the adhesion/barrier layer can be formed by electroplating (eiec_ating), electroless plating (elec^ss pla_ deposition or physical vapor deposition (such as splashing shovel), in which physical vapor deposition is used as a secret ageing method' The thickness of the metal splatter is 0.02 micrometers to 0.8 micrometers, and the thickness is preferably between 〇〇5 micrometers and 〇2 micrometers. Adhesive/blocking/x The layer of bribes and the blue layer of the blue layer can be followed by the electroplating process. The seed layer is usually formed by means of fine physical and sensitive methods. In addition, the material used for the seed layer can be gold, copper or silver. Record, turn, 铑, Ming or Shu' and usually the same as the thick metal layer in the subsequent electric ore process. The other 'seed layer can use electroplating, electroless ore, chemical vapor deposition or physical vapor phase balance surface The way to form, the needle and the position of the syllabus _ New Jia's formation, such as metal enamel plating process. The thickness of the seed layer is between 〇.〇5 μm to U μm and the thickness between 0.05 μm and 〇.8 μm is preferred. The thick metal layer, 8〇22 is formed by a low-resistance conductor, and the thickness of the 'further' thick metal layer 8012, 8〇22 usually formed by electroplating is usually between 〇5 μm and 100 μm, and The thickness between 3 micrometers and 2 micrometers is relatively thin, and the material of the thick metal layers 8012 and 8022 may be gold, copper, silver, and palladium: : iridium, platinum or iridium, among which gold, silver, The preferred thickness of palladium, rhodium, platinum or rhodium is between 微米 micrometers and 15 micrometers. The preferred thickness of copper is between 15 micrometers and micrometers.

Between MbUAUb-unTWB, the preferred thickness of nickel is between 〇·5 reddish and 6 microns. Alternatively, a cap/barrier layer (not shown) may alternatively be formed on the thick metal layers 8Q12, 8022 as a protection or diffusion barrier. The protective/barrier layer may be formed by electroplating, electroless galvanic, chemical vapor deposition or physical vapor deposition (e.g., sputtering) and formed by electroplating. Further, the thickness of the protective/barrier layer is in the range of from 5 μm to 5 μm, and further preferably from 〇 5 μm to 3 μm. The protective/barrier layer can be a nickel layer, a cobalt layer or a vanadium layer. In addition, an assembly-contact layer (not shown) may be selectively formed on the thick metal layer 8012, 8〇22 or the protective/barrier layer on the assembly or package (not shown) Above, in particular, a thick metal layer or a protective/barrier layer (not shown) formed on the topmost layer of the patterned metal layer 8〇. The assembled contact layer can be used as a wire bond or as a solder wettable for wire bonding, gold connection, solder ball mounting or solder connection. Alternatively, the assembled contact layer can be gold, silver, turn, geese, tantalum or niobium. Top polymer layer (p聚合物lymer kiss 01^99 polymer layer opening 990 (including 9919 and 9929 in the first embodiment; 9939 and 9939, in the third embodiment; and 9949 and 9949, in the fourth In an embodiment) a contact pad 8000 exposing the patterned metal layer 80 at the topmost end (including 8110 and 8120 in the first embodiment; 8310 and 8320 in the third embodiment; and 8110 and 8120 in the fourth embodiment) surface. The assembled contact layer exposed to the polymer layer opening 990 may be a bonding wire, a solder ball (for electric forging 200816373

IviiiUAuo-uorWB formed solder balls or soldered to a solder ball), a metal ball (such as tin-silver alloy formed by electroplating or a tin-silver alloy by soldering), one metal on other substrates or wafers Metal bump, one of the gold bumps on other substrates or wafers, one of the metal pillars on the substrate or wafer, or one of the other substrates or wafers Column (copperp〇st). For an integrated circuit contact pad made of aluminum formed by sputtering or copper formed by electroplating (formed by a chemical mechanical polishing process), the metal line or plane above the protective layer may be as follows The above-mentioned types, from bottom to top, are: (1) the seed layer of the gold material formed by the jinhe alloy/lin/the gold formed by electroplating; (7) the seed layer of the gold material formed by the titanium/antimony ore/plating Gold formed; (3) Group/(10) seed layer of gold material formed by gold/gold formed by electroplating; (4) chromium/seed layer of copper formed by sputtering/copper formed by electroplating, (5) Titanium alloy / seed layer made of splashed copper / copper formed by electricity money; (6) group / copper seed layer formed by sputtering / copper formed by electric ore; (7) titanium / splash a seed layer of mineral-shaped copper/copper formed by electroplating; (8) a seed layer of copper formed by chromium, titanium crane, or titanium/group/germanium splashing/copper formed by electric ore/nickel formed by electro-recording , (9) chromium, titanium tungsten alloy, titanium or group / copper seed layer formed of tantalum ore / copper formed by rapid plating / plating Nickel formed / gold, silver, imprint, tantalum, niobium or tantalum formed by electroplating, and (10) chromium, titanium alloy, titanium or group / copper formed seed layer of copper / copper formed by electric ore / Nickel formed by electric ore, gold, silver, Ming, 姥, 姥 or 形成 formed by electroless ore. The thickness of each of the patterned metal layers 8 系 is between 2 μm and 5 μm, and the thickness between 3 μm and % μm is preferably thick. 82 200816373

Ινττ,ο/Λ. uo-uuTWB degrees, if the patterned metal layer 80 is a metal line, the lateral design standard (width) is between 1 micrometer and 200 micrometers, and is between 2 micrometers and 50 micrometers. Preferably, if the patterned metal layer 80 is a metal plane, particularly as a power or ground reference voltage plane, the lateral design standard (width) is preferably greater than 2 〇〇 microns. In addition, the minimum distance between two adjacent metal lines or planes is between 丨 micrometers and 500 micrometers, and preferably between 2 micrometers and 15 micrometers. In some applications of the invention, the metal lines or planes may comprise only a thickness of between 2 microns and 6 microns (preferably between 3 microns and 5 microns) formed by sputtering. A selective adhesion/barrier layer under the I layer (including titanium, titanium alloy, titanium nitride, button or nitride layer). Continuing, a contact structure 89 can be selectively formed on the interface 8000 of the patterned metal layer 80. The contact structure 89 can be a metal bump, a solder bump, a solder ball, a gold bump, a copper bump. Copper bump, a metal pad, a solder pad, a gold pad (§1 (1 ping (1), a metal column (111 gamma 1 post), a solder A pillar post, a gold post or a copper post. An under bump metal (UBM) layer is under the contact structure 89, and the under bump metal layer includes Titanium, titanium tungsten alloy, titanium nitride, chromium, copper, chrome-copper alloy, button, nitride button, nickel, nickel-vanadium alloy, vanadium or cobalt layer, or a composite layer composed of the above materials. (including the underlying metal layer of the bump) may be one of the following types, from bottom to top: (1) Titanium/gold pads (Gold 83 200816373)

IVliiU/V UO-U13 TWB layer thickness between 1 micron and 15 microns); (2) titanium tungsten alloy / gold pad (gold layer thickness between 1 micron and 15 microns); 3) Nickel/gold pads (the thickness of the nickel layer is between 微米·5 μm and 10 μm, and the thickness of the gold layer is between 0.2 μm and 15 μm); (4) Titanium/gold bumps ( The thickness of the gold layer is between 7 microns and 40 microns); (3) Titanium-tungsten alloy/gold bumps (the thickness of the gold layer is between 7 microns and 40 microns); (6) Nickel/gold bumps (nickel layer) The thickness is between 5·5 μm and 10 m, and the thickness of the gold layer is between 7 μm and 40 μm); (7) Titanium, titanium tungsten alloy or chrome/copper/nickel/gold pads ( The thickness of the layer I is between 0.1 μm and 10 μm, and the thickness of the gold layer is between 〇·2 μm and 15 μm); (8) Titanium, titanium tungsten alloy, chromium, chromium copper alloy or nickel vanadium alloy / copper / nickel / gold bumps (the thickness of the copper layer is between 〇.1 micron to 10 microns, the thickness of the gold layer is between 7 microns and 40 microns); (9) titanium, titanium tungsten alloy , chrome, chrome-copper or nickel-vanadium alloy/copper/nickel/solder pads (copper The thickness is between 0.1 μm and 1 μm, and the thickness of the solder layer is between 0.2 μm and 30 μm); (i〇) titanium, titanium tungsten alloy, chromium, chromium copper alloy or nickel vanadium Alloy / copper / nickel / solder bumps or solder balls (the thickness of the copper layer is between (U micron to 1 〇 micron, the thickness of the solder layer is between 10 microns and 500 microns); (11) titanium , titanium tungsten alloy, chromium, chrome-copper alloy or nickel-vanadium alloy/copper column (the thickness of the copper layer is between 1 μm and 300 μm); (12) Qin, titanium tungsten alloy, chromium, chrome-copper or Nickel bismuth alloy / copper column / nickel (copper layer thickness between 10 microns and 300 microns); (13) titanium, titanium tungsten alloy, chromium, chrome copper alloy or nickel vanadium alloy / copper column / nickel / solder (The thickness of the copper layer is between 10 micrometers and 300 micrometers 'the thickness of the solder layer is between 丨 micrometers and 20 micrometers); (14) titanium, titanium tungsten carbide 84 200816373

MliUAUO-UlDrWB gold, chrome, chrome-copper or nickel-stark/copper/nickel/solder (copper layer thickness between 10 and 300 microns, solder layer thickness between 20 and 100 microns between). Another 'assembly method can be wire bonding, Tape Automated Bonding (TAB), chip-on-glass (COG), chip-on-board (COB), flip-chip array substrate flip chip Flip chip 〇n BGA substrate, chip-on-film (COF), chip-on-chip stack interconnection, stacked wafer package structure chip-on-Si-substrate stack interconnection). Another important feature of the structure 8 above the protective layer is that a polymeric material is used as a dielectric layer or an insulating layer on, under or between the patterned metal layers 8〇. The polymeric material can be used to make dielectric layers having a thickness greater than 2 microns. The polymer layer formed of a polymeric material may have a thickness between 2 microns and 100 microns and is preferably between 3 microns and 30 microns thick. The polymer layer 90 (including 95, 98, 99) used on the protective layer 5 may be p〇iyimide (PI), benzocyclobutene (BCB), poly(p-nonylbenzene) ( Paryiene), an epoxy-based material such as an epoxy resin or photoepoxy SU_8, an elastomer (elastomer) such as siiicone supplied by Sotec Microsystems of Renens, Switzerland. Alternatively, a solder mask material used in the printed circuit board industry can be used as the top polymer layer 99 (the topmost polymer layer on all of the patterned metal layers 80). Polyimine can be a photosensitive material (photosensitive material: ^ In addition, polyimine can be - nonionic 85 200816373

Ivix:vj/\ uu-uuTWB

?S^(non.i〇nicp〇lymide) , ^ ^ a AsaW i>^i|^^^^^(ether^basedp^^ vPIMELTM〇y^j^M sub-proliferation or penetration In the ionic heteroimine, it allows direct contact between copper and polyimide. And due to the relationship of nonionic polyimine, the distance between the copper lines or planes in the structure 8 above the protective layer can be close to i micrometers, for example between 1 micrometer and 5 micrometers, in other words, the distance between two metal lines or planes may be greater than 1 micrometer. In addition, for copper metal-based metal lines or planes and polymerization covering the metal lines or planes When the layer is a non-ionic polyimine, the metal line or the plane may be selectively free of a protective layer such as 〇11 (;叩), such as a nickel cap layer. Of course, in formation When a metal line or a plane is formed, a protective layer such as nickel may be formed on the copper layer to prevent copper ions from diffusing into the polymer layer. As shown in Fig. 15K, the purpose of forming an opening in the polymer layer is to Used to connect different patterned metal layers 8〇 to connect the thin lines below The metal layer 60 is either used to connect an extemai circuit. The polymer layer openings include (1) 9919, 9929, 9829, 9519, 9519, 9511, 9512 and 9514 in the first embodiment; (2) 9831, 9834, 9531, 9532, and 9534 are in the second embodiment; (3) 9939, 9939, 9831, 9834, 9839, 9539, 9539, 9531, 9532, and 9534 are in the third embodiment; and (4) 9949, 9949, 9849, 9549, 9511, 9512 and 9514 are in the fourth embodiment. The polymeric material may be photo-sensitive or non-photo-sensitive. Polymer, which is defined and patterned by exposure and development.

, TWB 200816373 mouth, and for Lai New polymer, it takes care of the opening of the first-kib-photoresist layer on the polymer layer, and then exposes and develops the photoresist to shape the photoresist in the photoresist' Dance this light again _ called the violent polymer layer for leg engraving or dry engraving to shape the polymer in the polymer, and finally complete the opening of the polymer layer by removing the photoresist. The size of the polymerization _ _ is between 2 micrometers and a few micrometers, and preferably between 5 micrometers and fine micrometers. In some designs, the opening of the polymer layer may also exceed the size of the micrometer. The other person layer opening can be (4) materialized as _, with _ positive phase (__ book mouth square), rectangle or polygon. The polylayer layer % is located between the protective layer 5 and the bottommost end of the patterned metal layer. The polymer layer opening 95 〇, signal, power supply _ or Vcc) and/or ground reference voltage (Vss) can be transferred between the thin wiring metal layer (9) and the patterned metal layer 8G. For the internal circuit 2 () (including 2 卜 22, ^, called 'polymer layer opening 9 别, 9532, 简 卿 卿 、 、 、, 532, 534, and its polymer layer opening 9531, 9532, 9534 The size is between "micron and 300 micrometers" and is preferably between 3 micrometers and micrometers. For regulators or inks, polymer layer openings, (d),

9514 is respectively aligned with the protective layer openings 519, 519, 5U, 512, 514; for the wafer external circuit 4 〇 (including 42, sentence, polymer layer opening 、 39, (6) 9, H 534 system knife aligning the protective layer opening 539, 539, 531, 532, 534; For the electrostatic discharge anti-Wei Road 44, the polymer layer opening state 9, (6) 1, (6) 2, % work 4 87 200816373 ΜϋυΑ υ υΐΜΛ υΐΜΛ Β Β Β 对准 对准 保护 保护 549 549 549 549 549 549 549 549 549 512, 514, another polymer layer opening 9519, 9519', 9511, 9512, 9514, or polymer layer opening 9539, 9539, 953, 9532, 9534 or the size of the polymer layer openings 9549, 9511, 9512, 9514 It may be larger, ranging from 5 microns to 1000 microns, and preferably between 10 microns and 200 microns. The polymer layer opening 950 on the protective layer opening 5 has two openings In the first open type, the polymer layer is open, for example, the polymer layer opening 9531 is larger than the lower protective layer opening 531, and the polymer sidewall of the polymer layer opening 9531 is located on the protective layer 5. In this type, a smaller one can be formed The protective layer opening 531 further forms a small contact pad on the top of the thin line metal layer. Therefore, the open type allows the topmost thin line metal layer to have a souther winding density (r〇 Uting dens^y); in the second open type, the bottom of the 'f layer opening, such as the bottom of the polymer layer opening Μ%, is smaller than the lower 539, and the polymer port (such as polymer) The polymer sidewall of layer opening 9539) is on the metal interface at the top of the thin-line metal layer. In this view, the layer \\ covers the sidewall of the opening of the protective layer, and the polymer layer is opened as The slope of the sidewall of the polymer layer opening 9539) is less than the slope of the sidewall of the opening of the protective layer and the adhesion/barrier/seed layer formed by subsequent metal sputtering has a good step coverage of zero. Better adhesion/barrier/seed metal step coverage ^The reliability of the wafer is important because the better adhesion/barrier/seed gold ladder can prevent the metal of the thick metal layer from spreading below. Line or polymer 88 200816373

Υο-υ i d TWB layer ' occurs to prevent the formation of intermetallic compounds (IMC) or metal diffusion. The polymer layer opening 980 within the polymer layer 98 is between the patterned metal layer 801 and the patterned metal layer 802. For the internal circuits 21, 22, 23, 24, the polymer layer openings 9831, 9834 are between 1 micrometer and 3 micrometers in size, and preferably between 3 micrometers and 1 micrometer micrometer. . For the polymer layer opening 9829 of the voltage regulator or transformer 41, or the polymer layer opening 9831, 9834, 9839 of the wafer external circuit 4 (including 42, 43) or the polymer layer opening 9849 of the ESD protection circuit 44 The size can be larger, ranging from 5 microns to 丨 (nine) microns, and preferably between 10 microns and 200 microns. The topmost pads of the patterned metal layer 802 exposed by the polymer layer openings 99 in the top polymer layer 99 can be used to connect external circuitry or as contact points for probes in chip testing. For the internal circuits 21, ^, 24, the top polymer layer 99 is not provided with a polymer layer opening; in addition, the polymer layer opening 9919 of the voltage regulator or transformer 41, the touch, or the chip external circuit 4 (including 42, 43) polymer layer opening 9939 or the electrostatic discharge protection circuit material of the poly person layer opening 9949, class 9, the size can be larger, the range is between 5 micrometers to (10) exposure, and It is preferred between 10 microns and 2 microns. The signal, power supply or ground reference voltage of the structure 8 on the input protection layer is transmitted to the internal circuit 2 through the fine circuit structure 6, the voltage regulator or the transformer 1 or the external circuit 40 or the electrostatic discharge protection circuit 44. in. In addition, fine line gold = knot 89 200816373

Jvmu a υο-υ 13 Γ WB structure 63 may be a thin line metal layer 60 formed by a shortest path method (for example, in a roughly aligned stacking manner) and a guide plug 6G, as shown in the figure 631, 632, 634, 639 and 639,. The 彡 彡 technology system for making the reduced-layer JiS structure 8 is significantly different from the lithography technique for the integrated circuit under the protective layer. The lithography process above the protective layer also includes coating and exposure photoresist. There are two types of photoresists for the structure 8 above the silk layer. The system is: (1) wet film photoresist (1 coffee _ _ _ _ _), which uses single or multiple spin coating or printing ( P is more ng) formed. The thickness of the wet film photoresist is between 3 microns and 60 microns, and preferably between 5 microns and 4 microns; and (2) dry film photoresist, It is formed by a laminating method. The thickness of the dry film photoresist is between 3 Å and 300 μm, and preferably between 5 Å and 15 Å. Further, the photoresist may be a positive type (p0Sitive_type) or a negative type (negative 4ype), and a positive-type thick ph〇t〇resist is preferable in obtaining a better resolution. When the polymer layer is a photosensitive material, the polymer layer can be patterned using only a lithography process (without etching). The photoresist is exposed using an alignment machine (with a job sinker) or a double (IX) stepper. This double (1) refers to the ratio of the pattern on the reticle on the wafer when the light beam is projected onto the wafer from a reticle (usually composed of quartz or glass) and is on the reticle. The pattern ratio is the same as the pattern ratio on the wafer. The beam wavelength used by the aligner or double stepper is 436 nm (g-line), 397 nm (h_line), 365 nm (i_lineh^ 200816373)

ivLbu/\ υο-υ 13 TWB h-line) or g/h/i line (combined with g_line, h-line and i-line). Use a double stepper (or double aligner) with a beam wavelength of g/h line or g/h/i line to provide greater light on exposure to thick photoresist or thick photosensitive polymers Lightintensity. Since the protective layer 5 can protect the underlying metal oxide semiconductor and the fine circuit structure 6 from moisture intrusion and penetration of sodium or other mobile ions and gold, copper or other transition metals, an integrated circuit wafer The upper protective layer structure 8 can be processed in a level 10 or a less stringent environment (e.g., grade 丨 (10)). A Class 100 clean room allows the maximum number of dust particles per cubic inch to be: no more than one dust particle containing 5 micrometers or less, and no more than 1 dust particle containing 1 micrometer or more. The dust particles containing more than or equal to 〇·5 μm do not exceed the excitation particles, the dust particles containing more than or equal to 〇·3 μm do not exceed 300 particles, and the dust particles containing 大于·2 μm or larger are not Zhao k 750 3 Particles larger than or equal to micron do not exceed 3 lions. The component layer 2 includes internal circuits 2 (including 21, 22, 23, and 24) in all of the real cases, and (1) the regulator or transformer 41 is in the first embodiment, and (7) the chip is externally connected (including 42 43) In the third embodiment; (3) Electrostatic discharge protection circuit 44 ^ In the example. In all embodiments of the invention, the internal circuitry, such as (including 曰24), includes a signal node, and the signal node is not/outside.卩 (Outside the day) circuit connection. When the signal of the internal circuit rib needs to be 'Bu, the signal must pass before 200816373 before connecting to the external circuit.

Miiu a υο-υ 13 fWB A chip-terminated external circuit, such as a wafer tri-state buffer, a chip-terminated external driver, a chip-terminated external receiver, or other external input/output (1/〇) circuit. Therefore, the internal circuit does not include a chip-terminated circuit. In the present invention, the internal circuit 20 (including 21, 22, 23, 24) may be an inverter (Nor gate) or an NAND gate, or an inverter (inverter). ), an AND gate, a gate (〇Rgate), a static random access memory cell (SRAM cell), a dynamic random access memory cell (DRAM cell), non-volatile stone Non-volatile memory cell, a flash memory cell, an erasable programmable read-only memory cell (EPROM cell), a read-only memory cell (R0MceU), a magnetic Random access memory (MRAM) unit, a sense amplifier, an operational amplifier (operational ampUfler, 〇p Amp, 〇pA), addition (adder), ^ - multiplex (multiplexer), ^-diplexer, multiplier, a class of analog/digital converter (A/D c〇nverter), a digital/analog converter (D/A converter), a complementary CMOS sensor cell, photo-sensitive diode, complementary A metal oxide semiconductor, a pair of carriers complementary metal oxide semiconductor, a pair of carriers% passage (1) Jie Shu 〇1 & 1% circuit) or the analog circuit (analog circuit). In addition, the internal circuit 20 (including 21, 22, 23, 24) is composed of at least one MOS transistor, such as an anti-gate or a gate, and the gate or the gate is at least one gold. Oxygen semi-transistor, the other gold-oxygen semi-transistor can be "channel 92 200816373

Iviiiu/\ υο-υ 13 TWB Width (Channel length) / Channel length" An N-type MOS half-electricity ratio between 〇·ΐ and 5 or between 0 and 2 to 2. A crystal, or a Ρ-type MOS transistor having a channel width/channel length ratio between 0.2 and 10 or between 〇4 and 4. In the first embodiment, the internal circuit 20 (including 21, 22, 23, 24) may be a power management chip or a power supply chip, the power management chip and the power supply chip being at least one MOS transistor And the MOS semi-transistor may be a p-type MOS transistor having a channel width/channel length ratio of between 4,000 and 400,000 or between 4 and 40,000, or Is an "N-type MOS semi-transistor with a channel width/channel length ratio between 2,000 and 200,000 or between 2, 〇〇〇 to 2 〇, 〇〇〇 < The currents of planes 81 and 82 are between 500 mA and 50 amps or between 5 mA and 5 mA. . S 'internal circuit 2 〇 can be defined by its peak input or output current (ie current flowing through a metal line or plane) or by its MOS half-transistor size (channel width divided by channel length ratio) To define. - The external circuit of the chip 4 (including 42, 43) can also be defined by its peak input or output current (ie current flowing through the metal line or plane), or by its gold oxide half crystal size ( The width of the channel divided by the ratio of the length of the channel) is wire. The definition of the internal circuit 2Q. and the external circuit 40 (including 42, 43) is applicable to all embodiments of the present invention. Therefore, 'Broadcasting can be used to ruin the road and protect the floor through the Lai layer. 93 200816373

金属 The metal line or plane above uo-unTWB is connected to the gate and gate, gate and source, gate and drain, source and source and drain of at least two gold and semi-crystals in the same line component It is bungee jumping and bungee jumping. Power Sources The dimensional characteristics and electrical characteristics between the patterned metal layer 80 and the thin wiring metal layer 60 of the structure 8 above the protective layer in all embodiments of the present invention will be described and compared. (1) Thickness of metal wiring The thickness of each of the patterned metal layer 8G is between 2 micrometers and 15 micrometers, and preferably between 3 micrometers and 2 micrometers, and each The thickness of the fine-line metal layer 曰 is between 0.05 μm and 2 μm, and preferably between 〇·2 μm and j μm. For a wafer designed in accordance with an embodiment of the present invention, the thickness of the patterned metal layer over a protective layer is given to the thickness of the fine-line metal layer, and the thickness ratio of the two is between 2 and 250. The range, with a thickness of 4 to 2 = = (2) the thickness of the dielectric layer per thickness of the protective layer (usually an organic material, such as a polymer), such as the thickness of the polymer layer 90, Between 2 micrometers and 15 micrometers, and preferably between gamma micrometers and 3 micrometers, and dielectric layer 3 per thin dielectric layer (compressive materials are inorganic materials such as oxides or nitrides) The thickness is between _micron and 2 micron' and bribes in (). 94 200816373

Ivu^vj.rv wyj ij TWB For a wafer designed according to an embodiment of the present invention, the thickness of the dielectric layer above a protective layer is greater than the thickness of any fine-line dielectric layer, and the thickness ratio of the two is It is preferably in the range between 2 and 250, and in the range between 4 and 20. (3) The sheet resistance of the metal layer and the sheet resistance of the resistor-metal layer are calculated by calculating the metal resistivity (metal is obtained by the thickness of the metal. A copper (thickness of 5 μm) material is patterned over the protective layer. The sheet resistance is approximately 4 milliohms per square (miii-ohm), while the sheet resistance of the patterned metal layer over a protective layer of gold (thickness 4 microns) is approximately 5.5 milliohms per square. The sheet resistance of the patterned metal layer above a protective layer is in the range of from 0.1 milliohms per square to 10 milliohms per square and is between 1 milliohm per square to 7 milliohms per square. The range is better. The fine-line metal layer of aluminum (thickness 〇·8 μm) formed by sputtering has a sheet resistance of about 35 ohms per square, and a copper is formed by the damascene process (thickness is 0.9 micron) thin wire metal layer with a sheet resistance of approximately 20 milliohms. The chip resistance of a thin line metal layer ranges from 4 millimeters per square millimeter to 4 (8) milliohms per square inch; In the mother square 15 milliohms to every square The range between ohms is preferred. The resistance per unit length of the metal line is obtained by dividing the sheet resistance by the width of the strip. The visibility is between 2 micrometers and 2 (8) micrometers, and preferably between 2 micrometers and 50 micrometers, and the lateral design standard (width) of the fine-line metal layer is 95 200816373

MEUA υϋ-UlMWB 疋; 丨 between 20 nm and i5 μm, and preferably between nanometers and 2 μm. The resistance per mm of the patterned metal layer above a protective layer is between 2 milliohms of resistance per mm length to 5 ohms per millimeter and is 5 inches per millimeter. Between milliohms and 2.5 ohms per millimeter is preferred, and the resistance per millimeter of a thin-line metal layer is between 500 ohms per millimeter and 3 millimeters per millimeter. It is preferably between $(9) milliohms per mm to 5 ohms per millimeter. For a wafer designed in accordance with an embodiment of the present invention, the unit length resistance of the patterned metal layer over a protective layer is less than the unit length resistance of any thin wiring metal layer, and the unit length resistance ratio of the two (fine line metal The layer is patterned from 3 to 250 in comparison to the patterned metal layer above the protective layer, and a range between 10 and 3 Å is preferred. (4) Capacitance per unit length of metal lines (capacitance (four) blood red ieng also) The unit length electric valley is related to the type and thickness of the dielectric, the width, distance and thickness of the metal line, and the surrounding metal in the horizontal and vertical directions. The polyethylenimine has a dielectric constant of about 3.3, and the phenylcyclobutene has a dielectric constant of about 2.5. Next, please refer to FIG. 20, which is exposed on the same patterned metal layer 802. A patterned metal layer 8〇2χ has two adjacent patterned metal layers 8 and a patterned metal layer. 802z' and a patterned metal layer 801w' under the patterned metal layer 8〇2 and the patterned metal layer 801w is separated from the patterned metal layer 802 by a polymer layer 98. Similarly, Figure 20 is also revealed in the same fine line gold 96 200816373

On the MJbUA υο-υ 13 fWB genus layer 602, a thin line metal layer 6〇2x has two adjacent thin line metal layers 602y and fine line metal layers 602z, and a fine line under the thin line metal layer 6〇2 The metal layer 601w is separated from the thin wiring metal layer 602 by a thin wiring dielectric layer 30. The unit length capacitor of the patterned metal layer 802x and the thin line metal layer 6〇2χ includes three components: (1) platecapacitance, which is the ratio of the metal line or the plane width divided by the dielectric thickness. a function; coupling capacitance, Qx (= Cxy + Cxz), which is a function of the ratio of the metal line or plane thickness, or the ratio of the line spadng, and (3) Fringing capacitance, c weight (=Cfl+c., which is a function of the thickness of the metal line or plane, the spacing between the phased metal lines or planes, and the thickness of the two poles. A patterned metal layer The capacitance per millimeter is between 0.1 PF (pic〇Farads) per mm to 2 mpg per mm, and is preferably between PF per mm long and l.5 pF per filament length. The capacitance per millimeter of the secret metal layer is between each length of the wire. It is preferably 4 centimeters per millimeter long, and is preferably between 4 pF per mm long and 2 pF per mm long. The wafer designed by the embodiment of the invention, the single-length capacitor system of the bribe metal layer, Any single-recorded capacitance of the thin-line metal layer, and the ratio of the early-bit length of the two (the thin-line metal layer is larger than the patterned metal layer) is between Μ and 2〇, and is between 2 and The range between 1() is preferred. (5) Resistor-capacitance constant of metal lines (RCc〇n plane) 97 200816373

Ivmo/\ υο-uoTWB - The signal transmission time on the metal line is calculated using the RC delay post d (four). Based on the contents of (3) and (4) above, the resistive capacity delay of a patterned metal layer is between _3 to 1 Gps (pi (10) coffee d) per mm and 0.25 to 2 ps per mm. The range between (pico second) is better, and a thin line 2 is between 1G and 1(mm)_range and 40 to 500ps per mm. Between the scope of the offering (4) is better. _ The wafer of the implementation of the yam, the RC paopagati〇n time of the reduced metal layer is less than any fine, secret The unit length resistance transfer _ of the layer, and the unit length RC paopagation delay time ratio (the thin line metal layer is more than the patterned metal layer) is between 5 and 500, and It is better between 1〇 and 3〇: Again, please refer back to Figure 15C to Figure 15L, which is revealed in the wafer 10 of the Yuancheng (such as 苐15A map or 15B shows the steps of forming the structure 8 above the protective layer. Each patterned metal layer 8 is formed by an embossing process (with the inlay copper process under the protective layer 5). Referring to Fig. 15C, a polymer layer 95 is deposited on the protective layer 5 and exposes the metal pad 600 exposed by the protective layer opening 50 through the polymer layer opening 950. If the polymer It is in liquid form, which can be deposited by spin coating or printing. If the polymer is a dry film, the dry film can be formed by a bonding method. For photosensitive polymers, polymer layer 95 utilizes alignment machine 98 200816373

MbUA Ub-υ 13 TWB or - (IX) stepper is exposed by fresh light, and through development, when the polymerized (4) 95 towel forms a polymer phase, the composition is non-photosensitive. 'And through the conventional twisting wire _ the polymer layer opening 950. The manner of patterning the polymer layer may be in the following manner: a hard mask (for example, a layer of oxidized stone, not shown) is deposited on the polymer layer 95 after coating the photoresist. On the ' while engraving the polymer layer (five) mouth, this ^ mask has a slow etchrate. In addition, the manner of patterning the polymer layer % (ie, the polymer layer 95 has a polymer layer opening 95 〇) may also utilize a screen printing method by using one of the patterned holes (h〇ie). Metal screens are formed, and the manner of screen printing does not require exposure and development. If the polymer layer is fine, it can be formed in the first sheet before it is attached to the wafer, so exposure and development are not required in this way. In addition, since the polymer layer 95 can be formed on the protective layer 5, the lowermost patterned metal layer 8 on the protective layer 5 can be formed on a relatively flat surface provided by the upper surface of the polymer layer. _L, so that it is possible to prevent leakage current between adjacent lines of the patterned metal layer 80, and to prevent coupling between the patterned metal layer 8 and the fine-line metal structure under the protective layer, and thus it is possible to provide A better electrical mic, she can also be used to omit the polymer layer 95 and save money in some applications. The polymer π 950 is aligned with the protective layer opening 5 〇 ' and the polymer layer opening 95 〇 may be larger or smaller than the protective layer opening 5 〇. Further, the formation of the protective layer opening 50 and the polymer layer opening 950 may also be the first 99 200816373

Ivudvj/\ υο-υ ij TWB deposit polymer layer 95 on the protective layer 5, then form a polymer slab 95 〇, and finally form a protective layer opening 5 〇, in this way, the size of the polymer layer opening is about The same size as the protective layer opening 50. At the same time (4), as shown in Figures 15D to 15H, a embossing process for forming the patterned metal layer 801 is revealed. In Fig. 15D, an adhesion/barrier/seed layer 8011 is deposited on the polymer layer %, in the polymer layer opening 95〇, and in the protective layer opening π 5G, wherein the adhesion is formed by deposition of money/ A preferred manner of barrier/seed layer 8〇11. When the material forming the thick metal layer is gold, the adhesion/barrier/seed layer_ is first formed by sputtering to form a thickness of 3,_A (A) titanium alloy or a bonding/barrier layer. Then, a gold seed layer having a thickness of W0 Å is formed by sputtering. When the material for forming the thick metal layer is copper, the formation of the adhesion/barrier/seed layer 8011 is fine (four), and the thickness of the adhesion/barrier layer of the chromium metal is formed, and the formation of the residence is 1, The adhesion/barrier layer of the metal is either an adhesion/barrier layer of a thickness of 3,_ private-titanium tungsten alloy, which is then sputtered to form a sub-layer having a thickness of 5, Å. Figure 15E reveals that a photoresist layer 71 is deposited and patterned on the adhesive seed layer __ sublayer. The photoresist layer 71 is applied by spin coating, and is exposed by an alignment machine or a 10-fold stepper, and a photoresist layer opening is formed in the photoresist layer 71. The photoresist layer opening technique is used to define the formation of a metal line or plane in the subsequent process with the polymer layer opening 95 and the protective layer opening %, and the contact is on the exposed metal to 0, and the connection is exposed. The metal connection _. In the first picture, to the electric mine 100 200816373

The MliUAUO-Ul^TWB pattern forms a thick metal layer 8012 on the seed layer exposed by the photoresist layer opening 710. The thick metal layer 8012 can be a gold layer having a thickness between 15 microns and 5 microns or a steel layer having a thickness between 2 microns and 2 microns. A cap/barrier layer (not shown) may be selectively formed on the thick metal layer 8〇12 by electroplating or electroless ore. An assembly/contact layer (4), which is not shown in the figure (10), may be further selectively formed on the thick metal layer 8012 and the barrier/barrier layer by means of electromineral or electroless plating. The assembly/contact layer may be of a thickness; a gold layer, a m- or a sap layer between G.G1 and 5 microns. As shown in Fig. 15G, the photoresist layer 7 is removed. In Fig. 15H, the self-aligned wet etching or dry etching is used to remove the layer not covered by the thick metal layer 8012. Adhesive / barrier / seed layer. When the removal is performed by the secret engraving method, a depressed portion _ercut) 8011' is formed at the bottom of the sidewall of the patterned metal layer 801, wherein the depressed portion 8〇11 is tied under the thick metal layer view, and although different When an anisotropies dry etch is applied, the above-described depressed portion 8011 does not occur. The whistle is also shown in Figures 151 and 15J, which expose the steps of forming a polymer layer 98 and a patterned metal layer 802 by the processes described in Figures 15C through 15H. Further, the processes shown in Figs. 151 and 15J can be repeatedly used to form the second metal layer, the fourth metal layer or more metal layers. If the protective layer upper structure 8 includes only two metal layers (patterned metal layer 8〇1 and patterned metal layer 802), a capply layer 99 is deposited on the patterned metal layer 101 200816373

Ινΐϋ〇/\ υο-υ 13 TWB 802 (the top of the face) and the polymer layer 98 covered by the patterned metal ^8〇2 are shown in Figure 15. The polymer layer opening 99 is formed in the top polymer layer 99 to be sub-exposed as a contact interface for connecting an external circuit. In some applications, such as when the thick metal layer is gold, the top polymer layer 99 can be optionally omitted. Figure 15 shows a wafer having both a fine line structure 6 and a structure 8 over the protective layer. The polymer layer opening of the top polymer layer 99 exposes the contact pads 8000. The wafer ore is cut (cut) into a plurality of individual wafers, and the contact pads of the individual wafers can be connected to an external circuit by the following method, which is: (1) a wire bonding process of a wire bonding process (gold wire, Ming (2) copper bumps, tantalum bumps or other metal bumps on other substrates), the substrate may be a stone wafer, a stone base, a ceramic substrate, an organic substrate, a spherical shape a grid-like array (BGA) substrate, a snagging gamma) substrate, a flexible tape or a glass substrate, and the height of the bumps on the substrate is between 5 micrometers and 30 micrometers H. Preferred between micrometers and 2 micrometers; (3) pillars on other substrates (gold pillars, copper pillars, solder pillars or other metal pillars) 'this substrate may be a stone wafer, a stone substrate, a germanium substrate , organic substrate, spherical grid array (BGA) substrate, flexible substrate, flexible tape: fleXiWe tape) or glass substrate 'and the height of the column on the substrate is ι〇 Between micron and 200 micron, and preferably between 3 and 12 micron; (4)-wire _ead Frame) or - a flexible conductor on the end of a metal wire (gold bump, copper bump, solder bump or other metal bump), this substrate 102 200816373

Ivuiu/\ uo-u i d fWB and a bump of between 5 micrometers and 20 is preferably between micrometers and 3 micrometers. A contact structure 89 formed on the contact pads 8A of an application towel can be used to connect an external circuit as shown in Fig. 15L. A bump underlying metal layer _) is formed under contact structure 89 for use as an adhesion and diffusion barrier. The contact structure can be (1) a solder pad formed by electro-mine or screen printing (thickness is between α! micron micrometers, and the difference between the money and the micron money) or Rod bumps (having a height between 1 〇 micron and micron, and preferably between 3 〇 micron and 12 〇 micron). Then, using the reflow-reflow process to form a spherical solder ball (the solder pad or the solder bump can be: 1) high-feed material (highleadsG a tin-lead alloy (PbSn) with a lead content of more than 85% by weight; 2 • eutectic solder, for example, a lead alloy containing about 37% by weight of lead component and a weight percentage of about 63 Å. , 3. Error-free solder (iea (j_g*ee, such as tin-silver alloy (SnAg) or tin-copper-silver alloy (SnCuAg). In addition, the under bump metal layer 891 may be a composite layer as described below (from bottom to top) Arrangement, including: titanium/nickel, titanium_nickel, titanium-tungsten alloy/nickel, titanium-tungsten alloy/copper/nickel, titanium/nickel/gold, titanium/copper/nickel/gold, titanium-niobium alloy/nickel/gold, Titanium alloy / copper / nickel / gold, titanium / copper / nickel / handle, titanium tungsten alloy / copper / recorded / 妃, chrome / chrome copper alloy, nickel vanadium alloy / copper, nickel / copper, nickel vanadium alloy / gold, Nickel/gold or nickel/handle; (2) gold pads formed by electroplating (thickness between ojm and 1μm, preferably between 1m and 5m), or Gold bump Between 103200816373

Ινΐϋ〇/\ υο-υ 13 TWB is between 5 micrometers and 40 micrometers, and preferably between 丨〇 micrometers and 2 micrometers. In addition, the under bump metal layer 891 may be a composite layer of titanium, titanium tungsten alloy, button, nitride button, titanium/copper/nickel (from bottom to top) or titanium tungsten alloy/copper/recorded composite Layer (arrangement from bottom to top); (3) metal ball formed by ball m〇unting. The metal ball may be a solder ball, a copper ball coated with a nickel layer on the surface, a copper ball coated with a nickel layer and a solder layer, or a nickel layer and a gold layer coated on the surface. a copper ball. In addition, the diameter of the metal sphere is between 1 Å and 500 μm, and is between 5 Å and 300 μm. In addition, the metal ball may be directly soldered on the surface of the contact pad 8000 exposed by the polymer layer opening 990 or on the under bump metal layer 891, and the under bump metal layer 891 formed to solder the metal ball may be Composite layers (from bottom to top) as described below, including titanium/nickel, titanium/copper/nickel, titanium-tungsten alloy/nickel, titanium-tungsten alloy/copper/record, titanium/nickel/gold, Titanium/copper/nickel/gold, titanium alloy/nickel/gold, titanium tungsten alloy/copper/nickel/gold, chin/copper/nickel/palladium, titanium tungsten alloy/copper/nickel/palladium, chrome/chromium copper alloy, Nickel alloy / copper, nickel / copper, nickel vanadium alloy / gold, nickel / gold or nickel / handle. In addition, after the metal ball is adhered, a s〇lder reflow process is usually required. After forming the contact structure 89, the wafer on the wafer is cut by means of metal cutting or cutting for packaging or assembly to be connected to an external circuit, wherein the assembly method can be used to tap the wire (connected to external organic, ceramic, glass). Or a pad on the substrate, or a wire connected to a lead frame or a flexible tape), tape automated bonding (TAB), tape carrier (4) e-chip_ca^ier, Tcp) package, glass Cladding seal 104 200816373

MtiUAUO-UnfWB package (COG), wafer direct package (COB), flip chip on BGA substrate, film flip chip bonding (C0F), film flip chip package (chip 〇n flex), stack A multi-chip package structure (dlip-on-chip stack interc_eetiQn), a chip-on_si_substrate stack interconnection structure, and the like. In the embossing process shown in FIGS. 15C to 15K, the step of exposing the exposed metal layer to form a patterned metal layer is to form an adhesion/barrier/seed layer once, and then forming a photoresist layer and The patterned metal layer is also plated only once, and finally the photoresist layer is removed and the adhesion/barrier/seed layer not covered by the patterned metal layer is removed. This type of system is singularly convex _ngle_embGss p_ss), that is, the process includes only one lithography process and one plating before removing the adhesion/barrier/seed layer not covered by the patterned metal layer. Process. A double-embossing process can form a patterned metal layer and a metal plug through the same adhesive/barrier/seed layer, while removing the adhesion that is not covered by the W-coated metal layer/ Before the barrier/seed layer, the lithography process and the electro-mine process are completed twice, wherein the first lithography process and the electroplating process are used to form a _ metal layer, and the second micro-hard process and electroplating Paste is used to form metal plugs. Referring to the first through the drawings, a double embossing process for forming the structure 8 over the protective layer on the wafer 10 as shown in the first or first SB is disclosed. Double float & preparation and _ 15C mesh · 15G head mouth corpse / Γ not the same as the earlier process 105 200816373

iVlUU/V UO-U1D TWB production steps. In Figure 15G, it removes the photoresist and leaves the episode/transfer/seed layer not under the thick metal layer 2. At this point, the steps of the double embossing process start to be different from the single embossing process. Please show the 16A to 16L at the same time, which reveals that the metal layer is formed by using the double embossing process. Forming with the metal plug 898' and using a single embossing process to form the topmost metal 35, forming an example of the _ metal layer structure above all of the implemented protective layers of the present invention _ the first lithography process The metal layer 8 (Fig. 15D to 15G) is shown with the electroplated residue. Next, please refer to the seeds in the adhesion/barrier/seed layer view as shown in Fig. 16A and Fig. 16B. a layer and a thick metal layer formed by electroplating, depositing a photoresist layer 72, and etching the photoresist layer 72 such that the photoresist layer 72: (1) forms a photoresist layer opening 720 on the thick gold (four), And exposing the thick metal layer (4) by using the photoresist layer opening 72; and/or (2) forming a photoresist layer opening 72〇 on the seed layer along with the adhesion/barrier/seed layer, and using the photoresist layer After opening 72〇, the seed layer of the adhesion/barrier/seed layer_ is exposed. Continue to 'remove the photoresist layer 72 A second electroplating process is performed to form a metal plug in the photoresist layer opening 720. In addition, a metal layer having a horizontal level lower than that of the metal plug 898 may be formed on the seed layer of the adhesion/barrier/seed layer. Weng, this metal layer 898 can be used on the package. The metal layer _ can be thinner than the thick metal layer or thicker than the thick metal layer. When the thickness of the metal layer is less than the thickness of the thick metal layer side 2 When, for example, less than 5 microns (preferably between i microns and 3 microns), Jin Gu can close to make a thicker metal layer view 106 200816373

MbUA υο-ui^TWB has a high density of interconnects, however, when the thickness of the metal layer 898 is greater than the thickness of the thick metal layer 8012, for example, greater than 5 microns (preferably, between 5 microns and Between 1 and 10 microns, the metal layer 898 can be used to make a lower resistance than the thick metal layer 8012. Then, referring to FIG. 16C, the photoresist layer 72' is removed to expose the thick metal layer 8012, the metal plug 898, the metal layer 898, and the adhesion under the thick metal layer 8012 and the metal layer. Barrier/seed 8〇11. Referring to Figure 10D, the adhesive/barrier/seed layer 8011 is removed from the thick metal layer 8〇12 and the metal layer 8 by using the side (4) and/or the dry side etch. Therefore, the patterned metal layer 8〇1, the metal plug 8卯 and the metal layer 8 are formed in this stage shown in Fig. 16D. Continuing to see Figure 16E, a polymer layer 98 is formed over the metal plug _, the metal layer _, the patterned metal layer, and the exposed first polymer layer 95. Referring to the schematic, the surface of the polymer layer 98 is planarized by a grinding, mechanical or chemical mechanical polishing process until a metal plug is exposed. Then, please refer to the same process as the first embossing process to form the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Continuing, referring to Figure 16L, a top polymer layer 99 is deposited and patterned to complete a protective overlayer structure 8 having two patterned metal layers. In addition, on the implant _ 〇 and/or the package, a contact structure 89 may be formed on the fine contact surface exposed by the polymer layer opening 99 如 as shown in the drawing. In addition, the patterns described in the 15th to 15th and the 16th to 16th are used to form the pattern 107 200816373

The fabrication steps of the iVLtlO/\UO-U13 fWB metal layer 801 and the metal embossing 898 double embossing process may also be repeated in the opening > into the second patterned metal layer (the topmost metal layer) and the second metal plug ( The figure is not shown above and this second metal plug can be used as a contact structure for connection to an external circuit. Finally, the descriptions and explanations relating to the spirit map to the 16L _ are applicable to all embodiments of the present invention. Referring to FIGS. 17A to m, a process step of forming a patterned metal layer, a patterned metal layer, and a patterned metal f 8〇3 is disclosed. The layered and patterned metal layer is formed by a double embossing process, and the patterned metal layer 8〇3 is formed by a single embossing process. First, as described in Figs. 15D to 15G and FIGS. 16D, the first double embossing process is used to form the patterned metal layer and the metal plug 898. Next, the process step '' as shown in Figs. 16E to 16F is to planarize the polymer 3598 after forming the polymer 3598 until the metal plug _ is exposed. Continuing to refer to the figure, the process steps before forming the patterned metal layer 8〇2 and the process of forming the patterned metal layer 801, the metal plug _ and the polymer layer 98 by the double embossing process in FIG. The steps are the same. However, for this Guna-extra metal layer, the design of the patterned metal layer and the metal plug base 898 in the figure is slightly different from the patterned metal layer of the tear-off pattern and the metal-based 898 Different. For the county, please refer to the process steps described in Figure 17 to Figure 1 to repeat the process of the process from the 15D to the continent and the 16A to the first to form a case of a gold metal plug 897 and -^ 108 200816373

ivubUA υο-υ i dTWB layer 97, and violent (four) metal plug 897. Silk mica, which is formed in the following manner: (1) deposition-adhesion/barrier/seed layer view 1; ship resistance layer; (3) open electrode in the photoresist layer, a thick metal layer; and (4) remove this The photoresist layer is formed to have a structure as shown in Fig. 17A. Then, referring to the ΐ7β figure, the photoresist layer 74 is deposited and patterned to form the photoresist layer opening 74 on the thick metal layer 8022, or directly form the photoresist layer opening, in the adhesion/barrier. / Seed layer 8021 on the seed layer. Referring to FIG. 17C, a metal plug 7 and a metal layer 897 are formed in the photoresist layer opening 740 and the photoresist layer opening 74 by means of electric ore, and the metal layer 897' can be used as a metal layer. 8卯, the same use. As shown in Figs. 17D to 17E, the photoresist layer 74 is removed, and the adhesion/barrier/seed layer 8〇21 which is not under the thick metal layer 8022 and the metal layer 897' is removed. Referring also to Figures 17F through 17G, a polymer layer 97 is deposited and the polymer layer 97 is planarized until the metal plug 897 is exposed. Next, please refer to FIGS. 17H to 171 at the same time, which discloses a step of forming a patterned metal layer 803 using a single embossing process, which is described as follows: (1) deposition adhesion/resistance early/seed layer 8031; (2) depositing and patterning a photoresist layer; (3) forming a thick metal layer 8032 by electroforming; and (4) removing the photoresist layer and removing the layer of the metal layer by self-alignment (seif_aiigned) Adhesive/barrier/seed layer 8031 under 8032. Finally, see Figure 17J, which reveals the formation of a polymer layer opening 990 by depositing a top polymer layer 99 and patterning the top polymer layer 99. Exposed to work 109 200816373

ivlC/Vj/\ υο-υ i j TWB is a complete structure for connecting the connection pads 8〇(8) to one of the external circuits. Referring to FIGS. 18A to 181, another process step of forming a patterned metal layer 801, a patterned metal layer 802, and a patterned metal layer 803 over a protective layer is disclosed, wherein the patterned metal layer is patterned. The 8 〇 1 舆 patterned metal layer 803 is formed using a single embossing process, and the second metal layer is formed using a double emboss 2 . First, referring to Fig. 18A, the patterned metal layer 8〇1 is formed by a single embossing process as described in the first to the first. Next, a polymer layer is deposited by patterning as described in Fig. 151, and the layer 98 is patterned to form a polymer layer opening 980 exposing the patterned metal layer 801. However, in order to accommodate an additional metal layer, the patterned metal layer and the polymer lai p Μ (4) design of Figure 18A are slightly different from the design of the i5i figure = the metal layer and the polymer layer opening. different. Further, as shown in the first to the first FIG. 1SG, the process steps of forming a patterned metal layer and a metal plug 7 using a double embossing process are disclosed, and are as follows: (1) Please refer to As shown in Fig. 18B, deposition formation - adhesion / barrier / seed: kiss '(2) eye as shown in Fig. 18C, depositing a photoresist layer 72, and etching the photoresist layer to form a photoresist layer opening 72〇, then in the photoresist of the photoresist layer η: a thick metal layer is plated in the second 720 with: and (3) the photoresist layer η is removed to form the structure shown in FIG. Then, the photoresist layer 73 is sub-patterned to form a photoresist layer opening 730 in thick gold 110 200816373

丄uo-u 1 j TWB is on the layer 8022, and/or the photoresist layer opening 73 is formed on the seed layer of the adhesion/barrier/seed layer 8021. Continuing, by means of electric ore, a metal plug 897 and a metal layer 897 are formed in the photoresist layer openings 73A, 730', and the metal layer 897' can be used as described in FIG. 16D. The same use of the metal layer 898. Referring to Figs. 18F to 18G, the photoresist layer 73 is removed, and the adhesion/barrier/seed layer 8〇21 which is not under the thick metal layer 8022 and the metal layer 897' is removed. Referring to Figure 18H, a polymer layer 97 is deposited and the polymer layer 97 is planarized until the metal plug 897 is exposed. Finally, please refer to FIG. 181, which illustrates the formation of the patterned metal layer 803 by the single embossing process described in FIGS. 17H to 171, and by depositing a top polymer layer 99 and a pattern. The top polymer layer 99 forms a polymer opening 99 that exposes a complete structure that is connected to the contact pads 8A of the external circuit as a connection line. Referring to FIGS. 19A to 19G, the process of forming a protective layer upper structure 8 on the wafer 1A as shown in FIG. 15A or FIG. 15B is disclosed, wherein the patterned metal layer 801 is The pattern is formed using a double embossing process, and the patterned metal layer 802 is formed using a single embossing process. First, in the i9A picture, use the 15D picture to 帛! The double embossing light step described in the 5G and 16A to 16F forms a patterned metal layer 801, a metal plug 898, a metal layer 898, and a polymer layer 98. Next, please refer to Fig. 19A to the touch diagram at the same time, which uses a same single embossing process as described in Figs. 15C to 15K to form a pattern 111 200816373

The MECiA U6-015TWB metallization layer 802, the polymer layer 97, a top top polymer layer 99, and the "polymer layer opening 990 expose the contact pads 8" and will not be described in detail herein. Finally, please refer to Figure 19H*, which cuts (cuts) the wafer into a plurality of individual wafers' and connects the external circuits through a paste-filled sugar pad circle, for example, using a wire-bonding wire 89, such as gold. Wire, inscription, wire or copper wire) Connect external circuits. Next, please refer to FIG. 21A to FIG. 21M, which are examples of the invention applied to a dynamic random access memory (DRAM) wafer in combination with the technical contents of the above embodiments and the structure above the protective layer. . First, as shown in FIG. 2ia, a plurality of dynamic random access memory cells (not shown), a plurality of external circuits, and a plurality of external circuits are disposed in the wafer 1A as shown in FIG. 15A or FIG. 15B. a plurality of internal circuits 2 〇, and at least an electronic fuse (electrical fijse, E-click 5 and at least one laser fUse 26 are respectively formed in the thin circuit structure 6 of the wafer 1), the fine circuit structure 6 includes four contacts, respectively, a first contact, a second contact, a second contact, and a fourth contact (not shown), and the electronic fuse includes a first end and a second An end point (not shown), and the first and second contacts of the thin circuit structure 6 are respectively connected by the first end point and the second end point of the electronic fuse 25 (for example, in the fine line structure 6) - the first-contact and the second contact of the first-thick-line metal layer. 'In addition, the laser fuse 26 also includes a third end of the line structure 6 which is not shown in the first end & a contact and a fourth turn (for example, a first contact and a second contact of a second thin line metal layer in the fine line structure 6) As regards the wafer 10112200816373

lVLGU/\ UO-U1D TWB structure and user's part refer to the content of the above 1st SA diagram, * the internal circuit 20 provided on the substrate 1 please refer to the part of the internal circuit 2〇 in the series of 5, wafer For the portion of the external circuit 40, please refer to the relevant portion of the third embodiment for the external circuit of the wafer. In 上勒容t, EI Wei 25 is a polysilic 〇n layer 2S1 with a scalarity between angstroms and 2,000 angstroms and a polycrystalline stone layer (5) with a thickness of 1,000 angstroms. A metal silicide layer 252 is formed between 3,000 angstroms, wherein the material of the metal second layer 252 comprises titanium, #, nickel or a crane, and the sheet resistance of the electronic fuse 25 before being blown is between Between 1 ohm and 15 ohms, in addition to and/or on the electronic fuse 25, there is an insulating layer having a dielectric record of less than 3, the secret layer comprising -oxygen. In addition, the material of the Lena Lin 26 includes copper, inscription or polycrystalline stone, and an opening 526 of the protective layer 5 is formed on the laser fuse %, and the opening 526 exposes a position on the laser fuse %. A layer of siiic〇n oxide (not shown). Next, before proceeding to the next step, the first wafer electrical test is performed to find the complete good grain, completely bad grain and repairable grain in the wafer 10, and the day of the T-recovery It is similar to the laser repair of the Japanese grain.) The laser repair is a method in which the laser blows the laser fuse 26 so that the first end point and the second point of the laser fuse 26 are k/f paths as shown in FIG. 21B, so that the repairable crystal grains are made. The film becomes completely fine, and as shown in FIG. 2ic, a polymer layer 95 is formed on the protective layer 5, the metal interface 600 exposed by the opening 50 of the protective layer, and the opening 526 is exposed 113 200816373

ΐνΐΓ, Ο / l UO-Ul ^ TWB on the oxidation pin, the new pair of complex layer 95 into the Wei, so that the polymer layer 95 forms a plurality of polymer layer openings 95 〇. Continuing, see the addition of the adhesion/barrier/seed layer 8011 on the polymer layer 95 and the exposed portion of the polymer opening (4), then see Figure 21E, in the adhesion/barrier A patterned photoresist layer 7 is formed on the seed layer 8011 and a thick metal layer 8〇12 is deposited in the photoresist layer opening 710 of the photoresist layer 71, as shown in FIG. Please also refer to the 21G to 21H, remove the photoresist layer 71, and then remove the adhesion/barrier/seed layer 8〇11 which is not under the thick metal layer to form a patterned metal layer. The patterned metal layer 801 includes a patterned metal layer 8a (including a thick metal layer 8_ and an adhesion/barrier/seed layer 8〇11a) and a patterned metal layer 8〇b (including a thick metal layer 8012b and adhesion). / barrier / seed layer 8 〇 nb). Wherein, the patterned metal layer is used to interconnect the internal circuit 20, and the internal circuit 2〇 can transmit the germanium or the poor material through the patterned metal layer 8〇1& or by patterning the metal layer 8〇 La provides the power required for the internal circuit 2, and the patterned metal layer 801b serves as a reconfiguration line for repositioning the metal pads 6 connecting the wafer external circuit 40 to a different location using the reconfiguration line. Contact pads. Referring to FIG. 211, a top polymer layer 99 is formed on the exposed polymer layer 95 and the patterned metal layer 8〇1 (including 8〇1& and 8〇1), and then the top polymerization is patterned. The layer 99 is formed to form a polymer opening 990. The patterned metal layer 8〇1b is connected to a contact pad 8〇〇〇 of the external circuit. Next, a second wafer electrical test can be selected to find the perfect grain, completely bad grain, and repairable grain in the wafer, and repairable in the wafer. Of 114 200816373

JvuiUA uo-υ 13 TWB die for electronic repair (on e repak) 'The way is to apply between 0.05 amps to 2 amps in % microsecond illusion micro - current through the electronic fuse 25 (M in Qing _ to _ Micro-material coffee, silk between g丨 ampere to 1 Andian - current through Wei Wei dangerous wire% for the silk), so that the electric _ _ burned: the metal fuse 252 of the electronic fuse 25 formed a gap 252, The electric enthalpy between the first end point and the second end point of the electronic fuse 25 is broken through the polycrystalline stone layer (5)^ ΐ granule layer 252, as shown in FIG. 21J, so that the repairable person/ , -·, 70 Wang good grain. At this time, the sheet resistance of the blown electronic fuse 25 is between 2 touch ohms and ohms. Then, the subsequent wafer ore cutting is performed (cutting step 3, and the grain can be selectively repaired before the wafer cutting (cutting) is performed. FIG. 21K shows the wafer 1 which will complete the structure above the protective layer. The tantalum ore is cut into 1 m wafers 10, and the contact pads _0 of the wafers 10 can be connected to the external circuit by a (four) system wire-bonding wire (gold wire, turn or touch, and optionally the aforementioned The three-wafer electrical test found the completely bad grain on the I"cutting and then the details of the money to continue the steps of this completely bad crystal / into the dragon's cost. See Figure 21L, Using an adhesive layer u to crystallize and pry the crystal on the package substrate, for example, the organic substrate u, and then perform the wire step wire 89' to connect the hard surface pad and the pad 15. Continue, proceed, and step (for example, ball_touch, Teng ), packaged in an encapsulation layer 17 at 115 200816373

iVLtiUA υο-υ 13 TWB wafer 10 on the organic substrate 13. Further, the price of the wafer fixed on the organic substrate i3 can also be stacked on the two wafers of the preferred type, or a plurality of wafers. Please refer to the first _ not 'money for two 1 (), _ pad 9 stacking axis on the organic substrate 13 - example, as shown, two wafers 1 〇, both use wire bonding, connect the contact pads The surface is thin-pad 15, but the two wafer job wires 89 can also be connected to the separate pads 15 instead of the bonding pads 15. In addition, the above-mentioned package base «may be a lead frame (four) fe_), and the material of the high-profile device such as seconds or copper.凊 Refer to FIG. 21N, which is a top view of the application of the first object in a dynamic random access memory. As shown in the figure, a wheel-in/output pad of a dynamic random access memory is along The center line setting of the motive access memory is finely utilized by the wafer 1' of the 21st L, and the DRAM can be connected to the central input/output through the patterned metal layer as the reconfigured line. The pads are reconfigured to the surrounding input/output pads so that the DRAM can be used in wire bonding in a snug (eg, stacked package). After the packaging step is completed, the first wafer electrical test is performed, and the all-good wafer 10, the completely bad wafer 10, and the repairable wafer 10 are screened, and then the good wafer is pre-processed. After burning-in, and after the pre-firing is completed, the wafer electrical test is performed again to select a good quality wafer. As for the first wafer power, the above-mentioned electronic repairing step is performed again to make the repairable wafer 10 into a good wafer 10, and then select the first 116 200816373

Ivir, 〇 / \ υ υ υ TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW TW A piece of electrical test was conducted to select a good quality wafer. The above methods and detailed descriptions can be applied to other types of memory, such as flash memory, static and random access memory, or in one application, in addition to being applicable to a dynamic random access memory. Logic (1〇gic) on the wafer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram of a circuit having a voltage regulator or a transformer. FIG. 1B is a schematic diagram of a circuit having a voltage regulator or a transformer according to the present invention. FIG. 1C is a circuit diagram showing the structure of the metal line or plane transmission voltage v(7) and the ground reference voltage Vss above the protective layer. Figure 2A is a top plan view of a conventional voltage regulator or transformer. 2B is a top plan view of the present invention having a voltage regulator or transformer. 2C is a top view of the structure of the present invention using the metal line or plane transport voltage να and the ground reference voltage Vss above the protective layer. Figure 3A is a schematic cross-sectional view of a conventional voltage regulator or transformer. Figure 3B is a schematic cross-sectional view of a voltage regulator or transformer of the present invention. FIG. 3C is a schematic cross-sectional view showing the structure of the metal line or plane transmission voltage v(3) and the ground reference voltage Vss above the protective layer. The 3D diagram of the present invention is a cross-sectional illustration of a voltage regulator or transformer of the present invention. Figure 4 is a transformer of the present invention. - .... . * · . . . - . : Figure 5A is a circuit diagram of a conventional internal circuit. 117 200816373

Mh: CjA06-015TWB Fig. 5B is a circuit diagram showing a second embodiment of the present invention. The 5C diagram is the inverter of the present invention. Figure 5D is an internal drive of the present invention. The 5E circle is the internal tristate buffer of the present invention. Figure 5F is a circuit diagram showing a memory cell of the present invention connected to an internal circuit through an internal tristate buffer, a metal line or plane on the protective layer, and a thin line metal structure under the protective layer. Figure 5G is a circuit diagram showing a memory cell of the present invention connected to an internal circuit through a circuit, a metal line or plane on the protective layer, and a thin line metal structure under the protective layer. Figure 5H is a schematic diagram of a memory cell of the present invention connected to the lightning circuit through a metal line or plane on the protective layer and a thin line metal structure under the protective layer. . The figure shows a circuit diagram of a memory unit through a circuit, an internal driving interface, a metal line on a shrew layer, or a thin circuit metal structure under a flat layer. Inventive--(4) Unit Twist Lock Circuit, Saki No., Baoji's Golden Secret Road Solution, Silk Crane, _Materials--Circuit Schematic Diagram of Internal Circuits i. Continuation _ f5K Diagram is the second embodiment of the present invention - Intent. Figure 5L is an internal receiver of the present invention. 118

200816373 ivmw/\ υο-υ i j TWB Figure 5M is an internal tristate buffer of the present invention. Figure 5N is a circuit diagram showing the internal circuit of the present invention connected to a memory cell through a fine-line metal structure under the protective layer, a metal line or plane on the protective layer, and an internal tri-state buffer. Figure 50 is a circuit diagram showing the internal circuit of the present invention through a metal line or plane on the thin-layer metal structure under the protective layer and connected to a memory cell through a circuit. Fig. 5P is a circuit diagram showing the circuit of one of the internal circuits of the present invention transmitted through the thin-line metal structure under the protective layer, the metal line or plane on the protective layer, and the _-scale to the memory unit. Figure 5Q is a schematic diagram of the circuit of the present invention for interconnecting a metal circuit or a flat self-receiver on a thin-layer metal structure under a protective layer through a protective layer and connecting to a memory cell through a circuit. One @本&月之_ internal circuit through the thin layer metal structure under the protective layer, protect the strong Jinguan Road scales, connect (four)·_ road to the memory of the single it's Wei. ^ Figure is the schematic diagram of the circuit. Figure 5T is an operational amplifier of the present invention. Figure 6 is a top plan view of a conventional internal circuit. (4) The schematic view of the second embodiment of the present invention is shown. 119 200816373

MiiUA υο-ui^TWB Figure 7A is a schematic cross-sectional view of a conventional internal circuit. Fig. 7B is a schematic cross-sectional view showing a single layer patterned metal layer in accordance with a second embodiment of the present invention. Fig. 7C is a schematic cross-sectional view showing a second embodiment of the present invention having two patterned metal layers. 7D is a schematic cross-sectional view showing a polymer layer between the protective layer and the lowermost patterned metal layer in the second embodiment of the present invention. Figure 8A shows the circuit of the conventional wafer. Figure 8B is a circuit diagram showing a third embodiment of the present invention. Figure 8C is a circuit diagram showing a third embodiment of the present invention. Figure 8D is a circuit diagram showing a third embodiment of the present invention. Figure 8E is a circuit diagram showing a third embodiment of the present invention. Figure 8F is a circuit diagram showing a third embodiment of the present invention. Figure 9A is a top plan view of a conventional wafer. Figure 9B is a top plan view of a third embodiment of the present invention. Figure 9C is a top plan view of a third embodiment of the present invention. Figure 9D is a top plan view of a third embodiment of the present invention. Figure 10A is a schematic cross-sectional view of a conventional wafer. 10B is a cross-sectional view showing a single layer patterned metal layer according to a third embodiment of the present invention. FIG. 0 120 200816373

ivLtiu/\ υο-υ i d TWB The IOC figure is a schematic cross-sectional view of a third embodiment of the present invention having two patterned metal layers. BRIEF DESCRIPTION OF THE DRAWINGS Figure 3 is a schematic cross-sectional view showing a polymer layer between a protective layer and a bottom layer of a single-layer patterned metal layer in accordance with a third embodiment of the present invention. Figure 10E is a schematic cross-sectional view showing a polymer layer between a protective layer and a bottom layer of two patterned metal layers in accordance with a third embodiment of the present invention. Figure 10F is a schematic cross-sectional view of a conventional wafer having a wire bond. The first touch diagram is a schematic view of a third embodiment of the present invention having a wire bonding (four) plane. The first brain diagram is a schematic cross-sectional view of a third embodiment of the present invention having a wire bonding. Figure f101 is a schematic cross-sectional view showing a third embodiment of the present invention having a wire bonding. Figure 11A is a wafer external drive of the present invention. Figure 11B is a wafer external receiver of the present invention. The lie diagram is a wafer tristate buffer of the present invention. Figure 11D is a wafer external drive of the present invention. Figure 11E is a wafer tristate buffer of the present invention. Figure 11F is an electrostatic discharge protection circuit of the present invention. = 11G® is a turn-for-turn. ^. A circuit diagram for directly inputting a voltage to an internal circuit for controlling external power supply and having an electrostatic discharge preventing circuit to prevent voltage or current surge generated by an externally supplied power supply. Figure 12B is a circuit diagram of a fourth embodiment of the present invention. 121 200816373

ινίϋΟΑ uo-u l d TWB Figure 12C is a circuit diagram of a fourth embodiment of the present invention. The first is a schematic of the embodiment of the present invention having two electrostatic discharge rigid circuits. 12E is the electrostatic discharge protection circuit of the present invention. Figure 13A shows a schematic view of a conventional externally supplied power supply that directly inputs human power _ internal circuits and has a static package to protect the external supply of lightning or spurs.苐13B is a top view of the fourth embodiment of the present invention. FIG. BC is a top view of a fourth embodiment of the present invention. FIG. FIG. 14B is a cross-sectional view showing a fourth embodiment of the present invention. 14C is a schematic cross-sectional view of a fourth embodiment of the present invention. 14D is a cross-sectional view of a fourth embodiment of the present invention. Figure 15A is a schematic cross-sectional view of a wafer. Figure 15B is a schematic cross-sectional view of a wafer. 15C to 15K are diagrams showing a process for forming a structure above the protective layer according to the present invention. FIG. 16 to FIG. 1 are a process for forming a structure above the protective layer of the present invention. FIGS. 17 to 17J are the protection of the present invention. One of the structures above the layer, process step 122 200816373

MbUAUO-UOrWB The structure of the upper layer of the 4th layer is the structure of the upper layer of the process step. The process of the process is the 18th to the 181th of the present invention. A schematic cross section. The 21st figure of the 21st brewing is the process of the gambling secret. Figure 21 is a top plan view of the present invention applied to a dynamic random access memory. [Main component symbol description] 1 substrate 2' gold oxide semi-transistor 6 fine circuit structure 10 wafer 11 adhesive layer 15 pad 19 pad high pad 21 internal circuit 23 internal circuit 25 electronic fuse 30 fine circuit dielectric layer 4 wafer External circuit 42 wafer external circuit 44 electrostatic discharge protection circuit 2 component layer 5 protective layer 8 protective layer over structure 10' wafer 13 organic substrate 17 package layer 20 internal circuit 22 internal circuit 24 internal circuit 26 laser fuse 30' opening 41 Voltage regulator or transformer 43 wafer external circuit 45 electrostatic discharge protection circuit 123 200816373

Miiu a υο-υ id TWB 50 protective layer opening 60' conductive plug 6Γ fine line metal structure 63 fine line metal structure 69 fine line metal structure 72 photoresist layer 74 photoresist layer 81 metal line or plane 83 metal line or plane 83t weight Configuring metal line 89' wire conductor 90 polymer layer 97 polymer layer 99 top polymer layer 201 source 203 gate 212 internal driver 213 internal tristate buffer 214 sense amplifier 216 through circuit 217 latch circuit 60 fine line metal Layer 61 fine line metal structure 62 fine line metal structure 66 metal top layer 71 photoresist layer 73 photoresist layer 80 patterned metal layer 82 metal line or plane 83r metal line or plane 89 contact structure 89t tin-lead bump 95 polymer layer 98 Polymer layer 200 internal structure 202 drain 211 inverter 212' internal receiver 213' internal tristate buffer 215 static random access memory unit 216' through circuit 217 'latch circuit 124 200816373

IVJ_DO/\ uo-u 1J TWB 218 operational amplifier 251 polysilicon layer 252' notch 410 reference voltage generator 421 wafer external driver 421" second stage 422' first stage 511 protective layer opening 514 protective layer opening 519 'protective layer opening 522 protective layer opening 526 opening 531 protective layer opening 532 protective layer opening 534 protective layer opening 539 protective layer opening 549 protective layer opening 559 protective layer opening 600 metal pad 602 fine line metal layer 602y fine line metal layer 219 differential circuit 252 metal Deuterated layer 400 wafer outer structure 410' current mirror circuit 421' first stage 422 wafer external receiver 422" second stage 512 protective layer opening 519 protective layer opening 521 protective layer opening 524 protective layer opening 529 protective layer opening 53 Γ protection Layer opening 532' protective layer opening 534' protective layer opening 539' protective layer opening 549' protective layer opening 559' protective layer opening 601w fine wiring metal layer 602x fine wiring metal layer 602z fine wiring metal layer 125 200816373 ΜϋυΑ υο-unfWB 611 thin line Road metal structure 612 fine line metal structure 612a fine line metal structure 612b fine line metal structure 612c fine line Dependent structure 614 fine line metal structure 618 fine line metal structure 619 fine line metal structure 619 'fine line metal structure 621 fine line metal structure 622 fine line metal structure 622a fine line metal structure 622b fine line metal structure 622c fine line metal structure 624 thin line Road metal structure 629 fine line metal structure 631 fine line metal structure 631, fine line metal structure 632 fine line metal structure 632a fine line metal structure 632b fine line metal structure 632c fine line metal structure 632a' fine line metal structure 632b' fine line metal Structure 632c' fine line metal structure 634 fine line metal structure 634' fine line metal structure 638 fine line metal structure 639 fine line metal structure 639' fine line metal structure 649 fine line metal structure 649" fine line metal structure 659 fine line metal structure 659' fine line metal structure 661 metal top layer 662 metal top layer 664 metal top layer 669 metal top layer 669' metal top layer 710 photoresist layer opening 720 photoresist layer opening 720' photoresist layer opening 126 200816373

Ivmu/\ uo-uid TWB 730 photoresist layer opening 740 photoresist layer opening 801 patterned metal layer 8 〇 lb patterned metal layer 802 patterned metal layer 802y patterned metal layer 803 patterned metal layer 812 patterned metal layer 831 Patterned metal layer 831b patterned metal layer 832a patterned metal layer 891 bump underlayer metal layer 897' metal layer 898' metal layer 980 polymer layer opening 2101 N-type gold oxide semi-transistor 2103 N-type gold oxide semi-transistor 2104P Type MOS semi-transistor 2107N type gold oxide semi-transistor 2109'N-type gold oxide semi-transistor 2111 N-type gold oxide semi-transistor 730' photoresist layer opening 740' photoresist layer opening 801a patterned metal layer 801w patterning Metal layer 802x patterned metal layer 802z patterned metal layer 811 patterned metal layer 821 patterned metal layer 831a patterned metal layer 832 patterned metal layer 832b patterned metal layer 897 metal plug 898 metal plug 950 polymer layer opening 990 polymerization Layer opening 2102P type gold oxide semi-transistor 2103'N type gold oxide semi-transistor 2104'P type gold oxide semi-transistor 2108P type gold oxide semi-transistor 2110'P type gold oxide semi-transistor 2112P type gold oxygen semi-electric crystal 127 200 816 373

iVlliUA UO-U13TWB 2113N gold oxide semi-transistor 2115 N-type gold oxide semi-transistor 2117N type gold oxide semi-transistor 2119N type gold oxide semi-transistor 2121 N-type gold oxide semi-transistor 2123 row selection transistor 2124'N type Gold Oxygen Half Crystal 2126 P Type Gold Oxygen Half Crystal 2128P Type Gold Oxygen Half Crystal 2129'N Type Gold Oxygen Half Crystal 2130'N Type Gold Oxygen Half Crystal 2132P Type Gold Oxygen Half Crystal 2134 Resistor Type 2136P Gold Oxygen Half Crystal 4102 P Type Gold Oxygen Half Crystal 4104P Type Gold Oxygen Half Crystal 4106P Type Gold Oxygen Half Crystal 4108ISf Type Gold Oxygen Half Crystal 4110P Type Gold Oxygen Half Crystal 4112 Conductive Crystal 4201 N Type Gold Oxygen Semi-transistor 2114P type gold oxide semi-transistor 2116P type gold oxide semi-transistor 2118P type gold oxide semi-transistor 2120N type gold oxide semi-transistor 2122 line selection transistor 2124 N-type gold oxide semi-transistor 2125N type gold-oxygen semi-electric Crystal 2127N type gold oxide semi-transistor 2129N type gold oxide semi-transistor 2130N type gold oxide semi-transistor 2131 P-type gold oxide semi-transistor 2133 capacitor 2135N type gold oxide semi-transistor 4101 P-type gold oxide semi-transistor 4103P type gold Oxygen semi-transistor 4105 P-type gold oxide semi-transistor 4107 N-type gold oxide semi-transistor 4109 P-type gold oxide semi-transistor 4111 electrically conductive crystal 4199 node 4202 P-type gold oxide semi-transistor 128 200816373

MliLrA UO-UnTWB 4203 N-type gold oxide semi-transistor 4205 N-type gold oxide semi-transistor 4207 N-type gold oxide semi-transistor 4209 N-type gold oxide semi-transistor 4331 reverse bias diode 4333 reverse bias diode 6121 fine line metal structure 6121b fine line metal structure 6141 fine line metal structure 6190' metal pad 6191 fine line metal structure 6321 fine line metal structure 6321b fine line metal structure 6341 fine line metal structure 6391 fine line metal structure 6490 metal pad 8000 Contact pad 8011' recess 8011b adhesion/barrier/seed layer 8012a thick metal layer 8021 adhesion/barrier/seed layer 4204 P-type gold oxide semi-transistor 4206P type gold oxide semi-transistor 4208P type gold oxide semi-transistor 4210P Type MOS semi-transistor 4332 reverse bias diode 6111 fine line metal structure 6121a fine line metal structure 6121c fine line metal structure 6190 metal pad 6290 metal pad 6311 fine line metal structure 6321a fine line metal structure 6321c fine line metal Structure 6390 metal pad 6391' fine line metal structure 6490' metal pad 8011 adhesion / barrier / seed layer 8011a adhesion / barrier / seed layer 8012 thick metal layer 8012 b thick metal layer 8022 thick metal layer 129 200816373

8031 Adhesive / Barrier / Seed Layer 8110 Contact Pad 8112 Thick Metal Layer 8121 Adhesive / Barrier / Seed Layer 8211 Adhesive / Barrier / Seed Layer 8310 Contact Pad 8311a Adhesive / Barrier / Seed Layer 8312 Thick Metal Layer 8312b Thick Metal layer 8321 Adhesive/barrier/seed layer 8321b Adhesive/barrier/seed layer 8322a Thick metal layer 9511 Polymer layer opening 9514 Polymer layer opening 9519' Polymer layer opening 9532 Polymer layer opening 9539 Polymer layer opening 9549 Polymerization Layer opening 9831 polymer layer opening 9839 polymer layer opening 9919 polymer layer opening 8032 thick metal layer 8111 adhesion/barrier/seed layer 8120 contact pad 8122 thick metal layer 8212 thick metal layer 8311 adhesion/barrier/seed layer 8311b Adhesive/Barrier/Seed Layer 8312a Thick Metal Layer 8320 Contact Pad 8321a Adhesive/Barrier/Seed Layer 8322 Thick Metal Layer 8322b Thick Metal Layer 9512 Polymer Layer Opening 9519 Polymer Layer Opening 9531 Polymer Layer Opening 9534 Polymer Layer opening 9539' polymer layer opening 9829 polymer layer opening 9834 polymer layer opening 9849' polymer layer opening 9929 polymer layer opening 130 200816373

MliUA U6-U15TWB 9939 polymer layer opening 9939' polymer layer opening 9949 polymer layer opening 9949' polymer layer opening 131

Claims (1)

200816373 ivlc〇/\ uo-015TWB X. Patent application scope 1.  A circuit component, comprising: a voltage regulator; an internal circuit; a first metal circuit connected to the voltage regulator; a second metal circuit connecting the internal circuit; a protective layer located at the stable And a second metal line disposed on the protective layer and connecting the first metal line and the second metal line. 2. The circuit component according to claim 1, wherein when the voltage regulator outputs a voltage value, the difference between the voltage value and a set target voltage value is divided by the set target voltage value. The system is less than 1 〇%. 3. The circuit component of claim 2, wherein the set target voltage of the voltage regulator is between 〇 5 volts and 1 volt volt. 4. The circuit component of claim 2, wherein the set target voltage value of the voltage regulator is between 〇 5 volts and 5 volts. 5. The circuit component of claim 1, wherein the internal circuit comprises a NOR gate. 6. The circuit component of claim 1, wherein the internal circuit comprises an OR gate. 7. The circuit component of claim 1, wherein the internal circuit comprises an AND gate. The circuit component of claim 1, wherein the internal circuit includes a NAND gate. 9. The circuit component of claim 1, wherein the internal circuit comprises a static random access memory cell. 1〇. The circuit component of claim 1, wherein the internal circuit comprises a dynamic random access memory cell (dram cell). The circuit component of claim 1, wherein the internal circuit comprises a non-volatile memory cell (n〇n-v〇lati le memory cell) 〇12 as described in claim 1 a circuit component, wherein the internal circuit includes a flash memory unit (f丨ash mem〇ry ce丨丨). 13. The circuit component of claim 1, wherein the internal &quot; circuitry comprises an erasable read only memory cell (EPROM cell). 14. The circuit component of claim 1, wherein the internal circuit comprises a ROM cell. The circuit component of claim 1, wherein the internal circuit comprises a magnetic random access memory (MRAM) unit. The circuit component of claim 1, wherein the circuit comprises a sense amplifier. The circuit component of claim 1, wherein the circuit component The internal circuit includes an operational amplifier (Operational Amplifier) 133 200816373 uo-015TWB 18.  The circuit component of claim 1, wherein the internal circuit comprises an adder. 19.  The circuit component of claim 1, wherein the internal circuit comprises a multiplexer. 20.  The circuit component of claim 1, wherein the internal circuit comprises a duplexer. twenty one.  The circuit component of claim 1, wherein the internal circuit comprises a multiplier. twenty two.  The circuit component of claim 1, wherein the internal circuit comprises an analog/digital converter (A/D converter). twenty three.  The circuit component of claim 1, wherein the internal circuit comprises a digital/analog converter (D/A Converter). twenty four.  The circuit component of claim 1, wherein the internal circuit comprises a complementary metal oxide semiconductor sensing cell unit (CMOS sensor cell).  The circuit component of claim 1, wherein the internal circuit comprises a photo-sensitive diode. 26.  The circuit component of claim 1, wherein the internal circuit comprises a bi-substrate complementary biCMOS circuit.  The circuit component of claim 1, wherein the internal circuit comprises a bipolar circuit unit. 28.  The circuit component of claim 1, wherein the first metal line comprises a thickness system of 0.  Between 05 microns and 21 microns 134 200816373 JVLliUA A layer of UO-015TWB. The circuit component of claim 1, wherein the first metal line comprises a copper layer having a thickness of between 0. 05 micrometers, 5 9 soils, and 4 micrometers. 30. The circuit component of claim 1, wherein the second metal line comprises an aluminum layer having a thickness between 微米·05 μm and 2 μm. The circuit component of claim 1, wherein the second metal line comprises a copper layer having a thickness between 〇·05 μm and 2 μm. 32. The circuit component of claim 1, wherein the material of the third metal line comprises gold. 33. The circuit component of claim 1, wherein the material of the second metal line comprises copper. 34. The circuit component of claim 1, wherein the material of the second metal line comprises silver. The circuit component of claim 1, wherein the material of the second metal line comprises platinum. 36. The circuit component of claim 1, wherein the material of the third metal line comprises palladium. 37. The circuit component of claim 1, wherein the material of the third metal line comprises nickel. 38. The circuit component structure of claim 2, wherein the third metal line comprises a first metal layer and a second metal 135 200816373 • ^aum 15TWB layer, the second metal layer being On the first metal layer. 39 . The circuit component structure of claim 38, wherein the second metal layer comprises a gold layer having a thickness of between 15 micrometers and 15 micrometers. 40. The circuit component structure of claim 38, wherein: the second metal layer comprises a steel layer having a thickness of between 15 micrometers and 5 micrometers. 41. The wiring component structure of item (4), wherein the second metal layer comprises a silver layer having a thickness of from 15 micrometers to 15 micrometers. 42: := The circuit component structure of claim 38, wherein the second metal layer comprises a surface layer having a thickness of from 15 micrometers to 15 micrometers. 43 » wherein: the circuit component structure described in Patent No. 38, the second metal layer comprises a circuit component structure having a thickness ranging from h5 micrometers to 15 micrometers, as claimed in claim 38 of the patent scope, The phase 'the second metal layer comprises a spiral layer having a thickness between 05 microns and 6 microns. 45 κ • In the case of the circuit component structure described in claim 38, one of the first metal layers includes a tungsten alloy layer having a thickness of from 0 02 μm to 〇 8 μm. 46 (4) material (4) 38 line component structure, basin, the first metal layer includes a thickness of 〇.  〇 2 micro-seeking to 〇.  8 micron 136 200816373 MliUAU6-〇l5TWB One titanium metal layer. I. The metal layer of the wire as described in claim 38 of the patent application includes a titanium nitride layer of a thickness of four (4). To 0. 8 micron = as for the towel, please refer to the line component described in item 38. The material-metal layer includes a thickness of G. G2 micron ° One of the button metal layers. 0·8 micron The line component described in item 38 of the towel (4) (4), the metal layer of the brother includes a thickness of 0 02 ', a layer of nitride button. Card to 0. 8 microns 50. In the case of the circuit component of claim 38, the first metal layer comprises a chrome metal layer having a thickness of between 2 and 2 micrometers. 5L is the circuit component structure as described in claim 38, wherein the first metal layer comprises a thickness of G. G2 micron to 〇. 8 micron one chrome-copper alloy layer. The circuit component according to claim 1, wherein the material of the protective layer comprises a nitrogen arsenide compound. The circuit component of claim 1, wherein the material of the protective layer comprises a phosphorous glass (PSG). 54. The circuit component of claim 1, wherein the material of the protective layer comprises an oxonium compound. 55. The Kanglu component of claim 2, wherein the material of the protective layer comprises a oxynitride compound. 137 200816373 iviriUA UO-015TWB 56. The circuit component of claim 1, wherein the material of the protective layer comprises a borophosphite glass (BPSG). 57. The circuit component structure of claim 1, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the third metal line. 58. The circuit component structure of claim 57, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 1 micron. 59.  The circuit component according to claim 57, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 μm and 1 μm. 60. The circuit component structure of claim 57, wherein the first polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 1 micrometer. 61. The circuit component structure of claim 2, wherein the first polymer layer comprises an epoxy layer having a thickness between 2 microns and 100 microns. The circuit component according to claim 1, wherein the internal circuit includes at least one N-type MOS device (NM 〇 s), and the channel width of the N-type MOS device (Channe 1 width) / Channel length ratio is between 01 and 5. The circuit component according to claim 1, wherein the internal circuit includes at least one N-type MOS device (NM〇s), and the channel width of the N 1 佥 NMOS device (Channel channel 138 200816373 The MbUA UO-015TWB channel length ratio is between 0 and 2 to 2.  The circuit component according to claim 1, wherein the internal circuit includes at least a P-type MOS device, and a channel width/channel length of the P-type MOS device Length) The ratio is between 0 and 2 to 10. 65.  The circuit component according to claim 1, wherein the internal circuit includes at least a P-type MOS device, and a channel width/channel length of the P-type MOS device The length) ratio is between 0.4 and 4. 66.  The circuit component of claim 1, wherein the current flowing through the third metal line is between 50 microamperes and 2 milliamperes. 67.  The circuit component of claim 1, wherein the current flowing through the third metal line is between 100 microamperes and 1 milliamperes. 68.  The circuit component of claim 1, wherein the second metal line is connected to a power node of the internal circuit.  The circuit component of claim 1, wherein the second metal line is connected to a ground node of the internal circuit.  The circuit component of claim 1, wherein the third metal line is not electrically connected to the outside. 71.  The circuit component of claim 1, further comprising a 139 200816373 ϋΑ^ϋΑ Ub-015TWB second polymer layer on the third metal line. 72. The circuit component structure of claim 71, wherein the polymer layer comprises a layer of a polyamidimide compound having a thickness between 2 microns and 1QQ microns. 73. The circuit component structure of claim 71, wherein the polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 micrometers and 1 micrometer. 74. The circuit component structure of claim 71, wherein the second polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and micrometers. 75. The circuit component structure of claim 71, wherein the second polymer layer comprises an epoxy layer having a thickness between 2 microns and 1 micron. 76. The circuit component of claim 1, further comprising a third polymer layer overlying all of the upper surface of the third metal line. 77. The circuit component structure of claim 76, wherein the third polymer layer comprises a layer of a polyamidimide compound having a thickness between 2 microns and 1 micron. 78. The circuit component structure of claim 76, wherein the third polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 1 micron. 79. The circuit component structure of claim 76, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 1 micrometer. 140 200816373 ινΐΓ,ο/\ uo-015TWB The circuit component structure of claim 76, wherein the first polymer layer comprises an epoxy resin having a thickness of between 2 micrometers and 100 micrometers. Floor. The circuit component described in Item 1 of the patent range of 81 β #中明, and the substrate including the 石 夕 承载 carries the voltage regulator. 82. The circuit component of claim 1, further comprising a substrate comprising germanium carrying the internal circuit. 83.  a circuit component, comprising: a transformer, an internal circuit; a younger metal circuit connecting the transformer; a metal circuit connected to the internal circuit; a protective layer, located in the transformer, The internal circuit, the first metal line and the second metal line; and a third metal line are disposed on the protective layer and connect the first metal line and the second metal line. 84. The circuit component of claim 83, wherein the transformer converts an input voltage into an output voltage that is different from the input voltage value. 85. The circuit component of claim 84, wherein the difference between the input voltage of the transformer and the output voltage divided by the output voltage is greater than 10%. 86. The circuit component of claim 84, wherein the output voltage of the transformer is between 1 volt and 10 volts. 141 200816373 MliUA UO-015TWB 87.  The circuit component of claim 83, wherein the internal circuit comprises a NOR gate. 88.  The circuit component of claim 83, wherein the internal circuit comprises an OR gate. 89.  The circuit component of claim 83, wherein the internal circuit comprises an AND gate. 90.  The circuit component of claim 83, wherein the internal circuit comprises a NAND gate. 91.  The circuit component of claim 83, wherein the internal circuit comprises a static random access memory cell (SRAM cell).  The circuit component of claim 83, wherein the internal circuit comprises a dynamic random access memory cell (DRAM cell).  The circuit component of claim 83, wherein the internal circuit comprises a non-volatile memory (non-vo 1 ati le memory cel 1) ° 94.  The circuit component of claim 83, wherein the internal circuit comprises a flash memory cel 1 . 95.  The circuit component of claim 83, wherein the internal circuit comprises an erasable read only memory unit (EPROM cell).  The circuit component of claim 83, wherein the internal circuit comprises a ROM cell. 142 200816373 jvmuA υο-015TWB 97.  The circuit component of claim 83, wherein the internal circuit comprises a magnetic EEPROM (MR AM) unit. 98.  The circuit component of claim 83, wherein the internal circuit comprises a sense amplifier. 99.  The circuit component of claim 83, wherein the internal circuit comprises an Operational Amplifier. 100.  The circuit component of claim 83, wherein the internal circuit comprises an adder. 101.  The circuit component of claim 83, wherein the internal circuit comprises a multiplexer. 102.  The circuit component of claim 83, wherein the internal circuit comprises a duplexer. 103.  The circuit component of claim 83, wherein the internal circuit comprises a multiplier. 104.  The circuit component of claim 83, wherein the internal circuit comprises an analog/digital converter (A/D converter). 105.  The circuit component of claim 83, wherein the internal circuit comprises a digital/analog converter (D/A Converter). 106.  The circuit component of claim 83, wherein the internal circuit comprises a complementary metal oxide semiconductor sensing cell unit (CMOS sensor cell).  The circuit component of claim 83, wherein the internal circuit comprises a photo-sensitive diode. 144 200816373 ivubUA UO-015TWB 108. The circuit component of claim 83, wherein the internal circuit comprises a bi-substance complementary metal oxide semiconductor (BiC) y [〇s circuit] 〇 109 The circuit component of claim 83, wherein the internal circuit comprises a bipolar circuit unit. 110. The circuit component of claim 83, wherein the first metal line comprises an aluminum layer having a thickness between 5 microns and 2 microns. 11L. The circuit component of claim 83, wherein the first metal line comprises a copper layer having a thickness between 〇·05 μm and 2 μm. The circuit component of claim 83, wherein the second metal line comprises an aluminum layer having a thickness of between 5 micrometers and 2 micrometers. 113. The circuit component of claim 83, wherein the second metal line comprises a copper layer having a thickness of between 5 micrometers and 2 micrometers. 114. The circuit component of claim 83, wherein the material of the third metal line comprises gold. The circuit component of claim 83, wherein the material of the second metal line comprises copper. 116. The circuit component of claim 83, wherein the material of the third metal line comprises silver. 117. The circuit component of claim 83, wherein the material of the third metal circuit of the 144 200816373 M±iUA UO-015TWB comprises platinum. The circuit component of claim 83, wherein the material of the third metal line comprises palladium. Λ 119. The circuit component of claim 83, wherein the material of the third metal line comprises nickel. The circuit component structure of claim 83, wherein the second metal circuit comprises a first metal layer and a second metal layer, the second metal layer being on the first metal layer . For example, the circuit component structure described in claim 120 of the patent scope, wherein the second metal layer comprises a thickness of between 1.5 micrometers and a micro-gold layer. 122. The circuit component structure of claim 120, wherein the second metal layer comprises a steel layer having a thickness between 1 and 5 microns. The structure of the circuit component of claim 120, wherein the second metal layer comprises a silver layer having a thickness of between 1.5 μm and 15 μm. 124. The circuit component structure of claim 120, wherein the second metal layer comprises a pin layer having a thickness of between 1.5 microns and 15 microns. 125. The circuit component structure of claim 120, wherein the second metal layer comprises a palladium layer having a thickness between 1.5 and 15 microns. ', 126 such as the line component structure described in claim 120 of the scope of the patent, its 145 200816373 ivu^/vu〇_015TWb 'the second metal layer includes a thickness of 0 · 5 microns to R, its micron 12 7 In the circuit component structure described in claim 20, the first metal layer comprises a titanium-tungsten alloy layer having a thickness of between 〇〇2 μm and 〇. · If the circuit component structure described in claim 120 is established, the first metal layer includes a thickness of 0.  02 micron / one of the u e a main 0. 8 micro and ^ titanium metal layer. The first metal layer comprises a layer of titanium nitride having a thickness of from 0.02 μm to 〇. 130. The circuit component structure of claim 12, wherein the first metal layer comprises a button metal layer having a thickness between 2 and 2 microns. The circuit element structure of claim 120, wherein the first metal layer comprises a nitride layer having a thickness of from 〇〇2 μm to 〇8 μm. 132. The circuit component structure of claim 120, wherein the first metal layer comprises a thickness of 0. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Road copper alloy layer. '134. For the wire component described in Section 83 of the patent application, the material of the 146 200816373 ivLtiu/\ uo-015TWB protective layer comprises a Nitrogen compound. 135.  The circuit component of claim 83, wherein the material of the protective layer comprises a phosphorous glass (PSG). 136.  The circuit component of claim 83, wherein the material of the protective layer comprises an oxonium compound. 137.  The circuit component of claim 83, wherein the material of the protective layer comprises a oxynitride compound. 138.  The circuit component of claim 83, wherein the material of the protective layer comprises borophosphorus bismuth glass (BPSG). 139.  The circuit component structure of claim 83, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the third metal line. 140.  The circuit component structure of claim 139, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 141.  The circuit component structure of claim 139, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 142.  The circuit component structure of claim 139, wherein the first polymer layer comprises a parylene polymer layer having a thickness of between 2 μm and 100 μm. 143.  The circuit component structure of claim 139, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 147 200816373 ΜϋυΑ Ub-015TWB 144.  The circuit component according to claim 83, wherein the internal circuit includes at least an N-type MOS device (NM0S), and the channel width/channel length of the N-type MOS device Length) The ratio is between 0.  Between 1 and 5. 145.  The circuit component according to claim 83, wherein the internal circuit includes at least an N-type MOS device (NM0S), and the channel width/channel length of the N-type MOS device Length) The ratio is between 0 and 2 to 2. 146.  The circuit component of claim 83, wherein the internal circuit comprises at least a P-type MOS device, and a channel width/channel length of the P-type MOS device Length) The ratio is between 0.  Between 2 and 10. 147.  The circuit component of claim 83, wherein the internal circuit comprises at least a P-type MOS device, and a channel width/channel length of the P-type MOS device The length) ratio is between 0.4 and 4. 148.  The circuit component of claim 83, wherein the current flowing through the third metal line is between 50 microamperes and 2 milliamperes. 149.  The circuit component of claim 83, wherein the current flowing through the third metal line is between 100 microamps and 1 milliamperes. 150.  The circuit component of claim 83, wherein the second metal line is connected to a power supply node of the internal circuit (power 148 200816373 ινυ^^/\ υο-015TWB node) 〇 151 · as claimed The circuit component of claim 83, wherein the metal-line is connected to a ground node of the internal circuit, 152. The circuit component of claim 83, wherein the third component The metal line is not electrically connected to the outside. 153. The circuit component of claim 83, further comprising a second polymer layer on the third metal line. 154. The circuit component structure of claim 153, wherein the second polymer layer comprises a layer of a poly-imine compound having a thickness between 2 microns and 100 microns. 155. The circuit component structure of claim 153, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness between 2 microns and 1 micron. 156. The circuit component structure of claim 153, wherein the second polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 1 micrometer. 157. The circuit component structure of claim 153, wherein the second polymer layer comprises an epoxy layer having a thickness between 2 microns and 1 micron. 158. The circuit component of claim 83, further comprising a layer of three polymer layers overlying all of the upper surface of the third metal line. 159. The circuit component structure of claim 158, wherein the third polymer layer comprises a poly-imine compound between 149 200816373 MiiUAUi)-015TWB having a thickness between 2 microns and 1 micron. Floor. 160. The circuit component structure of claim 158, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 1 micron. 161. The circuit component structure of claim 158, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 1 micrometer. 162. The circuit component structure of claim 158, wherein the third polymer layer comprises an epoxy layer having a thickness between 2 microns and 100 microns. 163. The circuit component of claim 83, wherein the transformer comprises a step-down transformer. 164. The circuit component of claim 83, wherein the transformer comprises a booster transformer. 165. The circuit component of claim 83, further comprising a base comprising a rock bearing. 166. The circuit component of claim 83, further comprising a substrate comprising germanium carrying the internal circuit. 167. A circuit component, comprising: a memory unit; a first internal circuit; a first metal circuit connected to the memory unit; a first metal circuit connected to the first internal circuit; a protective layer located in the memory unit ́s first internal circuit, the 150 200816373 ivir, u/\ uo-015TWB first metal line and the second metal line; and a third metal line And protecting the first metal line and the second metal line. 168.  The circuit component of claim 167, wherein the memory cell type comprises a static random access memory cell (SRAM cell) 169 169.  The circuit component of claim 167, wherein the memory cell type comprises a dynamic random access memory (DRAM) unit. 170.  The circuit component of claim 167, wherein the memory cell type comprises an erasable programmable read only memory (EPROM) unit. 171.  The circuit component of claim 167, wherein the memory cell type comprises an electronically erasable read only memory (EEPROM) unit. 172.  The circuit component of claim 167, wherein the memory cell type comprises a flash memory unit. 173.  The circuit component of claim 167, wherein the memory cell type comprises a read only memory (ROM) unit. 174.  The circuit component of claim 167, wherein the memory cell type comprises a magnetic random access memory (MRAM) unit. 175.  The circuit component of claim 167, further comprising a sense amplifier positioned between the memory unit and the first metal line of the 151 200816373 mi^ua UO-015TWB. 176.  The circuit component of claim 175, wherein the sense amplifier comprises a differential amplifier 177 177.  The circuit component of claim 175, further comprising a second internal circuit between the sense amplifier and the first metal line. 178.  The circuit component of claim 177, wherein the second internal circuit comprises a NOR gate. 179.  The circuit component of claim 177, wherein the second internal circuit comprises an OR gate. 180.  The circuit component of claim 177, wherein the second internal circuit comprises an AND gate. 181.  The circuit component of claim 177, wherein the second internal circuit comprises a NAND gate. 182.  The circuit component of claim 177, wherein the second internal circuit comprises an adder. 183.  The circuit component of claim 177, wherein the second internal circuit comprises a multiplexer. 184.  The circuit component of claim 177, wherein the second internal circuit comprises a duplexer. 185.  The circuit component of claim 177, wherein the second internal circuit comprises a multiplier (Mu 1 tipi ier). 186.  A circuit component as claimed in claim 177, wherein: 152 200816373 ivjLcur/\ uo-015TWB The second internal circuit comprises a complementary metal oxide semiconductor (CMOS). 187.  The circuit component of claim 177, wherein the second internal circuit comprises a bipolar complementary metal oxide semiconductor (BiCMOS). 188.  The circuit component of claim 177, wherein the second internal circuit comprises a bipolar circuit. 189.  The circuit component of claim 177, wherein the second internal circuit includes at least an N-type MOS device (NM0S), and the channel width/channel length of the N-type MOS device (Channel length) ratio is between 0.  Between 1 and 5. 190.  The circuit component of claim 17, wherein the second internal circuit includes at least one N-type MOS device (NM0S), and the channel width/channel of the N-type MOS device The length of the channel length is between 0. Between 2 and 2. 191.  The circuit component of claim 177, wherein the second internal circuit comprises at least a P-type MOS device, a channel width/channel length of the P-type MOS device (Channel length) ratio is between 0. Between 2 and 10. 192.  The circuit component of claim 177, wherein the second internal circuit comprises at least a P-type MOS device 153 200816373 ivLiiUA uo-015TWB (PMOS), the channel width of the P-type MOS device ( Channel width) / channel length ratio is 0.  Between 4 and 4. 193.  The circuit component of claim 177, wherein the current flowing through the third metal line is between 50 microamperes and 2 milliamperes. 194.  The circuit component of claim 177, wherein the current flowing through the third metal line is between 100 microamperes and 1 milliamperes. 195.  The circuit component of claim 175, further comprising an internal driver between the sense amplifier and the first metal line, the internal driver being composed of at least one metal oxide semiconductor component . 196.  The circuit component of claim 195, wherein the MOS device comprises a P-type MOS device (PM0S), and the channel width/channel length of the P-type MOS device Channel length) is between 3 and 60. 197.  The circuit component of claim 195, wherein the MOS device comprises a P-type MOS device (PM0S), and the channel width/channel length of the P-type MOS device Channel length) is between 5 and 20. 198.  The circuit component of claim 195, wherein the metal germanium semiconductor component comprises an N-type MOS device, and the channel width of the N-type MOS device is 154. 200816373 ivLbUA uo-015TWB The channel length ratio is between 1 · 5 and 30. 199.  The circuit component of claim 195, wherein the MOS device comprises an N-type MOS device, and a channel width/channel length of the N-type MOS device Channel length) ratio is between 2.  Between 5 and 10. 200.  The circuit component of claim 195, wherein the current flowing through the third metal line is between 500 microamps and 10 milliamps. 201.  The circuit component of claim 195, wherein the current flowing through the third metal line is between 700 microamperes and 2 milliamperes. 202.  The circuit component of claim 175, further comprising an internal buffer positioned between the sense amplifier and the first metal line. 203.  The circuit component of claim 175, further comprising an internal tri-states internal buffer between the sense amplifier and the first metal line. 204.  The circuit component of claim 175, further comprising a pass circuit between the sense amplifier and the first metal line. 205.  The circuit component of claim 175, further comprising a latch circuit positioned between the sense amplifier and the first metal line. 206. The circuit component of claim 167, wherein: 155 200816373 Mi^uA υο-015TWB The first internal circuit includes a NOR gate. 207.  The circuit component of claim 167, wherein the first internal circuit comprises an OR gate. 208.  The circuit component of claim 167, wherein the first internal circuit comprises an AND gate. 209.  The circuit component of claim 167, wherein the first internal circuit comprises a NAND gate. 210.  The circuit component of claim 167, wherein the first internal circuit comprises a sense amplifier. 211.  The circuit component of claim 167, wherein the first internal circuit comprises an operational amplifier (Operational Amplifier). 212.  The circuit component of claim 167, wherein the first internal circuit comprises an adder. 213.  The circuit component of claim 167, wherein the first internal circuit comprises a multiplexer. 214.  The circuit component of claim 167, wherein the first internal circuit comprises a duplexer. 215.  The circuit component of claim 167, wherein the first internal circuit comprises a multiplier. 216.  The circuit component of claim 167, wherein the first internal circuit comprises a digital/analog converter (D/A Converter) 217 / the circuit component of claim 167, wherein , 156 200816373 iviiiUA υο-015TWB The first internal circuit includes a complementary metal oxide semiconductor (CMOS) 〇 218. The circuit component of claim 167, wherein the first internal circuit comprises a photosensitive diode (photo-sensitive diode) 219. The circuit component of claim 167, wherein the internal circuit comprises a bipolar complementary metal oxide semiconductor (BiCMOS) 〇 220. The circuit component of item 167, wherein the first internal circuit comprises a bipolar circuit (bip〇lar circuit). The circuit component of claim 1, wherein the first metal line comprises a layer of a thickness between 5 microns and 2 microns. 222. The circuit component of claim 167, wherein the first metal line comprises a thickness system of 0. ~ Copper layer between 05 microns and 2 microns. 223. The circuit component of claim 167, wherein the second metal line comprises a thickness system of 0. A layer of between 05 microns and 2 microns. 224. The circuit component of claim 167, wherein the second metal line comprises a copper layer having a thickness between 5 microns and 2 microns. 225. The circuit component of claim 167, wherein, 157 200816373 mi^ua υο-015TWB, the material of the third metal line comprises gold. 226.  The circuit component of claim 167, wherein the material of the third metal line comprises copper. 227. The circuit component of claim 167, wherein the material of the third metal line comprises silver. 228.  The circuit component of claim 167, wherein the material of the third metal line comprises platinum. 229.  The circuit component of claim 167, wherein the material of the third metal line comprises palladium. 230.  The circuit component of claim 167, wherein the material of the third metal line comprises nickel. 231.  The circuit component structure of claim 167, wherein the third metal circuit comprises a first metal layer and a second metal layer, the second metal layer being on the first metal layer. 232.  The circuit component structure of claim 231, wherein the second metal layer comprises a thickness of 1. A layer of gold from 5 microns to 15 microns. 233.  The circuit component structure of claim 231, wherein the second metal layer comprises a thickness of 1. A copper layer of 5 microns to 50 microns. 234.  The circuit component structure of claim 231, wherein the second metal layer comprises a thickness of 1. A silver layer of 5 microns to 15 microns. 235.  For example, in the circuit component structure described in claim 231, the second metal layer includes a uranium layer having a thickness of between 1.5 μm and 15 μm in 158 200816373 υυ-0ΐ5χ. 236. The circuit component structure of claim 231, wherein the second metal layer comprises a layer having a thickness of between 15 microns and 15 microns. 237. The circuit component structure of claim 231, wherein the second metal layer comprises a thickness of 0. 5 micron to 6 micron nickel layer. The circuit component structure of claim 231, wherein the first metal layer comprises a titanium tungsten alloy layer having a thickness ranging from 〇·02 μm to 〇·8 μm. 9. The circuit component structure of claim 231, wherein the first metal layer comprises a titanium metal layer having a thickness of from 〇·02 μm to 〇·8 μ:. O yl • The circuit component structure as described in claim 231, wherein the first metal layer comprises a titanium nitride layer having a thickness ranging from 〇·02 μm to 〇·8 μm. 241. The circuit component structure of claim 231, wherein the first metal layer comprises a metal layer having a thickness ranging from 〇·〇2 μm to η “υ·行 micron. 242·If applying The circuit component structure of claim 231, wherein the first metal layer comprises a layer having a thickness ranging from 〇·02 μm to 〇 2-8 μm. 24 q as described in claim 231 The circuit component structure of the 159 200816373 ivic person uo-015TWB, the first metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome metal layer. 244.  The circuit component structure of claim 231, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome-copper alloy layer. 245.  The circuit component of claim 167, wherein the material of the protective layer comprises a nitrogen arsenide compound. 246.  The circuit component of claim 167, wherein the material of the protective layer comprises a phosphorous silicate glass (PSG). 247.  The circuit component of claim 167, wherein the material of the protective layer comprises a oxime compound. 248.  The circuit component of claim 167, wherein the material of the protective layer comprises a oxynitride compound. 249.  The circuit component of claim 167, wherein the material of the protective layer comprises borophosphon glass (BPSG). 250.  The circuit component structure of claim 167, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the third metal line. 251.  The circuit component structure of claim 250, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 252.  The circuit component structure of claim 250, wherein the first polymer layer comprises a layer of a phenylcyclobutadiene compound having a thickness of between 2 microns and 100 microns. 160 200816373 jvLbUA UO-015TWB 253.  The circuit component structure of claim 250, wherein the first polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 100 micrometers. 254.  The circuit component structure of claim 250, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 255.  The circuit component of claim 167, wherein the first internal circuit includes at least one N-type MOS device, and the channel width/channel length of the N-type MOS device (Channel length) ratio is between 0. Between 1 and 5. 256.  The circuit component of claim 167, wherein the first internal circuit includes at least one N-type MOS device, and the channel width/channel length of the N-type MOS device (Channel length) ratio is between 0. Between 2 and 2. 257.  The circuit component of claim 167, wherein the first internal circuit includes at least one P-type MOS device, and the channel width/channel length of the P-type MOS device (Channel length) ratio is between 0. Between 2 and 10. 258.  The circuit component of claim 167, wherein the first internal circuit comprises at least a P-type MOS device, and a channel width of the P-type MOS device (Channel 161 200816373 ivlc, o /\ uo-015TWB width)/Channel length ratio is 0.  Between 4 and 4. 259.  The circuit component of claim 167, wherein the current flowing through the third metal line is between 50 microamperes and 2 milliamperes. 260.  The circuit component of claim 167, wherein the current flowing through the third metal line is between 100 microamperes and 1 milliamperes. 261.  The circuit component of claim 167, wherein the second metal line is connected to an output node of the first internal circuit 〇 262.  The circuit component of claim 167, wherein the second metal line is connected to an input node of the first internal circuit 263.  The circuit component of claim 167, wherein the third metal line is not electrically connected to the outside. 264.  The circuit component of claim 167, further comprising a second polymer layer on the third metal line. 265.  The circuit component structure of claim 264, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. . 266.  The circuit component structure of claim 264, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 162 200816373 MliUA U6-015TWB 267.  The circuit component structure of claim 264, wherein the second polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 268.  The circuit component structure of claim 264, wherein the second polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 269.  The circuit component of claim 167, further comprising a third polymer layer overlying the entire upper surface of the third metal trace. 270.  The circuit component structure of claim 269, wherein the third polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 271.  The circuit component structure of claim 269, wherein the third polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 272.  The circuit component structure of claim 269, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 μm and 100 μm. 273.  The circuit component structure of claim 269, wherein the third polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 274.  Such as the line component described in claim 167, including &lt; The substrate containing germanium carries the memory unit:. 275. The circuit component of claim 167, further comprising 163 200816373 iviiiUA υο-015TWB a substrate containing germanium to intercept the internal circuit. 276. The circuit component of claim 175, further comprising an internal receiver positioned between the sense amplifier and the first metal line, the internal receiver being at least one gold oxide The semiconductor element is composed of. 277. The circuit component of claim 276, wherein the MOS device comprises a P-type MOS device (PM0S), and a channel width/channel length of the P-type MOS device The (Channel length) ratio is between 3 and 60. 278. The circuit component of claim 276, wherein the MOS device comprises a P-type MOS device (PM0S), and a channel width/channel length of the P-type MOS device The (Channel length) ratio is between 5 and 20. 279. The circuit component of claim 276, wherein the MOS device comprises an N-type MOS device, and a channel width/channel length of the N-type MOS device The ratio of the ratio is between 1.5 and 30. 280. The circuit component of claim 276, wherein the MOS device comprises an N-type MOS device, and a channel width/channel length of the N-type MOS device (Channel length) ratio between 2. 5 to 10. 281. The circuit component of claim 276, wherein the current flowing through the third metal line is between 500 microamps and 10 milliamperes. 164. The circuit component of claim 276, wherein the current flowing through the third metal line is between 700 microamps and 2 milliamps. 283. The circuit component of claim 175, further comprising an inverter between the sense amplifier and the first metal line, the inverter being at least a MOS semiconductor Component composition. 284. The circuit component of claim 167, wherein the third metal line acts as a data bus of the memory unit to transmit a data signal. 285. The circuit component of claim 167, wherein the third metal line acts as an address bus of the memory unit to transmit an address signal. 286. The circuit component of claim 167, wherein the signal transmitted by the third metal line comprises a clock signal. 287. The circuit component of claim 167, wherein the third metal line comprises at least four bit lines for transmitting signals. 288. The circuit component of claim 167, wherein the third metal line comprises at least 8 bit lines for transmitting signals. 289. The circuit component of claim 167, wherein the third metal line comprises at least 16 bit lines for transmitting signals. 290. The circuit component of claim 167, wherein the third metal line comprises at least 32 bit lines for transmitting signals. 291. The line component of claim 167, wherein the third metal line comprises at least 64 bit lines for transmitting signals. The circuit component of claim 167, wherein the third metal line includes at least 1024 bit lines for transmitting signals. 293. A circuit component comprising: an internal circuit; an f-chip circuit; a first metal line connecting the internal circuit; and a second metal line connecting the chip An external circuit; a protective layer disposed on the internal circuit, the external circuit of the wafer, the first metal line and the second metal line; and a third metal line disposed on the protective layer and connected to the The first metal line and the second metal line, and the current flowing through the third metal line is between 50 microamperes and 10 milliamperes. 294. The line component of claim 293, wherein the internal circuit comprises a NOR gate. 295. The circuit component of claim 293, wherein the internal circuit comprises an OR gate. 296. The circuit component of claim 293, wherein the internal circuit comprises an AND gate. 297. The circuit component of claim 293, wherein the internal circuit comprises a NAND gate. 298. The circuit component of claim 293, wherein the internal circuit comprises a static random access memory cell (SRAM cell) 299. The circuit component of claim 293, wherein , 166 200816373 MliLrA υο-015TWB The internal circuit includes a dynamic random access memory cell (DRAM cell). The circuit component of claim 293, wherein the internal circuit includes a non-volatile memory. The circuit component of claim 293, wherein the internal circuit comprises a flash memory cell. The circuit component of claim 293, wherein the internal circuit comprises an erasable read only memory unit (EPROM cell) 303. The circuit component as described in claim 293 Wherein, the internal circuit includes a read only memory unit (ROM ce 11). The circuit component of claim 293, wherein the internal circuit comprises a magnetic random access memory (MRAM) unit. 305. The circuit component of claim 293, wherein the internal circuit comprises a sense amplifier. 306. The circuit component of claim 293, wherein the internal circuit comprises an operational amplifier (Operational Amplifier) 307. The circuit component of claim 293, wherein the internal circuit comprises An adder. 308. The circuit component of claim 293, wherein: 167 200816373 lvrnuA UO-015TWB The internal circuit includes a multiplexer (Mul tiplexer). 309. The circuit component of claim 293, wherein the internal circuit comprises a duplexer. 310. The circuit component of claim 293, wherein the internal circuit comprises a multiplier. 311. The circuit component of claim 293, wherein the internal circuit comprises an analog/digital converter (A/D converter). 312. The circuit component of claim 293, wherein the internal circuit comprises a digital/analog converter (D/A Converter) q 313. The circuit component of claim 293, wherein The internal circuit includes a complementary metal oxide semiconductor (CMOS). 314. The circuit component of claim 293, wherein the internal circuit comprises a photo-sensitive diode. 315. The circuit component of claim 293, wherein the internal circuit comprises a bipolar complementary metal oxide semiconductor (BiCMOS) 〇 316. The circuit component of claim 293, wherein The internal circuit includes a bipolar circuit unit. 317. The circuit component of claim 293, wherein the internal circuit comprises at least an N-type MOS device (NM0S), a channel width/channel length of the N-type MOS device (Channel length) ratio between 0. 1 to 5. 318. The circuit component of claim 242, wherein the internal circuit comprises at least an N-type MOS device (NMOS), the 168 200816373 jvmuA υο-015TWB N-type MOS device channel width (Channel width) / Channel length (Channel length) ratio between 0. 2 to 2. 319. The circuit component of claim 293, wherein the internal circuit comprises at least a P-type MOS device (PV0S), and a channel width/channel length of the P-type MOS device (Channel length) ratio between 0. 2 to 10. The circuit component of claim 293, wherein the internal circuit comprises at least a P-type MOS device, and a channel width/channel length of the P-type MOS device The ratio of the ratio is between 0.4 and 4. 321. The circuit component of claim 293, wherein the external circuit of the wafer comprises at least an f-chip driver, the external driver of the wafer being at least one MOS component. Composition. 322. The circuit component of claim 321, wherein the MOS device comprises a P-type MOS device (PM0S), and a channel width/channel of the P-type MOS device The length of the channel length is between 40 and 40,000. 323. The circuit component of claim 321, wherein the MOS device comprises a P-type MOS device (PM0S), and a channel width/channel of the P-type MOS device The channel length ratio is between 60 and 600. 324. The circuit component of claim 321, wherein the MOS device comprises an N-type MOS device (NM0S), 169 200816373 ivlc, u/\ uo-015TWB, the N-type MOS semiconductor The channel width/channel length ratio of the component is between 20 and 20,000. 325. The circuit component of claim 321, wherein the MOS device comprises an N-type MOS device, and a channel width/channel of the N-type MOSFET device The channel length ratio is between 30 and 300. 326. The circuit component of claim 293, wherein the external circuit of the wafer comprises at least one off-chip reciver. 327. The circuit of claim 293. An element, wherein the external circuit of the wafer includes at least one off-chip tri-states buffer 328. The circuit component of claim 293, wherein the chip is externally connected The circuit includes at least one electrostatic discharge (ESD) protection circuit. 329. The circuit component of claim 328, wherein the ESD protection circuit comprises a reverse-biased diode 〇330. The circuit of claim 293 The element, wherein the first metal line comprises a layer of a thickness between 0. 05 microns and 2 microns. 331. The circuit component of claim 293, wherein the first metal line comprises a copper layer having a thickness between 0.05 and 2 microns. 332. The circuit component of claim 293, wherein: 170 200816373 iviiiUA υο-015TWB the second metal line comprises an aluminum layer having a thickness between 0.05 and 2 microns. 333. The circuit component of claim 293, wherein the second metal line comprises a copper layer having a thickness between 0.05 microns and 2 microns. 334. The circuit component of claim 293, wherein the material of the third metal line comprises gold. 335. The circuit component of claim 293, wherein the material of the third metal line comprises copper. 336. The circuit component of claim 293, wherein the material of the third metal line comprises silver. 337. The circuit component of claim 293, wherein the material of the third metal line comprises platinum. 338. The circuit component of claim 293, wherein the material of the third metal line comprises palladium. 339. The circuit component of claim 293, wherein the material of the third metal line comprises nickel. 340. The circuit component structure of claim 293, wherein the third metal line comprises a first metal layer and a second metal layer, the second metal layer being on the first metal layer. 341. The circuit component of claim 340, wherein the second metal layer comprises a gold layer having a thickness between 1.5 microns and 15 microns. 342. The circuit component structure of claim 340, wherein the second metal layer comprises a copper layer having a thickness of between 5 5 μm and 5 μm, as in the 171 200816373 ινίϋΟΑ uo-015TWB. 343. The circuit component structure of claim 34, wherein the second metal layer comprises a silver layer having a thickness between 1.5 microns and 15 microns. The circuit component structure of claim 340, wherein the second metal layer comprises a platinum layer having a thickness of from 5 μm to 15 μm. 345. The circuit component structure of claim 340, wherein the second metal layer comprises a layer I having a thickness of between 15 micrometers and 15 micrometers. 34 R as described in claim 340 a circuit component structure, wherein 'the second metal layer comprises a thickness of between 5 micrometers and 6 micrometers, a nickel layer. h, one of 347 micrometers; a circuit component structure as described in claim 340, Wherein the first metal layer comprises a thickness of 0.02 micrometers to 〇, and a titanium-tungsten alloy layer. 348. The circuit component structure of claim 340, wherein the first metal layer comprises a thickness 〇·〇 2 microns $ n. Flying to 0. 8 microns &lt;One metal layer. The first metal layer includes a line element structure having a thickness of between 微米·〇2 μm and 349· as described in claim 340 of the patent application, one of which is a titanium nitride layer.   In the circuit component 纟 172 200816373 mj^ua UO-015TWB, the first metal layer includes a thickness of 0. 02 microns to 0. One set of metal layers of 8 microns. 351.  The circuit component structure of claim 340, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. One layer of 8 micron nitride layer. 352.  The circuit component structure of claim 340, wherein the first metal layer comprises a thickness of 0.  02 microns to 0.  8 micron one chrome metal layer. 353.  The circuit component according to claim 340, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome-copper alloy layer. 354.  The circuit component of claim 293, wherein the material of the protective layer comprises a nitrogen hydrazine compound. 355.  The circuit component of claim 293, wherein the material of the protective layer comprises a constitutive glass (PSG). 356.  The circuit component of claim 293, wherein the material of the protective layer comprises a oxime compound. 357.  The circuit component of claim 293, wherein the material of the protective layer comprises a oxynitride compound. 358.  The circuit component of claim 293, wherein the material of the protective layer comprises borophosphon glass (BPSG). 359.  For example, the circuit component structure described in claim 293, A first polymer layer having a thickness between 2 microns and 100 microns is included between the protective layer and the third metal line. 173 200816373 ivmu/\ uo-015TWB 360.  The circuit component structure of claim 359, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 361.  The circuit component structure of claim 359, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 362.  The circuit component structure of claim 359, wherein the first polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 363.  The circuit component structure of claim 359, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 364.  The circuit component of claim 293, wherein the second metal line is connected to an output node of the external circuit of the chip 〇 365.  The circuit component of claim 293, wherein the second metal line is connected to an input node of the external circuit of the wafer.  The circuit component of claim 293, further comprising a wire formed on the third metal line to be electrically connected to an external circuit. 367.  The circuit component of claim 293, further comprising a second polymer layer on the third metal line. 368.  In the circuit component structure described in claim 367, in the 174 200816373 MJbUA UO-015TWB, the second polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 micrometers and 2 micrometers. . 369. The circuit component structure of claim 367, wherein the second polymer layer comprises a layer of a phenylcyclobutane compound having a thickness between 2 microns and 丨〇〇 microns. 370. The circuit component structure of claim 367, wherein the second polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 1 micrometer. 371. The circuit component structure of claim 367, wherein the second polymer layer comprises an epoxy layer having a thickness between 2 microns and 1 micron. 372. The circuit component of claim 293, further comprising a third polymer layer overlying all of the upper surface of the third metal line. 373.  The circuit component structure of claim 372, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 micrometers and 1 micrometer. 374.  The circuit component structure of claim 372, wherein the third polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 micrometers and 1 micrometer. 375.  The circuit component structure of claim 372, wherein the third polymer layer comprises a polymer layer having a thickness of from 2 μm to 眺-poly-p-xylene. : Micro is not 376.  The third polymer layer comprises an epoxy layer having a thickness of between 2 micrometers and 100 micrometers, as in the circuit component structure described in claim 372, in 175 200816373 JVUbUA υο-015TWB. 377.  The circuit component of claim 293, further comprising a substrate containing germanium carrying the internal circuit. 378.  The circuit component of claim 293, further comprising a substrate containing germanium carrying the external circuit of the wafer. 379.  A circuit component comprising: a first metal oxide semiconductor (MOS) device, the channel width/channel length ratio of the first MOS device being between 0.  1 to 10; a second MOS device; a first metal line connecting the first MOS device; a second metal line connecting the second MOS device; a protective layer, located at The first MOS device, the second MOSFET, the first metal line and the second metal line; and a third metal line on the protective layer and connected to the first metal line And the second metal line. 380.  The circuit component of claim 379, wherein the drain of the first MOS device is connected to the gate of the second MOS semiconductor component. 381.  The circuit component of claim 379, wherein the drain of the first MOS device is connected to the drain 382 382 of the second MOS semiconductor component.  A circuit component as claimed in claim 379, wherein: 176 200816373 MliUA UO-015TWB the drain of the first MOS device is connected to the source of the second MOS semiconductor component. 383.  The circuit component of claim 379, wherein the gate of the first MOS device is connected to the gate of the second MOS semiconductor component. 384.  The circuit component of claim 379, wherein the gate of the first MOS device is connected to the drain of the second MOS semiconductor component. 385.  The circuit component of claim 379, wherein the gate of the first MOS device is connected to the source of the second MOS semiconductor component. 386.  The circuit component of claim 379, wherein the source of the first MOS device is coupled to the gate of the second MOS semiconductor component. 387.  The circuit component of claim 379, wherein the source of the first MOS device is connected to the drain of the second MOS semiconductor component. 388.  The circuit component of claim 379, wherein the source of the first MOS device is coupled to the source of the second MOS semiconductor component. 389.  The circuit component of claim 379, further comprising a NOR gate, the anti-gate being composed of at least the first oxy-halide semiconductor component. 390.  The circuit component of claim 379, further comprising 177 200816373 ΜϋυΑ U0-015TWB OR gate, the sluice system being composed of at least the first MOS device. 391.  The circuit component of claim 379, further comprising an AND gate, and the gate is formed of at least the first MOS device. 392.  The circuit component of claim 379, further comprising a NAND gate, the gate is formed of at least the first MOS device. 393.  The circuit component of claim 379, further comprising a NOR gate, the anti-gate being composed of at least the second oxy-halide semiconductor component. 394.  The circuit component of claim 379, further comprising an OR gate, the gate being formed of at least the second MOS device. 395.  The circuit component of claim 379, further comprising an AND gate, and the gate is formed of at least the second MOS device. 396.  The circuit component of claim 379, further comprising a NAND gate, the gate is formed of at least the second MOS device. 397.  The circuit component of claim 379, further comprising an internal driver, the internal driver being composed of at least the second MOS component. 398.  The circuit component of claim 397, wherein: 178 200816373 ΜϋυΑ UO-015TWB, the second MOS device comprises a 金-type MOS device (PM0S), and the channel width of the NMOS-type MOS device The (Channel width) / Channel length ratio is between 3 and 60. 399.  The circuit component of claim 397, wherein the second MOS device comprises a P-type MOS device (PM0S), and a channel width/channel of the P-type MOS device The length of the channel length is between 5 and 20. 400.  The circuit component of claim 397, wherein the second MOS device comprises an N-type MOS device, and the channel width/channel of the N-type MOS device The length of the channel length is between 1.  Between 5 and 30. 401.  The circuit component of claim 397, wherein the second MOS device comprises an N-type MOS device, and the channel width/channel of the N-type MOS device The length of the channel length is between 2.  Between 5 and 10. 402.  The circuit component of claim 397, wherein the current flowing through the third metal line is between 500 microamps and 10 milliamps. 403.  The circuit component of claim 397, wherein the current flowing through the third metal line is between 700 microamperes and 2 milliamps 179 200816373 ivmu/\ υο-015TWB. 404. The circuit component of claim 379, further comprising an internal circuit comprising at least the second MOS component. 405. The circuit component of claim 404, wherein the second MOS device comprises an N-type MOS device (NM0S), and a channel width of the N-type MOS device The channel lenSth ratio is between 0 and 1 to 5. 406.  The circuit component of claim 404, wherein the second MOS device comprises an N-type MOS device, and the channel width of the N-type MOS device is The channel length ratio is between 〇·2 and 2. 407.  The circuit component of claim 404, wherein the second MOS device comprises a P-type MOS device, and a channel width/channel of the P-type MOS device The length of the channel length is between 0. Between 2 and 10. 408. The circuit component of claim 404, wherein the second MOS device comprises a P-type MOS device, and the channel thickness of the p-type MOS device is The ^ width)/channel iength ratio is between 〇·4 and 4. 180 200816373 IVLtiUA uo-015TWB 409.  The circuit component of claim 404, wherein the current flux flowing through the third metal line is between 50 microamperes and 2 milliamperes. 410.  The circuit component of claim 404, wherein the current flux flowing through the third metal line is between 100 microamperes and 1 milliamperes. 411.  The circuit component of claim 379, further comprising a NOR gate, the anti-gate being composed of at least the second oxy-halide semiconductor component. 412.  The circuit component of claim 379, further comprising an OR gate, the gate being formed of at least the second MOS device. 413.  The circuit component of claim 379, further comprising an AND gate, and the gate is formed of at least the second MOS device. 414.  The circuit component of claim 379, further comprising a NAND gate, the gate is formed of at least the second MOS device. 415.  The circuit component of claim 379, further comprising an inverter, the inverter being constructed of at least the second oxynitride component. 416.  The circuit component of claim 415, wherein the second MOS device comprises a P-type MOS device (PM0S), and a channel width of the P-type MOS device (Channel 181 200816373 ΜϋΟΑ υο -015TWB width) / Channel length ratio is between 3 and 60. 417.  The circuit component of claim 415, wherein the second MOS device comprises a P-type MOS device (PM0S), and a channel width/channel of the P-type MOS device The length of the channel length is between 5 and 20. 418.  The circuit component of claim 415, wherein the second MOS device comprises an N-type MOS device, and the channel width/channel of the N-type MOS device The length of the channel length is between 1. Between 5 and 30. 419.  The circuit component of claim 415, wherein the second MOS device comprises an N-type MOS device, and the channel width/channel of the N-type MOS device The length of the channel length is between 2. Between 5 and 10. 420.  The circuit component of claim 415, wherein the current flowing through the third metal line is between 500 microamps and 10 milliamps. 421.  For example, the circuit component of claim 415, wherein the current flowing through the third metal line is between 700 microamperes and 2 milliamperes. 422.  The circuit component of claim 379, further comprising 182 200816373 MiiUA υο-015TWB an internal circuit, the internal circuit being composed of at least the second MOS component. 423.  The circuit component of claim 422, wherein the second MOS device comprises an N-type MOS device (NM0S), and the channel width/channel of the N-type MOS device The length of the channel length is between 0. Between 1 and 5. 424.  The circuit component of claim 422, wherein the second MOS device comprises an N-type MOS device, and the channel width/channel of the N-type MOS device The length of the channel length is between 0. Between 2 and 2. 425.  The circuit component of claim 422, wherein the second MOS device comprises a P-type MOS device, and a channel width/channel of the N-type MOS device The length of the channel length is between 0. Between 2 and 10. 426.  The circuit component of claim 422, wherein the second MOS device comprises a P-type MOS device, and the channel width of the N-type MOS device is The channel length ratio is between 0.  Between 4 and 4. 427.  The circuit component of claim 422, wherein the current flowing through the third metal line is between 50 microamperes and 2 183 200816373 mi^ua UO-015TAVB milliamperes. 428.  The circuit component of claim 422, wherein the current flux flowing through the third metal line is between 100 microamperes and 1 milliamperes. 429.  The circuit component of claim 379, further comprising a power management chip, wherein the power management chip is formed of at least the second MOS device. 430.  The circuit component of claim 429, wherein the second MOS device comprises a P-type MOS device (PM0S), the width/length of the P-type MOS device channel The ratio is between 4,000 and 400,000. 431.  The circuit component of claim 429, wherein the second MOS device comprises a P-type MOS device (PM0S), and the channel/length of the P-type MOS device channel The ratio is between 4,000 and 40,000. 432.  The circuit component of claim 429, wherein the second MOS device comprises an N-type MOS device (NMOS), the width/length of the N-type MOS device channel The ratio is between 2,000 and 200,000. 433.  The circuit component of claim 429, wherein the second MOS device comprises an N-type MOS device (NMOS), the width/length of the N-type MOS device channel The ratio is between 2,000 and 20,000. 434.  The circuit component of claim 429, wherein the current flowing through the third metal line of 200816373 iviiiu/\ uo-015TWB is between 500 mA and 50 amps. 435.  The circuit component of claim 429, wherein the current flowing through the third metal line is between 500 milliamps and 5 amps. 436.  The circuit component of claim 379, further comprising a power supply chip, the power supply chip being formed of at least the second MOS device. 437.  The circuit component of claim 436, wherein the second MOS device comprises a P-type MOS device (PM0S), the width/length of the P-type MOS device channel The ratio is between 4,000 and 400,000. 438.  The circuit component of claim 436, wherein the second MOS device comprises a P-type MOS device (PM0S), the width/length of the P-type MOS device channel The ratio is between 4,000 and 40,000. 439.  The circuit component of claim 436, wherein the second MOS device comprises an N-type MOS device (NMOS), the width/length of the N-type MOS device channel The ratio is between 2,000 and 200,000. 440.  The circuit component of claim 436, wherein the second MOS device comprises an N-type MOS device (VOS), the width of the N-type MOS device channel (Channel) The ratio of lengths is between 2,000 and 20,000. 185 200816373 MliUA UO-015TWB 441.  The circuit component of claim 436, wherein the third metal line has a current flux between 500 mA and 50 amps. 442.  The circuit component of claim 436, wherein the third metal line has a current flux between 500 mA and 5 amps. 443.  The circuit component of claim 379, further comprising an internal reciver, the internal receiver being formed of at least the second MOS component. 444.  The circuit component of claim 443, wherein the second MOS device comprises a P-type MOS device, and a channel width/channel of the P-type MOS device The length of the channel length is between 3 and 60. 445.  The circuit component of claim 443, wherein the second MOS device comprises a P-type MOS device, and a channel width of the P-type MOS device. The channel length ratio is between 5 and 20. 446.  The circuit component of claim 443, wherein the second MOS device comprises an N-type MOS device, and the channel width/channel length of the N-type MOS device. (Channel length) ratio is between 1. Between 5 and 30. 186 200816373 mi^ua υο-015TWB 447.  The circuit component of claim 443, wherein the second MOS device comprises a 金-type oxy-half-capacitor component (LiS), the channel width of the 金-type MOS device ) / Channel length (Channel length) ratio is between 2.  Between 5 and 10. 448.  The circuit component of claim 443, wherein the current flowing through the third metal line is between 500 microamps and 10 milliamps. 449.  The circuit component of claim 443, wherein the current flowing through the third metal line is between 700 microamperes and 2 milliamperes. 450.  The circuit component of claim 379, further comprising an internal driver, the internal driver being composed of at least the second MOS component. 451.  The circuit component of claim 450, wherein the second MOS device comprises a P-type MOS device, and the channel width/channel of the P-type MOS device The length of the channel length is between 3 and 60. 452.  The circuit component of claim 450, wherein the second MOS device comprises a P-type MOS device (PMQS), and the channel width/channel of the P-type MOS device The length of the channel length is between 5 and 20. 187 200816373 MliUA U5-015TWB 453.  The circuit component of claim 450, wherein the second MOS device comprises an N-type MOS device (NM0S) 'Channel width/channel of the N-type MOS device The length of the channel length is between 1. Between 5 and 30. 454. The circuit component of claim 450, wherein the second MOS device comprises an N-type MOS device, and a channel width of the N-type MOS device Width) / Channel length (Channel length) ratio is between 2.  Between 5 and 10. 455.  The circuit component of claim 450, wherein the current flowing through the third metal line is between 500 microamperes and 1 milliamperes. 456.  For example, the scope of patent application is 450. The circuit component of item wherein the current flowing through the third metal line is between 700 microamperes and 2 milliamperes. </RTI> 457. The circuit component of claim 379, further comprising an internal buffer, the internal buffer being formed of at least the second MOS component. 458. The circuit component of claim 457, wherein the second MOS device comprises a P-type MOS device, a channel width of the P-type MOS device. The channel length ratio is between 3 and 6 。. 188 200816373 ivii^UA UO-015TWB 459.  The circuit component of claim 457, wherein the second MOS device comprises a P-type MOS device (PM0S), and the channel width/channel of the P-type MOS device The length of the channel length is between 5 and 20. 460.  The circuit component of claim 457, wherein the second MOS device comprises an N-type MOS device (NM0S), and the channel width/channel of the N-type MOS device The length of the channel length is between 1. Between 5 and 30. 461.  The circuit component of claim 457, wherein the second MOS device comprises an N-type MOS device (NM0S), and the channel width/channel of the N-type MOS device The length of the channel length is between 2. Between 5 and 10. 462.  The circuit component of claim 457, wherein the current flowing through the third metal line is between 500 microamps and 10 milliamps. 463.  The circuit component of claim 457, wherein the current flowing through the third metal line is between 700 microamperes and 2 milliamperes. 464.  The circuit component of claim 379, further comprising an internal tri-states internal buffer, the internal tri-state buffer being constructed by the second MOS device 189 200816373 jvLbUA υο-015TWB into. 465.  The circuit component of claim 379, wherein the first metal line comprises a thickness system of 0. An aluminum layer between 05 microns and 2 microns. 466. The circuit component of claim 379, wherein the first metal line comprises a thickness system of 0. A copper layer between 05 microns and 2 microns. 467.  The circuit component of claim 379, wherein the second metal line comprises a thickness system of 0. A layer of between 05 microns and 2 microns. 468.  The circuit component of claim 379, wherein the second metal line comprises a thickness system of 0.  A copper layer between 05 microns and 2 microns. 469.  The circuit component of claim 379, wherein the material of the third metal line comprises gold. 470.  The circuit component of claim 379, wherein the material of the third metal line comprises copper. 471.  The circuit component of claim 379, wherein the material of the third metal line comprises silver. 472.  The circuit component of claim 379, wherein the material of the third metal line comprises platinum. 473.  The circuit component of claim 379, wherein the material of the third metal line comprises palladium. 474.  The circuit component of claim 379, wherein the 190 200816373 JVUSUA Ub-015X^3 material of the third metal line comprises nickel. 475.  The circuit component structure of claim 379, wherein the third metal circuit comprises a first metal layer and a second metal layer. The second metal layer is on the first metal layer. 476.  For example, the wire component structure described in claim 475 of the patent, wherein the second metal layer comprises a thickness of 1. Gold layer from 5 microns to 15 microns. 477. The circuit component structure of claim 475, wherein the second metal layer comprises a steel layer having a thickness of from 5 μm to 5 μm. 478. The circuit component structure of claim 475, wherein the second metal layer comprises a layer having a thickness between 15 microns and a silver-silver layer. In the case of the circuit element structure described in claim 475, the second metal layer comprises a platinum layer having a thickness of between 5·5 μm and 15 μm. η 480. The circuit component structure as described in claim 475, wherein the second metal layer comprises a thickness of 1. 5 to 15 micron 2 palladium layer. 481. The circuit component structure of claim 475, wherein the second metal layer comprises a recording layer having a thickness of between 0.5 μm and 6 μm. 482 払 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士 士. The component structure, wherein the first metal layer comprises a thickness of 0. 02 micron to 〇.  8 micron 191 200816373 MliUA UO-015TWB One of the Qinhe alloy layers. 483.  The circuit component structure of claim 475, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one of the metal layers. 484.  The circuit component structure of claim 475, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. One layer of titanium nitride of 8 microns. 485.  The circuit component structure of claim 475, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. One set of metal layers of 8 microns. 486.  The circuit component structure of claim 475, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. One layer of 8 μm tantalum nitride layer. 487.  The circuit component structure of claim 475, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome metal layer. 488.  The circuit component structure of claim 475, wherein the first metal layer comprises a thickness of 0.  02 microns to 0. 8 micron one chrome-copper alloy layer. 489. The circuit component of claim 379, wherein the material of the protective layer comprises a nitrogen hydrazine compound. 490.  The circuit component of claim 379, wherein the material of the protective layer comprises a phosphorous glass (PSG). 491.  The circuit component according to claim 379, wherein 192 200816373 MliUA uo-015TWB the material of the protective layer comprises an oxonium compound. 492.  For example, the circuit component described in Section 379 of the specialist scope is applied, wherein the material of the protective layer comprises a oxynitride compound. 493.  The circuit component of claim 379, wherein the material of the protective layer comprises borophosphorus bismuth glass (BPSG). 494.  The circuit component structure of claim 379, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the third metal line. 495.  The circuit component structure as described in claim 379, further comprising a polyamidene compound layer having a thickness of between 2 micrometers and 100 micrometers between the protective layer and the third metal wiring. 496.  The circuit component structure of claim 495, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 497.  The circuit component structure of claim 495, wherein the first polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 100 micrometers. 498.  The circuit component structure of claim 495, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 499.  The circuit component of claim 379, wherein the third metal line is not electrically connected to the outside. 500.  The circuit component of claim 379, further comprising a second polymer layer on the third metal line. 193 200816373 ivlc,u/\ uo-015TWB 501.  The circuit component structure of claim 500, wherein the second polymer layer comprises a layer of a polyamicimide compound having a thickness of between 2 microns and 100 microns. 502.  The circuit component structure of claim 500, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 503.  The circuit component structure of claim 500, wherein the second polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 100 micrometers. 504.  The circuit component structure of claim 500, wherein the second polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 505.  The circuit component of claim 379, further comprising a third polymer layer overlying the entire upper surface of the third metal trace. 506.  The circuit component structure of claim 505, wherein the third polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 507.  The circuit component structure of claim 505, wherein the third polymer layer comprises a layer of a phenylcyclobutadiene compound having a thickness of between 2 microns and 100 microns. 508.  The circuit component structure of claim 505, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 194 200816373 uo-015TWB 509.  The circuit component structure of claim 505, wherein the third polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 510.  The circuit component of claim 379, further comprising a substrate comprising germanium carrying the first metal oxide semiconductor component. 511.  The circuit component of claim 379, further comprising a substrate comprising germanium carrying the second metal oxide semiconductor component. 512.  A circuit component, comprising: a first electrostatic discharge (ESD) protection circuit comprising a power supply node and a ground node and a signal contact; an internal circuit; a chip external circuit including a first signal a first metal line connecting the power node of the first electrostatic discharge protection circuit; a second metal line connecting the ground node of the first electrostatic discharge protection circuit; a three-metal circuit connecting the signal contact of the first ESD protection circuit and the first signal contact of the external circuit of the chip; a fourth metal line connecting the internal circuit; a protective layer located at the An ESD protection circuit, the first metal line, the second metal line, the third metal line and the fourth metal line; and a fifth metal line on the protective layer, the chip is connected to an external circuit 195 200816373 丄vii^^jr gossip-〇15TWB is connected to the fourth metal line through the fifth metal line. 513. The circuit component of claim 512, wherein the first metal line comprises a layer of a thickness between 〇·05 μm and 2 μm. 514. The circuit component of claim 512, wherein the first metal line comprises a steel layer having a thickness ranging from 〇·micron to 2 microns. 515. The circuit component of claim 512, wherein the second metal line comprises a layer of a thickness between 5 microns and 2 microns. 516.  The circuit component of claim 512, wherein the second metal line comprises a copper layer having a thickness between 5 microns and 2 microns. 517.  The circuit component of claim 512, wherein the third metal line comprises a thickness system (4). An aluminum layer between 5 microns and 2 microns. 518. The circuit component of claim 512, wherein the third metal line comprises a copper layer having a thickness between Q Q5 microns and 2 microns. 51. The circuit component of claim 512, wherein the fourth metal line comprises an aluminum layer having a thickness between q microns and between. The driving four metal (4) includes a copper layer between the thickness of the U5 micro green 2 micron 196 200816373 ivu^vj^ υυ-015TWB. 521. The circuit component of claim 512, wherein the material of the fifth metal line comprises gold. 522. The circuit component of claim 512, wherein the material of the fifth metal line comprises copper. 523. The circuit component of claim 512, wherein the material of the fifth metal line comprises silver. 524. The circuit component of claim 512, wherein. The material of the fifth metal line includes platinum. 525. The circuit component of claim 512, wherein the material of the fifth metal line comprises palladium. 526. The circuit component of claim 512, wherein the material of the fifth metal line comprises nickel. 527. The circuit component structure of claim 512, wherein the fifth metal line comprises a first metal layer and a second metal layer, the second metal layer being on the first metal layer. 528. The circuit component structure of claim 527, wherein the first metal layer comprises a gold layer having a thickness between 1 and 5 microns. 529. The circuit component structure of claim 527, wherein the first metal layer comprises a copper layer having a thickness between 1.5 and 50 microns. The circuit component structure of claim 527, wherein the second metal layer comprises a thickness of between Between 5 microns and 15 microns 197 200816373 Ivmvj^w-〇i5TWB A silver layer. The circuit component structure of 531, wherein the second metal layer comprises a layer of 15 to 15 molybdenum. 532.  The circuit component structure as described in claim 527, wherein the second metal layer comprises a palladium layer having a thickness of from 15 μm to 丨. 533.  The circuit component structure of claim 527, wherein the second metal layer comprises a nickel layer having a thickness of between 5 μm and 6 μm. 536 of 535.  The circuit element structure as described in claim 527, wherein the first metal layer comprises a titanium-tungsten alloy layer having a thickness of between 〇_〇2 μm and 〇8 μm. The circuit component structure of claim 527, wherein the first metal layer comprises a metal layer having a thickness of between 2 μm and 8·8 μm. The circuit component structure of claim 527, wherein the first metal layer comprises a titanium nitride layer having a thickness ranging from 〇·02 μm to 〇·8 μm. 537. The circuit component structure of claim 527, wherein the first metal layer comprises a metal layer having a thickness between 2 μm and 〇 8 μm. 8. 538. The circuit component structure of claim 527, wherein the first metal layer comprises a thickness between 〇 2 μm and 〇 8 μm 198 200816373 ivuj/vj. Rt.  υυ-015TWB One of the nitride layers. 539.  The circuit component structure of claim 527, wherein the first metal layer comprises a thickness of 0.  02 microns to 0.  8 micron one chrome metal layer. 540.  The circuit component structure of claim 527, wherein the first metal layer comprises a thickness of 0.  02 microns to 0.  8 micron one chrome-copper alloy layer. 541.  The circuit component of claim 512, wherein the material of the protective layer comprises a nitrogen hydrazine compound. 542.  The circuit component of claim 512, wherein the material of the protective layer comprises a phosphorous glass (PSG). 543.  The circuit component of claim 512, wherein the material of the protective layer comprises an oxonium compound. 544.  The circuit component of claim 512, wherein the material of the protective layer comprises a oxynitride compound. 545.  The circuit component of claim 512, wherein the material of the protective layer comprises borophosphorus bismuth glass (BPSG). 546.  The circuit component structure of claim 512, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the fifth metal line. 547.  The circuit component structure of claim 546, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 548. The circuit component structure of claim 546, wherein the first polymer layer comprises a phenylcyclobutene having a thickness of between 2 micrometers and 1 micrometer, in 199 200816373 υυ-015TWB Compound layer. 549. The circuit component structure of claim 546, wherein the first polymer layer comprises a parylene polymer layer having a thickness of from 2 micrometers to just micrometers. 550. The circuit component structure of claim 546, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 micrometers and 1 micrometer. 551. The circuit component of claim 512, further comprising a second polymer layer on the fifth metal line. 552. The circuit component structure of claim 551, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness between 2 microns and 1 micron. 553.  The circuit component structure of claim 551, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of from 2 micrometers to just micrometers. 554.  The circuit component structure of claim 551, wherein the second polymer layer comprises a parylene polymer layer having a thickness of between 2 μm and 1 μm. 555.  The circuit component structure of claim 551, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 micrometers and 1 micrometer. 556.  The circuit component of claim 512, further comprising a substrate of 3 turns carrying the first electrostatic discharge protection circuit, the internal electricity 200 200816373 ivuj/vjin.  The uu-015TWB circuit and the external circuit of the chip. 557.  A circuit component comprising: an internal circuit; an off-chip circuit comprising an input node coupled to an external circuit; a first metal line connecting one of the internal circuits a second metal line connecting one of the output nodes of the external circuit of the wafer; a protective layer disposed on the internal circuit, the external circuit of the wafer, the first metal line and the second metal line; The third metal line is located on the protective layer and connects the first metal line and the second metal line. 558.  The circuit component of claim 557, wherein the internal circuit comprises a NOR gate. 559.  The circuit component of claim 557, wherein the internal circuit comprises an OR gate. 560.  The circuit component of claim 557, wherein the internal circuit comprises an AND gate. 561.  The circuit component of claim 557, wherein the internal circuit comprises a NAND gate. 562.  The circuit component of claim 557, wherein the internal circuit comprises a static random access memory cell (SRAM cell) 563.  The circuit component of claim 557, wherein the internal circuit comprises a dynamic random access memory cell (DRAM 201 200816373 MECiA06-015TWB cell) 564 564.  The circuit component of claim 557, wherein the internal circuit comprises a non-volatile memory unit (non-volati le memory cel 1) ° 565.  The circuit component of claim 557, wherein the internal circuit comprises a flash memory cell. 566.  The circuit component of claim 557, wherein the internal circuit comprises an erasable read only memory cell (EPROM cell). 567.  The apparatus of claim 5, wherein the internal circuit comprises a read only memory unit (ROM ce 11). 568.  The circuit component of claim 557, wherein the internal circuit comprises a magnetic random access memory (MRAM) unit. 569.  The circuit component of claim 557, wherein the internal circuit comprises a sense amplifier. 570.  The circuit component of claim 557, wherein the internal circuit comprises an operational amplifier (Operational Amplifier) 571.  The circuit component of claim 557, wherein the internal circuit comprises an adder. 572.  The circuit component of claim 557, wherein the internal circuit comprises a multiplexer. 202 200816373 ivmo/i υο-015TWB 573.  The circuit component of claim 557, wherein the internal circuit comprises a duplexer. 574.  The circuit component of claim 557, wherein the internal circuit comprises a multiplier. 575.  The circuit component of claim 557, wherein the internal circuit comprises an analog/digital converter (A/D converter). 576.  The circuit component of claim 557, wherein the internal circuit comprises a digital/analog converter (D/A Converter). 577. The circuit component of claim 557, wherein the internal circuit comprises a complementary metal oxide semiconductor (CMOS). 578.  The circuit component of claim 557, wherein the internal circuit comprises a photo-sensitive diode. 579.  The circuit component of claim 557, wherein the internal circuit comprises a bipolar complementary metal oxide semiconductor (BiCMOS). 580.  The circuit component of claim 557, wherein the internal circuit comprises a bipolar circuit unit. 581.  The circuit component of claim 557, wherein the internal circuit comprises at least an N-type MOS device (NM0S), and a channel width/channel length of the N-type MOS device Length) The ratio is between 0. Between 1 and 5. 582.  The circuit component of claim 557, wherein the internal circuit comprises at least an N-type MOS device (NM0S), and the channel width of the N-type MOS device/channel 203 200816373 uu The ~015XAVB Channel length ratio is between 0 and 2 to 2. 583.  The circuit component of claim 557, wherein the internal circuit includes at least a P-type MOS device, and a channel width/channel length of the P-type MOS device Length) The ratio is between 0 and 2 to 10. 584.  The circuit component of claim 557, wherein the internal circuit includes at least a P-type MOS device, and a channel width/channel length of the P-type MOS device Length) The ratio is between 0·4 and 4 9 585.  The circuit component of claim 557, wherein the external circuit of the wafer comprises at least an off-chiP receiver, the external receiver of the wafer being at least one MOS device. Composition. 586.  The circuit component of claim 585, wherein the MOS device comprises a P-type MOS device (PM0S), and a channel width/channel length of the P-type MOS device Channel length) is between 40 and 40,000. 587.  The circuit component of claim 585, wherein the MOS device comprises a P-type MOS device (PM0S), and a channel width/channel length of the P-type MOS device Channel length) is between 60 and 600. 588. The circuit component of claim 585, wherein the MOS device comprises an N-type MOS device (NM0S), and the channel width/passage of the N-type MOS device 204 200816373 iviiiu/\ υο-015TWB The channel length ratio is between 20 and 20,000. 589.  The circuit component of claim 585, wherein the MOS device comprises an N-type MOS device, and a channel width/channel length of the N-type MOS device Channel length) is between 30 and 300. 590.  The circuit component of claim 557, wherein the external circuit of the wafer comprises at least one off-chip driver (591).  The circuit component of claim 5, wherein the external circuit includes at least one off-chip tri-states buffer 592 592.  The circuit component of claim 557, wherein the external circuit of the wafer includes at least one electrostatic discharge (ESD) protection circuit. 593.  The circuit component of claim 592, wherein the ESD protection circuit comprises a reverse-biased diode 594.  The circuit component of claim 557, wherein the first metal line comprises a thickness system of 0.  A layer between 05 microns and 2 microns. 595.  The circuit component of claim 557, wherein the first metal line comprises a thickness system of 0. A copper layer between 05 microns and 2 microns. 596.  The circuit component of claim 557, wherein the second metal line comprises a thickness system of 0. 05 micron to 2 micron 205 200816373 ivjju, vj^uu-015TWB between a layer of ginger. 597.  The circuit component of claim 557, wherein the second metal line comprises a thickness system of 0.  A copper layer between 05 microns and 2 microns. 598.  The circuit component of claim 557, wherein the material of the third metal line comprises gold. 599.  The circuit component of claim 557, wherein the material of the third metal line comprises copper. 600.  The circuit component of claim 557, wherein the material of the third metal line comprises silver. 601.  The circuit component of claim 557, wherein the material of the third metal line comprises platinum. 602.  The circuit component of claim 557, wherein the material of the third metal line comprises palladium. 603.  The circuit component of claim 557, wherein the material of the third metal line comprises nickel. &quot; 604.  The circuit component structure of claim 557, wherein the third metal line comprises a first metal layer and a second metal layer, the second metal layer being on the first metal layer. 605.  The circuit component structure of claim 604, wherein the second metal layer comprises a thickness of 1. A layer of gold from 5 microns to 15 microns. 606.  The circuit component structure of claim 604, wherein the second metal layer comprises a thickness of 1. From 5 microns to 50 microns 206 200816373 uu-〇15TWB A copper layer. 607. The circuit component structure of claim 604, wherein the second metal layer comprises a silver layer having a thickness of between 1. 5 microns and 15 microns. 608. The circuit component structure of claim 6, wherein the second metal layer comprises a layer of between 15 microns and 15 microns thick. 609. The circuit component structure of claim 6, wherein the second metal layer comprises an I-bar layer having a thickness between i5 micrometers and 15 micrometers. 610. The circuit component structure of claim 604, wherein the second metal layer comprises a thickness of between 〇 5 μm and 6 μm 611.  612. 613.  The circuit element structure as described in claim 6, wherein the first metal layer comprises a layer of 〇 2 μm to - titanium tungsten alloy. Micro water If you apply for the material described in item _ item ^ 筮 am dry, ,,. Structure: genus: genus layer including thickness TM2 micron to one as described in the patent specification 第 〇 6〇4 The first metal layer includes a thickness of 〇. 〇 2 micro Y, eight - titanium nitride layer. The U-printing patent scope of the scope of the patent line 604, the line of the Yuan Yuan, Ding,, mouth structure, a metal layer of the bean 包括 包括 including the thickness of 〇〇 2 7 , the lower main 0 · 8 micron 207 200816373 ινΐϋ ^ τ/\ υυ-015TWB One button metal layer. 615.  The circuit component structure of claim 604, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one nitride button layer. 616.  The circuit component structure of claim 604, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome metal layer. 617.  The circuit component structure of claim 604, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome-copper alloy layer. 618.  The circuit component of claim 557, wherein the material of the protective layer comprises a nitrogen hydrazine compound. 619.  The circuit component of claim 557, wherein the material of the protective layer comprises a phosphorous silicate glass (PSG). 620.  The circuit component of claim 557, wherein the material of the protective layer comprises an oxonium compound. 621.  The circuit component of claim 557, wherein the material of the protective layer comprises a oxynitride compound. 622.  The circuit component of claim 557, wherein the material of the protective layer comprises borophosphon glass (BPSG). 623.  The circuit component structure of claim 557, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the third metal line. 624.  In the circuit component structure of claim 623, in 208 200816373 ΜϋϋΑ U6-015TWB, the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 μm and 100 μm. 625.  The circuit component structure of claim 623, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 626.  The circuit component structure of claim 623, wherein the first polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 100 micrometers. 627.  The circuit component structure of claim 623, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 628.  The circuit component of claim 557, wherein the current flowing through the third metal line is between 50 microamperes and 10 milliamperes. 629.  The circuit component of claim 557, further comprising a second polymer layer on the third metal line. 630.  The circuit component structure of claim 629, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 631.  The circuit component structure of claim 629, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 632.  The circuit component structure of claim 629, wherein the second polymer layer comprises 209 200816373 ivjj_yvjn having a thickness of between 2 micrometers and 100 micrometers.  A polyparaxylene polymer layer between νυ-015TWB. 633.  The circuit component structure of claim 629, wherein the second polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 634.  The circuit component of claim 557, further comprising a third polymer layer overlying the entire upper surface of the third metal trace. 635.  The circuit component structure of claim 634, wherein the third polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 636.  The circuit component structure of claim 634, wherein the third polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 637.  The circuit component structure of claim 634, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. &quot; 638.  The circuit component structure of claim 634, wherein the third polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 639.  The circuit component of claim 557, further comprising a substrate containing germanium carrying the internal circuit. 640.  The circuit component of claim 557, further comprising a substrate containing germanium carrying the external circuit of the wafer. A line component comprising: 210 641.   200816373 ΜΕϋΑ 06-015TWB an analog circuit comprising at least one input node; a digital/analog converter (D/A Converter) comprising at least one output node; a first metal line connecting the An input node of the analog circuit; a second metal line connecting the output node of the digital/analog converter; a protection layer positioned in the analog circuit, the digital/analog converter, the first metal line, and the And a third metal line disposed on the protective layer and connecting the first metal line and the second metal line. 642.  The circuit component of claim 641, wherein the signal input by the analog circuit comprises a digital analog analog signal. 643.  The circuit component of claim 641, wherein the analog circuit comprises a NOR gate. 644.  The circuit component of claim 641, wherein the analog circuit comprises an OR gate. 645.  The circuit component of claim 641, wherein the analog circuit comprises an AND gate. 646.  The circuit component of claim 641, wherein the analog circuit comprises a NAND gate. 647.  The circuit component of claim 641, wherein the analog circuit comprises a sense amplifier. 648.  The circuit component of claim 641, wherein: 211 200816373 ivjj_/vj^v v/u-015TWB The analog circuit includes an operational amplifier (Operational Amplifier) ° 649.  The circuit component of claim 641, wherein the analog circuit comprises a pulse reshaping circuit ° 650.  The circuit component of claim 641, wherein the analog circuit comprises a switched-capacitor filter (° 651.  The circuit component of claim 641, wherein the analog circuit comprises a RC filter. 652.  The circuit component of claim 641, wherein the analog circuit comprises a P-type metal oxide semiconductor (PMOS). 653.  The circuit component of claim 6, wherein the analog circuit comprises an N-type metal oxide semiconductor (NMOS). 654.  The circuit component of claim 641, wherein the first metal line comprises a thickness system of 0.  A layer of between 05 microns and 2 microns. 655.  The circuit component of claim 641, wherein the first metal line comprises a thickness system of 0. A copper layer between 05 microns and 2 microns. 656.  The circuit component of claim 641, wherein the second metal line comprises a thickness system of 0.  An aluminum layer between 05 microns and 2 microns. 657.  The circuit component of claim 641, wherein 212 200816373 MEUA U5-015TWB the second metal line comprises a thickness system of 0.  A copper layer between 05 microns and 2 microns. 658.  The circuit component of claim 641, wherein the material of the third metal line comprises gold. 659.  The circuit component of claim 641, wherein the material of the third metal line comprises copper. 660.  The circuit component of claim 641, wherein the material of the third metal line comprises silver. 661.  The circuit component of claim 641, wherein the material of the third metal line comprises platinum. 662.  The circuit component of claim 641, wherein the material of the third metal line comprises palladium. 663.  The circuit component of claim 641, wherein the material of the third metal line comprises nickel. 664.  The circuit component structure of claim 641, wherein the third metal line comprises a first metal layer and a second metal layer, the second metal layer being on the first metal layer. 665.  The circuit component structure of claim 664, wherein the second metal layer comprises a thickness of 1. A layer of gold from 5 microns to 15 microns. 666.  The circuit component structure of claim 664, wherein the second metal layer comprises a thickness of 1.  A copper layer of 5 microns to 50 microns. 667.  For example, in the circuit component structure described in claim 664, in 213 200816373 and vanvvi-ObTWB, the second metal layer comprises a silver layer having a thickness of from 1 to 5 micrometers to is micrometers. 68. The circuit component structure of claim 664, wherein the second metal layer comprises a thickness of 1. Surface layer from 5 microns to 15 microns. R β π • The circuit component structure as described in claim 664, wherein the second metal layer comprises a layer having a thickness of from 15 μm to 15 μm. P ry λ • The circuit component structure as described in claim 664, wherein the second metal layer comprises a thickness of 0. One of 5 microns to 6 microns of nickel. 671. The circuit component structure of claim 664, wherein the first metal layer comprises a titanium tungsten alloy layer having a thickness between 0. 02 microns and 〇 8 microns. 672. The circuit component structure of claim 664, wherein the first metal layer comprises a thickness of between 0. 02 microns and 0. One of 8 micron titanium metal layers. 673. The circuit component structure of claim 664, wherein the first metal layer comprises a thickness between 〇·02 μm and 〇. 8 micron to titanium nitride layer. 67 4 .   • The circuit component structure as described in claim 664, wherein the first metal layer comprises a thickness of 0.  02 microns to 0.  8 micron one button metal layer. 675.  - The line component structure described in claim 664 of the patent scope, in the 214 015 TWB 200816373, the first metal layer comprises a thickness of 0.  02 microns to 0.  One layer of 8 μm tantalum nitride layer. 676.  The circuit component structure of claim 664, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome metal layer. 677.  The circuit component structure of claim 664, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. One layer of 8 μm copper alloy layer. 678.  The circuit component of claim 641, wherein the material of the protective layer comprises a nitrile compound. 679.  The circuit component of claim 641, wherein the material of the protective layer comprises a phosphorous silicate glass (PSG). 680.  The circuit component of claim 641, wherein the material of the protective layer comprises an oxonium compound. 681.  The circuit component of claim 641, wherein the material of the protective layer comprises a oxynitride compound. 682.  The circuit component of claim 641, wherein the material of the protective layer comprises borophosphon glass (BPSG). 683.  The circuit component structure of claim 641, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the third metal line. 684.  The circuit component structure of claim 683, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 215 200816373 υο-015TWB 685.  The circuit component structure of claim 683, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 686.  The circuit component structure of claim 683, wherein the first polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 687.  The circuit component structure of claim 683, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 688.  The circuit component of claim 641, wherein the third metal line is not electrically connected to the outside. 689.  The circuit component of claim 641, wherein the signal transmitted by the third metal line comprises a digital analog analog signal. 690.  The circuit component of claim 641, further comprising a second polymer layer on the third metal line. 691.  The circuit component structure of claim 690, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 692.  The circuit component structure of claim 690, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 and 100 microns. 693.  The circuit component structure of claim 690, wherein the second polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 100 micrometers. 216 200816373 ινυ^^τ/\ υο-015TWB 694.  The circuit component structure of claim 690, wherein the second polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 695.  The circuit component of claim 641, further comprising a third polymer layer overlying all of the upper surface of the third metal line. 696.  The circuit component structure of claim 695, wherein the third polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 697.  The circuit component structure of claim 695, wherein the third polymer layer comprises a layer of a phenylcyclobutadiene compound having a thickness of between 2 microns and 100 microns. 698.  The circuit component structure of claim 695, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 699.  The circuit component structure of claim 695, wherein the third polymer layer comprises an epoxy layer having a thickness of between 2 micrometers and 100 micrometers. 700.  The circuit component of claim 641, further comprising a substrate containing germanium carrying the analog circuit. 701.  The circuit component of claim 641, further comprising a substrate containing germanium carrying the digital/analog converter. 7 0 2.  A circuit component, comprising: an electrostatic discharge (ESD) protection circuit comprising a power supply node (power 217 200816373 ivjlc/Vj/\υυ-015TWB node) and a ground node; an internal circuit, including a a power node and a ground node; a first metal line connecting the power nodes of the internal circuit; a second metal line connecting the ground nodes of the internal circuit; and a third metal line connecting a power supply node of the ESD protection circuit; a fourth metal line connecting the ground node of the ESD protection circuit; the protection layer 'in the ESD protection circuit, the internal circuit, the first metal line, the second metal a line, the third metal line and the fourth metal line; a fifth metal line located on the protective layer, and connecting the first metal line and the third metal line; and a sixth metal line, On the protective layer, the second metal line and the fourth metal line are connected. 703.  The circuit component of claim 702, wherein the first metal line comprises a thickness system of 0.  A layer of between 05 microns and 2 microns. 704.  The circuit component of claim 702, wherein the first metal line comprises a thickness system of 0. A copper layer between 05 microns and 2 microns. 705.  The circuit component of claim 702, wherein the second metal line comprises a thickness system of 0. Between 05 microns and 2 microns 218 200816373 ινΐϋ〇/\ uo-015TWB is a layer of inscription. 706. The circuit component of claim 702, wherein the second metal line comprises a thickness system. A copper layer between 5 microns and 2 microns. 707. The circuit component of claim 7, wherein the third metal line comprises a layer of a thickness between 〇·05 μm and 2 μm. 708. The circuit component of claim 702, wherein the third metal line comprises a copper layer having a thickness between 5 microns and 2 microns. 709. The circuit component of claim 702, wherein:  The fourth metal line includes a layer of a thickness between 5 microns and 2 microns. 710. The circuit component of claim 702, wherein the fourth metal circuit comprises a copper layer having a thickness between 1 micrometer and 1 micrometer. 711. The circuit component of claim 702, wherein the material of the fifth metal line comprises gold. 712. The circuit component of claim 702, wherein the material of the fifth metal line comprises copper. 713. The circuit component of claim 702, wherein the material of the fifth metal line comprises silver. 714. The circuit component of claim 702, wherein the material of the fifth metal line comprises platinum. 219 200816373 υυ-015TWB 715.  The circuit component of claim 702, wherein the material of the fifth metal line comprises palladium. 716.  The circuit component of claim 702, wherein the material of the fifth metal circuit comprises nickel. 717.  The circuit component of claim 702, wherein the material of the sixth metal circuit comprises gold. 718.  The circuit component of claim 702, wherein the material of the sixth metal circuit comprises copper. 719.  The circuit component of claim 702, wherein the material of the sixth metal circuit comprises silver. 720.  The circuit component of claim 702, wherein the material of the sixth metal circuit comprises platinum. 721.  The circuit component of claim 702, wherein the material of the sixth metal circuit comprises palladium. 722.  The circuit component of claim 702, wherein the material of the sixth metal circuit comprises nickel. 723.  The circuit component structure of claim 702, wherein the fifth metal circuit comprises a first metal layer and a second metal layer, the second metal layer being on the first metal layer. 724.  The circuit component structure of claim 723, wherein the second metal layer comprises a thickness of 1. A layer of gold from 5 microns to 15 microns. 725.  The circuit component structure of claim 723, wherein the second metal layer comprises a thickness of 1. 5 microns to 50 microns 220 200816373 MbUA uo-015TWB A copper layer. 72β. The circuit component structure as described in claim 723, wherein the second metal layer comprises a thickness of 丨. 5 micron to ', - silver layer. </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; ‘, .   .   72» The circuit component structure of claim 723, wherein the second metal layer comprises a palladium layer having a thickness of between 1.5 and 15 microns. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 730 κ ^ The circuit component structure described in claim 723, wherein the first metal layer comprises a layer of a bismuth alloy having a thickness ranging from 微米2 to 88 μm. 731. The circuit component structure of claim 723, wherein the first metal layer comprises a titanium metal layer having a thickness between 2 μm and 〇 8 μm. 732. The circuit component structure of claim 723, wherein the first metal layer comprises a thickness between 〇·〇2 microns to q.  8 micron - titanium nitride layer. 733. The circuit component structure of claim 723, wherein the first metal layer comprises a metal layer having a thickness ranging from 微米·〇2 μm to 〇·8 μm 221 200816373 MJbUA UO-015TWB . 734.  The circuit component structure of claim 723, wherein the first metal layer comprises a thickness of 0. 02 levy rice to 0. One layer of 8 μm tantalum nitride layer. 735.  The circuit component structure of claim 723, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. One layer of 8 micron metal. 736.  The circuit component structure of claim 723, wherein the first metal layer comprises a thickness of 0. 02 microns to 0. One layer of 8 μm copper alloy layer. 737.  The circuit component structure of claim 702, wherein the sixth metal circuit comprises a third metal layer and a fourth metal layer, the fourth metal layer being on the third metal layer. 738.  The circuit component structure of claim 737, wherein the fourth metal layer comprises a thickness of 1. A layer of gold from 5 microns to 15 microns. % 739.  The circuit component structure of claim 737, wherein the fourth metal layer comprises a thickness of 1. A copper layer of 5 microns to 50 microns. 740.  The circuit component structure of claim 737, wherein the fourth metal layer comprises a thickness of 1. A silver layer of 5 microns to 15 microns. . 741.  The circuit component structure as described in claim 737, wherein the fourth metal layer comprises a thickness of 1. 5 microns to 15 microns 222 200816373 υυ-〇15Χ\^β A layer of inscription. 742β is the circuit component structure as described in claim 737, wherein the fourth metal layer comprises a thickness of 1. A layer of 5 microns to 15 microns. 743. The circuit component structure of claim 737, wherein the fourth metal layer comprises a nickel layer having a thickness of between 5 micrometers and 6 micrometers. 744. The circuit component structure of claim 737, wherein the third metal layer comprises a thickness of between 〇.  嫣 2 microns to 〇 8 microns of the alloy layer. 5. The circuit component structure of claim 737, wherein the second metal layer comprises a thickness of between 2 micrometers and 〇. One of 8 micron titanium metal layers. 746. The circuit component structure of claim 737, wherein the second metal layer comprises a titanium nitride layer having a thickness between 2 μm and 〇 8 μm. 747. The circuit component structure of claim 737, wherein the second metal layer comprises a button metal layer having a thickness between 〇·02 μm and 〇·8 μm. 7 4 8 κ The circuit component structure as described in claim 737 of the patent application, wherein the third metal layer comprises a thickness of between 0 02 μm and 〇. 8 micron nitride button layer. 749. The circuit component structure of claim 737, wherein the second metal layer comprises a chrome metal layer having a thickness between 〇2 μm and 〇8 μm 223 200816373 MbUA U0-015TWB. 750.  The circuit component structure of claim 737, wherein the third metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome-copper alloy layer. 751.  The circuit component of claim 702, wherein the material of the protective layer comprises a nitrile compound. 752.  The circuit component of claim 702, wherein the material of the protective layer comprises a phosphorous glass (PSG). 753.  The circuit component of claim 702, wherein the material of the protective layer comprises a monoxide compound. 754.  The circuit component of claim 702, wherein the material of the protective layer comprises a oxynitride compound. 755.  The circuit component of claim 702, wherein the material of the protective layer comprises a boron phosphide chopped glass (BPSG). 756.  The circuit component structure of claim 702, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the fifth metal line. 757.  The circuit component structure of claim 756, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 758.  The circuit component structure of claim 756, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 759.  In the circuit component structure described in claim 756, in 224 200816373 υυ-015TWB, the first polymer layer comprises a parylene polymer layer having a thickness of between 2 μm and 100 μm. 760.  The circuit component structure of claim 756, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 761.  The circuit component structure of claim 702, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the sixth metal line. 762.  The circuit component structure of claim 761, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 763.  The circuit component structure of claim 761, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 764.  The circuit component structure of claim 761, wherein the first polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 765.  The circuit component structure of claim 761, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 766.  The circuit component of claim 702, wherein the internal circuit comprises a NOR gate. 767.  The circuit component of claim 702, wherein the internal circuit comprises an OR gate. 225 200816373 Ml^UA UO-015TWB 768.  The circuit component of claim 702, wherein the internal circuit comprises an AND gate. 769.  The circuit component of claim 702, wherein the internal circuit comprises a NAND gate. 770.  The circuit component of claim 702, wherein the internal circuit comprises a static random access memory unit (SRAM cell) 771.  The circuit component of claim 702, wherein the internal circuit comprises a dynamic random access memory cell (DRAM cell) 772.  The circuit component of claim 702, wherein the internal circuit comprises a non-volatile memory unit (non-volati le memory cel 1) ° 773.  The circuit component of claim 702, wherein the internal circuit comprises a flash memory unit (flash memory cel 1) ° 774.  The circuit component of claim 702, wherein the internal circuit comprises an erasable read only memory unit (EPROM cell) 775 775.  The circuit component of claim 702, wherein the internal circuit comprises a ROM cell. 776.  The circuit component of claim 702, wherein the internal circuit comprises a magnetic random access memory (MRAM) unit. 226 200816373 ινιιιο/\ υο-015TWB 777.  The circuit component of claim 702, wherein the internal circuit comprises a sense amplifier. 778.  The circuit component of claim 702, wherein the internal circuit comprises an operational amplifier (Operational Amplifier) 779.  The circuit component of claim 702, wherein the internal circuit comprises an adder (adder &gt; 780.  The circuit component of claim 702, wherein the internal circuit comprises a multiplexer. 781.  The circuit component of claim 702, wherein the internal circuit comprises a duplexer. 782.  The circuit component of claim 702, wherein the internal circuit comprises a multiplier. 783.  The circuit component of claim 702, wherein the internal circuit comprises an analog/digital converter (A/D converter). 784.  The circuit component of claim 702, wherein the internal circuit comprises a digital/analog converter (D/A Converter). 785.  The circuit component of claim 702, wherein the internal circuit comprises a complementary metal oxide semiconductor (CMOS). 786.  The circuit component of claim 702, wherein the internal circuit comprises a photo-sensitive diode. 787.  The circuit component as claimed in claim 702, wherein the internal circuit comprises a bipolar complementary metal oxide semiconductor (BiCMOS) 227 227 200816373 ivlco/\ uo-015TWB 788.  The circuit component of claim 702, wherein the internal circuit comprises a bipolar circuit unit. 789.  The circuit component of claim 702, wherein the internal circuit comprises at least an N-type MOS device (NM0S), and the channel width/channel length of the N-type MOS device Length) The ratio is between 0.  Between 1 and 5. 790.  The circuit component of claim 702, wherein the internal circuit includes at least an N-type MOS device (NM0S), and the channel width/channel length of the N-type MOS device Channel length) ratio is between 0.  Between 2 and 2. 791.  The circuit component of claim 702, wherein the internal circuit comprises at least a P-type MOS device, a channel width/channel length of the P-type MOS device Channel length) ratio is between 0.  Between 2 and 10. 792.  The circuit component of claim 702, wherein the internal circuit includes at least a P-type MOS device, and a channel width/channel length of the P-type MOS device Length) The ratio is between 0.  Between 4 and 4. 793.  The circuit component of claim 702, wherein the current flowing through the fifth metal line is between 50 microamperes and 2 milliamperes. 794.  The circuit component of claim 702, wherein the current flowing through the fifth metal line is between 100 microamperes and 1 milliamperes. 228 200816373 L\LCjKJi\ uo-015TWB 795.  The circuit component of claim 702, wherein the current flowing through the sixth metal line is between 50 microamperes and 2 milliamperes. 796.  The circuit component of claim 702, wherein the current flowing through the sixth metal line is between 100 microamperes and 1 milliamperes. 797.  The circuit component of claim 702, further comprising a second polymer layer on the fifth metal line and the sixth metal line. 798.  The circuit component structure of claim 797, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 799.  The circuit component structure of claim 797, wherein the second polymer layer comprises a layer of a phenylcyclobutadiene compound having a thickness of between 2 microns and 100 microns. 800.  The circuit component structure of claim 797, wherein the second polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 801.  The circuit component structure of claim 797, wherein the second polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 802. The circuit component of claim 702, further comprising a third polymer layer overlying all of the upper surface of the fifth metal line and the sixth metal line. 229 200816373 iviiZ/VJ^L υυ-015TWB 803.  The circuit component as described in claim 802, wherein the third polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 micrometers and 100 micrometers. 804.  The circuit component structure of claim 802, wherein the third polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 805.  The circuit component structure of claim 802, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 806.  The circuit component structure of claim 802, wherein the third polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 807.  The circuit component of claim 702, wherein the ESD protection circuit comprises a reverse-biased diode 808.  The circuit component of claim 702, further comprising a substrate containing germanium carrying the electrostatic discharge protection circuit. 809.  The circuit component of claim 702, further comprising a substrate containing germanium carrying the internal circuit. 810.  a circuit component, comprising: an off-chip reciver comprising an input node and an output node; a memory cell; a first metal circuit connected to the chip for external reception The output section of the device 230 200816373 lYxx^vjjn.  a second metal line connecting the memory unit; a protective layer positioned on the external receiver of the wafer, the memory unit, the first metal line and the second metal line; a third metal line connecting the first metal line and the second metal line; a fourth metal line under the protective layer and connecting the input node of the external receiver of the wafer, and the fourth metal line includes at least a first metal pad is exposed in one of the openings of the protective layer; a fifth metal line is located above the protective layer and the fifth metal line includes a second metal pad, the second metal pad is electrically connected The first metal pad has a second metal pad position different from the first metal pad position in a top perspective view, and the second metal pad includes a thickness greater than 1. a first metal layer of 5 micrometers; and a wire positioned on the second metal pad. 811.  The circuit component of claim 810, wherein the external receiver of the wafer is composed of at least one MOS component. 812.  The circuit component of claim 811, wherein the MOS device comprises a P-type MOS device (PM0S), and a channel width/channel length of the P-type MOS device Channel length) is between 40 and 40,000. 813.  The circuit component of claim 811, wherein the MOS device comprises a P-type gold-germanium semiconductor device (PMOS), and the channel width of the P-type MOS device is 231 200816373 IviiiUA υο-015TWB The channel length ratio is between 60 and 600. 814.  The circuit component of claim 811, wherein the MOS device comprises an N-type MOS device, and the channel width/channel length of the N-type MOS device Channel length) is between 20 and 20,000. 815.  The circuit component of claim 811, wherein the MOS device comprises an N-type MOS device, and the channel width/channel length of the N-type MOS device Channel length) is between 30 and 300. 816.  The circuit component of claim 810, further comprising an electrostatic discharge (ESD) protection circuit connected to the first metal line. 817.  The circuit component of claim 7, wherein the ESD protection circuit comprises a reverse-biased diode 818 818.  For example, the circuit component described in claim 810, wherein the memory cell type includes a static random access memory cell (SRAM cell) 819 819.  The circuit component of claim 810, wherein the memory cell type comprises a dynamic random access memory (DRAM) unit. 820.  The circuit component of claim 810, wherein the memory cell type comprises an erasable programmable read only memory (EPROM) unit. 821.  For example, the circuit component described in claim 810 of the patent scope, wherein, 232 200816373 ivuiu/\ uo-015TWB, the type of the memory unit includes an electronically erasable read only memory (EEPROM) unit. 822.  The circuit component of claim 810, wherein the memory cell type comprises a flash memory unit. 823.  The circuit component of claim 810, wherein the memory cell type comprises a read only memory (ROM) unit. 824.  The circuit component of claim 810, wherein the memory cell type comprises a magnetic random access memory (MRAM) unit 0 825.  The circuit component of claim 810, wherein the first metal line comprises a thickness system of 0. An aluminum layer between 05 microns and 2 microns. 826.  The circuit component of claim 810, wherein the first metal line comprises a thickness system of 0.  A copper layer between 05 microns and 2 microns. 827.  The circuit component of claim 810, wherein the second metal line comprises a thickness system of 0.  A layer between 05 microns and 2 microns. 828.  The circuit component of claim 810, wherein the second metal line comprises a thickness system of 0.  A copper layer between 05 microns and 2 microns. 829.  The circuit component of claim 810, wherein the fourth metal line comprises a thickness system of 0.  A layer of between 05 microns and 2 microns. 233 200816373 υυ-015TWB 830.  The circuit component of claim 810, wherein the fourth metal line comprises a thickness system of 0.  A copper layer between 05 microns and 2 microns. 831.  The circuit component of claim 810, wherein the material of the third metal line comprises gold. 832.  The circuit component of claim 810, wherein the material of the third metal line comprises copper. 833.  The circuit component of claim 810, wherein the material of the third metal line comprises silver. 834.  The circuit component of claim 810, wherein the material of the third metal line comprises platinum. 835.  The circuit component of claim 810, wherein the material of the third metal line comprises palladium. 836.  The circuit component of claim 810, wherein the material of the third metal line comprises nickel. 837.  The circuit component structure of claim 810, wherein the third metal circuit comprises a second metal layer and a third metal layer, the third metal layer being on the second metal layer. 838.  The circuit component structure of claim 837, wherein the third metal layer comprises a thickness of 1.  A layer of gold from 5 microns to 15 microns. 839.  The circuit component structure of claim 837, wherein the third metal layer comprises a thickness of 1.  A copper layer of 5 microns to 50 microns. 234 200816373 ινιτΛΐ eight uo-015TWB 840.  The circuit component structure of claim 837, wherein the third metal layer comprises a thickness of 1. 5 micro-finish to a silver layer of 15 microns. 841.  The circuit component structure of claim 837, wherein the third metal layer comprises a thickness of 1.  A layer of 5 microns to 15 microns. 842.  The circuit component structure of claim 837, wherein the third metal layer comprises a thickness of 1.  One I bar layer from 5 microns to 15 microns. 843.  The circuit component structure of claim 837, wherein the third metal layer comprises a thickness of 0.  One of 5 microns to 6 microns of nickel. 844.  The circuit component structure of claim 837, wherein the second metal layer comprises a thickness of 0. 02 microns to 0. One of 8 micron alloy layers. 845.  The circuit component structure of claim 837, wherein the second metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one of the metal layers. 846.  The circuit component structure of claim 837, wherein the second metal layer comprises a thickness of 0. 02 microns to 0. One layer of titanium nitride of 8 microns. 847.  The circuit element companion structure of claim 837, wherein the second metal layer comprises a thickness of 0.  02 microns to 0.  8 micron one button metal layer. 235 200816373 ινυζ/^Λ υυ-015TWB 848.  The circuit component structure of claim 837, wherein the second metal layer comprises a thickness of 0. 02 microns to 0. One layer of 8 μm tantalum nitride layer. 849.  For example, the circuit component structure described in the patent specification, the second metal layer includes a thickness of 0. 02 microns to 0.  One layer of 8 micron metal. 850.  The circuit component structure of claim 837, wherein the second metal layer comprises a thickness of 0.  02 microns to 0.  8 micron one chrome-copper alloy layer. 851.  The circuit component of claim 810, wherein the material of the fifth metal line comprises gold. 852.  The circuit component of claim 810, wherein the material of the fifth metal line comprises copper. 853.  The circuit component of claim 810, wherein the material of the fifth metal line comprises silver. 854.  The circuit component of claim 810, wherein the material of the fifth metal line comprises platinum. 855.  The circuit component of claim 810, wherein the material of the fifth metal line comprises palladium. 856.  The circuit component of claim 810, wherein the material of the fifth metal line comprises nickel. 857.  The circuit component structure of claim 810, wherein the first metal layer comprises a gold layer having a thickness ranging from IV5 micrometers to 1:5 micrometers. 236. The method of claim 1 , wherein the first metal layer comprises a thickness of 1. A copper layer of 5 microns to 5 microns. 859. The circuit component structure of claim 810, wherein the first metal layer comprises a silver layer having a thickness of between 1.5 μm and κ 13 μm. 860. The circuit component structure of claim 810, wherein the first metal layer comprises a surface layer having a thickness of between 1. 5 microns and 15 microns. 861. The circuit component structure of claim 810, wherein the first metal layer comprises a layer having a thickness of between 1. 5 microns and 15 microns. 862. The circuit component structure of claim 810, wherein the first metal layer comprises a nickel layer having a thickness of between 5 micrometers and 6 micrometers. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 864 j. The circuit component structure as described in claim 863, wherein the fourth metal layer comprises a chain alloy layer having a thickness ranging from 0. 02 micrometers to 8 micrometers. O D η . The circuit component structure according to claim 863, wherein the fourth metal layer comprises a titanium metal layer having a thickness ranging from 〇·02 μm to 征 8 mm. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; 02 micron to 〇 · 8 micron one titanium nitride layer. 867. The circuit component structure of claim 863, wherein the fourth metal layer comprises a metal layer having a thickness ranging from 微米·〇2 μm to 〇·8 μm. 868. The circuit component structure of claim 863, wherein the fourth metal layer comprises a thickness of 0. 02 micron to 〇 · 8 micron one nitride button layer. 869. The circuit component structure of claim 863, wherein the fourth metal layer comprises a metal layer having a thickness between 0. 02 micrometers and 〇 8 micrometers. 870. The circuit component structure of claim 863, wherein the fourth metal layer comprises a chromium-copper alloy layer having a thickness ranging from 0. 02 micrometers to 8 nanometers. % 87L is the circuit component of claim 810, wherein the material of the protective layer comprises a nitrogen arsenide compound. 872. The circuit component of claim 810, wherein the material of the protective layer comprises a phosphorous glass (PSG). 873. The circuit component of claim 810, wherein the material of the protective layer comprises an oxonium compound. 874. The circuit component of claim 81, wherein the material of the protective layer comprises a oxynitride compound. 875. The circuit component of claim 810, wherein 238 200816373 ivlc^j/v uo-015TWB The material of the protective layer comprises borophosphorus bismuth glass (BPSG). 876. The circuit component structure of claim 810, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the third metal line. 877. The circuit component structure of claim 876, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 micrometers and 1 micrometer. 878. The circuit component structure of claim 876, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness between 2 microns and 1 micron. 879. The circuit component structure of claim 876, wherein the first polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 1 micrometer. 880. The circuit component structure of claim 876, wherein the first polymer layer comprises an epoxy layer having a thickness between 2 microns and 1 micron. 881. The circuit component structure of claim 810, further comprising a second polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the fifth metal line. 882. The circuit component structure of claim 881, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness between 2 microns and 1 micron. 883. The circuit component structure of claim 881, wherein the second polymer layer comprises a phenylcyclobutene between 239 200816373 MECiA O6-015TWB having a thickness between 2 microns and 1 micron. Compound layer. 884.  For example, the circuit component structure described in claim 881, wherein The second polymer layer comprises a parylene polymer layer having a thickness of between 2 microns and 100 microns. 885.  The circuit component structure of claim 881, wherein the second polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 886.  The circuit component of claim 810, wherein the current flowing through the third metal line is between 50 microamperes and 2 milliamperes. 887.  The circuit component of claim 810, wherein the current flowing through the third metal line is between 100 microamperes and 1 milliamperes. 888.  The circuit component of claim 810, further comprising a third polymer layer on the third metal line and the fourth metal line, the third polymer layer including at least one opening exposing the first A metal pad. 889.  The circuit component structure of claim 888, wherein the third polymer layer comprises a layer of a polyamidimide compound having a thickness of from 2 micrometers to 100 micrometers. 890.  The circuit component structure of claim 888, wherein the third polymer layer comprises a layer of a stupid cyclobutene compound having a thickness of between 2 microns and 100 microns. 891.  For example, in the circuit component structure described in claim 888, in the 240 200816373 ΜϋυΑ UO-015TWB, the third polymer layer comprises a parylene polymer having a thickness between 2 and 100 μm. Floor. 892.  The circuit component structure of claim 888, wherein the third polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 893.  The circuit component structure of claim 888, wherein the fifth metal line is on the third polymer layer. 894.  The circuit component of claim 810, further comprising a fourth polymer layer on the fifth metal line and the third metal line, the fourth polymer layer including at least one opening exposing the first Two metal pads. 895.  The circuit component structure of claim 894, wherein the fourth polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 896.  The circuit component structure of claim 894, wherein the fourth polymer layer comprises a layer of a phenylcyclobutadiene compound having a thickness of between 2 microns and 100 microns. 897. The circuit component structure of claim 894, wherein the fourth polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 898.  The circuit component structure of claim 894, wherein the fourth polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 899.  The circuit component as described in claim 810, further comprising 241 200816373 ivudvj/\ υο-015TWB A substrate containing germanium carries the external receiver of the wafer. 900.  The circuit component of claim 810, further comprising a substrate containing germanium carrying the memory unit. 901.  The circuit component of claim 810, further comprising a sense amplifier positioned between the memory unit and the second metal line. 902.  The circuit component of claim 901, wherein the sense amplifier comprises a differential amplifier ° 903.  The circuit component of claim 901, further comprising an internal circuit between the sense amplifier and the first metal line. 904.  The circuit component of claim 903, wherein the internal circuit comprises a NOR gate. 905.  The circuit component of claim 903, wherein the internal circuit comprises an OR gate. 906.  The circuit component of claim 903, wherein the internal circuit comprises an AND gate. 907.  The circuit component of claim 903, wherein the internal circuit comprises a NAND gate. 908.  The circuit component of claim 903, wherein the internal circuit comprises an adder. 909.  The circuit component of claim 903, wherein the internal circuit comprises a multiplexer. 910.  The circuit component of claim 903, wherein 242 200816373 ivLtiUA υο-015TWB The internal circuit includes a duplexer. 911.  The circuit component of claim 903, wherein the internal circuit comprises a multiplier. 912.  The circuit component of claim 903, wherein the internal circuit comprises a complementary metal oxide semiconductor (CMOS). 913.  The circuit component of claim 903, wherein the internal circuit comprises a bipolar complementary metal oxide semiconductor (BiCMOS). 914.  The circuit component of claim 903, wherein the internal circuit comprises a bipolar circuit unit. 915.  The circuit component of claim 903, wherein the internal circuit includes at least an N-type MOS device (NM0S), and a channel width/channel length of the N-type MOS device Length) The ratio is between 0 and 1 to 5. 916.  The circuit component of claim 903, wherein the internal circuit includes at least an N-type MOS device (NM0S), and a channel width/channel length of the N-type MOS device Length) The ratio is between 0 and 2 to 2. 917.  The circuit component of claim 903, wherein the internal circuit includes at least a P-type MOS device, and a channel width/channel length of the P-type MOS device Length) The ratio is between 0 and 2 to 10. 918.  The circuit component of claim 903, wherein the internal circuit comprises at least a P-type MOS device (PM0S), the 243 200816373 ivjlc/VJ/\ υυ-015TWB P-type MOS device channel The channel width/channel length ratio is between 0 and 4 to 4. 919.  The circuit component of claim 901, further comprising an internal driver between the sense amplifier and the second metal line, the internal driver being composed of at least one metal oxide semiconductor component . 920.  The circuit component of claim 919, wherein the MOS device comprises a P-type MOS device (PM0S), and the P-type MOS device has a channel width/channel length ( Channel length) is between 3 and 60. 921. The circuit component of claim 919, wherein the MOS device comprises a P-type MOS device, and a channel width of the P-type MOS device/ The channel length ratio is between 5 and 20. 922.  The circuit component of claim 919, wherein the MOS device comprises an N-type MOS device, and a channel width/channel length of the N-type MOS device Channel length) ratio is between 1.  Between 5 and 30. 923.  The circuit component of claim 919, wherein the MOS device comprises an N-type MOS device, and a channel width/channel length of the N-type MOS device Channel length) ratio is between 2.  Between 5 and 10. 924.  The circuit component of claim 901, further comprising an internal buffer between the sense amplifier and the second metal line of 244 200816373 MliUA 06-015TWB. 925.  The circuit component of claim 901, further comprising an internal tri-states internal buffer between the sense amplifier and the second metal line. 926.  The circuit component of claim 901, further comprising a pass circuit between the sense amplifier and the second metal line. 927.  The circuit component of claim 901, further comprising a latch circuit positioned between the sense amplifier and the second metal line. 928.  a circuit component comprising: a transformer comprising an input node and an output node; an internal circuit; a first metal line connecting the output node of the transformer; and a second metal line connecting the internal a protective layer disposed on the transformer, the internal circuit, the first metal line and the second metal line; a third metal line connecting the first metal line and the second metal line; a metal line under the protective layer and connected to the input node of the transformer, and the fourth metal line includes at least one first metal pad exposed to one of the openings of the protective layer; a fifth metal line located at Above the protective layer, the fifth metal line includes a second metal pad electrically connected to the first gold 245 200816373 ivlc^j/\ υο-015TWB susceptor, viewed from a top perspective view The second metal pad is different in position from the first metal pad, and the second metal pad includes a thickness greater than 1. a first metal layer of 5 micrometers; and a wire positioned on the second metal pad. 929.  The circuit component of claim 928, wherein the transformer converts an input voltage into an output voltage that is different from the input voltage value. 930.  The circuit component of claim 929, wherein the difference between the input voltage of the transformer and the output voltage divided by the output voltage is greater than 10%. 931.  The circuit component of claim 929, wherein the output voltage of the transformer is between 1 volt and 10 volts. 932.  The circuit component of claim 928, wherein the internal circuit comprises a NOR gate, the anti-salt gate being formed of at least one MOS element. 933.  The circuit component of claim 928, wherein the internal circuit comprises an OR gate, the gate system being composed of at least one MOS device. 934.  The circuit component of claim 928, wherein the internal circuit comprises an AND gate, and the gate is formed of at least one gold oxide conductor component. 935.  The circuit component of claim 928, wherein the internal circuit comprises a NAND gate, the NAND gate being composed of at least one MOS device. 246 200816373 JviiiUA UO-015TWB 936.  The circuit component of claim 928, wherein the internal circuit comprises a static random access memory cell (SRAM cell) 937.  The circuit component of claim 928, wherein the internal circuit comprises a dynamic random access memory cell (DRAM cell) 938 938.  The circuit component of claim 928, wherein the internal circuit comprises a non-volatile memory unit (non-volati le memory cel 1) ° 939.  The circuit component of claim 928, wherein the internal circuit comprises a flash memory cell. 940.  The circuit component of claim 928, wherein the internal circuit comprises an erasable read only memory unit (EPROM cell). 941.  The circuit component of claim 928, wherein the internal circuit comprises a ROM cell. 942.  The circuit component of claim 928, wherein the internal circuit comprises a magnetic random access memory (MRAM) unit. 943.  The circuit component of claim 928, wherein the internal circuit comprises a sense amplifier. 944.  The circuit component of claim 928, wherein the internal circuit comprises an operational amplifier (Operational 247 200816373 ivldu/\ uo-015TWB Amplifier) ° 945.  The circuit component of claim 928, wherein the internal circuit comprises an adder. 946.  The circuit component of claim 928, wherein the internal circuit comprises a multiplexer. 947.  The circuit component of claim 928, wherein the internal circuit comprises a duplexer. 948.  The circuit component of claim 928, wherein the internal circuit comprises a multiplier. 949.  The circuit component of claim 928, wherein the internal circuit comprises an analog/digital converter (A/D converter). 950.  The circuit component of claim 928, wherein the internal circuit comprises a digital/analog converter (D/A Converter). 951.  The circuit component of claim 928, wherein the internal circuit comprises a complementary metal oxide semiconductor sensing cell unit (CMOS sensor cell) 952 952.  The circuit component of claim 928, wherein the internal circuit comprises a photo-sensitive diode. 953.  Such as the line component described in claim 928. The internal circuit includes a bipolar complementary metal oxide semiconductor (BiCMOS) 954 954.  The circuit component of claim 928, wherein the internal circuit comprises a bipalSr Circuit unit. 955.  The circuit component of claim 928, wherein: 248 200816373 ivmur/v υο-015TWB, the internal circuit includes at least an N-type MOS device, and a channel width of the N-type MOS device ( Channel width) / channel length ratio is between 〇.  Between 1 and 5. 956. The circuit component of claim 928, wherein the internal circuit comprises at least an N-type MOS device (NM0S), and the channel width/channel length of the N-type MOS device Length) The ratio is between 〇.  Between 2 and 2. 957. The circuit component of claim 928, wherein the internal circuit comprises at least a P-type MOS device, a channel width/channel length of the P-type MOS device (Channel length) ratio is between 〇.  Between 2 and 10. 958. The circuit component of claim 928, wherein the internal circuit comprises at least a P-type MOS device, a channel width/channel length of the P-type MOS device (Channel length) ratio is between 〇.  Between 4 and 4. 959.  In the circuit component of claim 928, the internal % circuit includes a power management chip, the power management chip being composed of at least one MOS element. 960.  The circuit component of claim 959, wherein the MOS device comprises a P-type MOS device (PM0S), and a width/length ratio of the P-type MOS device channel is Between 4,000 and 400,000. 961.  The circuit component of claim 959, wherein the MOS device comprises a P-type MOSFET (PM0S), 249 200816373 jVLbUA υο-015TWB, the P-type MOS device channel The width/length ratio is between 4,000 and 4,000. 962.  The circuit component of claim 959, wherein the MOS device comprises an N-type MOS device, and a width/length ratio of the N-type MOS device channel is Between 2000 and 200,000. 963.  The circuit component of claim 959, wherein the MOS device comprises an N-type MOS device, and a ratio of twist/length of the N-type MOS device channel The system is between 2,000 and 20,000. 964.  The circuit component of claim 959, wherein the current flowing through the third metal line is between 500 mA and 50 amps. 965.  The circuit component of claim 959, wherein the current flowing through the third metal line is between 500 mA and 5 amps. 966.  The circuit component of claim 928, the internal circuit comprising a power supply chip, the power supply chip being comprised of at least one MOS component. 967.  The circuit component of claim 966, wherein the MOS device comprises a P-type MOS device (PM0S), and a width/length ratio of the P-type MOS device channel is Between 4,000 and 400,000. 968.  The circuit component of claim 966, wherein: 250 200816373 ivi^vj^uu-015TWB, the MOS device comprises a P-type MOS device (PMOS), and the P-type MOS device channel ( The width/length ratio of Channe 1) is between 4,000 and 4,000. 969.  The circuit component of claim 966, wherein the MOS device comprises an N-type MOS device (NM0S), and a width/length ratio of the N-type MOS device channel is Between 2000 and 200,000. 970.  The circuit component of claim 966, wherein the MOS device comprises an N-type MOS device (NM0S), and a width/length ratio of the N-type MOS device channel is Between 2000 and 20,000. 971.  The circuit component of claim 966, wherein the third metal line has a current flux between 500 mA and 50 amps. 972.  The circuit component of claim 966, wherein the third metal line has a current flux between 500 mA and 5 amps. 973.  The circuit component of claim 928, wherein the current flowing through the third metal line is between 50 microamperes and 2 milliamperes. 974.  The circuit component of claim 928, wherein the current flowing through the third metal line is between 100 microamperes and 1 milliamperes. 975.  The circuit component of claim 928, wherein: 251 200816373 ινΐϋ〇/\ υο-015TWB the second metal line is connected to one of the internal circuits (power node) 976.  + The line component as described in claim 928. The first metal line includes a layer of thickness between GG 5 microns and 2. 977. The circuit component of claim 928, wherein the first metal line comprises a copper layer having a thickness between 5 and 2 microns. 978. The circuit component of claim 928, wherein the second metal line comprises a layer of a thickness between 5 and 2 microns. 979. The circuit component of claim 928, wherein the second metal line comprises a copper layer having a thickness between 5 and 5 microns. 980. The circuit component of claim 928: I. The fourth metal circuit comprises an I-layer having a thickness ranging from 〇·〇5 microns to ”. 981. The circuit component of claim 928, wherein the fourth metal line comprises a copper layer having a thickness between 5 and 5 microns. 982. The circuit component of claim 928, wherein the material of the third metal line comprises gold. 983. The circuit component of claim 928, wherein the material of the third metal line comprises copper. Source node, of which, among the micrometers, among the micrometers, among the micrometers, among the micrometers, among the micrometers, among them, 252 200816373 JvubUA UD-015TWB 984.  The circuit component of claim 928, wherein the material of the third metal line comprises silver. 985.  The circuit component of claim 928, wherein the material of the third metal line comprises platinum. 986.  For example, the circuit component described in claim 928, wherein the material of the third metal line comprises palladium. 987.  The circuit component of claim 928, wherein the material of the third metal line comprises nickel. 988.  The circuit component structure of claim 928, wherein the third metal circuit comprises a second metal layer and a third metal layer, the third metal layer being on the second metal layer. 989.  The circuit component structure of claim 988, wherein the third metal layer comprises a thickness of 1. A layer of gold from 5 microns to 15 microns. 990.  The circuit component structure of claim 988, wherein the third metal layer comprises a thickness of 1. A copper layer of 5 microns to 50 microns. 991.  The circuit component structure of claim 988, wherein the third metal layer comprises a thickness of 1. A silver layer of 5 microns to 15 microns. 992.  The circuit component structure of claim 988, wherein the third metal layer comprises a cobalt layer having a thickness ranging from L 5 to 15 μm. 993.  The circuit component structure as described in claim 988, 253 200816373 υυ-015TWB, wherein the second metal layer comprises a layer having a thickness of between 1.5 μm and 15 μm. 994.  The circuit component structure of claim 988, wherein the second metal layer comprises a recording layer having a thickness of between 5 micrometers and 6 micrometers. 995.  The circuit component structure of claim 988, wherein the second metal layer comprises a thickness of 0. 02 micron to 〇. One of 8 micron titanium tungsten alloy layers. &quot;6. The circuit component structure as described in claim 988, wherein the second metal layer comprises a thickness of between 0.02 micrometers and 〇. One of 8 micron titanium metal layers. &lt;7. The circuit component structure of claim 988, wherein the second metal layer comprises a thickness of 0. 02 micron to 〇 · 8 micron one titanium nitride layer. 998. The circuit component structure of claim 988, wherein the second metal layer comprises a button metal layer having a thickness ranging from 0. 02 micrometers to 〇 8 micrometers. 999. The circuit component structure of the ninth aspect, wherein the second metal layer comprises a thickness of 0. 02 micron to 〇 8 micron one nitride button layer. 1000. The circuit component structure of claim 988, wherein the second metal layer comprises a thickness of 0. 02 micron to 〇. 8 micron one chrome metal layer. VIII 1001. The circuit component structure described in claim 988, in 254 200816373 ivLtiUA uo-015TWB, the second metal layer comprises a thickness of 0. 02 microns to 0. One layer of 8 μm copper alloy layer. 1002.  The circuit component of claim 928, wherein the material of the fifth metal line comprises gold. 1003.  The circuit component of claim 928, wherein the material of the fifth metal line comprises copper. 1004.  The circuit component of claim 928, wherein the material of the fifth metal line comprises silver. 1005.  The circuit component of claim 928, wherein the material of the fifth metal line comprises platinum. 1006.  The circuit component of claim 928, wherein the material of the fifth metal line comprises palladium. 1007.  The circuit component of claim 928, wherein the material of the fifth metal line comprises nickel. 1008.  The circuit component structure of claim 928, wherein the first metal layer comprises a thickness of 1. A layer of gold from 5 microns to 15 microns. 1009.  The circuit component structure of claim 928, wherein the first metal layer comprises a thickness of 1. A copper layer of 5 microns to 50 microns. 1010.  The circuit component structure of claim 928, wherein the first metal layer comprises a thickness of 1. A silver layer of 5 microns to 15 microns. 1011.  For example, in the circuit component structure described in claim 928, in the 255 200816373 ivii2u/\ uo-015TWB, the first metal layer includes a thickness of 1. A layer of 5 microns to 15 microns. 1012.  The circuit component structure of claim 928, wherein the first metal layer comprises a thickness of 1. One I bar layer from 5 microns to 15 microns. 1013.  The circuit component structure as described in claim 928, wherein the first metal layer comprises a thickness of 0.  One of 5 microns to 6 microns of nickel. 1014.  The circuit component structure of claim 928, wherein the fifth metal line comprises a fourth metal layer under the first metal layer. 1015.  The circuit component structure of claim 1014, wherein the fourth metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one of the Qinhe alloy layers. 1016.  The circuit component structure of claim 1014, wherein the fourth metal layer comprises a thickness of 0. 02 microns to 0. One of 8 micron titanium metal layers. 1017.  The circuit component structure of claim 1014, wherein the fourth metal layer comprises a thickness of 0. 02 microns to 0. One layer of titanium nitride of 8 microns. 1018.  The circuit component structure of claim 1014, wherein the fourth metal layer comprises a thickness of 0. 02 microns to 0. One layer of 8 micron metal. 1019.  For example, in the circuit component structure described in claim 1014, the 256 200816373 ivlc,o/\ υο-015TWB, the fourth metal layer includes a thickness of 0. 02 microns to 0. One layer of 8 μm tantalum nitride layer. 1020.  The circuit component structure of claim 1014, wherein the fourth metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome metal layer. 1021.  The circuit component structure of claim 1014, wherein the fourth metal layer comprises a thickness of 0. 02 microns to 0.  8 micron one chrome-copper alloy layer. 1022.  The circuit component of claim 928, wherein the material of the protective layer comprises a nitrogen arsenide compound. 1023.  The circuit component of claim 928, wherein the material of the protective layer comprises a phosphorous glass (PSG). 1024.  The circuit component of claim 928, wherein the material of the protective layer comprises a monoxide compound. 1025.  The circuit component of claim 928, wherein the material of the protective layer comprises a oxynitride compound. % 1026. The circuit component of claim 928, wherein the material of the protective layer comprises borophosphon glass (BPSG). 1027.  A circuit component structure as described in claim 928, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the third metal line. 1028.  The circuit component structure of claim 10, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 257 200816373π --------015TWB 1029. The circuit component structure of claim 1027, wherein the first polymer layer comprises a thickness between 2 microns and 1 micron. A layer of a phenylcyclobutene compound. 1030. The circuit component structure of claim 1, wherein the first polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 1 micrometer. 1031. The circuit component structure of claim 1, wherein the first polymer layer comprises an epoxy layer having a thickness between 2 microns and 1 micron. 1032. The circuit component structure of claim 928, further comprising a second polymer layer between 2 micrometers and 1 micrometer micron in the protective layer and the fifth metal circuit between. 1033. The circuit component structure of claim 1032, wherein the polymer layer comprises a layer of a polyamidimide compound having a thickness between 2 microns and 1 Å. 1034. The circuit component structure of claim 1, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness between 2 microns and 1QQ microns. 1035. The circuit component structure of claim 32, wherein the second polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 1 micrometer. . 1036. The circuit component structure of claim 1, wherein the second polymer layer comprises an epoxy layer having a thickness between 2 microns and between microns. 258 2008163 73015 TWb 1037. The circuit component of claim 928, further comprising a third polymer layer on the third metal line and the fourth metal line, the third polymer layer comprising at least one The opening exposes the first metal joint. 1038. The circuit component structure of claim 1, wherein the third polymer layer comprises a layer of a polyamidimide compound having a thickness between 2 microns and 1 micron. 1039. The circuit component structure of claim 1037, wherein the third polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 1 micron. 1040. The circuit component structure of claim 1, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 1 micrometer. 1041. The circuit component structure of claim 1, wherein the third polymer layer comprises an epoxy layer having a thickness between 2 microns and 1 micron. 1042. The circuit component structure of claim 1, wherein the fifth metal line is on the third polymer layer. 1043. The circuit component of claim 928, further comprising a fourth polymer layer on the metal lip line and the third metal line, the fourth polymer layer including at least one opening exposed The second metal is connected. 1 〇 44. The circuit component structure of claim 1043, wherein the fourth polymer layer comprises 259 015 TWB thickness from 2 micrometers to 100 micrometers 200816373 ATJLJUWJX A.  A layer of a polyamidimide compound between V/V/. 1045.  The circuit component structure of claim 1043, wherein the fourth polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 1046.  The circuit component structure of claim 1043, wherein the fourth polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 100 micrometers. 1047.  The circuit component structure of claim 1043, wherein the fourth polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 1048.  The circuit component of claim 928, further comprising a substrate containing germanium carrying the transformer. 1049.  The circuit component of claim 928, further comprising a substrate containing germanium carrying the internal circuit. 1050.  The circuit component of claim 928, wherein the transformer includes a step-down transformer. 1051.  The circuit component of claim 928, wherein the transformer includes a booster transformer. 1052.  The circuit component of claim 928, wherein the internal circuit comprises a complementary metal oxide semiconductor (CMOS). 1053.  A circuit component comprising: an electrostatic discharge (ESD) component comprising: a power node and a ground node; an internal circuit comprising a power supply node (power 260 2008163 73015TWB Node) and a ground node; a first metal line connecting a power node of the internal circuit; a first metal line 'connecting a ground node of the internal circuit; a compliant layer' at the electrostatic discharge element, the internal circuit, the first metal line, and a second metal line; a second metal line is disposed under the protective layer to connect the power supply node of the electrostatic discharge element, and the third metal line includes at least one first metal pad exposed to the protective layer a second metal line is disposed under the protective layer to connect the ground node of the electrostatic discharge element, and the fourth metal line includes at least one second metal pad exposed to the second opening of the protective layer a fifth metal line is located above the protective layer, and the fifth metal line includes a third metal pad electrically connected to the first metal pad, viewed from a top perspective view The third metal pad is located differently than the first metal joint, and the third full joint includes a thickness greater than one.  a first metal layer of 5 micrometers; a sixth metal circuit positioned above the protective layer, and the sixth metal circuit includes a fourth metal pad electrically connected to the first metal connection The pad, the fourth metal pad is viewed from a top perspective view different from the first metal pad position. The fourth metal pad includes a thickness greater than 1. A second metal layer of 5 microns; a first wire positioned on the third metal pad and a second wire positioned on the fourth metal pad. 1054. The circuit component of claim 1, wherein 261 200816373 1,315 TWB the first metal line comprises a layer of between 0.45 μm and 2 μm in thickness. 1055. The circuit component of claim 1, wherein the first metal line comprises a copper layer having a thickness between 〇·05 μm and 2 μm. 1056. The circuit component of claim 1, wherein the second metal line comprises a thickness system of 0. A layer of between 05 microns and 2 microns. 1057. The circuit component of claim 1, wherein the second metal line comprises a thickness system. ~ 5 to 2 microns between the ~ copper layer. 1058. The circuit component of claim 1, wherein the third metal line comprises a thickness system. An aluminum layer between 5 microns and 2 microns. 1059. The circuit component of claim 1, wherein the third metal line comprises a steel layer having a thickness between 5 microns and 2 microns. 1060. The circuit component of claim 1, wherein the fourth metal line comprises a layer of a thickness between 5 microns and 2 microns. 1061. The circuit component of claim 1, wherein the fourth metal line comprises a thickness system.  A copper layer between 5 microns and 2 microns. 1062. The circuit component of claim 1, wherein 262 015 TWB 200816373 of the fifth metal line comprises gold. 1063.  The circuit component of claim 1053, wherein the material of the fifth metal line comprises copper. 1064.  The circuit component of claim 1053, wherein the material of the fifth metal line comprises silver. 1065.  The circuit component of claim 1053, wherein the material of the fifth metal line comprises platinum. 1066.  The circuit component of claim 1053, wherein the material of the fifth metal line comprises palladium. 1067.  The circuit component of claim 1053, wherein the material of the fifth metal line comprises nickel. 1068.  The circuit component of claim 1053, wherein the material of the sixth metal circuit comprises gold. 1069.  The circuit component of claim 1053, wherein the material of the sixth metal circuit comprises copper. 1070.  The circuit component of claim 1053, wherein the material of the sixth metal circuit comprises silver. 1071.  The circuit component of claim 1053, wherein the material of the sixth metal circuit comprises platinum. 1072.  The circuit component of claim 1053, wherein the material of the sixth metal circuit comprises palladium. 1073.  The circuit component of claim 1053, wherein the material of the sixth metal circuit comprises nickel. 1074.  In the line component structure described in claim 1053, in the 263 015 TWB 200816373, the first metal layer comprises a gold layer having a thickness of between 1.5 μm and 15 μm. 1075. The circuit component structure of claim 1, wherein the first metal layer comprises a thickness of 1. A copper layer of 5 microns to 5 microns. 1076. The circuit component structure of claim 501, wherein the first metal layer comprises a silver layer having a thickness of between 1.5 and 15 microns. 1077. The circuit component structure of claim 1, wherein the first metal layer comprises a uranium layer having a thickness of between 1.5 and 15 microns. 1078. The circuit component structure of claim 1, wherein the first metal layer comprises a layer having a thickness between 1.5 and 15 microns. 1. The circuit component structure as described in claim 1053, wherein the first metal layer comprises a thickness of 0. 5 micron to 6 micron recording layer. 1080. The circuit component structure of claim 1053, wherein the second metal layer comprises a thickness of 1. A layer of gold from 5 microns to microns. The structure of the circuit component as described in claim 1053, wherein the second metal layer comprises a thickness of 1. A steel layer of 5 microns to 5 microns. 〆, 10 8 2 · In the case of the line component structure described in Item No. 53 of the lord*^ γ 甲 甲, 264 200816373 丄VfV/ 015TWB, the second metal layer includes a thickness of 1 • One silver layer from 5 microns to i5 microns. 1083. The circuit component structure of claim 1, wherein the second metal layer comprises a layer of a thickness ranging from 1.5 micrometers to is micrometers. 1084. The circuit component structure of claim 1, wherein the second metal layer comprises a thickness of 1. A saturated layer of 5 microns to 15 microns. 1085. The circuit component structure of claim 1, wherein the second metal layer comprises a nickel layer having a thickness of between 5 micrometers and 6 micrometers. 1086. The circuit component of claim 1, wherein the fifth metal line comprises a thickness of between 0. 02 micrometers and 〇. One of the 8 micrometer titanium tungsten alloy layers is under the first metal layer. 1087. The circuit component of claim 501, wherein the fifth metal line comprises a titanium metal layer having a thickness between 〇·〇2 μm and 〇·8 μm in the first metal layer under. 1088. The circuit component of claim 1, wherein the fifth metal line comprises a titanium nitride layer having a thickness between 〇·〇2 μm and 〇·8 μm in the first metal Under the layer. 1089. The circuit component of claim 1, wherein the fifth metal line comprises a metal layer having a thickness between 〇·02 μm and 〇·8 μm under the first metal layer . 1090. The circuit component of claim 1, wherein: 265 200816373· ________015TWB the fifth metal line comprises a nitride button layer having a thickness ranging from 〇·02 μm to 0.8 μm. Under the first metal layer. 1091. The circuit component of claim 1, wherein the fifth metal circuit comprises a thickness of between 微米·〇2 micrometers to 0.  A layer of 8 micron metal is below the first metal layer. 1092. The circuit component of claim 1, wherein the fifth metal line comprises a thickness ranging from 〇·02 micron to 0. A layer of 8 micron chrome copper alloy is under the first metal layer. 1093. The circuit component of claim 1053, wherein the sixth metal circuit comprises a titanium-tungsten alloy layer having a thickness between 〇·〇2 μm and 0.8 μm under the first metal layer . 1094. The circuit component of claim 1053, wherein the sixth metal line comprises a thickness of 0. 02 microns to 0. A layer of titanium metal of 8 microns is below the first metal layer. 1095. The circuit component of claim 1053, wherein the sixth metal circuit comprises a titanium nitride layer having a thickness between 〇·〇2 micrometers and 0.8 micrometers under the first metal layer . The circuit component of claim 1053, wherein the sixth metal line comprises a metal layer having a thickness between 〇·02 μm and 0.8 μm below the first metal layer. 1097. The circuit component of claim 1053, wherein the sixth metal line comprises a thickness of 0. A nitride button layer of 02 micrometers to 0.8 micrometers is located under the first metal layer. 1098· The line clock according to item 1053 of the patent application scope, wherein 266 015TWB 200816373 Α. Ύ JLA-J i \y vy The sixth metal line includes a thickness of 0. 02 microns to 0. A layer of chrome metal of 8 microns is located beneath the first metal layer. 1099.  The circuit component of claim 1053, wherein the sixth metal line comprises a thickness of 0.  02 microns to 0. A layer of 8 micron chrome copper alloy is under the first metal layer. 1100.  The circuit component according to claim 1053, wherein the material of the protective layer comprises a nitrogen hydrazine compound. 1101.  The circuit component according to claim 1053, wherein the material of the protective layer comprises a phosphorous glass (PSG). 1102.  The circuit component according to claim 1053, wherein the material of the protective layer comprises a monoxide compound. 1103.  The circuit component of claim 1053, wherein the material of the protective layer comprises a oxynitride compound. 1104.  The circuit component according to claim 1053, wherein the material of the protective layer comprises a boron stellite glass (BPSG). 1105.  A circuit component structure as described in claim 1053, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the fifth metal line. 1106.  The circuit component structure according to claim 1105, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 μm and 100 μm. 1107.  The circuit component structure of claim 1, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 267 315TWB 200816373 1108. The circuit component structure of claim 11, wherein the first polymer layer comprises a parylene having a thickness of between 2 micrometers and 2 micrometers. Molecular layer 9 1109. The circuit element structure of claim 11, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 micrometers and 1 micrometer. 1110. The circuit component structure of claim 1, wherein a first polymer layer having a thickness between 2 microns and 100 microns is between the protective layer and the sixth metal line. . A circuit element structure as described in claim 1110, wherein the polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 μm and 1 μm. 1112. The circuit component structure of claim 11, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 1 micron. 1113. The circuit component structure of claim 11, wherein the polymer layer comprises a poly(p-phenylene terbene) polymer layer having a thickness of between 2 micrometers and 1 micrometer. 1114. The circuit component structure of claim 4, wherein the first polymer layer comprises an epoxy layer having a thickness between 2 microns and 1 micron. 1115. The circuit component of claim 1, wherein the internal circuit comprises a NOR giate (1116), wherein the circuit component of claim 1053, wherein 2〇〇816373015TWB This internal circuit includes an OR gate.  The circuit component of claim 1053, wherein the internal circuit comprises an AND gate. 1118.  The circuit component of claim 1053, wherein the internal circuit comprises a NAND gate. 1119.  The circuit component of claim 1053, wherein the internal circuit comprises a static random access memory cell (SRAM cell) ° 1120.  The circuit component of claim 1053, wherein the internal circuit comprises a dynamic random access memory cell (DRAM cell).  The circuit component of claim 1053, wherein the internal circuit comprises a non-volatile memory unit (non-volati le memory cel 1) ° 1122.  The circuit component of claim 1053, wherein the internal circuit comprises a flash memory unit (flash memory cel 1) ° 1123.  The circuit component of claim 1053, wherein the internal circuit comprises an erasable programmable read only memory unit (EPROM cell). 1124.  The circuit component of claim 1053, wherein the internal circuit comprises a ROM cell. 1125.  The circuit component according to claim 1053, wherein the internal circuit comprises a magnetic random access memory (itiagnetic 269 015TWB 200816373 丄i v/vy RAM, MRAM) unit. 1126.  The circuit component of claim 1053, wherein the internal circuit comprises a sense amplifier. 1127.  The circuit component of claim 1053, wherein the internal circuit comprises an operational amplifier (Operational Amplifier). 1128.  The circuit component of claim 1053, wherein the internal circuit includes an adder. 1129.  The circuit component of claim 1053, wherein the internal circuit comprises a multiplexer. 1130.  The circuit component of claim 1053, wherein the internal circuit comprises a duplexer. 1131.  The circuit component of claim 1053, wherein the internal circuit comprises a multiplier. 1132.  The circuit component of claim 1053, wherein the internal circuit comprises an analog/digital converter (A/D converter). 1133.  The circuit component of claim 1053, wherein the internal circuit comprises a digital/analog converter (D/A Converter). 1134.  The circuit component of claim 1053, wherein the internal circuit comprises a complementary metal oxide semiconductor (CMOS). 1135.  The circuit component of claim 1053, wherein the internal circuit comprises a photo-sensitive diode. 1136.  The circuit component of claim 1053, wherein the internal circuit comprises a dual carrier complementary MOS 270 2008163 730l5TWB (BiCMOS). 1137.  The circuit component of claim 1053, wherein the internal circuit comprises a bipolar circuit unit. 1138.  The circuit component of claim 1053, wherein the internal circuit includes at least an N-type MOS device (NM0S), and a channel width/channel length of the N-type MOS device Length) The ratio is between 0.  Between 1 and 5. 1139.  The circuit component of claim 1053, wherein the internal circuit includes at least an N-type MOS device (NM0S), and a channel width/channel length of the N-type MOS device Length) The ratio is between 0 and 2 to 2. 1140.  The circuit component according to claim 1053, wherein the internal circuit includes at least a P-type MOS device, and a channel width/channel length of the P-type MOS device Length) The ratio is between 0 and 2 to 10. 1141.  The circuit component according to claim 1053, wherein the internal circuit includes at least a P-type MOS device, and a channel width/channel length of the P-type MOS device The length) ratio is between 0.4 and 4. 1142.  The circuit component of claim 1053, wherein the current flowing through the fifth metal line is between 50 microamperes and 2 milliamperes. 1143.  The circuit component of claim 1053, wherein the current flowing through the fifth metal line is between 100 microamperes and 1 milliamperes. 271 015 TWB 200816373 ▲ ▼-auwx-#x a.  Between vf v culture. 1144. The circuit component of claim 1053, wherein the current flowing through the sixth metal line is between 50 microamperes and 2 milliamperes. 1145. The line component of claim 1, wherein the current flowing through the sixth metal line is between 1 〇〇 microamperes and 1 milliamperes. 1146. The circuit component of claim 501, further comprising a second polymer layer on the fifth metal line and the sixth metal line. 1147. The circuit component structure as described in the claims η &quot; wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 micrometers and loo micrometers. 1148. The circuit component structure of claim 1, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness between 2 microns and 1 micron. 1149. The circuit component structure of claim 1, wherein the second polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 1 micrometer. 1150. The circuit component structure of claim 1146, wherein the second polymer layer comprises an epoxy layer having a thickness between 2 microns and loo microns. 1151. The circuit component according to claim 1053, further comprising a d-three polymer layer covering all of the upper surfaces of the first jade wire and the sixth metal 272 015TWB 200816373 circuit. 1152.  The circuit component structure of claim 1151, wherein the third polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 1153.  The circuit component structure of claim 1151, wherein the third polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 1154.  The circuit component structure of claim 1, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 1155.  The circuit component structure of claim 1 151, wherein the third polymer layer comprises an epoxy layer having a thickness between 2 microns and 100 microns. 1156.  The circuit component of claim 1053, wherein the electrostatic discharge component comprises a reverse-biased diode (1157).  The circuit component according to claim 1053, further comprising a substrate containing the stone to carry the electrostatic discharge element. 1158.  A circuit component as described in claim 1053, further comprising a substrate containing germanium carrying the internal circuit. 1159.  A circuit component comprising: an analog circuit comprising at least one output node ' ^ ': : :· : - ;: ' i; VX , ;; : ; a ratio/digital converter ( In /DC on verier, the system includes at least one 273 015 TWB 200816373 input node and an output node; a first metal line connecting the output node of the analog circuit; and a second metal line connecting the analog/digital converter The input node; a protection layer located on the analog circuit, the analog/digital converter, the first metal line and the second metal line; a third metal line located on the protective layer and connected The first metal line and the second metal line; a fourth metal line under the protective layer and connected to the output node of the analog/digital converter, and the fourth metal line includes at least one first metal connection The pad is exposed in one of the openings of the protective layer; a fifth metal line is located above the protective layer and the fifth metal line includes a second metal pad, the second metal pad electrically connecting the first A metal pad, a top perspective view of the concept of a second metal different from the first contact position Sook metal pad position, pad confusion second metal includes a thickness of greater than 1. a first metal layer of 5 micrometers; and a wire positioned on the second metal pad. 1160.  The circuit component as claimed in claim 1159, wherein the signal input by the analog circuit comprises a digital analog analog signal. 1161.  A circuit component as claimed in claim 1159, wherein the analog circuit comprises a NOR gate. 1162. The circuit component of claim 1, wherein the analog circuit comprises an OR gate. 1163. The circuit component of claim 1, wherein the analog circuit comprises an AND gate. 1164.  The circuit component of claim 1, wherein the analog circuit comprises a NAND gate. 1165.  A circuit component as claimed in claim 1159, wherein the analog circuit comprises a sense amplifier. 1166.  The circuit component as claimed in claim 1159, wherein the analog circuit comprises an operational amplifier (Operational Amplifier) 〇 1167.  A circuit component as claimed in claim 1159, wherein the analog circuit comprises an adder. 1168.  The circuit component of claim 1, wherein the analog circuit comprises a multiplexer. 1169.  The circuit component of claim 1, wherein the analog circuit comprises a duplexer. 1170.  A circuit component as claimed in claim 1159, wherein the analog circuit comprises a multiplier (Mu 11 i p 1 i er ). 1171.  The circuit component of claim 1, wherein the analog circuit comprises a complementary metal oxide semiconductor (CMOS). 1172.  The circuit component of claim 1, wherein the analog circuit comprises a photo-sensitive diode. 1173.  The circuit component of claim 1, wherein the analog circuit comprises a bipolar complementary metal oxide semiconductor (BiCMOS) 〇 1174.  For example, the circuit component described in claim 1159, wherein 275 200816373 *.  v/vr 015TWB This analog circuit includes a bipolar circuit unit. 1175. The circuit component of claim 1, wherein the analog circuit comprises a pulse reshaping circuit (1176), wherein the circuit component of claim 1159, wherein The analog circuit includes a switched-capacitor filter. 1177. The circuit component of claim 1, wherein the analog circuit comprises a resistor-capacitor filter (RC fiiter). 1178. The circuit component of claim 1, wherein the analog circuit comprises a P-type metal oxide semiconductor (PM〇s). 1179. The circuit component of claim 1, wherein the analog circuit comprises an N-type metal oxide semiconductor (NMOS). 1180. The circuit component of claim 1, wherein the first metal line comprises a thickness system. A layer of between 05 microns and 2 microns. 1181. The circuit component according to claim 1159, wherein the first metal line comprises a thickness system. A copper layer between 05 microns and 2 microns. 1182. The circuit component of claim 1, wherein the second metal line comprises a layer of between 〇·〇5 mm to 2 μm. 1183. The circuit component of claim 1, wherein the metal circuit comprises a copper layer having a thickness between 276 and 2008 16373015 twb of 5 μm to 2 μm. 1184. The circuit component of claim U59, wherein the fourth metal line comprises a layer having a thickness between 〇·05 μm and 2 μm. 1135. The circuit component of claim 1, wherein the fourth metal line comprises a copper layer having a thickness between 微米·05 μm and 2 μm. 1186. The circuit component of claim 1, wherein the material of the third metal line comprises gold. 1187. The circuit component of claim 1, wherein the material of the third metal line comprises copper. 1188. The circuit component of claim 1, wherein the material of the third metal line comprises silver. 1189. The circuit component of claim 1, wherein the material of the third metal line comprises platinum. 1190. The circuit component of claim 1, wherein the material of the third metal line comprises palladium. 1191. The circuit component of claim U59, wherein the material of the third metal line comprises nickel. 1192. The circuit component structure of claim 1, wherein the second metal line comprises a second metal layer and a third metal layer. The third metal layer is on the second metal layer. 1193. For example, in the circuit component structure described in the patent application, the third metal layer has a thickness of 277 200816373 &quot; Hawthorn i5TWB gold layer of L 5 micrometers to 15 micrometers. call. The circuit component structure as described in claim 1192, wherein the third metal layer comprises a thickness of 1. A copper layer of 5 micrometers to 5 micrometers. &lt;&lt;&gt;&gt; 1195. The circuit component structure of claim 1, wherein the third metal layer comprises a silver layer having a thickness of from 5 micrometers to 15 micrometers. U96. The circuit component structure of claim 1, wherein the second metal layer comprises a uranium layer having a thickness of between 1.5 and 15 microns. The circuit component structure as described in claim 1192, wherein the third metal layer comprises a thickness of 1. A sharp layer from 5 microns to 15 microns. The circuit component structure as described in claim 1192, wherein the third metal layer comprises a nickel layer having a thickness of between 5 μm and 6 μm. 9. The circuit component structure of claim 1692, wherein the second metal layer comprises a titanium tungsten alloy layer having a thickness ranging from 2 micrometers to 8 micrometers. 200. The circuit component structure of claim 1 , wherein the second metal layer comprises a titanium metal layer having a thickness between 2 μm and 〇 8 μm.丨·As claimed in claim 92, the second metal layer comprises a thickness ranging from 〇·02 μm to 0.  8 microns 278 200816373msT 015TWB One of the titanium nitride layers. 1202. The circuit component structure as described in the ninth application of the patent application, wherein the second metal layer comprises a ruthenium metal layer having a thickness ranging from 微米·〇2 μm to 〇·8 μm. 1203. The circuit component structure of claim 1, wherein the second metal layer comprises a thickness of 0. 02 micron to 〇 · 8 micron one nitride button layer. 1204. The circuit component structure of claim 1, wherein the second metal layer comprises a chrome metal layer having a thickness ranging from 2 micrometers to 8 micrometers. 1205. The circuit component structure of claim 1, wherein the second metal layer comprises a copper alloy layer having a thickness ranging from 微米2 to 〇8 μm. 1206·If the patent application scope The circuit component structure of the first aspect, wherein the first metal layer comprises a thickness of 1. A layer of gold from 5 microns to 15 microns. ^ 1207. The circuit component structure as described in claim 5, wherein the first metal layer comprises a thickness of 1. A copper layer of 5 microns to 5 microns. </ RTI> 1208. The circuit component structure as described in claim 5 (5), wherein the first metal layer comprises a thickness of 1. A silver layer of 5 microns to π microns. 1209. The circuit component structure of claim 1, wherein the first metal layer comprises a uranium layer having a thickness of between 丨 5 micrometers and 15 micrometers 279 200816373olST -------- 015TWB. 1210. The circuit component structure of claim 1, wherein the first metal layer comprises a thickness of 1. A saturated layer of 5 microns to ι 5 microns. 1211. The circuit component structure of claim 1, wherein the first metal layer comprises a recording layer having a thickness of between 5 micrometers and 6 micrometers. 1212. The circuit component structure of claim 1, wherein the fifth metal line comprises a fourth metal layer under the first metal layer. 1213. The circuit component structure of claim 1, wherein the fourth metal layer comprises a titanium tungsten alloy layer having a thickness ranging from 2 micrometers to 2 nanometers. 1214. The circuit component structure as described in claim 119, wherein the fourth metal layer comprises a thickness of between 2 μm and 〇. One layer of 8 micron metal. 1215. The circuit component structure of claim 1212, wherein the fourth metal layer comprises a thickness of between 〇.  〇 2 microns to 〇.  One layer of titanium nitride of 8 microns. 1216. The circuit component structure of claim 1, wherein the fourth metal layer comprises a thickness of between 〇. 〇 2 microns to 〇 · 8 microns One button metal layer. 1217. The circuit component structure of claim 1212, wherein the fourth metal layer comprises a thickness of between 〇. 〇 2 microns to 0. 8 micron 280 2008163 73015TWB One layer of tantalum nitride. 1218.  The circuit component structure of claim 1212, wherein the fourth metal layer comprises a thickness of 0.  02 microns to 0. One layer of 8 micron metal. 1219.  The circuit component structure of claim 1212, wherein the fourth metal layer comprises a thickness of 0. 02 microns to 0. 8 micron one chrome-copper alloy layer. 1220.  The circuit component according to claim 1159, wherein the material of the protective layer comprises a nitrogen hydrazine compound. 1221.  The circuit component of claim 1, wherein the material of the protective layer comprises a phosphorous glass (PSG). 1222.  The circuit component according to claim 1159, wherein the material of the protective layer comprises a oxime compound. 1223.  The circuit component according to claim 1159, wherein the material of the protective layer comprises a oxynitride compound. 1224.  The circuit component according to claim 1159, wherein the material of the protective layer comprises borophosphorus bismuth glass (BPSG). 1225.  A circuit component structure as described in claim 1159, further comprising a first polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the third metal line. 1226.  The circuit component structure of claim 12, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. Γ227. The first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 micrometers and 100 micrometers, as in the circuit element structure of claim 1225, in the 281, 2008, 163, 730, TWB. 1228.  The circuit component structure of claim 12, wherein the first polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 1229.  The circuit component structure of claim 12, wherein the first polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 1230.  A circuit component structure as described in claim 1159, further comprising a second polymer layer having a thickness between 2 microns and 100 microns between the protective layer and the fifth metal line. 1231.  The circuit component structure of claim 12, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 microns and 100 microns. 1232.  The circuit component structure of claim 12, wherein the second polymer layer comprises a layer of a phenylcyclobutadiene compound having a thickness of between 2 microns and 100 microns. 1233.  The circuit component structure of claim 12, wherein the second polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 1234.  The circuit component structure of claim 12, wherein the second polymer layer comprises an epoxy layer having a thickness of between 2 microns and 100 microns. 1235.  For example, the circuit component described in the scope of claim 1, item 1159: further includes 282 200816373, 15TWB. A substrate containing germanium carries the analog circuit. 1236.  The circuit component as described in claim 1159, further comprising a substrate containing germanium carrying the analog/digital converter. 1237.  a circuit component comprising: a semiconductor substrate; a thin circuit structure 'located on the semiconductor substrate, an electrical fuse located in the thin circuit structure, the electronic fuse including a first end point and a a second end point, wherein the first end point and the second end point of the electronic fuse are respectively connected to one of the first contact point and the second contact point of the thin line structure; a protective layer located in the thin line structure And at least one metal circuit layer on the protective layer, the gold circuit layer electrically connected to the fine circuit structure. 1238.  The circuit component of claim 1237, further comprising a laser fuse, the laser fuse comprising a first end point and a second end point, the first end of the laser fuse The point and the second end point are respectively connected to one of the third contact point and the fourth contact point of the fine line structure. 1239.  The circuit component of claim 12, wherein the protective layer further comprises an opening on the laser fuse. 1240.  The circuit component of claim 12, wherein the silicon oxide layer is disposed on the laser safety edge, and the yttrium oxide layer is exposed to the opening of the protective layer. Inside. 1241.  The circuit component of claim 12, wherein the 283 200816373 - the laser fuse is blown by a laser such that the first end and the second end of the laser fuse form an open circuit. 1242.  The circuit component of claim 12, wherein the laser fuse comprises aluminum. 1243.  The circuit component of claim 12, wherein the laser fuse comprises copper. 1244.  The circuit component of claim 12, wherein the laser fuse comprises a polysilicon layer. 1245.  The circuit component of claim 1237, wherein the electronic fuse comprises a polycrystalline layer and a metal silicide layer, the metal deuteration layer being on the polysilicon layer. 1246.  The circuit component of claim 1245, wherein the electronic fuse is blown by a current, and the electronic fuse is blown to form a gap in the metal deuteration layer, so that the electronic fuse has the first end point and the Current between the second terminals is transmitted through the polysilicon layer, and the metal deuteration layer forms an open circuit. 1247.  The circuit component of claim 1245, wherein the metal deuteration layer has a thickness of between 200 and 2,000 angstroms. 1248.  The circuit component of claim 12, wherein the polycrystalline germanium layer has a thickness between 1000 and 3,000 angstroms. 1249.  The circuit component of claim 1245, wherein the metal deuteration layer comprises titanium. 1250.  The circuit component of claim 1245, wherein the metal slab layer comprises an initial. 284 200816—373 015TWB 1251.  The circuit component of claim 1245, wherein the metal deuteration layer comprises nickel. 1252.  The circuit component of claim 1245, wherein the metal secondary layer comprises a crane. 1253.  The circuit component of claim 1237, wherein the electronic fuse has a sheet resistance between 1 ohm and 15 ohms when not blown. 1254.  The circuit component of claim 1237, wherein when the electronic fuse is blown, the sheet resistance of the electronic fuse is between 100 ohms and 10,000 ohms. 1255.  A circuit component as described in claim 1237 is a dynamic random access memory (DRAM) wafer. 1256.  A line component as described in claim 1237 is a flash memory chip. 1257.  A circuit component as described in claim 1237 is a logic chip. 1258.  A circuit component as described in claim 1237 is a memory chip. 1259.  The circuit component of claim 1237, further comprising an insulating layer on the electronic fuse, the dielectric constant of the insulating layer being less than 3 〇 1260.  The circuit component of claim 1237, further comprising an insulating layer under the electronic fuse, the insulating layer having a dielectric constant of less than 3. 285 015TWB 200816373 1261.  The circuit component of claim 1260, wherein the insulating layer comprises an oxidized chopping compound. 1262.  The circuit component structure as described in claim 1237, wherein the thin circuit structure has a thickness of 0. a plurality of fine-line dielectric layers, a plurality of conductive plugs, and a plurality of fine-line metal layers of 05 micrometers to 2 micrometers, wherein the thin-line dielectric layers are on the semiconductor substrate, and the thin-line metal layers are located in the thin wiring layers The one of the electrical circuit layers is electrically connected to each other by the conductive plugs. 1263.  The circuit component structure as described in claim 1262, wherein the dielectric constant values of the thin circuit dielectric layers are between 1.  5 to 3.  5. 1264.  The circuit component of claim 1262, wherein the thin circuit metal layer comprises a thickness system of 0.  An I-lu layer between 05 microns and 2 microns. 1265.  The circuit component of claim 1262, wherein the thin circuit metal layer comprises a thickness system of 0.  A copper layer between 05 microns and 2 microns. 1266.  The circuit component structure of claim 1262, wherein the thin circuit metal layer comprises the first contact and the second contact, and the first end and the second end of the electronic fuse respectively Connecting the first contact and the second contact. 1267.  The circuit component structure of claim 1237, wherein the metal circuit layer comprises a thickness of between 1 β 5 μm and 15 μm: a gold layer 1268.  For example, in the circuit component structure described in claim 1237, in the 200816373-015TWB, the metal circuit layer includes a thickness of 1.  A copper layer of 5 microns to 50 microns. 1269.  The circuit component structure as described in claim 1237, wherein the metal circuit layer comprises a thickness of 1.  A silver layer of 5 microns to 15 microns. 1270.  The circuit component structure as described in claim 1237, wherein the metal circuit layer comprises a thickness of 0.  One of 5 microns to 6 microns of nickel. 1271.  The circuit component structure as described in claim 1237, wherein the metal circuit layer comprises a thickness of 1. One I bar layer from 5 microns to 15 microns. 1272. The circuit component structure of claim 1237, wherein the metal circuit layer comprises a thickness of 1. A layer of uranium from 5 microns to 15 microns. 1273.  For example, the circuit component structure described in claim 1237 includes a thickness of 0. 02 microns to 0. One of the 8 micron titanium layers &quot; under the metal circuit layer. 1274.  For example, the circuit component structure described in claim 1237 includes a thickness of 0. 02 microns to 0. One of the 8 micron titanium tungsten alloy layers is under the metal circuit layer. 1275.  For example, the paint path component structure described in claim 1237 includes a thickness of 0.  02 microns to 0.  One of the 8 micron titanium nitride layers is under the metal wiring layer. 1276.  For example, the line element selection structure described in claim 1237, 287 2008163 73. In 015TWB, it also includes a thickness of 0.  02 microns to 0.  One of the 8 micron base metal layers is below the metal circuit layer. 1277.  For example, the circuit component structure described in claim 1237 includes a thickness of 0.  02 microns to 0.  One of the 8 micron layers of tantalum nitride is under the metal circuit layer. 1278.  For example, the circuit component structure described in claim 1237 includes a thickness of 0. 02 microns to 0. One of the 8 micron chrome metal layers is below the metal circuit layer. 1279.  For example, the circuit component structure described in claim 1237 includes a thickness of 0. 02 microns to 0. One of the 8 micron chrome-copper alloy layers is under the metal circuit layer. 1280.  The circuit component structure as described in claim 1237, wherein the material of the protective layer comprises a nitrile compound. 1281.  The circuit component structure as described in claim 1237, wherein the material of the protective layer comprises a phosphorous bismuth glass (PSG). 1282.  The circuit component structure as described in claim 1237, wherein the material of the protective layer comprises a oxime compound. 1283.  The circuit component structure according to claim 1237, wherein the material of the protective layer comprises a oxynitride compound. 1284.  The circuit component structure of claim 1237, wherein the semiconductor substrate is provided with a plurality of internal circuits electrically connected to the thin circuit structure. 1285.  A circuit component as claimed in claim 1284, wherein the internal circuit comprises a NOR gate. 288 015TWB 200816373 丄1· V/V/ 1286.  A circuit component as claimed in claim 1284, wherein the internal circuit comprises an OR gate. 1287.  A circuit component as claimed in claim 1284, wherein the internal circuit comprises an AND gate. 1288.  The circuit component of claim 1284, wherein the internal circuit comprises a NAND gate. 1289.  The circuit component of claim 1284, wherein the internal circuit comprises a dynamic random access memory cell (DRAM cell) 〇 1290.  The circuit component of claim 1284, wherein the internal circuit comprises a flash memory cell. 1291.  The circuit component of claim 1284, wherein the internal circuit comprises an erasable read only memory cell (EPROM cell). 1292.  A circuit component as claimed in claim 1284, wherein the internal circuit comprises a read only memory unit (ROM ce 11). 1293.  The circuit component of claim 1284, wherein the internal circuit comprises a magnetic random access memory (MRAM) unit. 1294.  The circuit component of claim 1284, wherein the internal circuit comprises a sense amplifier (sense ampl if ier). 1295.  The circuit component of claim 1284, wherein the internal circuit comprises an operational amplifier (Operational 2008163 73. 015TWB Amplifier). 1296.  A circuit component as claimed in claim 1284, wherein the internal circuit comprises an adder. 1297.  A circuit component as claimed in claim 1284, wherein the internal circuit comprises a multiplexer. 1298.  The circuit component of claim 1284, wherein the internal circuit comprises a duplexer. 1299.  A circuit component as claimed in claim 1284, wherein the internal circuit comprises a multiplier. 1300.  The circuit component of claim 1284, wherein the internal circuit comprises an analog/digital converter (A/D converter). 1301.  The circuit component of claim 1284, wherein the internal circuit comprises a digital/analog converter (D/A Converter). 1302.  The circuit component of claim 1284, wherein the internal circuit comprises a complementary metal oxide semiconductor (CMOS). 1303.  The circuit component of claim 1284, wherein the internal circuit comprises a photo-sensitive diode. 1304.  The circuit component of claim 1284, wherein the internal circuit comprises a bipolar complementary metal oxide semiconductor (BiCMOS) 〇 1305.  The circuit component of claim 1284, wherein the internal circuit comprises a bi-sub-circuit (b i ρο 1 ar c i rcu i t) unit. , ^306. The circuit component of claim 1284, wherein the internal circuit includes at least an N-type MOS device (NM0S), and the channel width of the 290 20 08 1 63 73015 TWB N-type MOS device (Channel width) ) / Channel length ratio is between 0·1 and 5 fa]. 1307.  a circuit component as claimed in claim 1284, wherein the internal circuit includes at least &lt; N-type MOS device (NM0S), the channel width/channel length ratio of the N-type MOS device is between 〇_2 and 2. 1308. The circuit component of claim 1284, wherein 'the internal circuit includes at least one P-type MOS device (PM0S), and the channel width/channel length of the P-type MOS device The (Channel length) ratio is between 0 and 2 to 10. 1309. The circuit component of claim 1284, wherein the internal circuit includes at least a P-type MOS device, and a channel width/channel length of the P-type MOS device The (Channel length) ratio is between 0.4 and 4. 1310. The circuit component according to claim 1237, further comprising an off-chip circuit, wherein the external circuit is composed of at least one MOS component, and is electrically connected. To the fine line structure. 1311. The circuit component of claim 1310, wherein the MOS device comprises a P-type MOS device (PM0S), and a channel width/channel of the P-type MOS device The length of the channel length is between 40 and 40 and 0〇0. 1312: The circuit element according to claim 1310, wherein the MOS device comprises a P-type MOS device "PM0S", 291 2008163 73.015TWB, the channel width of the P-type MOS device ( The Channel width)/Channel length ratio is between 60 and 600. 1313. The circuit component of claim 1310, wherein the MOS device comprises an N-type MOS device, and a channel width/channel of the N-type MOS device The length of the channel length is between 20 and 20,000. 1314. The circuit component of claim 1310, wherein the MOS device comprises an N-type MOS device, and a channel width/channel of the N-type MOS device The channel length ratio is between 30 and 300. 1315. The circuit component of claim 1310, wherein the external circuit of the wafer is an f-chip driver (1316). The circuit of claim 1310 An element, wherein the external circuit of the chip is a f-chip reciver. The circuit component of claim 1310, wherein the external circuit of the chip is A f-chip buffer of the type 1310. The circuit component of claim 1310, wherein the external circuit of the chip is a chip-terminated external tri-state buffer (of f- Chip tri-states buffer). 1319. The circuit component of claim 1237, further comprising an electrostatic discharge (ESD) protection circuit, and the electrostatic discharge protection circuit is connected to the fine circuit structure 292 200816373. 1320. The circuit component according to Item 1319, wherein the ESD protection circuit comprises a reverse-biased diode 1321. The circuit component structure as described in claim 1237, further including a thickness A first polymer layer between 2 micrometers and 100 micrometers is between the protective layer and the metal circuit layer. 1322. The circuit component structure of claim 1321. The polymer layer comprises a layer of a polymethylene imine compound having a thickness of between 2 and 100 micrometers. The circuit element structure of claim 1321. The first polymer layer comprises a thickness. A layer of a monophenylcyclobutane compound of between 2 micrometers and 100 micrometers. The circuit component structure of claim 1321. The first polymer layer comprises A poly-p-xylene polymer layer having a degree of between 2 and 100 micrometers. The circuit component structure of claim 1321. The first polymer layer comprises a thickness of 2 An epoxy layer between micrometers and 100 micrometers. 1326. The circuit component of claim 1237, further comprising a second polymer layer on the metal wiring layer. 1327. The circuit component structure of item 1326, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness of between 2 micrometers and 100 micrometers. 293 2008163 73.015TWB 1328. The circuit component structure of the present invention, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 micrometers and 100 micrometers. 1329. The circuit of claim 1326. The element structure, wherein the second polymer layer comprises a parylene polymer layer having a thickness of between 2 micrometers and 100 micrometers. 1330. The circuit component structure as described in claim 1326, Wherein, the second polymer layer comprises an epoxy resin layer having a thickness of between 2 micrometers and 100 micrometers. 1331. The circuit component according to claim 1237, further comprising a third polymer layer The circuit element structure of claim 1331, wherein the third polymer layer comprises a layer having a thickness of between 2 micrometers and 100 micrometers. A layer of a quinone imine compound. 1333. The circuit component structure of claim 1331, wherein the third polymer layer comprises a layer of a phenylcyclobutene compound having a thickness of between 2 microns and 100 microns. 1334. The circuit component structure of claim 1331, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 microns and 100 microns. 1335. The circuit component structure of claim 1331, wherein the third polymer layer comprises an epoxy layer having a thickness between 2 microns and 100 microns. 1336. A process for a circuit component, comprising: 294 2008163 73015TWB providing a semiconductor substrate, a fine-line metal structure, an electrical fuse, and a protective layer, the fine circuit structure being located The electronic fuse includes a first end point and a second end point on the semiconductor substrate, and the first end point and the second end point of the electronic fuse are respectively connected a first contact and a second contact of the thin circuit structure, wherein the protective layer is on the fine circuit structure; forming a metal circuit layer on the protective layer; after the metal circuit layer is formed, applying a current The electronic fuse is blown by the electronic fuse. 1337. The process of providing the thin circuit structure includes the step of forming a laser fuse in the thin circuit structure, the laser fuse including a first end point, in the process of the circuit component described in claim 1336. And a second end point, the first end point and the second end point of the laser fuse are respectively connected to one of the third contact point and the fourth contact point of the thin line structure. 1338. The process of providing a circuit component according to claim 1337, wherein the step of providing the protective layer further comprises forming an opening on the laser fuse. 1339. The process of circuit component according to claim 1337, further comprising a silicon oxide layer on the laser fuse, and the yttrium oxide layer is exposed to the opening of the protective layer Inside. 1340. The process of providing a line component as described in claim 1337, wherein the step of providing the laser fuse comprises providing a copper-containing laser fuse. 295 200816373.015TWB 1341. The process of providing a line component according to claim 1337, wherein the step of providing the laser fuse comprises providing a laser fuse including the name. 1342. The process of providing a line component as described in claim 1337, wherein the step of providing the laser fuse comprises providing a laser fuse comprising a polysilicon. 1343. The process of applying a line component as described in claim 1336, wherein the step of applying the current comprises applying a current between 0.05 amps and 2 amps. 1344. The process of applying the current component as described in claim 1336, wherein the step of applying the current comprises applying a current between 0.1 amps to 1 ampere. 1345. The process of applying a line component as described in claim 1336, wherein the step of applying the current comprises applying a current in a period of from 50 microseconds to 1800 microseconds. 1346. The process of applying the line component of claim 1336, wherein the step of applying the current comprises applying a current between 100 microseconds and 900 microseconds. 1347. The process of claim 10, wherein the step of providing the electronic fuse comprises forming a polysilicon layer and a metal silicide layer, the metal germanium layer On the polycrystalline layer. 1348. The process of claim 4, wherein the step of blowing the electronic fuse comprises forming a gap in the gold 296 200816373-------015TWB is a deuterated layer, such that the electron A current between the first end of the fuse and the second end is transmitted through the polysilicon layer, and the metal deuteration layer forms an open circuit. 1349. The process of forming a circuit component according to claim 1347, wherein the step of forming the metal deuteration layer comprises forming the metal deuteration layer having a thickness between 200 and 2000 angstroms. 1350. The process of forming a circuit component according to claim 1347, wherein the step of forming the polysilicon layer comprises forming the polysilicon layer having a thickness between 1000 and 3000 angstroms. 1351. The process of forming a circuit component according to claim 1347, wherein the step of forming the metal deuteration layer comprises forming the metal deuteride layer comprising titanium. 1352. The process of forming a circuit component according to claim 1347, wherein the step of forming the metal deuteration layer comprises forming the metal-bearing layer containing cobalt. 1353. The process of forming a circuit component according to claim 1347, wherein the step of forming the metal deuteration layer comprises forming the metal-bearing layer containing nickel. 1354. The process of forming a circuit component according to claim 1347, wherein the step of forming the metal deuteration layer comprises forming the metal-bearing layer containing tungsten. 1355. The process of circuit component according to claim 1336, wherein the electronic fuse has a sheet resistance between 1 ohm and 15 ohms when not blown. 297 2008163 73 01面 1356. The process of the circuit component according to claim 1336, wherein the electronic fuse has a sheet resistance of between 100 ohms and 10,000 ohms when the electronic fuse is blown. between. 1357. The circuit component is a dynamic random access memory (DRAM) wafer as claimed in claim 1336. 1358. The circuit component is a flash memory chip as claimed in claim 1336. 1359. The circuit component is a logic wafer as claimed in claim 1336. 1360. The circuit component is a memory wafer as claimed in the application of the circuit component of claim 1336. 1361. The process of the circuit component of claim 1, wherein the step of providing the fine circuit structure comprises: forming a thin-line dielectric layer having a thickness of 0.05 μm to 2 μm, located on the semiconductor substrate And the fine-line dielectric layer has a plurality of via holes; forming a plurality of conductive plugs in the via holes; and forming a plurality of fine-line metal layers having a thickness of between 0.05 μm and 2 μm, and the fine-line metal layers The plurality of fine-line dielectric layers are disposed on one of the thin-line dielectric layers, and the thin-circuit metal layers are electrically connected to each other by the conductive plugs. The thin-layer dielectric layer of the dielectric constant having a dielectric constant value of between 1.5 and 3.5, as described in the above-mentioned application. . 298. The method of claim 1 , wherein the thin line metal layer comprises the first contact and the second contact, the first end of the electronic fuse and The second end is respectively connected to the first contact and the second contact of the thin line metal layer. 1364. The process of claim 4, wherein the step of forming the thin-line dielectric layer comprises forming a layer of germanium oxide on the electronic fuse. 1365. The process of claim 10, wherein the step of forming the thin-line dielectric layer comprises forming a layer of germanium oxide under the electronic fuse. 1366. The process of claim 10, wherein the step of forming the thin-line dielectric layer comprises forming a layer of nitrogen oxynitride on the electronic fuse. 1367. The process of forming a line component according to claim 1361, wherein the step of forming the thin-line dielectric layer comprises forming a layer of ruthenium oxynitride under the electronic fuse. 1368. The process of forming a circuit component according to claim 1361, wherein the step of forming the thin wiring metal layer comprises forming an aluminum layer having a thickness of between 0.05 μm and 2 μm. 1369. The process of claim 4, wherein the step of forming the thin line metal layer comprises forming a copper layer having a thickness between 0.05 microns and 2 microns. 1370. The process of providing a circuit component according to claim 1336, wherein the step of providing the protective layer comprises a chemical vapor deposition 299 200816373, 15TWB (Chemical Vapor Deposition, CVD) process. 1371. The process of providing a circuit component according to claim 1336, wherein the step of providing the protective layer comprises depositing a layer of a ruthenium nitride compound. 1372. The process of providing a circuit component according to claim 1336, wherein the step of providing the protective layer comprises depositing a phosphorous glass layer (PSG). 1373. The process of providing a circuit component according to claim 1336, wherein the step of providing the protective layer comprises depositing a layer of an oxonium compound. 1374. The process of providing a circuit component according to claim 1336, wherein the step of providing the protective layer comprises depositing a layer of oxynitride compound. 1375. The process of forming a circuit component according to claim 1336, wherein the step of forming the metal wiring layer comprises forming a gold layer having a thickness of between 1.5 micrometers and 15 micrometers. 1376. The process of claim 4, wherein the forming the metal wiring layer comprises forming a copper layer having a thickness between 1.5 microns and 15 microns. 1377. The process of claim 4, wherein the forming the metal wiring layer comprises forming a silver layer having a thickness between 1.5 microns and 15 microns. 1378. The process of forming the circuit component according to claim 1336, wherein the step of forming the metal wiring layer comprises forming a nickel layer having a thickness of between 0.5 μm and 6 μm. 1微米. The thickness of the metal circuit layer comprising the thickness of 1. 5 micrometers to 15 micrometers is formed by the method of the present invention, wherein the metal circuit layer is formed to have a thickness of between 1. 5 micrometers and 15 micrometers. The first layer. 1380. The process of forming the circuit component according to claim 1336, wherein the step of forming the metal wiring layer comprises forming a palladium layer having a thickness of between 1.5 μm and 15 μm. 1 381. The process of forming the circuit component according to claim 1336, wherein the step of forming the metal circuit layer comprises forming a titanium layer having a thickness between 0.02 micrometers and 0.8 micrometers. under. 1382. The process of forming a circuit component according to claim 1, wherein the step of forming the metal circuit layer comprises forming a titanium-tungsten alloy layer having a thickness between 0.02 micrometers and 0.8 micrometers. Under the circuit layer. 1383. The process of forming a circuit component according to claim 1, wherein the step of forming the metal circuit layer comprises forming a titanium nitride layer having a thickness of between 0.02 micrometers and 0.8 micrometers. Under the circuit layer. 1384. The process of forming a circuit component according to claim 1336, wherein the step of forming the metal circuit layer comprises forming a germanium metal layer having a thickness between 0.02 micrometers and 0.8 micrometers under the metal circuit layer. . 1385. The process of forming a circuit component according to claim 1, wherein the step of forming the metal circuit layer comprises forming a layer of tantalum nitride at a thickness of between 0.02 micrometers and 0.8 micrometers. Under the circuit layer. 1386. The process of forming a circuit component according to claim 1336, wherein the step of forming the metal circuit layer comprises forming a chrome metal layer having a thickness between 0.02 μm and 〇β 8 μm in the metal line Under the layer. 1 </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The layer is disposed under the metal circuit layer. 1388. The process of the circuit component according to claim 1336, wherein the step of providing the semiconductor substrate comprises: setting a plurality of internal circuits on the semiconductor substrate, the internal circuit is electrically Connected to the thin circuit structure. 1389. The process of circuit component according to claim 1388, wherein the step of setting the internal circuit comprises setting an internal circuit including a NOR gate. The process of the circuit component described in claim 1388, wherein the step of setting the internal circuit includes setting an internal circuit including an OR gate. 1391. The circuit component according to claim 1388 The process, wherein the step of setting the internal circuit includes setting an internal circuit including an AND gate. 1392. The process of the circuit component of claim 88, wherein the step of setting the internal circuit comprises: providing an internal circuit including a NAND gate. 1393. The process of the circuit component according to claim 1388, wherein The step of setting the internal circuit includes setting a DRAM cell. 1394. The process of the circuit component according to claim 1388, wherein the step of setting the internal circuit includes setting A flash memory unit (f lash memory cel 1) ° 302 200816373—Na 1395. The process of circuit component as described in claim 1388, wherein the step of setting the internal circuit includes setting an erasable Program read-only memory unit (EPROM cel l) 1396. For the process of applying the line component described in the patent prince 1388, the step of setting the internal circuit includes setting a read-only unit (ROM cel) 1) 〇1397. The process of circuit component according to claim 1388, wherein the step of setting the internal circuit comprises setting a magnetic The device accesses a memory (magnetic RAM, MRAM) unit. 1398. The process of circuit component according to claim 1388, wherein the step of setting the internal circuit comprises setting a sense amplifier 0 1399 The process of the circuit component described in claim 1388, wherein the step of setting the internal circuit includes setting an operational amplifier (Aperture Amplifier) 1400. The process of the circuit component described in claim 1388, The step of setting the internal circuit includes setting an adder (1401). The process of the circuit component according to claim 1388, wherein the step of setting the internal circuit includes setting a multiplexer ( Multiplexer) ° 1402. The process of circuit component according to claim 1388, wherein the step of setting the internal circuit comprises setting a pair; a device (Diplexer) 303 2008163 73.015TWB 1403. The process of the line component, wherein the step of setting the internal circuit comprises setting a multiplier (Multip Lier) 1404. The process of setting the circuit component as described in claim 1388, wherein the step of setting the internal circuit includes setting an analog/digital converter (A/D converter). 1405. The process of setting the circuit component according to claim 1388, wherein the step of setting the internal circuit comprises setting a digital/analog converter (D/A Converter). 1406. The process of circuit component according to claim 1388, wherein the step of disposing the internal circuit comprises providing a complementary metal oxide semiconductor (CMOS). 1407. The process of circuit component according to claim 1388, wherein the step of setting the internal circuit comprises setting a photo-sensitive diode 〇1408. As described in claim 1388. The circuit component process, wherein the step of setting the internal circuit comprises setting a bipolar complementary metal oxide semiconductor (BiCMOS). 1409. The process of providing the circuit component according to claim 1388, wherein the step of setting the internal circuit comprises setting a bipolar circuit unit. 1410. The process of circuit component according to claim 1388, wherein the step of disposing the internal circuit comprises: providing an N-type MOS device (NMOS), the channel width of the N-type MOS device 304 200816 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。. 1411. The process of circuit component according to claim 1388, wherein the step of setting the internal circuit comprises: setting an N-type MOS device (NM0S), a channel width of the N-type MOS device (Channel) The ratio of the channel length is between 0.2 and 2. 1412. The process of circuit component according to claim 1388, wherein the step of setting the internal circuit comprises: providing a P-type MOS device, a channel width of the P-type MOS device (Channel) The ratio of the ratio of the channel length is between 0.2 and 10. 1413. The process of circuit component according to claim 1388, wherein the step of setting the internal circuit comprises: providing a P-type MOS device, a channel width of the P-type MOS device (Channel) The ratio of the ratio of the channel length is between 0.4 and 4. 1414. The process of claim 10, wherein the step of providing the semiconductor substrate comprises: providing at least one off-chip circuit on the semiconductor substrate; It is composed of at least one MOS device, and the external circuit of the wafer is electrically connected to the thin circuit structure. 1415. The process of claim 4, wherein the MOS device comprises a P-type MOS device 2008163 73.01 surface (PM0S), and the channel width of the P-type MOS device (Channel) The width)/channel length ratio is between 40 and 40,000. 1416. The process of claim 4, wherein the MOS device comprises a P-type MOS device, and a channel width of the P-type MOS device. The channel length ratio is between 60 and 600. 1417. The process of claim 4, wherein the MOS device comprises an N-type MOS device, and a channel width of the N-type MOS device. The channel length ratio is between 20 and 20,000. 1418. The process of claim 4, wherein the MOS device comprises an N-type MOS device, and the channel width of the N-type MOS device is ) / Channel length ratio is between 30 and 300. 1419. The process of circuit component according to claim 1414, wherein the step of disposing the external circuit of the wafer comprises setting an off-chip driver. 1420. The process of circuit component according to claim 1414, wherein the step of disposing the external circuit of the wafer comprises setting an off-chip reciver. 306, V-015TWB 200816373 1421. The process of circuit component according to claim 1414, wherein the step of disposing the external circuit of the wafer comprises setting a wafer off-chip buffer. 1422. The process of circuit component according to claim 1414, wherein the step of setting the internal circuit comprises setting an off-chip tri-states buffer. 1423. The process of claim 4, wherein the step of providing the semiconductor substrate comprises providing at least one electrostatic discharge (ESD) protection circuit on the semiconductor substrate, and the electrostatic discharge protection circuit is electrically Connect to the fine line structure. 1424. The process of claim 4, wherein the electrostatic discharge protection circuit comprises a reverse-biased diode 〇1425. The circuit of claim 1336 In the process of forming the metal circuit layer, a first polymer layer having a thickness of between 2 micrometers and 100 micrometers is formed on the protective layer. 1426. The process of claim 4, wherein the first polymer layer comprises a layer of a polyamidimide compound having a thickness between 2 microns and 100 microns. 1427. The process of claim 4, wherein the first polymer layer comprises a layer of a phenylcyclobutene compound having a thickness between 2 microns and 100 microns. 1428. The process of claim 4, wherein the first polymer layer comprises a poly-pair of 307 015 TWB 200816373 τ 八 γ \j\j with a thickness between 2 μm and 1 Q0 μm. Toluene polymer layer. 1429. The process of claim 4, wherein the first polymer layer comprises an epoxy layer having a thickness between 2 microns and 100 microns. 1430. The process of forming the metal wiring layer further comprises forming a second polymer layer on the metal wiring layer, as in the process of applying the circuit component described in claim 1336. 1431. The process of claim 4, wherein the second polymer layer comprises a layer of a polyamidimide compound having a thickness between 2 microns and 100 microns. 1432. The process of claim 4, wherein the second polymer layer comprises a layer of a phenylcyclobutene compound having a thickness between 2 microns and 100 microns. 1433. The process of claim 4, wherein the second polymer layer comprises a parylene polymer layer having a thickness between 2 microns and 100 microns. 1434. The process of claim 4, wherein the second polymer layer comprises an epoxy layer having a thickness between 2 microns and 100 microns. 1435. The process of forming the metal wiring layer, further comprising forming a third polymer layer over the entire upper surface of the metal wiring layer, in the process of forming the wiring component according to claim 1336. 1436. The process of claim 5, wherein the third polymer layer comprises a layer of a polyamidimide compound between 308 200816373015TWB having a thickness between 2 microns and 100 microns. 1437. The process of claim 1 wherein the third polymer layer comprises a layer of a phenylcyclobutane compound having a thickness between 2 microns and 100 microns. 1438. The process of the circuit component of claim 1, wherein the third polymer layer comprises a parylene polymer layer having a thickness of between 2 microns and 100 microns. 1439. The process of claim 4, wherein the third polymer layer comprises an epoxy layer having a thickness between 2 microns and 100 microns. 309