TW200803528A - Video encoders and graphic processing units - Google Patents

Abstract

An exemplary graphics processing unit (GPU) comprises: an instruction decoder; and a video processing unit. The instruction decoder is configured to decode a plurality of deblocking filter acceleration instructions. The deblocking filter instructions are associated with a filter used by a particular video decoder. The video processing unit (VPU) is configured to receive parameters encoded by the deblocking filter acceleration instructions. The VPU is further configured to determine one of a plurality of first pixel data sources from the received parameters. The VPU is further configured to determine one of a plurality of second pixel data sources from the received parameters. The VPU is further configured to to load a first block of pixel data from the determined first pixel data source. The VPU is further configured to load second block of pixel data from the determined second pixel data source.

Description

200803528

V. IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to image compression and decompression, and more particularly to a graphics processing unit having image compression and decompression features. [Prior Art] Personal computers and consumer electronics are used in various entertainment products. These entertainment items can be roughly classified into two categories: those using computer-generated graphics, such as computer games; and those using compressed video streams, such as pre-recorded programs to digital On a video disc (DVD), or by a cable turtle or an angry star, a digital program is provided to a set-top box. The second type also includes a coded analog video stream', for example, implemented by a digital video recorder (DVR). The computer graphics are usually generated by a graphics processing unit (GPU). A graphics processing unit is a special type of microprocessor built on computer game consoles and some personal computers. A graphics processing unit is optimized to quickly perform three-dimensional primitive objects, such as triangles, quads, and the like. These basic objects are described by a plurality of vertices, each of which has an attribute (e.g., a color) and a texture can be applied to the base object. The result is a two-dimensional array of 6Client's Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林环辉/2007/06/14 6 200803528 v Pi xe 1 s ), displayed on a computer monitor or monitor. The encoding and decoding of video streams involves different kinds of operations, such as discrete cosine transform, motion estimation, motion compensation, and deblocking filters. These calculations are typically handled by a general purpose central processing unit (CPU) in conjunction with special hardware logic circuits, such as application specific integrated circuits (ASICs). Lu consumers therefore need multiple computing platforms to meet their entertainment needs. There is therefore a need for a single computing platform that can handle computer graphics and video encoding/decoding. SUMMARY OF THE INVENTION Embodiments disclosed herein provide a system and method for video compression deblocking. An exemplary graphics processing unit (Gpu) includes: an instruction decoder and a video processing unit. The instruction decoder is set to decode • a plurality of deblocking effector acceleration instructions. The deblocking filter and the wave accelerator command are all associated with a deblocking filter used by a particular video decoder. The video processing unit is configured to receive a parameter encoded by the deblocking effect for the acceleration command. The video processing unit is further configured to determine one of the plurality of first pixel data sources from the receiving parameter. The video processing unit is further configured to determine one of the plurality of second pixel data sources from the received parameter. The video processing unit is further configured to download a first pixel data block from the determined third memory source. The video processing unit is further configured to download a second pixel data block from the determined second memory source. 7Clienfs Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/final/林璟辉/2007/06/14 7 200803528 % > " [Embodiment] Man who is strict with video shame! For graphics and video coding and / or decoding - exemplary operation: port = block diagram. System} (10) contains a general purpose (3) U 11 〇 (hereafter the processor), a graphics processor (_ 120, memory 130 and The bus 140 and the image processing/processing unit 12A include a video acceleration unit (10), /, an accelerated video code and/or decoding, which will be described later. The video processing unit 12 〇 video acceleration work _ The instruction executed on the graphics processing unit i2Q. Fortunately, the human body is decoded to 16 and the video acceleration driver 17 is located in the memory 13A, and the decoder 160 and the video acceleration driver 17 are executed in the main processing state no. The decoder 160 can also issue a video acceleration command to the graphics processing unit 12 through a main processor interface 180 provided by the video acceleration driver 17A. In this way, the system sends a video acceleration command to the graphics processing. Unit 120 The processor software (h〇st pr〇cess〇r_software) performs video encoding and/or decoding, and the graphics processing unit ι2〇 responds to these instructions through a portion of the acceleration decoder 160. In some embodiments, only a small portion The decoder 16 is executed on the main processor 110, and most of the decoders 16 are executed by the graphics processing unit 12' under the driver's minimal overload. In this way, the computationally intensive blocks are often executed (computationally The intensive blocks are unloaded to the graphics processing unit 120, and the more complex operations are performed by the main processor no. 8Clienfs Docket N〇.;S3U06-0011 TT's Docket No:0608-A41238-TW/final/林璟辉/2007/ 06/14 8 200803528 ? In some embodiments, a dense computational function implemented by the VPU 150 within the graphics processing unit 120 includes an in-loop deblocking filter hardware acceleration logic circuit (IDF 'ini00p deblocking filter hardware acceleratioii logic 400, also known as in-loop block effect filter 4 (10) or deblocking policing filter 400. Some embodiments of VPU 150 include multiple loops Blocking filter exemplary hardware acceleration logic circuitry, e.g., a filter with different coding standards such as VC-1 and H · 264 match. For example, the embodiment shown in FIG. 5, wherein the VPU 150 includes a 264 internal loop deblocking filter hardware acceleration logic circuit 170 and a VC_in-loop deblocking filter hardware acceleration logic circuit 400 (afterwards) Combined with Figure 4). Another example of intensive computing functions is to determine the boundary strength (BS, b〇undary strength) of each filter. The above structure thus makes the following operations flexible: performing some special functions on the decoder 160 to perform a shaderpr〇gram on the macroblock (marc〇bl〇ck) on the main processor 11〇 (for example, go Blocking or calculating the boundary strength); or performing most of the decoder 160' on the graphics processing unit 12' utilizing pipeline pipelining and parallelization (European aUeii(8). In some decoders, 160 in the graphics processing unit 12 In the embodiment executed on the ,, the deblocking processing is a thread of synchronization between the decoders of the decoders. In the first figure, a plurality of video acceleration features for interpreting the graphics processing unit 12 are omitted. Necessary and familiar with the familiar components of this memory. Signal decoder ^Clienfs Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 200803528 by j 2 Figure 1 is a block diagram of the video decoder 160 in Fig. 1. In the second figure, the special case of the problem is 'solution. 16Q applies Ιτυ Η· 264 video compression rule ^, and 'skilled by the skilled person should know Figure 2 decoder The initial description of the system 3 code, the video decoder also describes similar to η··, the operation of the decoder, such as smpte ^ and see. ^ 'Although shown as -_ processing unit (10) - In part, familiar with this technique, it is understood that some of the decoders disclosed herein can also be implemented in a figure other than a processing list, for example, an independent logic circuit, a part of a special application integrated circuit (ASIC). The input bit stream 205 is first processed by an entropy decoder (entr〇py dec〇der) 210. Entropy coding has the advantage of statistically statistic redundancy: - some patterns appear more often than other patterns, so Often appearing is represented by a shorter code. Entropy coding includes Huffman coding and run-length encoding. After entropy coding, the data is represented by a spatial decoder (Spatial dec〇der). Processed by 215, which has the advantage that, in fact, adjacent pixels in a pattern are generally identical or related so that only the difference is encoded. In this exemplary embodiment, spatial decoding boundary 215 includes a An inverse quantizer 220 is coupled to an inverse discrete cosine transform (IDCT) function 230. The output of the IDCT function 230 can be viewed as a graph (235) consisting of a number of pixels. ... the graph 235 is processed to be smaller Sub-blocks, called giant tiles. The JJ 2 video compression specification uses a giant tile size of 16x16 pixels, while other compression specifications can use other sizes. The huge block in the graphic 235 and the previously decoded picture item lOClienfs Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 200803528 Inter prediction processing, or combined with the information of other giant tiles of 235, is called intra-prediction prediction processing. The input bit stream 2〇5 is applied by the entropy decoder 2〇5 to inter-picture or in-plane prediction according to each type of pattern. L, the entropy decoder 21 produces a motion vect〇r 245 output when inter-plane prediction is applied. The motion vector 245 is used for the temporary code, which has the advantage that, in fact, it is common to have the same value for $•f in a series of graphics. The change from the -picture to the other - is encoded as a shift binary 245. Motion compensation block 250 clocks one or more previously decoded graphics 255 into motion vector 245 to produce a predicted pattern (2 yang). When inter-panel prediction is applied, spatial compensation block 270 combines the information from the adjacent macroblocks with the giant tiles within graphics 235 to produce a predicted pattern (2Y5). The combiner 280 adds the graphic 235 to the output of the mode selector (m〇de selectQ]r 285. The mode selector 285 uses the entropy decoded bitstream to determine the predictive graph (265) produced by the junction compensator 280 using the motion compensation block 250 or the predictive graph (275) generated using the spatial compensation block 270. The encoding process causes artifacts such as discontinuities along the edges of the giant tile and discontinuities along the edges of the sub-blocks within the giant tile. The result is that an edge appears in the solution of the solution to the stone, but not originally. The deblocking filter 290 is applied to the combined pattern output by the combiner 280 to remove these edge products. The decoded pattern 295 generated by the filter is used to decode the next graphic. 1 lClienf s Docket N〇.:S3U06-0011 TT's Docket NO:0608-A41238-TW/fmal/林璟辉/2007/06/14 11 200803528 In the discussion of the figure, part of the decoder ι60 is executed on the main processor no, and the decoder 160 also has the advantage of providing video acceleration instructions by the graphics processing unit 12. In particular, in some embodiments, deblocking filtering The processor 29 uses one or more instructions provided by the graphics processing unit 12 to implement filtering using relatively low computational cost. The deblocking filter 290 is a multi-tap filter based on proximity. The pixel values adjust the pixel values at the edges of the sub-blocks. Different embodiments of the deblocking filter 290 can be used depending on the compression specification implemented by the decoder 160. Each specification uses a different filter parameter. For example, the size of the sub-block, the number of pixels updated by the filtering operation, the frequency of application of the filter (eg, every N columns or rows). In addition, each specification uses a different filter length structure. Those skilled in the art are familiar with the art. It should be understood that multi-cell filtering is not discussed here. The structure of the specific unit is not discussed here. The U-deblocking filter is defined by the VC-ι specification. The block-effect filter embodiment will be described in conjunction with the Figure 4. First, VC-1 filtering The sub-block pixel arrangement of the device will be described in conjunction with Figure 3. Figure 3 shows two adjacent 4x4 sub-blocks (310, 320), defined as columns R1-R4 and rows Cl-C8. The vertical boundary between the two sub-blocks is 330 Lines C4 and C5. The VC-1 filter operates for each 4x4 sub-block. For the leftmost sub-block, the VC-1 filter checks for a predetermined group of pixels in a predetermined column (3) (Ρ1 Ρ2, Ρ3). If the predetermined group of pixels reaches a certain standard, update another pixel Ρ4 in the same predetermined column. The standard is 12Client's Docket N〇.: S3U06-0011 TT's Docket No: 0608-A41238-TW/fmal/ Lin Yihui/2007/06/14 12 200803528 - by the pre The calculation of the pixels in the group depends on the special set of comparisons. Those skilled in the art should understand that these calculations and comparisons can also be a set of taps, and detailed calculations and comparisons will be combined later. Figure 5: The update value is also based on the operation performed on the pixels in the predetermined group. The VC-1 filter processes the rightmost sub-block in analogy, and determines whether the pixels P6, P7, and P8 reach a standard. The standard updates P5. In other words, the VC-1 filter is a predetermined column (R3) of a group of predetermined pixels - edge pixels P4 and P5 - based on the values of other groups of predetermined pixels in the same column, the value of P4 is based on PI, P2, P3, The value of P5 is based on P6, P7, and P8. The VC-1 conditionally updates the same group of predetermined pixels of the remaining columns based on the values calculated for the predetermined group of pixels (edge pixels P4, P5) of the predetermined column (R3). As a result, P4 in R1 is updated based on PI, P2, and P3 in R1, but only after P4 and P5 in R3 are updated. Similarly, P5 in R1 is updated based on P6, P7, and P8 in R1, but only after P4 and P5 in R3 are updated. Columns 2 and 4 are also treated in a similar manner, m w . On the other hand, some pixels of a pixel in a predetermined third column are filtered or updated when the other pixels in the third column reach a standard. This filter involves performing comparisons and calculations on these other pixels. If the other pixels in the third column do not meet the criteria, the corresponding pixels in the remaining columns are filtered in an analogy manner, as described above. Some embodiments of the deblocking filter 290 disclosed herein use a groundbreaking technique to first filter the third column and then filter the other columns. These groundbreaking technologies will be combined with the 13th Client5s Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 200803528 — 4,5,6A—6D, more detailed Description. Figure 3 illustrates the vertical edges of a column. Those skilled in the art should be able to understand that the same image can be rotated by 90 degrees to indicate that the horizontal edges are processed. Those skilled in the art will also appreciate that although V(>1 uses the third column of the four columns as a predetermined column for determining the conditional update of other columns, the principles disclosed herein can be applied to embodiments using other predetermined columns. (e.g., the first column, the second column, etc.) may also be applied to other embodiments that form different numbers of sub-blocks. Similarly, those skilled in the art will also appreciate that although 10 checks the value of a group of pixels to set To update the value of the pixel, the principles disclosed herein can also be applied to embodiments in which other pixels have been verified and other pixels have been set. For an example, P2 and P3 can be tested to determine the updated value of P4. The P3 can be set according to the values of P2 and P4. The video acceleration unit 150 in the graphics processing unit 120 is an in-loop deblocking filter (IDF), for example, a block-effect filtering in the loop of the VC-1 specification. Implementing a hardware acceleration logic circuit. A graphics processing unit instruction implements the hardware acceleration logic circuit, which will be described later. A conventional method for implementing a block-effect filter in a VC-1 loop Each column/row is processed in parallel because the same pixel calculation is performed on each column/row of a sub-block. This conventional method filters two adjacent 4x4 sub-blocks per cycle, but requires an increase in the number of logic gates to execute. The groundbreaking method used by the VC-1 circuit to remove the block effect filter hardware acceleration logic circuit 400 first processes the third column/row of pixels, and if the pixels reach the required standard, then sequentially process the remaining The three columns/rows. This groundbreaking method uses fewer logical gates than the conventional method, which replicates the columns / 14Clienfs Docket No. :S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 14 200803528 '磔2, this is the case. The sequential processing of the VC-l Ifd acceleration logic circuit 400 filters two adjacent 4χ4 sub-blocks every 4 cycles. This longer filtering time is The instruction processing cycle of the graphics processing unit 12 is the same, wherein the conventional method has a faster filtering, which is faster than the required speed, resulting in waste of the number of logic gates. Figure 4 is a block in the VC-1 loop. Effect filter hardware acceleration The hardware of circuit 400 describes a list of virtual codes. Although not using a hardware description language (HDL), examples such as Veri 1 〇g and VHDL use a virtual code, those skilled in the art should deal with these The virtual code is quite familiar. These people should understand that when actually described, these codes should be compiled and then synthesized into the number of logic gate configurations that make up the partial video acceleration unit 150. These people should be aware that these logic gates can be various Technical implementations, such as an application-specific integrated circuit (ASIC), programmable logic gate array (PGA), or field-programmed logic gate array (FPGA). The 410 segment of this private code is a module definition. The VC-1 loop de-blocking filter hardware acceleration logic circuit 4 has many input parameters. The sub-block to be filtered is specified by the block parameter. If the vertical parameter is True, the acceleration logic 4 considers the block parameter as a 4x8 block (see Figure 3) and performs vertical edge filtering. If the vertical parameter is False, the acceleration logic circuit 4 considers the block parameter as an 8x4 block (see Figure 3) and performs a horizontal edge tear wave. The code section 420 starts a generation of loops (itera〇n 15Client's Docket No.: S3U06-0011 TT's Docket No: 0608-A41238-TW/final/林璟辉/2007/06/14 15 200803528 ::loop), Set the value of this loop parameter variable. When the loop is passed for the first time, the loop parameter is set to 3, so the third line is processed first. Subsequent loop iteration settings The loop parameters are 1, 2 and 4. Using these parameters, the VC-1 in-loop deblocking filter hardware acceleration logic circuit 400 repeats four times, processing 8 pixels at a time, one of which can be a horizontal column or a vertical line. Each column is processed by row acceleration logic circuit 500 (see Figure 5). In some embodiments, the row acceleration logic circuit 500 is implemented as an HDL sub-module and will be described in conjunction with FIG. • Section 430 tests the vertical parameters to determine the execution of vertical or horizontal edge filtering. Based on the result, the eight elements of the row array variable are initialized from the row of the 4x8 input block or the row of the 8x4 input block. Section 440 determines whether the third line is processed by comparing the loop parameter (set by section 420) to 3. If the loop parameter is 3, another rain control variable, ProcessingPixel3 and FILTER_OTHER-3 are set to true. If the loop parameter is not 3, set ProcessingPixel3 to true. Section 450 illustrates another HDL module 'Lu VCl-IDC_Fi 1 ter_Line, which applies the current trip. (As described in connection with Figure 3, the row filter updates the edge pixel values based on neighboring pixel values.) The parameters supplied to the sub-module include the control variables ProcessingPixel3, FILTERJ) THEtL3 and the loop parameters. In one embodiment, the VC-1 in-loop deblocking filter hardware acceleration logic circuit 400 has an additional input parameter, a quantized value, which is also provided to the sub-module. After the sub-module processes the column, the VC-1 loop de-blocking filter 16Client's Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 16 200803528 W· The 'hardware acceleration logic circuit 400 continues the iteration loop with a loop parameter update value in section 420. In this way, the filter is applied to the third row of the input block, followed by the first row, the second row, and the fourth row. Figure 5 is a list of hardware description language codes for the acceleration logic circuit 5 (10) that implements the sub-modules described above. The section of the code is a module definition. The row acceleration logic circuit 500 has a number of input parameters. The line system to be filtered is defined as the line input parameter. ProcessingPixel3 is an input parameter. If the behavior is in the first or third column, it is set to true by higher level logic. The parameter FILTER - OTHER - 3 - the start is set to true by the higher layer logic circuit, and is adjusted by the line acceleration logic circuit 500 according to the pixel value. Section 520 performs various pixel value operations as determined by VC-1. (Because the calculation can be understood with reference to the specifications of VC-1, these operations will not be described in detail.) Section 530 tests the ProcessingPixel3 parameters provided by the higher layer VC-1 loop deblocking filter hardware acceleration logic circuit 400. . If ProcessingPixel3 is true, then section 530 initializes a control variable number DO_FILTER to a predetermined value, true. The various results of the operations in the middle of the segment 52 are used to determine if the other 3 rows are to be processed. If the pixel operation result indicates that the other three rows are not processed, then D0_FILTER is set to be if ProcessingPixel3 is false, and segment 540 is used as input parameter FILTER_0THER_3 (by the higher layer VC-1 loop to remove the block effect filter hardware acceleration logic circuit 400 settings) to set the value of D0_FILTER. If DO_FILTER is true, segment 550 tests the DCLFILTER variable and updates the edge pixels P4, P5 of the row variable (see Figure 3). 17Clienfs Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 17 200803528 Section 560 tests the ProcessingPixel3 parameter and updates FILTERJ)THER„3. The FILTER_ The THER_3 variable is used to convey the status information of different examples in this module. If ProcessingPixel3 is true, then section 550 updates the FILTER_0THER_3 parameter with the value of D0_FILTER. This technique is used to describe the higher layer module of this module ( That is, VC1 - InloopFilter ) provides the FILTER_0THER_3 value updated by the YC_1_INL00PFILTER_LINE low-level module of this example to another VC_1-1NL00PFILTER_LINE. Those skilled in the art should understand that the virtual code of the 5th figure can be synthesized in various ways. A logical idle arrangement is implemented that implements row acceleration logic circuit 500. One of the arrangements is illustrated in Figures 6A-D, which together form a block diagram of row acceleration logic circuit 500. Those skilled in the art should have a V (> The internal block-effect filter algorithm and logic circuit structure are familiar. Therefore, the components of the 6A-D diagram will not be detailed. The characteristics of the speed logic circuit 500. Those skilled in the art should understand that the operation involved in the 'VC-ι loop deblocking filter' includes the following 'where Ρ1-Ρδ means that the pixel is in the processed column/row. Position AO = (2*(Ρ3 - Ρ6) - 5*(P4 - Ρ5) + 4) >> 3

Al - (2*(P1 - Ρ4) - 5*(Ρ2 - Ρ3) + 4) » 3 Α2 = (2*(Ρ5 - Ρ8) - 5*(Ρ6 - Ρ7) + 4) >> 3 clip = (Ρ4 - Ρ5)/2 Each of the first 3 operations involves 3 subtractions, 2 multiplications, q additions, and 1 right shift. One of the lines of acceleration logic circuit 5 in Figure 6A 18Clienf s Docket No. :S3U06-0011 TT's Docket N〇:0608-A41238-TW/fmal/林璟辉/2007/06/14 18 200803528 'Partial use of shared logic The circuit sequentially calculates AO, A1, A2 instead of using specific independent logic blocks for AO, A1, A2. The logic gate and/or power consumption is reduced by avoiding the logic block repeating 'processing the inputs sequentially using the multiplexer. Multiplexers 605, 610, 615, and 620 are used to select different inputs from pixel registers P1-P8 for different timing periods, and these inputs are provided to the respective shared logic blocks. Logic circuit blocks 625 and 630 each perform a subtraction. The logic circuit block 635 is implemented by multiplying the left shift by 1 bit by 2 ° by 5 lines, by shifting 1 bit (_) to the left, followed by the adder 645. Adder 650 adds the output of left shifter 635, a constant 4, and the negative of the 645 output. Finally, logic circuit block 655 performs a right shift of 3 bits. In the first timing cycle, an input T = 1 is supplied to each of the multiplexers 605, 610, and 615, and the value of A1 is calculated and stored in the register 66. In the second timing cycle, an input T = 2 is supplied to each of the multiplexers 6 〇 5, 61 〇 and 615, and the value of Α 2 is calculated and stored in the register 665. In the third timing cycle, an input Τ = 3 is supplied to each of the multiplexers 605, 61 〇 and 615, and the value of Α 0 is stored in the register 670. The presence of the registers 66〇, β65, 67〇 2 values A1, Α2, and A3 will be used by the partial line acceleration logic circuit 5 of the sixth drawing, which will be described later. The output of the Ρ4 register (671) and the output of the semaphore (673) will be used by the partial line of the 6C diagram, which will be described later. Those skilled in the art should also understand the additional operations involved in the V (M-loop back-blocking filter): ^ 19Clienfs Docket N〇.: S3U06-0011 TT's Docket No:0008-A41238-TW/fmal/林璟辉/2007/06/14 19 200803528 死D二五*((sign(A0) * A3) - A0)/8 if (CLIP > 0) { if (D < 0) D 2 0 if (D &gt ; CLIP)

D - CLIP } else { if (D > 0) D = 0 if (D < CLIP)

® D = CLIP Section 6B of the row acceleration logic circuit 500 receives input from the portion of the row acceleration logic circuit 500 of Figure 6A and calculates D (675). Referring again to Figure 6A, CLIP (677) is generated as follows: Pixels P4 and P5 are subtracted from logic circuit block 679, and the result is shifted right by logic block 680 (integer divided by 2) to produce CLIP 677. Returning to Figure 6B, A1 can be retrieved from the scratchpad 660 in the first cycle, and A2 can be self-registered in the second cycle. 665 20Client's Docket N〇.:S3U06-0011 XT's Docket No:0608-A41238-TW/fmal / 林璟辉/2007/06/14 20 200803528 Acquired, = can be obtained from the register 670 in the third cycle. Thus, the partial line acceleration logic circuit 500 of Fig. 6 of the fourth cycle calculates D (675) based on the above-described formula. The equation of the line up logic circuit 500 utilizes (675) to update the pixels of P4, P5: set. In particular, P buckles P4-D and P5 = P5+D. Although the sixth Α, 6β first fishing, Ό 5 single column/row (for example, a single group of pixel positions P0-P8) indicates °, the operation of the third column/row of the two sub-blocks affects the other three columns/rows of the sub-block. The two-line acceleration logic circuit 500 utilizes a groundbreaking method to implement the behavior. When the independent filtering operation is started from the front - parallel - complete, 'combination = 6A, 6B diagram description, shown in the 6G, 6D diagram part of the line acceleration logic = road 5 〇〇 conditional choice to update the position. In other words, the ν(>1 loop-in-the-box politic filter hardware acceleration logic circuit 400 determines that the original value was rounded back or the new value was written back. In contrast, a conventional method, - the inner loop of the block The effect filter uses a loop, so it is executed independently of the filter condition. ^ As explained earlier, the fourth diagram explains that the line of the acceleration logic circuit 5q is operated in a loop: in a repeating section 420. There are 2 instances of the instantiat section 450. In addition, the example of the row acceleration logic circuit 500 uses two parameters, Pr〇cessingPixei3 and FILTER_〇THER_3. These parameters of the row acceleration logic circuit 500 are as follows: P4, P5 conditionally updated. Mai's see Figure 6C, the result of the register being written to the subtractor 681, wherein the subtractor 681 has an input of P4 (671), 〇 or D (675), according to D0_FILTER (683) Similarly, the register P5 writes the result of the adder 685, where the adder 2IClient^ Docket No,:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/ 14 21 200803528 685 There is an input for P5 ( 673), which is 〇 d (675), depending on the value of DO-FILTER (683). Therefore, the update value of 'P4 is the original p4 value (if D〇J? ILTE)R is false), or P4-D. Similarly, p5 The updated value is the original p5 value (if DO_FILTER is false), or P5+D. Those skilled in the art should understand that when processing the third column of a sub-block, the standard for updating P4 with P4-D is : ((ABS(AO) < PQUANT) OR (A3 < ABS(AO)) OR (CLIP !- 0) DO-FILTER 683 is calculated by the partial line acceleration logic circuit 500 which tests these conditions in Fig. 6D The multiplexer provides an input to the 〇R gate 697, if ABS(AO) < PQUANT selects a true output, the others are false. The multiplexer 689 provides another input to the 0R gate 697, if A3< ABS (A0) selects a true output, others are false. Multiplexer 691 provides another input to 〇R gate β97, if CLIP ! =0 then selects a true output, others are false. D0_FILTER 683 is more The tool 693 provides a control input of a Pixel-3 (695) to select an output of the output R gate 697 or an input signal FILTER_OTHER-3 (699). Input

Processing—Pixel—3 (695) and FILTER—OTHER—3 (699) previously combined with FIG. 4 and exemplifying the higher layer VC-1 in-loop deblocking filter hardware acceleration logic circuit of row acceleration logic circuit 500〇 The virtual code of 〇 has already been explained. Going back to Figure 4, when the third row/column is processed (the first lap), Processing-Pixel-3 (695) is set to true, and the others are false. Based on the conditions for PQUANT, ABS(AO), and CLIP, an intermediate variable DO-FILTER is recorded, regardless of whether P4/P5 is updated. Finally FILTER—OTHER 3 22Clienfs Docket No. :S3U06-0011 TT’s Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 22 200803528 #. The value of (699) is set from the intermediate variable D0_FILTER. The result of the row acceleration logic circuit 500 of the logic circuit portion of FIGS. 6C and 6 is that the pixel position of P4 and P5 in 4 adjacent columns/rows is set as a filtered value every 4 cycles (according to AO-A3, PQUANT, CLIP, etc. variables) or write their original values again. The VC-1 deblocking acceleration unit 400 pioneered the combination of parallel and sequential, as previously described. Parallel processing provides faster execution delays. Although parallelization increases the number of logic gates, the increase_quantity is offset by the sequential processing of the other. The number of logic gates is not increased by using the above-described sequential processing method. Deblocking Filter One of the embodiments of the deblocking filter (IPF) specified by VC-1 has been described above. Some embodiments of graphics processing unit 120 include a hardware acceleration unit for H.264 deblocking. Those familiar with the art should be familiar with the square-effect filter in the H.264 loop, so only * a brief overview of the filtering operation. H. 264 loop despeckle effect filter is a conditional filter applied to all graphs

A 4X4 square edge, unless the Disable—DeblockinfFilter—IDC is defined as the edge. The filter is applied sequentially to all of the giant tiles to increase the giant tile address. For each giant block, the vertical edges are first filtered from left to right, then horizontally from top to bottom (the opposite order of VC-1 application). Thus, the tiles from the top and left of the current giant block are used. The sample values of the giant block filtered and filtered may be filtered again. 23Clienfs Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW7final/林环辉/2007/06/14 23 200803528 ' Η· 264 In-Circuit Deblocking Filter Hardware Acceleration Unit 700 Some advanced features The virtual code description will be described in conjunction with the hardware of FIG. Although not using a virtual hardware description language (HDL), such as Verilog and VHDL, a virtual code is used, and those skilled in the art should be familiar with these virtual codes. These individuals should be aware that when described in actual HDL, these codes should be compiled and then synthesized into a number of logic gate configurations that form part of the video acceleration unit 150. These people should be aware that these logic gates can be implemented in a variety of technologies, such as a specific application • an integrated circuit (ASIC), a programmable logic gate array (PGA), or a field-programmed logic gate array (FPGA). The 710-segment module definition of this code (m〇(iule definition). Η· 264 loop-in-blocking filter hardware acceleration logic circuit 7(10) has many input parameters. The sub-block to be filtered is determined by the block parameter ( Block parameter) If the vertical parameter is True, the acceleration logic 7 considers the block parameter as a 4x8 block and performs vertical edge filtering. If the vertical parameter is false (10), The acceleration logic then treats the block parameters as 8x4 squares (see Figure 3) and performs horizontal edge filtering. The section 720 of the code begins - iterati〇n loop, which sets the value of the loop parameter variable. Using these parameters, the block-effect filter hardware acceleration logic circuit in the 264 loop is repeated 4 times, each time processing 8 pixels, where - the line can be - horizontal column or vertical line, depending on the vertical parameters . As will be described in more detail below, each line is executed twice by the line acceleration logic circuit 800 (see Fig. 8). 24Client’s Docket N〇.:S3U06-0011 TT’s Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 24 200803528 Section 730 tests the vertical parameters to determine the vertical or horizontal edge filtering. Based on the result, the 8 elements of the row array variable are initialized from the row of the 4 8 input = block or the 8 x 4 input block. When instantiated, the code of section 730 in conjunction with section 72's crystal code becomes multiplexed and bit-located logic (sometimes referred to as reassembly logic, swizzling l〇gic) According to the code description, 'moving the bit from the input block of the memory to the appropriate bit position in the p temporary storage boundary. It should be noted that the analogy for the VC-1 deblocking filter 400 in Fig. 4 of the code 2 of the sections 720, 73 is the same as the analogous. As a result of this selection, a single multiplex/recombination logic circuit block is generated and used in the 264 internal loop deblocking filter logic circuit 700 and the VC-1 loop deblocking filter circuit 400. The section 750 retrieves the parameters used in the actual filter from the information contained in the 1264 instructions provided by the graphics processing unit 12A. The bs (boundary second degree) and chromaEdgeFlag parameters are used in the H264 loop to block filtering and are familiar to those skilled in the art. The parameters i and indexB correspond to the alpha and beta parameters used in the H.264 loop deblocking filter, which are also familiar to those skilled in the art. One of the inventive features of the graphics processing unit 120 is that the incjeXA, indexB, and bS parameters are not calculated by the block motion filter hardware acceleration logic circuit 700 in the H.264 loop, but by the execution unit 940 within the graphics processing unit 12. Calculation (described later in conjunction with Figure 9). By using 25Clienfs Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 200803528 EU instruction to realize the calculation of bS, indexA, indexB, can be executed by the graphics processing unit The operational power of unit 940 and the general purpose, the in-loop deblocking filter hardware acceleration logic circuit 7 (10). This choice avoids the need for additional, potentially complex logic circuits in the loop to remove the block effect filter hardware acceleration logic. In another embodiment, the parameters, indexA, indexB are computed by the code executed on the main processor 11 (see Figure i). Section 750 illustrates another HDL module, H264-Deblock-Filter-Line, which applies the current line. The parameters supplied to the submodule include control variables taken from the above EU commands, and the LeftTop parameter. One of the groundbreaking features of the logic circuit 7 calls the line filter twice, with only half of the pixels updated per call, with the updated half being indicated by the LeftTop parameter. This design measures the number of logic gates but requires more clock cycles. Those skilled in the art should understand how to model the filter line module with different parameter values to produce different logic blocks for rain, with inputs such as two halves of the pixel block. After the sub-module processes the column, the hardware acceleration logic circuit 7 continues the iteration loop with a loop parameter update value in segment 720. In this way, apply H264J)eblock_Filter_Line to lines 1-4 of the input box. 8A, B show a hardware description virtual code for row acceleration logic circuit 800 that implements the H264_Deblock_Fi 1 ter_Line submodule described above. As shown in FIG. 8A, the row module 800 is divided into a module definition block 810, a corresponding parameter block 820, and a calculation pixel block 830. Those familiar with the art should be able to understand the module definition block 26Client's Docket N〇 from the code of 8A::S3U06-0011 TT's Docket No:0608-A41238-TW/final/林璟辉/2007/06/14 26 200803528 810, will not be explained. Corresponding parameter block 820 calls the other rain subroutine (described in conjunction with FIG. 8B) to correspond to the parameter IndexA' IndexB provided by the H.264 loop deblocking filter hardware acceleration logic circuit 700 to the alpha and beta parameters. Alpha and Beta, and ChromaEdge Flag, are then used by section 830 to apply the filter by calculating new pixel values based on alpha, beta, ChromaEdge and neighboring pixel values. The actual virtual code for the segment is not shown, as those skilled in the art should know how to implement a deblocking filter for 10 single rows, as described in the H.264 specification. The groundbreaking features of row acceleration logic circuit 800 are further illustrated in the logic section, getAlphaBeta 850 and getThreshold 870, shown in Figure 8B. These logical sections correspond to the subroutines used by the corresponding parameter section 820 of Figure 8A. As shown in Fig. 8B, the read only memory (ROM) table uses the relative Apha and Beta values from IndexA and IndexB. Similarly, the ROM table is used to calculate the threshold. In some embodiments of graphics processing unit 120, wherein the H.264 deblocking function is implemented by graphics processing unit instructions. The graphics processing unit 120 will be described in greater detail in conjunction with FIG. 10, emphasizing the particular selection of graphics processing unit instructions to implement H.264 deblocking acceleration. The principle of the multi-departition effect instruction of the graphics processor The instruction set of the graphics processing unit 120 is included in the software. The partial decoder 160 can be used to accelerate a deblocking filter. 27Client's Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 27 200803528 A groundbreaking technology provides more than one multi-graphics processing single 70 command to speed up specific Go to the block effect filter. The in-plane deblocking filter 290 is originally sequential, so a particular filter must filter the pixels in a certain order (e.g., EL 264 specifies from right to right and then top to bottom). Thus, previously filtered or updated pixels are taken as input when filtering the back pixels. The main processor processes the pixel values stored in the conventional memory' which causes the pixels to be read and written one by one. However, the nature of this sequence cannot be properly coordinated when the block-in-band filter 290 in the loop uses the /graphic processing unit to speed up the partial filtering process. Conventional graphics processing soap cells store pixels in a texture cache and the graphics processing unit pipeline design does not follow one-to-one (back-to-back) read and write texture caches. It is disclosed herein that some embodiments of graphics processing unit I20 provide multiple graphics processing unit instructions that can be used together to speed up a particular deblocking filter. Some of these instructions use texture cache as a pixel data source, while some instructions use a graphics processing unit execution unit as a data source. The in-loop deblocking filter 290 suitably uses these different graphics processing unit instructions to achieve read and write pixels one after the other. The following is a summary of the data flowing through the graphics processing unit 120, followed by the interpretation of the deblocking acceleration command provided by the graphics processing unit 120 and the in-loop deblocking filter 290. Graphic Processing Unit Flow Figure 9 is a diagram of the data flow of the graphics processing unit 120, wherein the instruction stream is from the left arrow of Figure 9, and the image or graphics stream is from the right arrow 28Client5s Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/final/林璟辉/2007/06/14 28 200803528 ' Figure 9 omits several components that are familiar to those skilled in the art, and it is not necessary to interpret the in-loop deblocking features of the graphics processing unit 12〇. An instruction stream processor 910 receives an instruction 920 from a system bus (not shown) and decodes the instruction to generate instruction material 930, such as vertex data. Graphics processing unit 12 supports a conventional graphics processing instruction and instructions for accelerating video encoding and/or decoding. Conventional graphics processing instructions involve problems such as vertex shading, geometry shading, and pixel shading. Thus, the instruction material 930 is applied to a pool 940 of shader execution units. Execution unit 940 necessarily uses a texture filter unit (TFU) 950 to apply a texture to a pixel. The texture data is cached from the texture cache 960, which is appended to the main memory (not shown). Some instructions are sent to the video accelerator 150, the operation of which will be described later. The resulting data is then processed by a post-packer (post-packer 970) which compresses the data. After post-processing, the data generated by the video acceleration unit is provided to an execution i on unit pool 940. The execution of the video encoding/decoding acceleration instructions, such as the aforementioned de-blocking filtering instructions, differs in many respects from the conventional graphics instructions described above. First, the video acceleration command is executed by the video acceleration unit 150 instead of the shader execution unit. Second, the video acceleration instructions do not use their texture data. However, the image data used by the video acceleration command and the texture data used by the graphics commands are both 2-dimensional arrays. The graphics processing unit 120 is similar to 29Client's Docket No.: S3U06-0011 TT, s Docket No: 0608-A41238-TW/fmal/林璟辉/2007/06A4 29 200803528 With this advantage, the texture filtering unit 950 is used to download to the video acceleration unit 150. The image data thus makes the texture cache 96 〇 to capture some of the scenes operated by the video acceleration unit 150. Therefore, as shown in Fig. g, the video acceleration unit 150 is located between the texture filtering unit 950 and the post-packer gw. The texture filter unit 905 checks the instruction material 930 retrieved from the instruction g 2 . The instruction material 930 further provides a coordinate of the desired image highlight in the texture filtering unit 950 texture cache 9β. In one embodiment, these coordinates indicate that ❿ is U, V pairs. Those skilled in the art should be familiar with this. When the instruction 920 is a video acceleration command, the captured instruction material further instructs the texture filtering unit 950 to skip the texture filter (not shown) in the texture filtering unit 950. According to this method, the texture filtering unit 950 is manipulated as a video acceleration command to download image data to the video acceleration unit 150. The video acceleration unit 150 receives the image data from the texture wave unit 905 on the data path, and the command material 930 on the command path, and performs an operation on the image data according to the command data 930. The image data output by the video acceleration unit 150 is fed back to the execution unit pool 940 after being processed by the post wrapper 970. Deblocking Instructions The embodiment of graphics processing unit 120, described herein, provides a VC-1 deblocking filter and H.264 deblocking filter hardware acceleration. The VC-1 deblocking filter is accelerated by a graphics processing unit instruction ("IDF_VC-1"), while the H.264 deblocking filter is commanded by three graphics processing units. 30Client's Docket N〇_:S3U06-0011 TT ,s Docket No:0608-A41238-TW/fmal/林璟辉/2007/06八4 30 200803528 IDF_J264—2”) ("IDF-H264_0", "idF_H264_J" acceleration. As described earlier, 'each graphics processing unit command system Decoded and parsed into instruction material 930, which can be regarded as a specific number of sets of instructions 'shown in the first table. IDF_H264_X instructions share some common parameters, while others are unique to each instruction. The skilled artisan should understand that these parameters can be encoded using various opcodes and instruction formats, so these topics will not be discussed here. Table 1 · IDFJI264 Instruction Parameter Parameter Size Operation Unit Description FieldFlag (Input) 1-bit If FieldFlag == 1 then Field Picture, Other Frame Picture TopFieldFlag (Input) 1-bit If TopFieldFlag = 2, then Top-Field-Picture, Other Bottom-F i e1d-P i cture If set FieldFlag. PictureWidth (Input) 16-bit, for example, 1920 PictureHeight (Input) 16-bit for HDTV For example, 1080 YC Flag 1-bit Control-2 Y plane or chroma plane 31Clienfs Docket for 30P HDTV N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 31 200803528

Field Direction 1 - Bit Control-1 CBCR Flag 1-bit Control-1 -_ - — —- Cb or Cr __ BaseAddress (Input) 32-bit unsigned for IDF_H64_0 and IDFJ6〇: in texture memory Sub-block basic address ___-BlockAddress (Input) 13.3 format, omit the fractional part SRC1[0:15] SRC1[31:16]-V for IDF_H64_0: texture sub-for the whole sub-block (about basic address) IDF—Η64__1: The texture coordinates of the remaining sub-blocks (for the basic address) are not used in IDF_H64_2. DataBlockl 4x4x8-bits are not used in IDFJH64—0. SRC2[127:0] is used for IDF—H64J: the first half of the sub-block Or left half, FilterDirection SRC2[127:0] according to Control 2 parameter is used for IDF-H64~2: first (even) register pair DataBlock2 4x4x8-bit in IDF-H64-0 or IDF —32Client5s Docket No. is not used in H64-1. S3U06-0011 TT's Docket No:0608, A41238-TW/fmal/林璟辉/2007/06/14 32 200803528 SRC2[255:128] ---- For IDF— H64_2: second (odd) register to Sub-block 128-bit, --- The blocking effect (Output) Element 8x4x8-bit sub-block --- (128-bit) number of input parameters used in determining binding by the texture filter unit 950 of the 4x4 block fetch address. gaseA (the idress parameter indicates the starting point of the texture data in the texture cache. The upper left square of this area is given to

BaseAddress parameter. The pictureHeight and PictureWidth rounding parameters are used to determine the range of the square, the lower left coordinate. Finally, the video graphic can be a progressive scan (pr0gessive) or an inter 1 ace. Right is the interlaced broom', which consists of two directions (below the upper pawn). The texture wave early 950 uses F i e 1 dF 1 ag pseudo TopFieldFlag to properly process the interlaced scanned image. The deblocking 8x4x8 bit output system is provided for a target temporary cry, and is also written back to the execution unit pool 940. Writing the deblocking effect back to the execution unit pool 940 is a "modify in place" operation, which is necessary in some decoder implementations, such as Η·264 where the pixel values in the square, right Below, it is calculated based on the previous results. However, the decoder does not have this limitation relationship like H.264. In VC-1, each 8χ8 boundary (first vertical and then horizontal) is filtered. All vertical edges can thus be performed substantially in parallel, with the 4x4 edges being filtered later. Parallelization can be utilized because only two pixels (one edge) are updated, and these pixels are not 33Clienfs Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 33 200803528 - Used to calculate other edges. Since the deblocking data is written back to the execution unit pool 940 instead of the texture cache 960, a different H264-X instruction is provided that the sub-blocks are retrieved from different locations. This can be seen in the first table, in the description of BlockAddress, the Data Block 1 and Data Block 2 parameters. The IDF-H264-0 instruction fetches the entire 8x4x8 sub-block from texture cache 960. The IDF-H264-1 instruction fetches half of the sub-blocks from texture cache 960 and fetches half from execution unit pool 940. The function of the IDF-H264-X command as a function of decoder 160 will be described in more detail in connection with FIG. Next, the processing of converting the captured pixel data by the texture filtering unit 950 and the execution unit pool 940 before supplying the pixel data to the video acceleration unit 15A will be described. The instruction parameters of the image data are provided to the texture filtering unit 950 for the coordinates of the sub-block address to be extracted from the texture cache 960 or from the execution unit pool 940. The image data contains the brightness (Y) and chroma (Cb, Cr) planes. A YC flag ^ The input parameter defines whether to process the Y plane or the CbCr plane. When processing the luminance (Y) data, as indicated by the YC flag parameter, the texture filtering unit 950 retrieves the sub-block and provides the 128-bit as a VC-1 loop deblocking filter hardware acceleration logic circuit 40. 〇 input (such as the block input parameter of the VC-1 accelerator example in Figure 4). The resulting data is written to the target scratchpad as a set of 4 registers - register (ie, DST, DST+1, DST+2, DST+3). When processing chroma data, as indicated by the YC flag parameter, Cb and 34Clienfs Docket N〇.:S3U06-0011 IT's Docket No:0608-A41238_TW/fmal/林璟辉/2007/06/14 200803528 Sai, Cr The block-effect filter hardware acceleration logic circuit 400 will be continuously processed by the VC-1 loop. The resulting data is written to texture cache 960 °. In some embodiments, this write action occurs in each cycle, with 256 bits written per cycle. Some video acceleration unit embodiments use interlaced sweeping CbCr planes, each of which is half the width and half the length. In these embodiments, the texture filtering unit 950 de-interlaces the CbCr sub-block data for the video acceleration unit to communicate with the texture filter, the wave unit 950, and the video acceleration unit 15 . In particular, texture filtering unit 950 writes two 4x4 Cb blocks to the buffer, and then writes two 4x4 Cr squares to the buffer. The 8χ4 Cb block is first processed by the vc-1 loop to the block effect filter hardware acceleration logic circuit 400, and the resulting data is written to the texture cache 96〇. Next, the 8x4 Cr block is processed by the block-effect filter hardware acceleration logic circuit 400 in the VC-i loop, and the generated data is written to the texture cache 96 〇. The video acceleration unit 150 uses the CbCr flag parameters to manage this sequential processing. Spring Using the Square Blocking Command In conjunction with the previous Figure 1, the decoder 160 executes on the main processing crying 11 但 but also utilizes the video acceleration command provided by the graphics processing unit 120. In particular, the embodiment of the H.264 loop deblocking filter 290 uses a specific IDF-H264-X combination to process the edges, extracting some sub-blocks from the texture cache 960 and executing them in the order specified by H.264. The cell pool picks up some others. With proper combination, these IDF-H264-X instructions achieve one pixel read and write. 35Clienfs Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/final/林璟辉/2007/06/14 35 200803528 α ·* ν Figure 10 is the block for the 16x16 giant block of Η·264 Figure. This giant tile is cut into 16 4x4 sub-blocks, each of which will perform a deblocking effect. The four sub-blocks in Figure 10 can be defined by columns and rows (for example, R1, C2).丨 264 defines the processing of the vertical edges at the processing horizontal edges, as shown in Figure 10 (a-h). Therefore, the deblocking filter is applied to the edge between a pair of sub-blocks, and the sub-block pairs are filtered in this order, wave edge a = [block to left of R1, C1] | [Rl, Cl]; [block To • left of R2,C1] I [R2,C1]; [block to left of R3, Cl] I [R3, Cl]; [block to left of R4,C1] I [R4,C1] edge b[ R1,C1] I [R2, C2] ; [ R2, Cl ] | [R2, C2]; [R3,C1] I [R3,C2] ; [ R4,C1] I [R4,C2]; edge c II [R1,C2] I [R2,C3] ; [ R2,C2] | [R2,C3]; [R3,C2] I [R3,C3] ; [ R4,C2] I [R4,C3]; edge d =[Rl,C3] I [R2,C4] ; [ R2,C3] | [R2,C4]; ❿ [R3,C3] I [R3,C4] ; [ R4,C3] I [R4,C4]; Edge e= [block to top of R1,C1] | [Rl,Cl] ; [block to top of R1,C2] I [R1,C2]; [block to top of Rl,C3] I [Rl, C3] ; [block to top of R1,C4] I [R1,C4] edge f2[R1,C1] I [R2,C1] ; [R1,C2] | [R2,C2]; [R1,C3] I [ R2,C3]; [R1,C4] | [R2,C4] edge g2[R2,C1] I [R3,C1] ; [R2,C2] | [R3,C2]; 36Clienfs Docket No. :S3U06- 0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 36 200803528 [R 2,C3] I [R3, C3]; [R2,C4] | [R3, C4] edge h-[R3, Cl] | [R4, Cl] ; [R3?C2] | [R4, C2]; [ R3, C3] I [R4, C3]; [R35C4] | [R4?C4] For the first pair of sub-blocks, the texture cache 96 is downloaded, since no pixels have been changed due to the application of the filter. Although the filter of the i-th vertical edge (a) is such that the pixel value of (R1, C1) can be changed, the vertical edge of the second column actually shares all the pixels with the vertical edge of the column. Therefore, the second bell block (edge b) is also downloaded from the texture cache 960. Since the vertical edges between two adjacent columns do not share the same, the third pair (edge c) and the fourth pair (edge d) sub-blocks. The specific IDF-H264-X command issued by the in-loop deblocking filter 29 determines that the pixel data is to be downloaded from that location. The order of processing the first vertical edge (a) by the IDFJI264-X instruction used by the in-loop deblocking filter 290 is: IDF - H264 - 0 SRCl - address of (R1, C1); Spring IDF_H264 - 0 SRCl ^ address Of (R2, Cl); IDF—H264—0 SRCl^address of (R3, C1); IDF_H264—0 SRCl=address of (R4, Cl); Next, the in-loop deblocking filter 290 processes the second vertical Edge (b), starting with (Rl, C2). The leftmost 4 pixels in the 8x4 sub-block defined as (ri, C2) overlap with the rightmost pixel of the (Rl, Cl) sub-block. These are processed by the vertical edge filter of (Rl 'C1) and may also be updated, and the weight of the pixel is thus read from the execution unit pool 940 instead of the texture cache 960. However, the 4 pixels on the far right of the (Rl, C2) sub-block have not been filtered, so 37Client, s Docket No. : S3U06-0011 TT's Docket No: 0608-A41238-TW/fmal/林环辉/2007/ 06/14 200803528

Read from texture cache 960. Sub-blocks (R2, C2) to (R4, C2) are also the same. The in-loop deblocking filter 290 performs the result by commanding the following IDF-H264-X sequence to process the second vertical edge (b) to complete the result: IDF-H264-1 SRCl^address of (R1, C2); IDF_J264j SRCl=address of (R2,C2); IDF—H264—1 SRCl-address of (R3?C2); IDF—H264—1 SRCl-address of (R4?C2); When processing the 3rd vertical edge (c) , starting with (R1, C3). The leftmost 4 pixels in the (ri, C3) 8x4 sub-block overlap with the rightmost pixel of the (R1, C2) sub-block, and thus are read from the execution unit pool 940 instead of the texture cache 960. However, the 4 pixels to the far right of the (Rl, C2) sub-block are not yet filtered, so they are read from texture cache 960. The sub-blocks (Rl, C2) to (R4, C2) are also the same. A similar situation occurs at the last vertical edge (d). Therefore, the in-loop deblocking filter 290 processes the remaining 2 vertical edges c and d by ordering the following IDF_H264_x: IDF_H264-1 SRCl=address of (R1, C3); IDF-H264-1 SRCl= Address of (R2,C3); IDF_H264-1 SRCl^address of (R3?C3); IDF_H264-1 SRCl=address of (R4,C3); IDF_H264-1 SRCl^address of (R1,C4); IDF-H264 —1 SRCl-address of (R2, C4); IDF_H264_1 SRCl-address of (R3, C4); IDF_H264_1 SRCl^address of (R4, C4); The horizontal edge (eh) is then processed. At this point, the deblocking filter has been 38Client’s Docket N〇.:S3U06-0011 TT,s Docket No:0608-A41238-TW/final/林璟辉/2007/06/14 38 200803528

Applies to each sub-block in the giant tile, so each pixel may have been updated. Therefore, each sub-block sent to perform horizontal edge filtering is read from execution unit pool 940 instead of texture cache 960. Therefore, the in-loop deblocking filter 290 processes the horizontal edge by ordering the following IDF_H264_x: IDF_H264_2 SRCl=address of (R1, C1); IDF_H264_2 SRCl^address of (R2, C1); IDF-H264-2 SRC1 Address of (R3, Cl); IDF_H264-2 SRCl=address of (R4,Cl); IDF-H264-2 SRCl=address of (R1,C2); IDF-H264-2 SRCl^address of (R2,C2 IDF_H264_2 SRCl^address of (R3, C2); IDF_H264_2 SRCl=address of (R4, C2); IDF-H264-2 SRCl=address of (R1,C3); According to this method, the complex filtering operation is through the graphics The processing unit instruction set is implemented. The entire deblocking filtering operation is often too complex to be implemented as a single instruction filter. For example, the H·264 filter is too complex, including horizontal and vertical paths. In addition, the block size is also quite large. Therefore, instead of constructing a hardware management filter, it is better to combine the individual instructions (for example, macros) in sequence, and these sequences of instructions are used to process 4x4 blocks. This makes it possible to use the execution unit resources, which are ready, thus minimizing the need for complex control structures in the block effect filter in the loop, thus reducing the hardware and memory in the in-loop deblocking filter unit. The needs of the body. On the other hand, these filtering instructions are implemented in the deblocking filter 290 instead of the instructions executed on the execution unit 39Clienfs Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007 /06/14 39 200803528 * # - Implementation is advantageous because the filter contains some scalar operations (such as data reorganization, table lookup, conditional filtering), which is not for vector-based execution units. efficient. Any block diagram in a program description or flowchart should be understood to mean a module, segment or portion of code containing one or more executable instructions for implementing steps in a particular logic circuit or in a private sequence. . Those skilled in the software department should be aware that other implementation methods are also included in the scope of the disclosure. In other implementations, the functions may be performed out of the order shown or disclosed, including substantially synchronous or reverse, depending on the functionality involved. The systems and methods disclosed herein can be implemented in software, hardware, or a combination thereof. In some embodiments, the system and/or method is implemented in software stored in memory and executed by a suitable processor located in a computing device (including but not limited to a microprocessor, microcontroller, network Road processor, can be reassembled processor, expandable processor). In other embodiments, the 哕 system and/or method is implemented by a logic circuit, including but not limited to a programmable logic device (PLD), a programmable gate array (PGA), and a field. A programmable gate array (FPGA) or an application specific circuit (ASIC). In other embodiments, this logical statement is done in a graphics processor or graphics processing unit (GPU). The systems and methods disclosed herein can be embedded in any computer readable medium and used to execute a system, device, or device. The instruction is executed 4〇aient, s Docket N〇.:S3U06-0011 TT’s Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 200803528

The system includes any computer-based system, a system containing a processor, or other system that can retrieve and execute these instructions from the instruction execution system. The computer-readable medium can be any tool that can be used to store, store, communicate, transfer or transfer the program for use or in connection with the execution system of the instruction. The computer readable medium can be, for example, a non-limiting example of a computer readable medium that uses electronic technology for a system or medium that is electronically based, magnetic, optical, electromagnetic, infrared, or semiconductor technology. (non-restrictive) may include: a line with one or more electrical (electronic) connections; - random access memory (RAM); - read-only memory (ROM, read-only memory) ; Can be erased to be programmable (EPROM or flash memory). Computers using magnetic technology; specific examples of media 2 (non-restrictive) may include: specific examples of computer readable media that can carry computer disk m technology (non-restrictive) can be packaged, fiber, and portable CD-ROM (CD-ROM). The present invention is illustrated and described herein by way of example only, and the invention is not limited by the scope of the invention, and without departing from the spirit of the invention. A number of different modifications and structurally equivalent alpha changes are implemented within the scope and scope of the patent application. Therefore, the scope of the patent application attached is widely and in a pervasive manner, and is presented before the scope of the subsequent patent application. [Illustration of the drawing] The exemplary first figure is for graphics and video coding. And/or decoding of 41Client, s Docket N〇,: S3U06-0011 TT's Docket No: 0608-A41238-TW/final/Lin Huanhui/2007/06/14 200803528 Block diagram of the computing platform. Figure 2 is a block diagram of the video decoder 160 in Figure 1. Figure 3 illustrates the sub-block pixel settings of a VC-1 filter. Figure 4 is a first block of the VC-1 loop deblocking filter hardware. The hardware of the acceleration logic circuit 400 describes a list of virtual codes. Figure 5 is a list of hardware description language code for the acceleration logic circuit 500 of Figure 4. Figure 6A-D shows a block diagram of the acceleration logic circuit of lines 4 and 5. Figure 7 H. 264 loop de-blocking filter hardware acceleration unit 700 hardware description virtual code. The 8A and 8B diagrams show the hard description virtual code for the line acceleration logic circuit 8〇〇. Figure 9 is a data flow diagram of the graphics processing unit 12 of Figure 1. Figure 10 is a block diagram of a 16x16 giant tile used by H.264. [Main component symbol description] 100~ system, 110-- general purpose CPU, 120~ graphics processor (GPU), 130~memory, 140~bus, 150~video acceleration unit (γρυ), 160~soft decoder , 170~ video acceleration drive. 205~ input bit stream, 210~en entropy decoder, 215~space decoder, 220~inverting quantizer, 230~inverted discrete cosine transform, 235~ graphics, 245~moving vector, 250~moving compensation, 255 ~ Previously decoded graphics, 265~predicted graphics, 270~space compensation, 280~adder, 290~deblocking filter 42Client's Docket No.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/ 06/14 200803528 '' Waves, 295~ decoding graphics. 310-320 ~ two adjacent 4x4 sub-squares, 330 ~ vertical boundaries. 400~loop to block effect filter hardware acceleration logic circuit, 41〇~ module definition section, 420~ iteration loop section, 430~test vertical parameter section, 440~ comparison loop parameter and 3 zone Segment, 450~ example section. 500~row acceleration logic circuit, 510~module definition section, 520~pixel value luth operation section, 530~ comparison loop parameter and 3 section, 540~test DCLFIuer section, 550~update status section. 605-610-615-620 ~ multiplexer, 625-630-679 ~ subtractor, 635-640-655-680 ~ logic circuit block, 645-650 ~ adder, 660-665-670 ~ register, 671~P4 register output, 673~P5 register output. 681~Subtractor, 685~Adder. 687-689-691-693~ multiplexer, 697~OR gate. 10 700~Η·2β4 loop deblocking filter hardware acceleration unit, 71〇~module definition section, 720~ iteration loop section, 730~test vertical parameter section, 740~take parameter area Segment, 750~ example section. 800 to line acceleration logic circuit, 810 to module definition section, 82 〇 to corresponding table number section, and 830 to pixel calculation section. 910~ instruction stream processor, 920~ instruction, 930~ instruction data, 94〇~ execution unit pool, 950~texture filter unit, 960~ texture cache, 97〇~after 43Client, s Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/final/林璟辉/2007/06/14 43 200803528 ” Wrapper. 44Client5s Docket N〇.:S3U06-0011 TT's Docket No:0608-A41238-TW/fmal/林璟辉/2007/ 06/14

Claims (1)

200803528 ^ X. Patent application scope · 1. A graphics processing unit includes: a decoder configured to decode a first and a second deblocking filter gain acceleration command, the first and second deblocking filter accelerators The instructions are each associated with a deblocking filter used by a particular video decoder; and a video processing unit configured to receive the first parameter encoded by the first deblocking filter glitch acceleration command, and Determining, by the receiving first parameter, a first memory source, the first memory source being located in one of a plurality of memory sources of the graphics processing unit, and receiving the second deblocking filter Acquiring a second parameter encoded by the instruction, and determining a second memory source specified by the receiving second parameter, the second memory source being located in one of a plurality of memory sources of the graphics processing unit, wherein The video processing unit is further configured to download a first pixel data block from the determined first memory source, and apply the deblocking filter to The first pixel data block, and a second pixel data block is downloaded from the determined second memory source, and the deblocking filter is applied to the pixel data block. 2. The graphics processing unit of claim 1, wherein the plurality of memory sources are included in a texture cache and an execution unit in the graphics processing unit. 3. The graphics processing unit of claim 1, wherein the first memory source and the second memory source are used to achieve one pixel read and write. 45Client’s D〇cket N〇.:S3U06-0011 TT’s Docket No:0608-A41238-TW/final/林璟辉/2007/06/14 45 200803528 4. If the pattern of the i-th item of the patent application and the second memory source are both the graphic processing sheet _ /, the middle of the fifth. If the memory source of the patent item is in the graphics processing unit A 纟 70 /, the second memory source is in the graphics processing unit ^ &&; take the 'the hopper - the execution unit. 6. The graphic a < shape processing unit of claim 1 of the patent scope, the first and second memory sources of the first and second memory sources are the graphic processing single -: the second brother 7 · the graphic processing of the first item of the patent scope The unit, the bean two-way effect filter acceleration command system is related to Η. 264祯^ " The video processing unit used in the video transcoder includes: - the video processing unit 'μ is applied to one of the deblocking filters associated with the specific video decoder; the decoding is, and e is paired a plurality of deblocking filter acceleration instruction decoding associated with the deblocking chopper; a second texture unit configured to provide a pixel: #料到该视频处理单元' for the deblocking filter; An execution unit is configured to perform a graphics processing function on the pixel data, wherein the video processing unit is further configured to receive the parameter encoded by the deblocking effect, and determine that one of the parameters is specified by the receiving parameter a memory source corresponding to the texture filter unit or the execution unit 'and determining that one of the second memory sources corresponds to the texture filter unit or the execution unit specified by the receiving parameter; the video processing Early is set to download a 46Clienfs Docket N〇 from the first memory source.: S3U06-0011 TT's Docket No: 0608-A41238-TW/fmal/林璟辉/ 2007/06/14 200803528; * a pixel block, and downloading a second pixel block from the second memory source, and applying the deblocking filter to the first pixel data block and applying the deblocking filter Up to the second pixel data block, in accordance with the received parameters. 9. The graphics processing unit of claim 8, wherein the video processing unit is further configured to apply to the deblocking filter, the execution unit is further configured to calculate the at least one filter according to at least one filter parameter. The parameter is based on the first pixel data block. • 10. The graphics processing unit of claim 8 wherein the de-effecting filter acceleration command is associated with a chopper used by the 264264 video decoder. 11. The graphics processing unit of claim 8, wherein the first memory source defined by the receiving parameter corresponds to a texture filtering unit, and the second memory source defined by the receiving parameter corresponds to an execution unit. To achieve one pixel read and write. 12. The video encoder comprises: a plurality of execution unit instructions configured to calculate at least one deblocking filter configuration parameter associated with a pixel data block and a special video coding specification, and further configured to execute in a graphic a coloring execution unit within the processing unit; a plurality of deblocking effect instructions configured to apply to the deblocking filter conforming to the calculated filter configuration parameter, and further configured to execute in the graphics processing unit Video processing unit. 13·If you apply for the video encoder of the 12th patent range, the one should go to 47Clienfs Docket N〇.:S3U06-0011 TT s Docket No:0608-A41238-TW/fmal/林环辉/2007/06/14 47 200803528 The square effect filter is added to the instructional fish TT c^nA ^ ^ waver correlation.糸 糸 H H H H 遽 遽 遽 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 The de-blocking filter is used to control the ^^, A and 禝------the memory source, one is the pixel data block, and the other one is another ^ the Wei de-blocking filter, the wave source The first and second blocks define a second memory*. The feU is in the graph 16. As in the patent application, the first 15th in the patent range - V e _, /5 Α _Λ , the visual encoder, wherein the first sentence is a texture cache in the graphics processing unit. 2: the video encoder of the 15th item, wherein the first:: t: body source is in the graphic A texture cache is processed in the processing unit, and a memory source is an execution unit in the graphics processing unit. Λ, as in the video of the fifteenth patent application, wherein the first and the first Α龙源 are both The execution unit I9. in the graphics processing unit, such as the video encoder of the patent scope #12, wherein the de-square effect filtering The acceleration command is related to the H.264 video solution. ‘48Client’s Docket N〇.:S3U06-0011 TT’s Docket No:0608-A41238-TW/fmal/林璟辉/2007/06/14 48