[go: up one dir, main page]

Baldev et al., 2021 - Google Patents

A directional and scalable streaming deblocking filter hardware architecture for HEVC decoder

Baldev et al., 2021

Document ID
10393038578564041715
Author
Baldev S
Rathore P
Peesapati R
Anumandla K
Publication year
Publication venue
Microprocessors and Microsystems

External Links

Snippet

In this work, a directional streaming hardware architecture for Deblocking Filter (DBF) of High-Efficiency Video Coding (HEVC) decoder is presented. The architecture uses adaptive parallel and pipeline processing strategies for low power and high-performance applications …
Continue reading at www.sciencedirect.com (other versions)

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51Motion estimation or motion compensation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43Hardware specially adapted for motion estimation or compensation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/46Embedding additional information in the video signal during the compression process
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00Image coding, e.g. from bit-mapped to non bit-mapped
    • G06T9/007Transform coding, e.g. discrete cosine transform

Similar Documents

Publication Publication Date Title
Veredas et al. Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes
US8116379B2 (en) Method and apparatus for parallel processing of in-loop deblocking filter for H.264 video compression standard
US9351003B2 (en) Context re-mapping in CABAC encoder
US20080267293A1 (en) Video Encoder Software Architecture for VLIW Cores
Ben Atitallah et al. An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules
Kammoun et al. Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application
Baldev et al. A directional and scalable streaming deblocking filter hardware architecture for HEVC decoder
Kalali et al. An approximate HEVC intra angular prediction hardware
Azgin et al. A computation and energy reduction technique for HEVC intra prediction
Kopperundevi et al. A high throughput hardware architecture for deblocking filter in HEVC
Peesapati et al. Design of streaming deblocking filter for HEVC decoder
Shahid et al. Parallel H. 264/AVC fast rate-distortion optimized motion estimation by using a graphics processing unit and dedicated hardware
Baldev et al. Scalable wavefront parallel streaming deblocking filter hardware for HEVC decoder
Nunez-Yanez et al. A configurable and programmable motion estimation processor for the H. 264 video codec
Kopperundevi et al. An efficient hardware architecture for deblocking filter in HEVC
Kim et al. An efficient architecture of in-loop filters for multicore scalable HEVC hardware decoders
Doan et al. Multi-asip based parallel and scalable implementation of motion estimation kernel for high definition videos
Kopperundevi et al. Methods to develop high throughput hardware architectures for HEVC Deblocking Filter using mixed pipelined-block processing techniques
Babionitakis et al. A real-time H. 264/AVC VLSI encoder architecture
Liao et al. The algorithm and VLSI architecture of a high efficient motion estimation with adaptive search range for HEVC systems
Roszkowski et al. Intra prediction for the hardware H. 264/AVC high profile encoder
Verderber et al. HW/SW codesign of the MPEG-2 video decoder
Shafique et al. Hardware/software architectures for low-power embedded multimedia systems
Parlak et al. A low power implementation of H. 264 adaptive deblocking filter algorithm
OHIRA et al. A low power media processor core performable CIF30 fr/s MPEG4/H26x video codec