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TW200703006A - Back-off timing mechanism - Google Patents

Back-off timing mechanism

Info

Publication number
TW200703006A
TW200703006A TW095108028A TW95108028A TW200703006A TW 200703006 A TW200703006 A TW 200703006A TW 095108028 A TW095108028 A TW 095108028A TW 95108028 A TW95108028 A TW 95108028A TW 200703006 A TW200703006 A TW 200703006A
Authority
TW
Taiwan
Prior art keywords
retries
command
entry
timer expiration
expiration value
Prior art date
Application number
TW095108028A
Other languages
English (en)
Other versions
TWI305616B (en
Inventor
Shigehiro Asano
Tsutomu Ishii
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW200703006A publication Critical patent/TW200703006A/zh
Application granted granted Critical
Publication of TWI305616B publication Critical patent/TWI305616B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
TW095108028A 2005-04-06 2006-03-09 Back-off timing system and method for back-off timing TWI305616B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/100,081 US7290074B2 (en) 2005-04-06 2005-04-06 Back-off timing mechanism

Publications (2)

Publication Number Publication Date
TW200703006A true TW200703006A (en) 2007-01-16
TWI305616B TWI305616B (en) 2009-01-21

Family

ID=37064013

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095108028A TWI305616B (en) 2005-04-06 2006-03-09 Back-off timing system and method for back-off timing

Country Status (3)

Country Link
US (1) US7290074B2 (zh)
CN (1) CN100454279C (zh)
TW (1) TWI305616B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7373444B2 (en) * 2005-04-15 2008-05-13 Kabushiki Kaisha Toshiba Systems and methods for manipulating entries in a command buffer using tag information
TWI322354B (en) * 2005-10-18 2010-03-21 Via Tech Inc Method and system for deferred command issuing in a computer system
US7519752B2 (en) * 2006-02-07 2009-04-14 International Business Machines Corporation Apparatus for using information and a count in reissuing commands requiring access to a bus and methods of using the same
US7536584B2 (en) * 2006-06-08 2009-05-19 Dot Hill Systems Corporation Fault-isolating SAS expander
US7673185B2 (en) * 2006-06-08 2010-03-02 Dot Hill Systems Corporation Adaptive SAS PHY configuration
US7613859B2 (en) * 2007-09-12 2009-11-03 Kabushiki Kaisha Toshiba Back-off timing mechanism in a digital signal processor
KR101065480B1 (ko) * 2007-12-19 2011-09-19 한국전자통신연구원 저밀도 패리티 검사 부호의 고속 검사노드 갱신 장치 및 그방법
CN102547912B (zh) * 2012-01-17 2015-08-05 电信科学技术研究院 一种接入控制方法及装置
CN103226457B (zh) * 2013-04-28 2016-03-02 惠州市德赛西威汽车电子股份有限公司 一种显示处理器的显示控制方法
CN115933860B (zh) * 2023-02-20 2023-05-23 飞腾信息技术有限公司 一种处理器系统、处理请求的方法及计算设备

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784590A (en) 1994-06-29 1998-07-21 Exponential Technology, Inc. Slave cache having sub-line valid bits updated by a master cache
US6112019A (en) 1995-06-12 2000-08-29 Georgia Tech Research Corp. Distributed instruction queue
US5864707A (en) 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5897656A (en) 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US6147978A (en) * 1997-01-08 2000-11-14 Qualcomm Incorporated Method and apparatus for preventing message collisions in a half-duplex communication system
US6240479B1 (en) 1998-07-31 2001-05-29 Motorola, Inc. Method and apparatus for transferring data on a split bus in a data processing system
US6360308B1 (en) 1998-09-30 2002-03-19 Lsi Logic Corporation Buffer controller
US6473399B1 (en) * 1998-11-30 2002-10-29 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for determining an optimum timeout under varying data rates in an RLC wireless system which uses a PDU counter
US6732208B1 (en) 1999-02-25 2004-05-04 Mips Technologies, Inc. Low latency system bus interface for multi-master processing environments
US6772383B1 (en) 1999-05-27 2004-08-03 Intel Corporation Combined tag and data ECC for enhanced soft error recovery from cache tag errors
US6493776B1 (en) 1999-08-12 2002-12-10 Mips Technologies, Inc. Scalable on-chip system bus
US6490642B1 (en) 1999-08-12 2002-12-03 Mips Technologies, Inc. Locked read/write on separate address/data bus using write barrier
US6636906B1 (en) 2000-04-28 2003-10-21 Hewlett-Packard Development Company, L.P. Apparatus and method for ensuring forward progress in coherent I/O systems
US6820165B2 (en) 2000-08-31 2004-11-16 Hewlett-Packard Development Company, L.P. System and method for increasing the count of outstanding split transactions
US6694390B1 (en) * 2000-09-11 2004-02-17 Intel Corporation Managing bus transaction dependencies
US6658520B1 (en) 2000-09-26 2003-12-02 Intel Corporation Method and system for keeping two independent busses coherent following a direct memory access
US6728816B1 (en) * 2001-02-09 2004-04-27 Lsi Logic Corporation Simple mechanism for guaranteeing in order read data return on a split transaction bus
US7127562B2 (en) 2003-06-11 2006-10-24 International Business Machines Corporation Ensuring orderly forward progress in granting snoop castout requests
US7203780B2 (en) 2005-02-22 2007-04-10 Kabushiki Kaisha Toshiba System and method for facilitating communication between devices on a bus using tags

Also Published As

Publication number Publication date
CN1845085A (zh) 2006-10-11
CN100454279C (zh) 2009-01-21
US20060230205A1 (en) 2006-10-12
TWI305616B (en) 2009-01-21
US7290074B2 (en) 2007-10-30

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees