TW200605324A - Scalable planar DMOS transistor structure and its fabricating methods - Google Patents
Scalable planar DMOS transistor structure and its fabricating methodsInfo
- Publication number
- TW200605324A TW200605324A TW093122797A TW93122797A TW200605324A TW 200605324 A TW200605324 A TW 200605324A TW 093122797 A TW093122797 A TW 093122797A TW 93122797 A TW93122797 A TW 93122797A TW 200605324 A TW200605324 A TW 200605324A
- Authority
- TW
- Taiwan
- Prior art keywords
- ring
- region
- scalable
- source
- surrounded
- Prior art date
Links
- 238000009792 diffusion process Methods 0.000 abstract 6
- 238000002513 implantation Methods 0.000 abstract 4
- 239000004065 semiconductor Substances 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The scalable planar DMOS transistor structure of the present invention comprises a scalable source region surrounded by a planar gate region. The scalable source region comprises a p-base diffusion region being formed in a n- epitaxial semiconductor layer through a ring-shaped implantation window, a n+ source diffusion ring being formed in a surface portion of the p-base diffusion region through the ring-shaped implantation window, a p+ contact diffusion region being formed in a middle semiconductor surface portion through a self-aligned implantation window being surrounded by the ring-shaped implantation window, and a self-aligned source contact window being formed on the p+ contact diffusion region and the n+ source diffusion ring surrounded by a sidewall dielectric spacer. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on a gate dielectric layer and capped locally with or without metal-silicide layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW93122797A TWI246181B (en) | 2004-07-29 | 2004-07-29 | Scalable planar DMOS transistor structure and its fabricating methods |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW93122797A TWI246181B (en) | 2004-07-29 | 2004-07-29 | Scalable planar DMOS transistor structure and its fabricating methods |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI246181B TWI246181B (en) | 2005-12-21 |
| TW200605324A true TW200605324A (en) | 2006-02-01 |
Family
ID=37191345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW93122797A TWI246181B (en) | 2004-07-29 | 2004-07-29 | Scalable planar DMOS transistor structure and its fabricating methods |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI246181B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI812995B (en) * | 2020-08-13 | 2023-08-21 | 大陸商杭州芯邁半導體技術有限公司 | Fabrication method of SiC MOSFET device |
-
2004
- 2004-07-29 TW TW93122797A patent/TWI246181B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI812995B (en) * | 2020-08-13 | 2023-08-21 | 大陸商杭州芯邁半導體技術有限公司 | Fabrication method of SiC MOSFET device |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI246181B (en) | 2005-12-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |