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TW200605306A - Micro-electronic package structure - Google Patents

Micro-electronic package structure

Info

Publication number
TW200605306A
TW200605306A TW093121847A TW93121847A TW200605306A TW 200605306 A TW200605306 A TW 200605306A TW 093121847 A TW093121847 A TW 093121847A TW 93121847 A TW93121847 A TW 93121847A TW 200605306 A TW200605306 A TW 200605306A
Authority
TW
Taiwan
Prior art keywords
metal plate
circuit layer
chip
micro
package structure
Prior art date
Application number
TW093121847A
Other languages
Chinese (zh)
Other versions
TWI238509B (en
Inventor
Chu-Ching Hu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW093121847A priority Critical patent/TWI238509B/en
Application granted granted Critical
Publication of TWI238509B publication Critical patent/TWI238509B/en
Publication of TW200605306A publication Critical patent/TW200605306A/en

Links

Classifications

    • H10W70/09—
    • H10W70/60—
    • H10W72/241—
    • H10W72/874—
    • H10W72/884—
    • H10W72/9413—
    • H10W90/736—
    • H10W90/754—

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A micro-electronic package structure is proposed, wherein at least a semiconductor chip is disposed on a metal plate via a heat-conductive adhesive for dissipating the heat produced from the chip. At least an insulating layer and at least a circuit layer are formed on the metal plate, wherein the circuit layer is electrically connected to the chip via conductive structures. At least an opening is formed in the metal plate for embedding passive components, which are electrically connected to the circuit layer via conductive structures formed in the insulating layer. A plurality of conductive elements are formed on the circuit layer for providing the chip disposed on the metal plate to connect outside directly.
TW093121847A 2004-07-22 2004-07-22 Micro-electronic package structure TWI238509B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093121847A TWI238509B (en) 2004-07-22 2004-07-22 Micro-electronic package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093121847A TWI238509B (en) 2004-07-22 2004-07-22 Micro-electronic package structure

Publications (2)

Publication Number Publication Date
TWI238509B TWI238509B (en) 2005-08-21
TW200605306A true TW200605306A (en) 2006-02-01

Family

ID=37000291

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093121847A TWI238509B (en) 2004-07-22 2004-07-22 Micro-electronic package structure

Country Status (1)

Country Link
TW (1) TWI238509B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI413231B (en) * 2006-12-29 2013-10-21 育霈科技股份有限公司 RF module package

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101894825B1 (en) * 2011-10-03 2018-10-04 인벤사스 코포레이션 Stub minimization for multi-die wirebond assemblies with parallel windows

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI413231B (en) * 2006-12-29 2013-10-21 育霈科技股份有限公司 RF module package

Also Published As

Publication number Publication date
TWI238509B (en) 2005-08-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees