200536262 九、發明說明： 【發明所屬之技術領域】 一種提供遲滯值予 Λ谷受範圍的方法 本發明係關於輸入接受器，尤其是 輸入接受器，以提供輸入信號適當的雜 及裝置。 【先前技術】 在早期積體電路的設計中，互補 (鳴)輪出驅動器被規劃為推挽式元件。 路溫度、供應電壓及製造過程的差異，輸 ： =波動，而雜訊同時亦為匯集在積體電路之裝置數量 近年來’由於技術的進展，導致裝置尺寸及 逐乂的降低’設計者被迫更積積地在外部匯 = 問題’以使系統内的電路運作速度能最大化。最近工^ 器問題的觀念為自推_挽式輸出轉而趨向： 使用差動輸入接受器。差動輸入接受器的一側被 、 考電壓’另-側則由開路汲極血苓 開路汲肺_通道裝置#由晶衣i所㈣。典型的 則自曰^二 而匯流排拉昇電阻 則自曰曰片内或自外部提供，例如在系統主機板等。 上述類型的輸出驅動器盛行於工業界，由英代 f ntd)所開發的奔騰（Pentium)X86系列的微處理器就 I 一例。奔騰（Pentium)微處理器使用開路汲極队通出、 衣置驅動-UV匯流排，其參考間值為咖。較新的匯流 200536262 排規格則使用更低的電壓，例如參考閾值為0.83V的 1.25V匯流排。通常使用56歐姆拉昇終端，並且在拉降 阻抗則未指定時，開路汲極通道裝置被使用來符合匯流排 的切換及時序規格。工業界採用Assisted Gunning Transceiver Logic (AGTL ， Assisted Gunning Transceiver Logic ，援助發身于接 收邏輯電路）這個名稱來廣泛描述這類連接這類匯流排之 裝置。這些裝置被習稱為AGTL裝置或AGTL邏輯或簡稱 AGTL。 然而習知的輸入接受器在輸入信號具有高雜訊的場合 有其缺點。具有南雜訊的輸入信號會在積體電路上導致錯 誤觸發及不當運作上。就該些接受器，其觸發或切換的門 檻是由鄰近設計切換閾值的一電壓範圍所界定。而此一電 壓範圍的限制大致是由製造過程、操作溫度及操作電壓所 決定。其他輸入裝置如施密特觸發裝置（Schmidt Trigger device)被設計成可為輸入信號提供遲滯值，但乃是以降低 速度、增加耗能及額外的匯流排負擔等做為代價。 若依據較新匯流排規格而降低電壓，會使雜訊的容受 度隨之降低，而使雜訊問題愈形嚴重。因此亟須提供一種 輸入接受器，可以容受更高的雜訊，而仍能在匯流排操作 電壓下維持正確邏輯運算，包含在較新規格下的較低電 壓。亦為所亟需者乃是提供一種輸入接受器，可以取代習 知輸入接受器，而具有較高的雜訊免疫力，而不會付出如 現今使用遲滯值之裝置，像施密特觸發裝置的代價。 200536262 【發明内容】 《所欲解決之問題》 本發明所欲解決之問題為：提供一種使用滯後變動參 考值的輸入接受器，具有較高的雜訊免疫力，可以容受更 咼的雜訊，而仍能在匯流排操作電壓維持正確邏輯運算， 且無習知使用遲滯值裝置的缺點。 《解決問題之手段》 本發明之一實施例提供一種具有遲滯值的輸入接受 态，其包括.一差動放大器；一參考電路，其具有一參考 $點並產生一在標稱閾值電壓的參考信號；以及一切換堆 豐裝置。此一放大器具有接受一輸入信號之一第一輸入 端’，接至參考節點之-第二輸人端，以及—輸出端以提 供-第-輸出信號’該輪出信號具有第一及第二狀態以指 不^述輸入信號的狀態。此一切換堆疊裝置，連接差動放 大器輸出端及參考節點’並根據位於上或下閾值電壓之間 且與輪入信號相反方向的第一輸出信號，調整參抑號。 在本發明之一特定實施例中，輸入信號係提供^動 放大器的-反相輸入端’故而第一輸出信號與輸入信號在 相反的方向進行切換。在此實施例，還可以提供一 以反相第-輸出信號，進而提供一第二輪出： 入信號的狀態。 日不勒 此電路可以是一分壓器，其可劃分電源電壓以 產生茶考信號。此一參考電路具有一中節點，做為產生參 200536262 考信號用的參考節點。在一更明確的實施例中，此一分壓 器包含複數p-通道裝罝，該些p-通道裝罝在電源電壓信號 及接地端間，以串連方式相連接。每一 P-通道裝罝具有連 接在一起的一基體（bulk)和一源極（source)，及連接在一起 的一閘極(gate)和一沒極（drain)。就AGTL架構而言，第一 中節點提供一參考信號’該參考信號的標稱值約為電源電 壓信號的三分之二。 此切換堆疊裝置可包含一 P-通道裝罝及一 N-通道裝 置。此一 P-通道裝罝具有一源極連接至差動放大器輸出 端，及一閘極和一没極都連接至參考節點。此一 N-通道裝 罝具有一源極連接至差動放大器輸出端，一汲極連接至參 考節點，及一閘極連接至分壓器。在此一例子中，分壓器 可包含一第二中節點，該第二中節點連接至N-通道裝罝的 閘極。在AGTL架構中，第一中節點具有約為電源電壓信 號的三分之二的標稱電壓，，第二中節點具有約為電源電 壓信號的三分之一的標稱電壓。 依本發明之一實施例，本發明提供一積體電路，其包 括：一電源接腳及一接地接腳，二者共同接受一匯流排電 壓；一差動放大器，其由匯流排電壓提供電源；一參考電 路；及一切換電路。該差動放大器，具有一反相輸入端以 接受一輸入信號，一非反相輸入端以接受一參考信號，及 一輸出端以提供具有第一及第二狀態的一數位信號，用以 指示輸入信號的狀態。該參考電路橋接電源接腳及接地接 腳，並提供位於一標稱閾值電壓的參考信號。該切換電 200536262 路’連接至差動放大器的輸出端 態，調整參考信號至高或低於標稱閾= 電壓。 』丄、卜閾值 此二考電路可以建構成—種電阻式分壓器 -弟-中㈣’以提供參考信號。例如，此“二有 器可包含複數p_通道裝置，該些p•通道I置被昼 接腳及接地接腳之間。每—ρ·通道裝Μ 電源 -基體和源極’及連接在-起的1極和汲 致的電壓劃分。 乂達成一 包含包含一第二中節點;且此-切換電路可 匕3 Ρ_通迢裝置及一N-通道震置。此一 分別連接至第一中節點的一閘極和—汲極：置：有 放大器輸出端一源極。此一Ν_通道 ：：動 篦一 Φ雜β 及極連接至 弟中即.、、、占，一閘極連接至第二中節點， 差動放大器輪出端。在AGTL架構中，第接至 匯流排電壓的三分之二的標稱電 =約為 流排電壓的三分之-的標稱電壓。'―中即具有約為匯 依本叙明之一實施例，本發明提供一 值的輪人接受器之方法，其包括：提;_且=:有遲滞 壓的參考節點；以一差動放大器比較參考節== 入信號電壓，該差動放大器係在 及：二:、-輸 ，亍切換…動放大器切換至較高；低電壓 考節點雷厭r 干又门包座日寸’增加參 電麗時，減壓；及當差動放大器切換至較低 夕荟考郎點電壓至一下閾值電壓。 200536262 提供參考節點的一可能方式是：在電壓來源的端點間 堆疊複數個第一 P_通道裝置並形成一中節點。增加參考節 點，壓至上閾值電壓的一可能方式是：啟動連接至p_通道 堆，裝置之其他p_通道裝置。減少參考節點電壓至一下閾 值電壓的一可能方式是：啟動連接通道堆疊裝置之一 N_ 通逼裝置。以差動放大器比較參考節點電壓與一輸入信號 电壓的可此方式疋.當輸入信號電壓低於下閾值電壓， 差動放大器切換至較高電壓；及當輪入信號電壓高於上閾 值電壓，差動放大器切換至較低電壓。 《對於先前技術之效果》 本發明之具有遲滯值輸入接受器，具有較高的雜訊免 疫力，可以容受更高的雜訊，而仍能在匯流排操作電壓維 持正確邏輯運算，且無習知使用遲滯值裝置的降低速度、、 增加耗能及額外的匯流排負擔等缺點。 【實施方式】 下述内容可使此領域中具有通常技術者得據以實施本 發明，就本發明之較佳實施例所做的各種變更修飾，或將 揭露於此的技術思想再應用於其他實施例，對習於此項技 術者而言，係屬明顯而可輕易完成者。因此發明人並無意 將本發明限制於該些被描述於此的實施例，而是在符合本 發明所揭露的技術思想及新穎特徵之下，賦予本發明最廣 之權利範圍。 〃 10 200536262 由於發明人認知到具有適當雜訊容受範圍的輸入接受 器的需求，於是開發出一種具有遲滯值且較習知輸入接受 器更大雜訊容受範圍的輸入接受器及方法，其將參照第一 至第四圖描於下。 第一圖為習知輸入接受器100的示意圖，其係使用於 AGTL架構開路汲極匯流排。習知輸入接受器100包括： 一差動放大器U1 ，其具有一反相輸入端以接受參考信號 REF，一非反相輸入端以接受輸入信號PDPADIN ;及一輸籲 出端以提供輸出信號OUT。參考信號REF是自匯流排電源 信號VTT衍生到一切換閾壓值，VTT及REF係晶片外產生 並經由pads(未示於圖中）提供給晶片。在一 AGTL架構 中，匯流排電源信號VTT約為1.5V，而切換閾壓值REF貝|J 定為2/3 VTT—或約1.0V。當PDPADIN信號經REF信號， U1的轉換是被要求的。在所示構造中，當輸入信號 PDPADIN低於REF，輸出信號OUT在低值，而當輸入信號 PDPADIN高於REF，輸出信號OUT轉為高值。 < 當輸入信號PDPADIN具有高雜訊時，輸入接受器100 表現不佳。更且，依較新的匯流排規格，匯流排電源信號 VTT被降為1·25V ，參考信號REF則被降為約0.83V (1.25V 的2/3)閾壓值，雜訊容忍範圍亦被等比例的縮小，使得雜 訊的問題更難以被克服。如前所述，其他輸入裝置，例如 施密特觸發裝置（Schmidt Trigger device)，雖有提，一遲滯值 (hysteresis)予輸入信號，但此乃是以降低速度、增加耗能及 額外的匯流排負擔等做為代價。 200536262 第二圖為本發明一實施例之輸入接受器2⑻的示意 圖，其依據AGTL架構開路使用於汲極匯流排構造。其包 括一差動放大器U1以接受輸入信號PDPADIN。但在此一 輸入接受器200，輸入信號PDPADIN卻是提供給差動放大 器U1的反相輸入端，而另一個具遲滯值的參考信號 HREF則提供給非反相輸入端。差動放大器U1在其輸出 端顯示一 GRASS信號，此一 GRASS信號具有相對於輸入信 號PDPADIN狀態的反相狀態。輸入接受器200亦包括一反· 相器U2 ，其具有一輸入端以接受GRASS信號及一輸出端 以提供OUT信號，OUT信號為一非反相版的PDPADIN信 號。 參考信號HREF衍生自匯流排電源信號VTT並具有一 如同習知差動輸入接受器100之REF信號的標稱閾值。依 AGTL架構，如果VTT為1.5V，貝|J HREF具有1.0V的標稱 閾值，如果VTT為1.25V ，則HREF具有0_83V的標稱閾 值。AGTL架構的實施例只是例示性的，其他的電壓值和 _ 操作模式亦被考慮使用。此一 HREF信號並非來自於晶片 外，而是產自於晶片内。更且，此一 HREF信號具有兩個 操作電壓值，一個稍高於標稱閾值電壓，另一個稍低於標 稱閾值電壓，而使用那一個閾值電壓則取決於GRASS信號 的狀態。如此，HREF信號並非一單一電壓值，而是一具 有遲滯值的參考信號，其如下述。 一分壓器201 ，做為一參考電路，產生HREF信號的 標稱閾值電壓。此分壓器201係由三個實質相同的P-通道 12 200536262 · 裝罝PI、P2及P3，在匯流排電源信號VTT及一參考端子或 接腳如接地端GND之間，以串連方式堆疊而成。Ρ1的源極 連接VTT，其汲極及閘極在一第一中節點203相連，該第 一中節點203產生HREF信號。Ρ2的源極連接中節點 203 ，其汲極及閘極在一第二中節點205相連。P3的源極 連接中節點205，其汲極及閘極在接地端GND相連。每 PI、P2及P3的基體（或N-井或井連接線（welltie))各自與其 源極連接。如此，P1的源極及基體與VTT等電位，而P3的馨 閘極及汲極則均接地。P1的閘極及汲極與P2的源極及基體 等電位，P2的閘極及汲極與P3的源極及基體等電位。如 此，分壓器201以一種對稱的組態形成，並將VTT電壓均 分為三等分。如此，節點203的標稱電壓值約為（2/3) VTT，而節點205的電壓值約為（1/3) VTT。 輸入接受器200包括一“弱”堆疊裝置207 ，其具有 一 P-通道裝置P4及N-通道裝置N1 。GRASS信號被提供給 N1及P4的源極。N1及P4的汲極及P4的閘極在節點203 _ 連接。N1的閘極連接節點205，P4的基體連接VTT。在 另一種組態中，N1及P4基體節點可連接至GRASS信號。 堆疊裝置207做為一切換電路，依GRASS信號的變換，而 稍為增加或減少節點203參考信號HREF的閾值電壓。隨 著輸入信號PDPADIN與參考信號HREF比較的結果的變 換，差動放大器U1依高或低閾值電壓變換GRASS信號的 狀態。HREF信號以輸入信號PDPADIN變化方向的反方向 增加或減少，如此便可依GRASS信號變換提供遲滯值。在 13 200536262 所示的電路構造中，P1到P3具有相等的大小，而相較於PI 到P3，N1及P4則為較“弱”的裝置。如將述於後者，滯 後變動的程度可用調整N1及P4對P1到P3的相對大小來調 整0 第三圖為輸入接受器200運作的時序圖，其中以輸入 信號PDPADIN及參考信號HREF的電壓值為縱軸，而時間 為橫軸。時間刻度並非特定，而是依個別的裝置或應用而 定。輸入信號PDPADIN以在〇·〇ν至1.25V間振蕩或切換的_ 週期波呈現。匯流排電源信號VTT，依AGTL架構，以具 有約1.25V電壓的虛線呈現。HREF的標稱閾值電壓約為 0.83V ’以標有2/3 VTT的第一條點線呈現。在起始時間 T0(在非特定刻度時間座標=0·0)時，輸入信號PDPADIN在 其最低電壓值ov 。當輸入信號PDPADIN的電壓低於參考 信號href電壓值時，GRASS信號為高值；而當GRASS信 唬為咼值’ N1為關而P4為開；而當N1為關而P4為開 時，在節點203的參考信號href電壓便被拉升而高於標_ 稱閾值電壓的2/3VTT。在所示的電路構造中，相較於叫 朽’ P4是相對較“弱，，的裝置’所以如圖所示的上閾值電 壓HREF+ ’ HREF電壓只增加到高出％ 約編v ，即 0·88ν。如此，當在輸入信號pDPADIN低於來考彳古號 壓的時間點τ〇 ’參考信號咖f電壓起^在上 閾值迅蜃HREF+ 〇 輸入信號PDPADIN電壓持續上升直到在 聞值電壓Η膨，在此時點差動放大器饥進^^上 14 200536262 作，而將GRASS信號變為低值。而當GRASS信號為低值， P4為關而N1為開；而當P4為關而N1為開時，在節點 203的參考信號HREF電壓便被拉下而低於標稱閾值電壓 的2/3 VTT。在所示的電路構造中，相較於P1到P3，N1是 相對較“弱”的裝置，所以如圖所示的下閾值電壓HREF —，HREF電壓只減少到低於2/3 VTT約50mV ，gp 0.78V。如此，當大約在輸入信號PDPADIN高於參考信號 HREF的上閾值電壓HREF+的時間點T1，參考信號HREF 電壓被拉低至下閾值電壓HREF —。輸入信號PDPADIN繼 續增加至以301標示的最高值，然後再下降，直到在T2時 間低於下閾值電壓HREF —。當輸入信號PDPADIN下降而 在T2時間低於下閾值電壓HREF —時，差放大器U1進行 切換動作，而將GRASS信號拉至高值。當GRASS信號變為 高值，N1關閉而P4再度開啟，而參考信號HREF也再切 換回上閾值電壓HREF+，並週而復始地重複相似的過程。 輸出信號OUT回應GRASS信號的轉換而轉換，並提供一 PDPADIN信號的非反相表現。 輸入接受器200及第三圖輸入接受器200運作的時序 圖所例示的實施例顯示：相對於2/3 VTT的標稱閾值電壓， HREF遲滯值的變化範圍約為100mV。100mV遲滯值的變 化範圍己足以在許多的應用上容受雜訊，且不會導致上述 習知遲滯值裝置-如施密特觸發裝置-的不良效果。為說 明的方便，輸入信號PDPADIN以一週期性的信號呈現，但 也可以是任何其他種類的信號，包括二位元或數位邏輯的 15 200536262 ' * 信號。雖然輸入信號PDPADIN在此是以一相對“乾淨”的 信號呈現，但即使輸入信號PDPADIN加入高達數十mV的 雜訊亦不會干擾切換動作的正確運作。尤其，當HREF遲 滯值防止GRASS信號被錯誤觸發或振蕩時，HREF遲滯值 就能使差動放大器U1正確的切換。如同習於此項技術者 所能領會者，遲滯值的範圍可藉由調整N1及P4相對於P-通道堆疊裝置P1至P3的大小而達成。 此P-通道裝置被規劃為相對精確且均勻的電阻裝置， 其分割匯流排電源信號VTT而得到2/3 VTT的電壓值，以做 為比較及切換之用。差動放大器U1直接或間接地接受來 自匯流排電源信號VTT的電源，並在該電源的範圍一VTT 電壓至GND接地電壓之間對進行對GRASS信號的切換。於 是，當N1關而P4開，P4實際上是處於與P1並聯的狀態， 在VTT及節點203之間的總電阻因而降低，HREF的電壓 值因此而提高到上閾值電壓HREF+。同時，當P4關而N1 開，N1實際上是處於與P2及P3並聯的狀態，在GND接地 端及節點203之間的總電阻因而降低，HREF的電壓值因 此而降低到下閾值電壓HREF —。其他替代性的構造亦可 被考慮，例如以電阻器或其他電阻性裝置建構分壓器 201 。在此替代性的構造中或在另外的情況，N1及P4可 被電阻式裝置及切換電路取代，以針對GRASS信號在 HREF+及HREF —間調整參考信號HREF 。 第四圖為根據本發明例示性實施例之建構差動輸入接 受器方法的流程圖。在第一方塊401 ，一標稱電壓值被提 16 200536262 ' ‘ 供給一參考節點。在所示的實施例中，此是由在匯流排電 壓源VTT及GND之間堆疊具有一中節點的複數P-通道裝置 而達成。在次一方塊403 ，使用一差動放大器對一輸入信 號及蒼考郎點電壓進行比較’該差動放大器在一電壓南值 及一電壓低值間進行切換。在一實施例中，當輸入信號電 壓低於一下閾值電壓時，差動放大器切換至電壓高值，而 當輸入信號電壓高於一上閾值電壓時，差動放大器切換至 電壓低值。同時，差動放大器接受匯流排電壓VTT，並在· VTT電壓間進行切換。200536262 IX. Description of the invention: [Technical field to which the invention belongs] A method for providing a hysteresis value to the range of Λ valley acceptance The present invention relates to an input receiver, especially an input receiver, to provide an appropriate input device for the input signal. [Previous Technology] In the design of early integrated circuits, complementary (single) wheel-out drivers were planned as push-pull components. Differences in circuit temperature, supply voltage, and manufacturing process, lose: = fluctuations, and noise is also the number of devices that are integrated in the integrated circuit. It is necessary to accumulate more externally = problem 'in order to maximize the speed of circuit operation in the system. Recently, the concept of the mechanical problem has shifted towards self-push-pull output: the use of differential input receivers. One side of the differential input receiver is measured by the voltage, and the other side is opened by the open-circuit drain electrode and the open-circuit drain channel_channel device # by crystal clothing. Typically, the bus pull-up resistors are provided on-chip or externally, such as on the system motherboard. The above-mentioned type of output driver prevails in the industrial world. One example is the Pentium X86 series microprocessor developed by the British fntd). The Pentium microprocessor uses an open-drain team to connect and drive a UV bus, and its reference interval is coffee. Newer bus 200536262 bus specifications use lower voltages, such as a 1.25V bus with a reference threshold of 0.83V. A 56 ohm pull-up terminal is usually used, and when the pull-down impedance is not specified, an open-drain channel device is used to meet bus switching and timing specifications. The industry uses the name Assisted Gunning Transceiver Logic (AGTL, Assisted Gunning Transceiver Logic) to describe such devices that connect such buses extensively. These devices are known as AGTL devices or AGTL logic or AGTL for short. However, the conventional input receiver has disadvantages in the case where the input signal has high noise. Input signals with south noise can cause false triggering and improper operation on integrated circuits. For these receivers, the threshold for triggering or switching is defined by a voltage range adjacent to the switching threshold of the design. The limitation of this voltage range is roughly determined by the manufacturing process, operating temperature, and operating voltage. Other input devices such as Schmidt Trigger devices are designed to provide hysteresis for input signals, but at the cost of reduced speed, increased energy consumption, and additional bus load. If the voltage is lowered according to the newer bus specifications, the noise tolerance will be reduced accordingly, and the noise problem will become more serious. It is therefore imperative to provide an input receiver that can tolerate higher noise while still maintaining correct logic operations at bus operating voltages, including lower voltages at newer specifications. It is also necessary to provide an input receiver that can replace the conventional input receiver and has a high noise immunity without paying for devices such as Schmitt triggering devices that use hysteresis values today. The price. 200536262 [Summary of the Invention] "Problems to be Solved" The problem to be solved by the present invention is to provide an input receiver using a hysteresis reference value, which has higher noise immunity and can tolerate more noise. , While still being able to maintain the correct logic operation at the bus operating voltage, and there is no known disadvantage of using a hysteresis device. "Means for Solving Problems" An embodiment of the present invention provides an input acceptance state with a hysteresis value, which includes: a differential amplifier; a reference circuit having a reference $ point and generating a reference at a nominal threshold voltage Signals; and a switching stacker. The amplifier has a first input terminal that receives an input signal, a second input terminal connected to a reference node, and an output terminal to provide a first output signal. The round-out signal has first and second signals. The state refers to a state where the input signal is not described. In this switching device, a differential amplifier output terminal and a reference node are connected, and the reference number is adjusted according to a first output signal located between the upper or lower threshold voltage and opposite to the turn-in signal. In a specific embodiment of the present invention, the input signal is provided as the -inverting input terminal of the amplifier, so that the first output signal and the input signal are switched in opposite directions. In this embodiment, it is also possible to provide a state of inverting the first-output signal, thereby providing a second round of out: input signals. This circuit can be a voltage divider, which can divide the power supply voltage to generate the tea test signal. This reference circuit has a middle node as a reference node for generating the reference signal of 200536262. In a more specific embodiment, the voltage divider includes a plurality of p-channel devices, and the p-channel devices are connected in series between the power voltage signal and the ground terminal. Each P-channel device has a bulk and a source connected together, and a gate and a drain connected together. As far as the AGTL architecture is concerned, the first mid-node provides a reference signal, which has a nominal value of about two thirds of the power supply voltage signal. The switching stacker may include a P-channel device and an N-channel device. This P-channel device has a source connected to the output of the differential amplifier, and a gate and an electrode are both connected to the reference node. This N-channel device has a source connected to the differential amplifier output, a drain connected to a reference node, and a gate connected to a voltage divider. In this example, the voltage divider may include a second intermediate node connected to the gate of the N-channel device. In the AGTL architecture, the first middle node has a nominal voltage of about two thirds of the power supply voltage signal, and the second middle node has a nominal voltage of about one third of the power supply voltage signal. According to an embodiment of the present invention, the present invention provides an integrated circuit including: a power pin and a ground pin, both of which jointly receive a bus voltage; a differential amplifier, which is powered by the bus voltage ; A reference circuit; and a switching circuit. The differential amplifier has an inverting input terminal for receiving an input signal, a non-inverting input terminal for receiving a reference signal, and an output terminal for providing a digital signal with first and second states for indicating. The state of the input signal. This reference circuit bridges the power and ground pins and provides a reference signal at a nominal threshold voltage. This switching circuit 200536262 is connected to the output terminal of the differential amplifier and adjusts the reference signal to high or lower than the nominal threshold = voltage.丄 丄, threshold value These two test circuits can be constructed—a resistive voltage divider—brother-zhong ㈣ ’to provide a reference signal. For example, this "dual device may include a plurality of p-channel devices, and these p-channels I are placed between the day and ground pins. Each -ρ · channel is equipped with a power source-matrix and source 'and connected between -A 1-pole and induced voltage division. 乂 Achieved includes a second middle node; and the -switching circuit can be 3 P_pass device and an N-channel vibration set. This one is connected to the first A gate and a drain of a middle node: set: there is a source at the output end of the amplifier. This N_channel :: every one of the β and β is connected to the middle, that is, a gate. The pole is connected to the second middle node and the output of the differential amplifier. In the AGTL architecture, the nominal voltage of the two-thirds of the bus voltage is equal to the nominal voltage of about one-third of the bus voltage. .'-- There is an embodiment of the present invention described in the present invention. The present invention provides a method of a human receiver, which includes: mentioning; and =: a reference node with hysteresis pressure; Comparing the reference section of the dynamic amplifier == the input signal voltage, the differential amplifier is located in: two :,-input, 亍 switching ... the dynamic amplifier is switched to a higher ; Low voltage test node thief r dry gate door seat size increases when the electric power is increased; and when the differential amplifier is switched to a lower threshold voltage to the threshold voltage. 200536262 Provide reference node One possible way is: stack a plurality of first P_channel devices between the end points of the voltage source and form a middle node. One possible way to increase the reference node and press to the upper threshold voltage is to start the connection to the p_channel stack, the device Other p_channel devices. One possible way to reduce the reference node voltage to the lower threshold voltage is to start an N_ pass device connected to the channel stacking device. A differential amplifier can be used to compare the reference node voltage to an input signal voltage.疋. When the input signal voltage is lower than the lower threshold voltage, the differential amplifier is switched to a higher voltage; and when the turn-in signal voltage is higher than the upper threshold voltage, the differential amplifier is switched to a lower voltage. Effects on the Prior Art Invented receiver with hysteresis value, has higher noise immunity, can tolerate higher noise, and still be able to operate at the bus voltage It has the disadvantages of maintaining correct logic operations, and not knowing the use of hysteresis devices to reduce speed, increase energy consumption, and extra bus load. [Embodiment] The following content can be implemented by those skilled in the art based on this. The present invention, various changes and modifications made to the preferred embodiments of the present invention, or the technical ideas disclosed herein can be applied to other embodiments. It is obvious and easy to complete for those skilled in the art. Therefore, the inventor does not intend to limit the present invention to the embodiments described herein, but rather accords the broadest scope of rights to the present invention in accordance with the technical ideas and novel features disclosed by the present invention. 〃 10 200536262 As the inventors recognized the need for an input receiver with an appropriate noise tolerance range, they developed an input receiver and method with a hysteresis value and a larger noise tolerance range than conventional input receivers. It is described below with reference to the first to fourth figures. The first figure is a schematic diagram of a conventional input receiver 100, which is used in an AGTL architecture open-drain bus. The conventional input receiver 100 includes: a differential amplifier U1 having an inverting input terminal to receive the reference signal REF, a non-inverting input terminal to receive the input signal PDPADIN, and an input terminal to provide an output signal OUT . The reference signal REF is derived from the bus power signal VTT to a switching threshold voltage. VTT and REF are generated outside the chip and provided to the chip via pads (not shown). In an AGTL architecture, the bus power signal VTT is about 1.5V, and the switching threshold REF | J is set to 2/3 VTT—or about 1.0V. When the PDPADIN signal passes the REF signal, U1 conversion is required. In the configuration shown, when the input signal PDPADIN is lower than REF, the output signal OUT is at a low value, and when the input signal PDPADIN is higher than REF, the output signal OUT is turned to a high value. < When the input signal PDPADIN has high noise, the input receiver 100 performs poorly. Moreover, according to the newer bus specifications, the bus power signal VTT is reduced to 1.25V, and the reference signal REF is reduced to a threshold voltage of about 0.83V (2/3 of 1.25V), and the noise tolerance range is also Being reduced in proportion, the problem of noise is more difficult to overcome. As mentioned earlier, other input devices, such as the Schmidt Trigger device, have a hysteresis for the input signal, but this is to reduce speed, increase energy consumption, and extra sink Exclude burdens as a price. 200536262 The second figure is a schematic diagram of an input receiver 2⑻ according to an embodiment of the present invention, which is used in an open circuit based on the AGTL architecture for a drain bus structure. It includes a differential amplifier U1 to accept the input signal PDPADIN. However, in this input receiver 200, the input signal PDPADIN is provided to the inverting input terminal of the differential amplifier U1, and another reference signal HREF with a hysteresis value is provided to the non-inverting input terminal. The differential amplifier U1 displays a GRASS signal at its output. This GRASS signal has an inverted state with respect to the state of the input signal PDPADIN. The input receiver 200 also includes an inverting phase converter U2, which has an input terminal to receive the GRASS signal and an output terminal to provide the OUT signal. The OUT signal is a non-inverted version of the PDPADIN signal. The reference signal HREF is derived from the bus power signal VTT and has a nominal threshold like the REF signal of the conventional differential input receiver 100. According to the AGTL architecture, if VTT is 1.5V, JHREF has a nominal threshold of 1.0V, and if VTT is 1.25V, HREF has a nominal threshold of 0_83V. The embodiment of the AGTL architecture is only exemplary, and other voltage values and _ operating modes are also considered for use. This HREF signal does not come from outside the chip, but is produced inside the chip. Moreover, this HREF signal has two operating voltage values, one slightly above the nominal threshold voltage and the other slightly below the nominal threshold voltage, and which threshold voltage is used depends on the state of the GRASS signal. As such, the HREF signal is not a single voltage value, but a reference signal with a hysteresis value, which is as follows. A voltage divider 201 is used as a reference circuit to generate the nominal threshold voltage of the HREF signal. This voltage divider 201 is composed of three essentially identical P-channels 12 200536262 · Equipped with PI, P2, and P3, in series connection between the bus power signal VTT and a reference terminal or pin such as the ground terminal GND Stacked. The source of P1 is connected to VTT, and its drain and gate are connected at a first middle node 203, which generates a HREF signal. The source of P2 is connected to the middle node 203, and its drain and gate are connected to a second middle node 205. The source of P3 is connected to the middle node 205, and its drain and gate are connected to the ground terminal GND. The matrix (or N-well or welltie) of each PI, P2, and P3 is connected to its source, respectively. In this way, the source and base of P1 are at the same potential as VTT, while the gate and drain of P3 are both grounded. The gate and drain of P1 are equipotential to the source and base of P2, and the gate and drain of P2 are equipotential to the source and base of P3. As such, the voltage divider 201 is formed in a symmetrical configuration and divides the VTT voltage into three equal parts. In this way, the nominal voltage value of the node 203 is about (2/3) VTT, and the voltage value of the node 205 is about (1/3) VTT. The input receiver 200 includes a "weak" stacking device 207 having a P-channel device P4 and an N-channel device N1. The GRASS signal is provided to the sources of N1 and P4. The drains of N1 and P4 and the gate of P4 are connected at node 203_. The gate of N1 is connected to node 205, and the base of P4 is connected to VTT. In another configuration, N1 and P4 base nodes can be connected to GRASS signals. As a switching circuit, the stacking device 207 slightly increases or decreases the threshold voltage of the reference signal HREF of the node 203 according to the conversion of the GRASS signal. As the result of the comparison between the input signal PDPADIN and the reference signal HREF changes, the differential amplifier U1 changes the state of the GRASS signal by a high or low threshold voltage. The HREF signal increases or decreases in the opposite direction to the direction of change of the input signal PDPADIN, so that the hysteresis value can be provided according to the GRASS signal transformation. In the circuit configuration shown in 13 200536262, P1 to P3 are of equal size, and compared to PI to P3, N1 and P4 are “weak” devices. As will be described in the latter, the degree of hysteresis can be adjusted by adjusting the relative sizes of N1 and P4 to P1 to P3. The third diagram is the timing diagram of the operation of the input receiver 200, where the voltage values of the input signal PDPADIN and the reference signal HREF are used. Is the vertical axis and time is the horizontal axis. The time scale is not specific but depends on the individual device or application. The input signal PDPADIN is presented as a _ periodic wave that oscillates or switches between 〇ν to 1.25V. The bus power signal VTT is represented by a dotted line with a voltage of about 1.25V according to the AGTL architecture. The nominal threshold voltage of HREF is approximately 0.83V 'and is represented by the first dotted line labeled 2/3 VTT. At the start time T0 (the time coordinate at the non-specific scale = 0 = 0), the input signal PDPADIN is at its lowest voltage value ov. When the voltage of the input signal PDPADIN is lower than the reference signal href, the GRASS signal is a high value; and when the GRASS signal is a threshold value 'N1 is off and P4 is on; and when N1 is off and P4 is on, in The reference signal href voltage of node 203 is pulled up and is higher than 2/3 VTT of the nominal threshold voltage. In the circuit configuration shown, compared to the device called 'P4', the device is relatively weak, so the upper threshold voltage HREF + 'HREF voltage as shown in the figure only increases to %%, about v, that is 0 · 88ν. In this way, when the input signal pDPADIN is lower than the time when the ancient signal pressure was measured τ〇 'the reference signal coffee voltage starts from the upper threshold 阈 HREF + 〇 The input signal PDPADIN voltage continues to rise until the voltage value Η At this time, the point of the differential amplifier is ^^ 14 200536262, and the GRASS signal becomes a low value. When the GRASS signal is a low value, P4 is off and N1 is on; and when P4 is off and N1 is on When on, the reference signal HREF voltage at node 203 is pulled down and is lower than 2/3 VTT of the nominal threshold voltage. In the circuit configuration shown, N1 is relatively "weak" compared to P1 to P3 The device, so the lower threshold voltage HREF — as shown in the figure, the HREF voltage is only reduced to about 50mV below 2/3 VTT, gp 0.78V. So when the input signal PDPADIN is higher than the upper threshold voltage of the reference signal HREF At time T1 of HREF +, the voltage of the reference signal HREF is pulled down to the lower threshold voltage HREF —. The input signal PDPADIN continues to increase to the highest value indicated by 301, and then decreases until it falls below the lower threshold voltage HREF at time T2 — When the input signal PDPADIN falls and falls below the lower threshold voltage HREF at time T2 — The difference amplifier U1 switches to pull the GRASS signal to a high value. When the GRASS signal becomes high, N1 is turned off and P4 is turned on again, and the reference signal HREF is switched back to the upper threshold voltage HREF +, and the similar process is repeated again and again. The output signal OUT is converted in response to the conversion of the GRASS signal, and provides a non-inverted representation of the PDPADIN signal. The timing diagram of the operation of the input receiver 200 and the third input receiver 200 illustrated in the illustrated example shows that relative to 2 / 3 Nominal threshold voltage of VTT, the range of HREF hysteresis value is about 100mV. The range of 100mV hysteresis value is enough to tolerate noise in many applications, and will not cause the above-mentioned conventional hysteresis devices-such as Schmitt The special effect of the special trigger device. For the convenience of explanation, the input signal PDPADIN is presented as a periodic signal, but it can also be any other kind. Signals, including two-bit or digital logic 15 200536262 '* signals. Although the input signal PDPADIN is presented here as a relatively "clean" signal, even if the input signal PDPADIN adds noise up to tens of mV, it will not interfere The correct operation of the switching action. In particular, when the HREF hysteresis value prevents the GRASS signal from being triggered or oscillated by mistake, the HREF hysteresis value enables the differential amplifier U1 to switch correctly. As can be appreciated by those skilled in the art, the range of the hysteresis value can be achieved by adjusting the sizes of N1 and P4 relative to the P-channel stacking devices P1 to P3. This P-channel device is planned as a relatively accurate and uniform resistor device, which divides the bus power signal VTT to obtain a voltage value of 2/3 VTT for comparison and switching. The differential amplifier U1 directly or indirectly receives power from the bus power signal VTT, and switches the GRASS signal between the power source range VTT voltage and the GND ground voltage. Therefore, when N1 is off and P4 is on, P4 is actually in a parallel state with P1. The total resistance between VTT and node 203 is thus reduced, and the voltage value of HREF is increased to the upper threshold voltage HREF +. At the same time, when P4 is off and N1 is on, N1 is actually in a parallel state with P2 and P3. The total resistance between GND and node 203 is reduced, and the voltage value of HREF is reduced to the lower threshold voltage HREF — . Other alternative configurations are also contemplated, such as constructing the voltage divider 201 with a resistor or other resistive device. In this alternative configuration or in other cases, N1 and P4 can be replaced by resistive devices and switching circuits to adjust the reference signal HREF between HREF + and HREF — for GRASS signals. The fourth figure is a flowchart of a method of constructing a differential input receiver according to an exemplary embodiment of the present invention. In the first block 401, a nominal voltage value is raised 16 200536262 '′ is supplied to a reference node. In the embodiment shown, this is achieved by stacking a plurality of P-channel devices with a middle node between the bus voltage sources VTT and GND. At next block 403, a differential amplifier is used to compare an input signal and Cangkorang point voltage ', the differential amplifier switches between a voltage south value and a voltage low value. In one embodiment, when the input signal voltage is lower than the lower threshold voltage, the differential amplifier is switched to a high voltage value, and when the input signal voltage is higher than an upper threshold voltage, the differential amplifier is switched to a low voltage value. At the same time, the differential amplifier accepts the bus voltage VTT and switches between the VTT voltages.
在次一方塊405，當差動放大器切換至電壓高值，參 考節點電壓被增加至上閾值電壓。在所示的實施例中，此 是由啟動連至第一 P-通道堆疊裝置的一第二卩_通道裝置而 達成。而在次一方塊407，當差動放大器切換至電壓低 值，參考節點電壓被減少至下閾值電壓。在所示的實施例 中，此是由啟動連至第一 P-通道堆疊裝置的一 N-通道裝置 而達成。 I 依本發明之實施例而實施之差動接受器有數個勝於習 知接受器的優點。本發明使設計者能在積體電路或晶片中 使用一種差動接受器，其雜訊容受範圍明顯高於習知差動 接受器迄今為止所能提供者。例如，差動輸入接受器200 可以實施於一積體電路，其接受的VTT匯流排電壓係來自 外部來源。在所示的實施例中，HREF信號是内生自VTT 信號。輸入信號PDPADIN可自外部或内部來源提供。 HREF信號的遲滯值可以對抗一高雜訊的輸入信號 17 200536262 PDPADIN。如同本說明所述’遲滯值的變化範圍可藉由調 整堆疊裝置的大小而增加。本發明對在低電壓操作的差動 輸入接受器具有顯著的優點，例如使用於較新的匯流排規 格的％合，其預期將會使用1.25V的匯流排且具有〇 83v 的閾值電壓。 雖然在此本發明己參照一些較佳實施例做相當詳細的 描述，但其他實施例或變化亦在本發明的預期之内。例 如，分壓器201亦可以使用其他精密或一般的電阻器或電 阻式裝置。同樣地，裝罝Ρ4及N1亦可以電阻式裝置及電 子式切換裝置或類似裝置取代。 雖然本發明在此使用AGTL的匯流排規格及其相關輸 入規範加以描述，但在此發明人亦要強調本發明之範圍係 超出AGTL而及於需要對輸入之雜訊免疫的任何應用。 習於此技術者當應明瞭：以本發明所揭露之觀念及特 定的實施例為基礎而設計或修改成其他構造以達成與本發 明目標相同之功能，其均不脫離本發明之精神與由申請專 利範圍所定之權利範圍。 【圖式簡單說明】 一第一圖為依AGTL規範使用於開路汲極匯流排的習知 接受器示意圖。 第二圖為依AGTL規範使用於開路汲極匯流排的本發 明一實施例之例示性接受器的示意圖。 第二圖為第二圖之本發明一實施例之例示性輸入接受 18 200536262 器運作的時序圖。 第四圖為根據本發明例示性實施例之建構具有遲滯值 差動輸入接受器之方法的流程圖。 【主要元件符號說明】 元件及信號 100 習知輸入接受器 200 本發明一實施例之輸入接受器 201 分壓器 202 第一中節點 205 第二中節點 207 “弱”堆疊裝置 U1 差動放大器 REF 參考信號 PDPADIN 輸入信號 OUT 輸出信號 VTT 匯流排電源信號 HREF 具遲滯值的參考信號 GRASS 差動放大器輸出信號 PI P-通道裝罝 P2 P-通道裝罝 P3 P-通道裝罝 P4 P-通道裝置 N1 N-通道裝置 HREF + 上閾值電壓At next block 405, when the differential amplifier is switched to a high voltage value, the reference node voltage is increased to an upper threshold voltage. In the illustrated embodiment, this is achieved by activating a second channel device connected to the first P-channel stacking device. On the next block 407, when the differential amplifier is switched to a low voltage, the reference node voltage is reduced to a lower threshold voltage. In the illustrated embodiment, this is achieved by activating an N-channel device connected to the first P-channel stacking device. I The differential receiver implemented in accordance with an embodiment of the present invention has several advantages over conventional receivers. The present invention enables designers to use a differential receiver in an integrated circuit or chip, and its noise tolerance range is significantly higher than that of conventional differential receivers so far. For example, the differential input receiver 200 may be implemented in an integrated circuit, and the VTT bus voltage it receives is from an external source. In the embodiment shown, the HREF signal is an endogenous VTT signal. The input signal PDPADIN can be provided from an external or internal source. The hysteresis value of the HREF signal can counteract a high-noise input signal. 17 200536262 PDPADIN. As described in this description, the range of the hysteresis value can be increased by adjusting the size of the stacking device. The present invention has significant advantages for differential input receivers operating at low voltages, such as the% combination used in newer bus specifications, which is expected to use a 1.25V bus and have a threshold voltage of 083V. Although the present invention has been described in some detail with reference to some preferred embodiments, other embodiments or variations are also contemplated by the present invention. For example, the voltage divider 201 can also use other precision or general resistors or resistive devices. Similarly, the mountings P4 and N1 can also be replaced by resistive devices and electronic switching devices or similar devices. Although the present invention is described herein using the bus specification of AGTL and its related input specifications, the inventor also emphasizes that the scope of the present invention is beyond AGTL and for any application requiring immunity to input noise. Those skilled in the art should understand that designing or modifying into other structures based on the concepts and specific embodiments disclosed in the present invention to achieve the same function as the object of the present invention, all do not depart from the spirit and reason of the present invention. The scope of rights set by the scope of patent application. [Schematic description] A first diagram is a schematic diagram of a conventional receiver used in an open-drain busbar according to the AGTL specification. The second figure is a schematic diagram of an exemplary receiver of an embodiment of the present invention used in an open-drain busbar according to the AGTL specification. The second figure is a timing diagram of an exemplary input acceptance 18 200536262 device according to an embodiment of the present invention in the second figure. The fourth figure is a flowchart of a method of constructing a differential input receiver with hysteresis according to an exemplary embodiment of the present invention. [Symbol description of main components] Component and signal 100 Known input receiver 200 Input receiver 201 Voltage divider 202 First middle node 205 Second middle node 207 “Weak” stacking device U1 Differential amplifier REF Reference signal PDPADIN Input signal OUT Output signal VTT Bus power signal HREF Reference signal with hysteresis GRASS Differential amplifier output signal PI P-channel device P2 P-channel device P3 P-channel device P4 P-channel device N1 N-channel device HREF + upper threshold voltage
19 200536262 HREF - 下閾值電壓 GND 接地端 步驟 401 一標稱電壓值被提供給一參考節點 403 使用一差動放大器對一輸入信號及參考節點電壓進 行比較 405 當差動放大器切換至電壓高值，參考節點電壓被增0 加至上閾值電壓 407 當差動放大器切換至電壓低值，參考節點電壓被減 少至下閾值電壓19 200536262 HREF-lower threshold voltage GND ground step 401 A nominal voltage value is provided to a reference node 403 A differential amplifier is used to compare an input signal with a reference node voltage 405 When the differential amplifier is switched to a high voltage value, Reference node voltage is increased from 0 to the upper threshold voltage 407 When the differential amplifier is switched to a low voltage value, the reference node voltage is reduced to the lower threshold voltage
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