CN1691044A - An input receiver with hysteresis value, its construction method and integrated circuit - Google Patents

Abstract

The invention relates to an input receptor with hysteresis value, comprising: a differential amplifier having a first input terminal for receiving an input signal, a second input terminal connected to a reference node, and an output terminal for providing a first output signal having a first state and a second state respectively indicative of the state of the input signal; a reference circuit providing a reference node and generating a reference signal at a nominal threshold voltage value; and a stack device connected to the output terminal of the differential amplifier and the reference node, and adjusting the reference signal between the upper threshold voltage and the lower threshold voltage in a direction opposite to the input signal according to the first output signal. The invention has a hysteresis value input receiver, has higher noise immunity, can bear higher noise, can still maintain correct logic operation at the bus operating voltage, and does not have the defects of speed reduction, energy consumption increase, extra bus burden and the like of the traditional hysteresis value device.

Description

An input receiver with hysteresis value, its construction method and integrated circuit

technical field

The present invention relates to an input acceptor, and more particularly to a method and device for providing an input acceptor for a hysteresis value to provide an appropriate noise tolerance range for an input signal.

Background technique

In the design of early integrated circuits, complementary metal-oxide-semiconductor (CMOS) output drivers were planned as push-pull devices. As a result, the output bus noise can fluctuate significantly depending on circuit temperature, supply voltage, and manufacturing process variations, while the noise is also a function of the number of devices assembled on the integrated circuit.

In recent years, due to the continuous development of technology, the size of devices and the voltage used have been gradually reduced. Designers are forced to deal with noise problems more actively on external buses in order to maximize the speed of circuit operation in the system. The industry's recent approach to solving the output driver problem has shifted from push-pull outputs to differential input receivers. One side of the differential input receiver is connected to a reference voltage, and the other side is driven by an open-drain N-channel device. Typical open-drain N-channel devices are provided on-chip, and the bus pull-up resistors are provided on-chip or externally, such as on a system motherboard or the like.

The above-mentioned types of output drivers are prevalent in the industry, and the Pentium (Intel) X86 series microprocessor developed by Intel is one example. Pentium microprocessors use open-drain N-channel output devices to drive a 1.5V bus with a reference threshold of 1.0V. Newer bus specifications use lower voltages, such as a 1.25V bus with a reference threshold of 0.83V. Typically 56 ohm pull-up terminations are used, and while pull-down impedance is not specified, open drain channel devices are used to meet bus switching and timing specifications. The industry uses the name Assisted Gunning Transceiver Logic (AGTL, Assisted Gunning Transceiver Logic, Assisted Transceiver Logic Circuit) to broadly describe devices connected to this type of bus. These devices are known as AGTL devices or AGTL Logic or simply AGTL.

However, existing input receivers have disadvantages where the input signal is highly noisy. Input signals with high noise can cause false triggers and improper operation on integrated circuits. For these receptors, the triggering or switching threshold is defined by a voltage range adjacent to the designed switching threshold. The limitation of this voltage range is roughly determined by the manufacturing process, operating temperature and operating voltage. Other input devices such as Schmidt Trigger devices are designed to provide hysteresis for input signals, but at the expense of reduced speed, increased power consumption, and additional bus load.

As the voltage is reduced according to the newer bus specification, the noise tolerance is reduced, which makes the noise problem more and more serious. There is therefore an urgent need to provide an input receiver that can tolerate higher noise levels while still maintaining correct logic operations at bus operating voltages, including lower voltages in newer specifications. Also for those in need is an input receiver that can replace existing input receivers with higher noise immunity without the expense of today's devices that use hysteresis values, like Schmitt trigger devices.

Contents of the invention

The technical problem to be solved by the present invention is to provide an input receiver using a hysteresis variable reference value, which has higher noise immunity, can withstand higher noise, and can still maintain correct logic operation under the bus operating voltage, and There is no disadvantage of conventional hysteresis value devices.

In order to achieve the above object, the present invention provides an input receiver with a hysteresis value, which is characterized in that it includes: a differential amplifier, which has a first input terminal for receiving an input signal, connected to a reference node A second input terminal, and an output terminal providing a first output signal, the first output signal has a first state and a second state respectively used to indicate the state of the input signal; a reference circuit, which provides the the reference node and generate a reference signal at a nominal threshold value; and a stack device connected to the output of the differential amplifier and the reference node, and based on the first output signal, and the The opposite direction of the input signal adjusts the reference signal between an upper threshold voltage and a lower threshold voltage.

The above-mentioned input receiver is characterized in that the reference circuit includes a voltage divider, the voltage divider has a first middle node as the reference node, and divides a power supply voltage signal to generate the reference signal.

The above-mentioned input receiver is characterized in that the voltage divider includes a plurality of P-channel devices, and the plurality of P-channel devices are connected in series between the power supply voltage signal and the ground terminal.

The above-mentioned input receiver is characterized in that each P-channel device has a substrate and a source connected together, and a gate and a drain connected together.

The above-mentioned input receiver is characterized in that the first middle node provides the reference signal, and the nominal value of the reference signal is about two-thirds of the power supply voltage signal.

The above input acceptor, wherein said stacked device comprises: a P-channel device having a source connected to said differential amplifier and having a gate and a drain connected to said reference node; and An N-channel device having a source connected to the output of the differential amplifier, a drain connected to the reference node, and a gate connected to the voltage divider.

The above input acceptor is characterized in that said voltage divider comprises a second intermediate node connected to said gate of said N-channel device.

The above input acceptor, wherein said first intermediate node has a nominal voltage value of about two-thirds of said supply voltage signal, and wherein said second intermediate node has a nominal voltage value of approximately two-thirds of said supply voltage signal One-third of a nominal voltage value of a signal.

The above-mentioned input acceptor is characterized in that it further includes: the input signal is provided to an inverting input terminal of the differential amplifier, wherein the first output signal is switched in a direction opposite to that of the input signal ; and an inverter, which has an input connected to the output of the differential amplifier, and an output for providing a second output signal to indicate the state of the input signal.

The present invention also provides an integrated circuit, which is characterized in that it includes: a power pin and a ground pin, both of which receive a bus voltage; a differential amplifier, which is powered by the bus voltage and has an inverting an input terminal to receive an input signal, a non-inverting input terminal to receive a reference signal, and an output terminal to provide a digital signal having first and second states to indicate the state of the input signal; a reference circuit, which bridges between the power pin and ground pin and provides the reference signal at a nominal threshold voltage; and a switching circuit which connects the output of the differential amplifier and operates according to the The state of the digital signal is adjusted to adjust the reference signal to an upper or lower threshold voltage that is higher or lower than the nominal threshold voltage.

The above-mentioned integrated circuit is characterized in that the reference circuit includes a resistive voltage divider, and the resistive voltage divider has a first middle node to provide the reference signal.

The above integrated circuit is characterized in that the resistive voltage divider comprises a plurality of P-channel devices stacked between the power pin and the ground pin.

The above-mentioned integrated circuit is characterized in that each of the plurality of stacked P-channel devices includes a substrate and a source connected together, and a gate and a drain connected together.

The above-mentioned integrated circuit is characterized in that the switching circuit comprises: the voltage divider including a second mid-node; a first P-channel device having a gate respectively connected to the first mid-node pole and a drain, and a source connected to the output of the differential amplifier; and an N-channel device having a drain connected to the first mid-node, connected to the first A gate of the two middle nodes, and a source connected to the output terminal of the differential amplifier.

The above integrated circuit, wherein said first middle node has a nominal voltage value of about two-thirds of said bus voltage, and wherein said second middle node has a nominal voltage value of about three-thirds of said bus voltage. One-third of a nominal voltage value.

The present invention also provides a method for constructing an input receiver with a hysteresis value, which is characterized in that it includes: providing a reference node with a nominal threshold voltage; using a differential amplifier to compare the reference node voltage with the input signal voltage, and the differential amplifier is in switching between a higher voltage and a lower voltage; increasing the reference node voltage to an upper threshold voltage when the differential amplifier switches to a higher voltage; and decreasing the reference node when the differential amplifier switches to a lower voltage voltage to below the threshold voltage.

The above-mentioned method for constructing an input receiver with a hysteresis value is characterized in that the step of providing a reference node includes stacking a plurality of first P-channel devices between the terminals of the voltage source and setting up a middle node.

The above method of constructing an input receiver with a hysteresis value is characterized in that the step of increasing the reference node voltage includes activating a second P-channel device connected to the plurality of first P-channel devices. Channel device steps.

The above method of constructing an input receiver with a hysteresis value is characterized in that said step of reducing the reference node voltage comprises activating an N-channel device connected to said plurality of first P-channel devices A step of.

The above method for constructing an input receiver with a hysteresis value is characterized in that the step of comparing the reference node voltage with the input signal voltage includes switching the differential amplifier to a higher voltage when the input signal voltage is lower than the lower threshold voltage; and When the input signal voltage is higher than the upper threshold voltage, the differential amplifier switches to a lower voltage step.

The efficacy of the present invention lies in that the hysteresis value input receiver has higher noise immunity, can withstand higher noise, and can still maintain correct logic operation at the bus operating voltage, and does not have the reduction speed of the existing hysteresis value device. , Increase energy consumption and additional bus burden and other disadvantages.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

Figure 1 is a schematic diagram of an existing receiver used for an open-drain bus according to the AGTL specification;

2 is a schematic diagram of a receiver according to an embodiment of the present invention used in an open-drain bus according to the AGTL specification;

FIG. 3 is a timing diagram of the operation of the input receiver of an embodiment of the present invention in FIG. 2;

FIG. 4 is a flowchart of a method for constructing a differential input receiver with hysteresis in an embodiment of the present invention.

Among them, reference signs:

100-input receiver

200-input receiver, 201-voltage divider

203-the first middle node, 205-the second middle node

207 - "Weak" stack device

U1-differential amplifier, REF-reference signal

PDPADIN-input signal, OUT-output signal

VTT-bus source signal, HREF-reference signal with hysteresis value

GRASS-differential amplifier output signal

P1, P2, P3, P4-P-channel device

N1-N-channel device

HREF+-upper threshold voltage, HREF--lower threshold voltage

GND-ground terminal

Step 401 - providing a nominal voltage value to a reference node

Step 403 - Using a differential amplifier to compare an input signal with the reference node voltage

Step 405 - When the differential amplifier switches to a voltage high value, the reference node voltage is increased to the upper threshold voltage

Step 407 - When the differential amplifier switches to a voltage low value, the reference node voltage is reduced to the lower threshold voltage

Detailed ways

FIG. 1 is a schematic diagram of a conventional input receiver 100 used in an open-drain bus of an AGTL structure. The conventional input receiver 100 includes: a differential amplifier U1 having an inverting input terminal for receiving a reference signal REF, a non-inverting input terminal for receiving an input signal PDPADIN; and an output terminal for providing an output signal OUT. The reference signal REF is derived from the bus power signal VTT to a switching threshold value. VTT and REF are generated outside the chip and provided to the chip through pads (not shown). In an AGTL architecture, the bus power signal VTT is about 1.5V, and the switching threshold REF is set at 2/3 VTT or about 1.0V. When the PDPADIN signal passes through the REF signal, a transition of U1 is required. In the configuration shown, when the input signal PDPADIN is lower than REF, the output signal OUT is low, and when the input signal PDPADIN is higher than REF, the output signal OUT goes high.

The input receiver 100 does not perform well when the input signal PDPADIN has high noise. Moreover, according to the newer bus specification, the bus power signal VTT is reduced to 1.25V, the reference signal REF is reduced to about 0.83V (2/3 of 1.25V) threshold value, and the noise tolerance range is also proportionally reduced , making it more difficult to overcome the noise problem. As mentioned earlier, other input devices, such as Schmidt Trigger devices, provide a hysteresis value (hysteresis) to the input signal, but this is done by reducing speed, increasing power consumption, and additional bus load. cost.

FIG. 2 is a schematic diagram of an input receiver 200 according to an embodiment of the present invention, which is open-circuited and used in a drain bus structure according to the AGTL architecture. It includes a differential amplifier U1 to receive the input signal PDPADIN. But in the input receiver 200, the input signal PDPADIN is provided to the inverting input terminal of the differential amplifier U1, and another reference signal HREF with a hysteresis value is provided to the non-inverting input terminal. Differential amplifier U1 exhibits at its output a GRASS signal having an inverted state relative to the state of input signal PDPADIN. The input receiver 200 also includes an inverter U2 having an input terminal for receiving the GRASS signal and an output terminal for providing the OUT signal, which is a non-inverted version of the PDPADIN signal.

The reference signal HREF is derived from the bus power signal VTT and has the same nominal threshold as the REF signal of the conventional differential input receiver 100 . According to the AGTL architecture, HREF has a nominal threshold of 1.0V if VTT is 1.5V, and a nominal threshold of 0.83V if VTT is 1.25V. The embodiment of the AGTL architecture is only a preferred embodiment, other voltage values and modes of operation are also contemplated. This HREF signal does not come from outside the chip, but is generated inside the chip. Also, this HREF signal has two operating voltage values, one slightly above the nominal threshold voltage and the other slightly below the nominal threshold voltage, and which threshold voltage to use depends on the state of the GRASS signal. Thus, the HREF signal is not a single voltage value, but a reference signal with a hysteresis value, which is as follows.

A voltage divider 201, as a reference circuit, generates the nominal threshold voltage of the HREF signal. The voltage divider 201 is formed by stacking three substantially identical P-channel devices P1, P2 and P3 in series between the bus power signal VTT and a reference terminal or pin such as the ground terminal GND. The source of P1 is connected to VTT, and the drain and gate of P1 are connected to a first middle node 203, and the first middle node 203 generates the HREF signal. The source of P2 is connected to the middle node 203 , and the drain and gate of P2 are connected to a second middle node 205 . The source of P3 is connected to the middle node 205 , and the drain and gate of P3 are connected to the ground terminal GND. The substrate (or N-well or well tie) of each P1, P2 and P3 is connected to its source respectively. In this way, the source and base of P1 are at the same potential as VTT, while the gate and drain of P3 are both grounded. The gate and drain of P1 are at the same potential as the source and base of P2, and the gate and drain of P2 are at the same potential as the source and base of P3. As such, voltage divider 201 is formed in a symmetrical configuration and divides the VTT voltage into thirds. Thus, the nominal voltage value of the node 203 is about (2/3)VTT, and the voltage value of the node 205 is about (1/3)VTT.

The input receiver 200 includes a "weak" stack device 207 having a P-channel device P4 and an N-channel device N1. The GRASS signal is provided to the source of N1 and P4. The drains of N1 and P4 and the gate of P4 are connected at node 203 . The gate of N1 is connected to node 205, and the base of P4 is connected to VTT. In another configuration, the N1 and P4 substrate nodes can be connected to the GRASS signal. The stacking device 207 is used as a switching circuit to slightly increase or decrease the threshold voltage of the reference signal HREF at the node 203 according to the transformation of the GRASS signal. As the result of comparing the input signal PDPADIN with the reference signal HREF changes, the differential amplifier U1 switches the state of the GRASS signal according to the high or low threshold voltage. The HREF signal increases or decreases in the opposite direction of the change of the input signal PDPADIN, thus providing a hysteresis value according to the change of the GRASS signal. In the circuit configuration shown, P1 to P3 are of equal size, while N1 and P4 are "weaker" devices compared to P1 to P3. As will be described in the latter, the degree of hysteresis variation can be adjusted by adjusting the relative sizes of N1 and P4 to P1 to P3.

FIG. 3 is a timing diagram of the operation of the input receiver 200 , where the voltage values of the input signal PDPADIN and the reference signal HREF are plotted on the vertical axis, and time is plotted on the horizontal axis. The time scale is not specific but depends on the individual device or application. The input signal PDPADIN appears as a periodic wave oscillating or switching between 0.0V and 1.25V. The bus supply signal VTT, according to the AGTL architecture, is presented as a dashed line with a voltage of about 1.25V. The nominal threshold voltage for HREF is approximately 0.83V, represented by the first dotted line labeled 2/3 VTT. At an initial time T0 (at unscaled time coordinate = 0.0), the input signal PDPADIN is at its lowest voltage value of 0V. When the voltage of the input signal PDPADIN is lower than the voltage value of the reference signal HREF, the GRASS signal is high; and when the GRASS signal is high, N1 is off and P4 is on; and when N1 is off and P4 is on, the node The voltage of the reference signal HREF of 203 is pulled up to be higher than 2/3VTT of the nominal threshold voltage. In the circuit structure shown, P4 is a relatively "weak" device compared to P1 to P3, so the upper threshold voltage HREF+ as shown in the figure, the HREF voltage only increases to about 50mV higher than 2/3 VTT, That is 0.88V. Thus, when the input signal PDPADIN is lower than the voltage of the reference signal HREF at the time point T0, the voltage of the reference signal HREF is initially at the upper threshold voltage HREF+.

The voltage of the input signal PDPADIN continues to rise until it exceeds the upper threshold voltage HREF+ at time T1, at which point the differential amplifier U1 performs a switching action, and the GRASS signal becomes a low value. And when the GRASS signal is low, P4 is off and N1 is on; and when P4 is off and N1 is on, the reference signal HREF voltage at node 203 is pulled down to be lower than 2/3 of the nominal threshold voltage VTT. In the circuit structure shown, N1 is a relatively "weak" device compared to P1 to P3, so the lower threshold voltage HREF- as shown in the figure, the HREF voltage is only reduced to about 50mV below 2/3 VTT , ie 0.78V. Thus, when the input signal PDPADIN is higher than the upper threshold voltage HREF+ of the reference signal HREF at about time T1, the voltage of the reference signal HREF is pulled down to the lower threshold voltage HREF−. The input signal PDPADIN continues to increase to the highest value indicated by 301, and then decreases until it is lower than the lower threshold voltage HREF- at time T2. When the input signal PDPADIN falls and is lower than the lower threshold voltage HREF- during T2, the differential amplifier U1 performs a switching action to pull the GRASS signal to a high value. When the GRASS signal becomes high, N1 is turned off and P4 is turned on again, and the reference signal HREF is switched back to the upper threshold voltage HREF+, and the similar process is repeated again and again. The output signal OUT transitions in response to transitions of the GRASS signal and provides a non-inverted representation of the PDPADIN signal.

The embodiment shown in the input receiver 200 and the timing diagram of the operation of the input receiver 200 in FIG. 3 shows that the variation range of the HREF hysteresis value is about 100 mV with respect to the nominal threshold voltage of 2/3 VTT. A hysteresis variation range of 100 mV is sufficient for noise tolerance in many applications without causing the aforementioned adverse effects of existing hysteresis devices such as Schmitt trigger devices. For the convenience of illustration, the input signal PDPADIN is presented as a periodic signal, but it can also be any other kind of signal, including binary or digital logic signal. Although the input signal PDPADIN is presented as a relatively “clean” signal, even if the input signal PDPADIN adds noise up to tens of mV, it will not interfere with the correct operation of the switching operation. In particular, the HREF hysteresis value enables the differential amplifier U1 to switch correctly while preventing the GRASS signal from being falsely triggered or oscillating. As will be appreciated by those skilled in the art, a range of hysteresis values can be achieved by adjusting the size of N1 and P4 relative to the P-channel stack devices P1 to P3.

The P-channel device is designed as a relatively accurate and uniform resistance device, which divides the bus power signal VTT to obtain a voltage value of 2/3 VTT for comparison and switching purposes. The differential amplifier U1 directly or indirectly receives the power from the bus power signal VTT, and switches the GRASS signal within the range of the power supply - VTT voltage to GND ground voltage. Therefore, when N1 is turned off and P4 is turned on, P4 is actually connected in parallel with P1, the total resistance between VTT and node 203 decreases, and the voltage of HREF increases to the upper threshold voltage HREF+. At the same time, when P4 is off and N1 is on, N1 is actually in parallel with P2 and P3, the total resistance between GND and node 203 is reduced, and the voltage value of HREF is therefore reduced to the lower threshold voltage HREF- . Other alternative configurations are also contemplated, such as constructing the voltage divider 201 from resistors or other resistive devices. In this alternative configuration or in other cases, N1 and P4 can be replaced by resistive devices and switching circuits to adjust the reference signal HREF between HREF+ and HREF- for the GRASS signal.

FIG. 4 is a flowchart of a method for constructing a differential input receiver according to an exemplary embodiment of the present invention. In step 401, a nominal voltage value is provided to a reference node. In the embodiment shown, this is accomplished by stacking multiple P-channel devices with a middle node between the bus voltage source VTT and GND. In step 403, an input signal is compared with the reference node voltage using a differential amplifier that switches between a voltage high value and a voltage low value. In one embodiment, when the input signal voltage is lower than a lower threshold voltage, the differential amplifier switches to a high voltage value, and when the input signal voltage is higher than an upper threshold voltage, the differential amplifier switches to a low voltage value. At the same time, the differential amplifier receives the bus voltage VTT and switches between VTT voltages.

In step 405, when the differential amplifier switches to a voltage high value, the reference node voltage is increased to the upper threshold voltage. In the illustrated embodiment, this is accomplished by activating a second P-channel device connected to the first P-channel stack device. And in step 407, when the differential amplifier switches to a voltage low value, the reference node voltage is reduced to the lower threshold voltage. In the embodiment shown, this is accomplished by activating an N-channel device connected to the first P-channel stack device.

A differential receiver implemented in accordance with an embodiment of the present invention has several advantages over existing receivers. The present invention enables the designer to use a differential receiver in an integrated circuit or chip with a noise tolerance range significantly higher than what prior differential receivers have heretofore been able to provide. For example, the differential input receiver 200 can be implemented in an integrated circuit that receives the VTT bus voltage from an external source. In the illustrated embodiment, the HREF signal is endogenous from the VTT signal. The input signal PDPADIN can be provided from an external or internal source. The hysteresis of the HREF signal can counteract a noisy input signal PDPADIN. As described in this specification, the range of variation of the hysteresis value can be increased by adjusting the size of the stacking device. The present invention has significant advantages for differential input receivers operating at low voltages, eg for use in newer bus specifications, which are expected to use a 1.25V bus and have a threshold voltage of 0.83V.

Although the invention has been described in some detail herein with reference to certain preferred embodiments, other embodiments or variations are also contemplated by the invention. For example, the voltage divider 201 can also use other precision or general resistors or resistive devices. Likewise, the devices P4 and N1 can also be replaced by resistive devices and electronic switching devices or similar devices.

Although the invention is described herein using the bus specification of AGTL and its associated input specifications, the inventors here also emphasize that the scope of the invention goes beyond AGTL to any application where immunity to incoming noise is desired.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding changes All changes and modifications should belong to the protection scope of the claims of the present invention.

Claims (20)

1. An input receiver with a hysteresis value, comprising: A differential amplifier having a first input terminal for receiving an input signal, a second input terminal connected to a reference node, and an output terminal providing a first output signal having are respectively used to indicate the first state and the second state of the state of the input signal; a reference circuit providing the reference node and generating a reference signal at a nominal threshold value; and a stack device connected to the output terminal of the differential amplifier and the reference node, and adjusts between an upper threshold voltage and a lower threshold voltage according to the first output signal in a direction opposite to the input signal the reference signal. 2. The input receiver according to claim 1, wherein the reference circuit comprises a voltage divider, the voltage divider has a first middle node as the reference node, and divides a power supply voltage signal to generate the reference signal. 3. The input receiver according to claim 2, wherein the voltage divider comprises a plurality of P-channel devices connected in series between the supply voltage signal and the ground terminal. catch. 4. The input receiver of claim 3, wherein each P-channel device has a substrate and a source connected together, and a gate and a drain connected together. 5. The input receiver according to claim 2, wherein the first middle node provides the reference signal, and the nominal value of the reference signal is about two-thirds of the power voltage signal. 6. The input acceptor of claim 2, wherein said stacking means comprises: a P-channel device having a source connected to the differential amplifier and having a gate and a drain connected to the reference node; and An N-channel device having a source connected to the output of the differential amplifier, a drain connected to the reference node, and a gate connected to the voltage divider. 7. The input receiver of claim 6, wherein said voltage divider includes a second intermediate node connected to said gate of said N-channel device. 8. The input receiver of claim 7, wherein said first intermediate node has a nominal voltage value of about two-thirds of said supply voltage signal, and wherein said second intermediate The nodes have a nominal voltage value that is approximately one third of the supply voltage signal. 9. The input receiver according to claim 1, further comprising: the input signal is provided to an inverting input of the differential amplifier, wherein the first output signal is switched in a direction opposite to that of the input signal; and An inverter has an input terminal connected to the output terminal of the differential amplifier, and an output terminal for providing a second output signal to indicate the state of the input signal. 10. An integrated circuit, characterized in that it comprises: a power pin and a ground pin, both of which receive a bus voltage; A differential amplifier powered by the bus voltage and having an inverting input to receive an input signal, a non-inverting input to receive a reference signal, and an output to provide a digital signal to indicate the state of the input signal; a reference circuit bridged between the power pin and ground pin and providing the reference signal at a nominal threshold voltage; and A switching circuit, which is connected to the output terminal of the differential amplifier, and adjusts the reference signal to an upper or lower threshold voltage that is higher or lower than the nominal threshold voltage according to the state of the digital signal. 11. The integrated circuit of claim 10, wherein the reference circuit comprises a resistive voltage divider having a first middle node for providing the reference signal. 12. The integrated circuit of claim 11, wherein the resistive voltage divider comprises a plurality of P-channel devices stacked between the power pin and the ground pin between. 13. The integrated circuit of claim 12, wherein each of said plurality of stacked P-channel devices comprises a body and a source connected together, and a body and a source connected together. gate and drain. 14. The integrated circuit of claim 11, wherein the switching circuit comprises: the voltage divider including a second intermediate node; a first P-channel device having a gate and a drain respectively connected to the first mid-node, and a source connected to the output of the differential amplifier; and an N-channel device having a drain connected to the first mid-node, a gate connected to the second mid-node, and a source connected to the output of the differential amplifier . 15. The integrated circuit of claim 14, wherein said first mid-node has a nominal voltage value of approximately two-thirds of said bus voltage, and wherein said second mid-node has a A nominal voltage value of approximately one third of the bus voltage. 16. A method of constructing an input receiver with a hysteresis value, comprising: Provide a reference node with a nominal threshold voltage; Comparing the reference node voltage and the input signal voltage with a differential amplifier, the differential amplifier switches between a higher voltage and a lower voltage; increasing the reference node voltage to an upper threshold voltage when the differential amplifier switches to a higher voltage; and When the difference amplifier switches to a lower voltage, the reference node voltage is reduced to a lower threshold voltage. 17. The method of constructing an input receiver with a hysteresis value according to claim 16, wherein said step of providing a reference node comprises stacking a plurality of first P-channel devices between terminals of a voltage source, and setting up The steps of the middle node. 18. The method of constructing an input receiver having a hysteresis value according to claim 16, wherein said step of increasing the reference node voltage comprises activating a second P-channel device, the second P-channel device being connected to The step of said plurality of first P-channel means. 19. The method of constructing an input receiver having a hysteresis value according to claim 16, wherein said step of reducing the reference node voltage comprises activating an N-channel device connected to said Steps for a plurality of first P-channel devices. 20. The method for constructing an input receiver with a hysteresis value according to claim 16, wherein the step of comparing the reference node voltage with the input signal voltage comprises differential the step of switching the amplifier to a higher voltage; and switching the differential amplifier to a lower voltage when the input signal voltage is higher than the upper threshold voltage.

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